PseudoLoweringEmitter.cpp revision 6d3d7656539188b496089a3313ed4d13759adba3 
1//===- PseudoLoweringEmitter.cpp - PseudoLowering Generator -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#define DEBUG_TYPE "pseudo-lowering"
11#include "CodeGenInstruction.h"
12#include "CodeGenTarget.h"
13#include "llvm/ADT/IndexedMap.h"
14#include "llvm/ADT/SmallVector.h"
15#include "llvm/ADT/StringMap.h"
16#include "llvm/Support/Debug.h"
17#include "llvm/Support/ErrorHandling.h"
18#include "llvm/TableGen/Error.h"
19#include "llvm/TableGen/Record.h"
20#include "llvm/TableGen/TableGenBackend.h"
21#include <vector>
22using namespace llvm;
23
24namespace {
25class PseudoLoweringEmitter {
26  struct OpData {
27    enum MapKind { Operand, Imm, Reg };
28    MapKind Kind;
29    union {
30      unsigned Operand;   // Operand number mapped to.
31      uint64_t Imm;       // Integer immedate value.
32      Record *Reg;        // Physical register.
33    } Data;
34  };
35  struct PseudoExpansion {
36    CodeGenInstruction Source;  // The source pseudo instruction definition.
37    CodeGenInstruction Dest;    // The destination instruction to lower to.
38    IndexedMap<OpData> OperandMap;
39
40    PseudoExpansion(CodeGenInstruction &s, CodeGenInstruction &d,
41                    IndexedMap<OpData> &m) :
42      Source(s), Dest(d), OperandMap(m) {}
43  };
44
45  RecordKeeper &Records;
46
47  // It's overkill to have an instance of the full CodeGenTarget object,
48  // but it loads everything on demand, not in the constructor, so it's
49  // lightweight in performance, so it works out OK.
50  CodeGenTarget Target;
51
52  SmallVector<PseudoExpansion, 64> Expansions;
53
54  unsigned addDagOperandMapping(Record *Rec, DagInit *Dag,
55                                CodeGenInstruction &Insn,
56                                IndexedMap<OpData> &OperandMap,
57                                unsigned BaseIdx);
58  void evaluateExpansion(Record *Pseudo);
59  void emitLoweringEmitter(raw_ostream &o);
60public:
61  PseudoLoweringEmitter(RecordKeeper &R) : Records(R), Target(R) {}
62
63  /// run - Output the pseudo-lowerings.
64  void run(raw_ostream &o);
65};
66} // End anonymous namespace
67
68// FIXME: This pass currently can only expand a pseudo to a single instruction.
69//        The pseudo expansion really should take a list of dags, not just
70//        a single dag, so we can do fancier things.
71
72unsigned PseudoLoweringEmitter::
73addDagOperandMapping(Record *Rec, DagInit *Dag, CodeGenInstruction &Insn,
74                     IndexedMap<OpData> &OperandMap, unsigned BaseIdx) {
75  unsigned OpsAdded = 0;
76  for (unsigned i = 0, e = Dag->getNumArgs(); i != e; ++i) {
77    if (DefInit *DI = dynamic_cast<DefInit*>(Dag->getArg(i))) {
78      // Physical register reference. Explicit check for the special case
79      // "zero_reg" definition.
80      if (DI->getDef()->isSubClassOf("Register") ||
81          DI->getDef()->getName() == "zero_reg") {
82        OperandMap[BaseIdx + i].Kind = OpData::Reg;
83        OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
84        ++OpsAdded;
85        continue;
86      }
87
88      // Normal operands should always have the same type, or we have a
89      // problem.
90      // FIXME: We probably shouldn't ever get a non-zero BaseIdx here.
91      assert(BaseIdx == 0 && "Named subargument in pseudo expansion?!");
92      if (DI->getDef() != Insn.Operands[BaseIdx + i].Rec)
93        throw TGError(Rec->getLoc(),
94                      "Pseudo operand type '" + DI->getDef()->getName() +
95                      "' does not match expansion operand type '" +
96                      Insn.Operands[BaseIdx + i].Rec->getName() + "'");
97      // Source operand maps to destination operand. The Data element
98      // will be filled in later, just set the Kind for now. Do it
99      // for each corresponding MachineInstr operand, not just the first.
100      for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
101        OperandMap[BaseIdx + i + I].Kind = OpData::Operand;
102      OpsAdded += Insn.Operands[i].MINumOperands;
103    } else if (IntInit *II = dynamic_cast<IntInit*>(Dag->getArg(i))) {
104      OperandMap[BaseIdx + i].Kind = OpData::Imm;
105      OperandMap[BaseIdx + i].Data.Imm = II->getValue();
106      ++OpsAdded;
107    } else if (DagInit *SubDag = dynamic_cast<DagInit*>(Dag->getArg(i))) {
108      // Just add the operands recursively. This is almost certainly
109      // a constant value for a complex operand (> 1 MI operand).
110      unsigned NewOps =
111        addDagOperandMapping(Rec, SubDag, Insn, OperandMap, BaseIdx + i);
112      OpsAdded += NewOps;
113      // Since we added more than one, we also need to adjust the base.
114      BaseIdx += NewOps - 1;
115    } else
116      llvm_unreachable("Unhandled pseudo-expansion argument type!");
117  }
118  return OpsAdded;
119}
120
121void PseudoLoweringEmitter::evaluateExpansion(Record *Rec) {
122  DEBUG(dbgs() << "Pseudo definition: " << Rec->getName() << "\n");
123
124  // Validate that the result pattern has the corrent number and types
125  // of arguments for the instruction it references.
126  DagInit *Dag = Rec->getValueAsDag("ResultInst");
127  assert(Dag && "Missing result instruction in pseudo expansion!");
128  DEBUG(dbgs() << "  Result: " << *Dag << "\n");
129
130  DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
131  if (!OpDef)
132    throw TGError(Rec->getLoc(), Rec->getName() +
133                  " has unexpected operator type!");
134  Record *Operator = OpDef->getDef();
135  if (!Operator->isSubClassOf("Instruction"))
136    throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
137                                 "' is not an instruction!");
138
139  CodeGenInstruction Insn(Operator);
140
141  if (Insn.isCodeGenOnly || Insn.isPseudo)
142    throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
143                                 "' cannot be another pseudo instruction!");
144
145  if (Insn.Operands.size() != Dag->getNumArgs())
146    throw TGError(Rec->getLoc(), "Pseudo result '" + Operator->getName() +
147                                 "' operand count mismatch");
148
149  unsigned NumMIOperands = 0;
150  for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i)
151    NumMIOperands += Insn.Operands[i].MINumOperands;
152  IndexedMap<OpData> OperandMap;
153  OperandMap.grow(NumMIOperands);
154
155  addDagOperandMapping(Rec, Dag, Insn, OperandMap, 0);
156
157  // If there are more operands that weren't in the DAG, they have to
158  // be operands that have default values, or we have an error. Currently,
159  // Operands that are a sublass of OperandWithDefaultOp have default values.
160
161
162  // Validate that each result pattern argument has a matching (by name)
163  // argument in the source instruction, in either the (outs) or (ins) list.
164  // Also check that the type of the arguments match.
165  //
166  // Record the mapping of the source to result arguments for use by
167  // the lowering emitter.
168  CodeGenInstruction SourceInsn(Rec);
169  StringMap<unsigned> SourceOperands;
170  for (unsigned i = 0, e = SourceInsn.Operands.size(); i != e; ++i)
171    SourceOperands[SourceInsn.Operands[i].Name] = i;
172
173  DEBUG(dbgs() << "  Operand mapping:\n");
174  for (unsigned i = 0, e = Insn.Operands.size(); i != e; ++i) {
175    // We've already handled constant values. Just map instruction operands
176    // here.
177    if (OperandMap[Insn.Operands[i].MIOperandNo].Kind != OpData::Operand)
178      continue;
179    StringMap<unsigned>::iterator SourceOp =
180      SourceOperands.find(Dag->getArgName(i));
181    if (SourceOp == SourceOperands.end())
182      throw TGError(Rec->getLoc(),
183                    "Pseudo output operand '" + Dag->getArgName(i) +
184                    "' has no matching source operand.");
185    // Map the source operand to the destination operand index for each
186    // MachineInstr operand.
187    for (unsigned I = 0, E = Insn.Operands[i].MINumOperands; I != E; ++I)
188      OperandMap[Insn.Operands[i].MIOperandNo + I].Data.Operand =
189        SourceOp->getValue();
190
191    DEBUG(dbgs() << "    " << SourceOp->getValue() << " ==> " << i << "\n");
192  }
193
194  Expansions.push_back(PseudoExpansion(SourceInsn, Insn, OperandMap));
195}
196
197void PseudoLoweringEmitter::emitLoweringEmitter(raw_ostream &o) {
198  // Emit file header.
199  emitSourceFileHeader("Pseudo-instruction MC lowering Source Fragment", o);
200
201  o << "bool " << Target.getName() + "AsmPrinter" << "::\n"
202    << "emitPseudoExpansionLowering(MCStreamer &OutStreamer,\n"
203    << "                            const MachineInstr *MI) {\n"
204    << "  switch (MI->getOpcode()) {\n"
205    << "    default: return false;\n";
206  for (unsigned i = 0, e = Expansions.size(); i != e; ++i) {
207    PseudoExpansion &Expansion = Expansions[i];
208    CodeGenInstruction &Source = Expansion.Source;
209    CodeGenInstruction &Dest = Expansion.Dest;
210    o << "    case " << Source.Namespace << "::"
211      << Source.TheDef->getName() << ": {\n"
212      << "      MCInst TmpInst;\n"
213      << "      MCOperand MCOp;\n"
214      << "      TmpInst.setOpcode(" << Dest.Namespace << "::"
215      << Dest.TheDef->getName() << ");\n";
216
217    // Copy the operands from the source instruction.
218    // FIXME: Instruction operands with defaults values (predicates and cc_out
219    //        in ARM, for example shouldn't need explicit values in the
220    //        expansion DAG.
221    unsigned MIOpNo = 0;
222    for (unsigned OpNo = 0, E = Dest.Operands.size(); OpNo != E;
223         ++OpNo) {
224      o << "      // Operand: " << Dest.Operands[OpNo].Name << "\n";
225      for (unsigned i = 0, e = Dest.Operands[OpNo].MINumOperands;
226           i != e; ++i) {
227        switch (Expansion.OperandMap[MIOpNo + i].Kind) {
228        case OpData::Operand:
229          o << "      lowerOperand(MI->getOperand("
230            << Source.Operands[Expansion.OperandMap[MIOpNo].Data
231                .Operand].MIOperandNo + i
232            << "), MCOp);\n"
233            << "      TmpInst.addOperand(MCOp);\n";
234          break;
235        case OpData::Imm:
236          o << "      TmpInst.addOperand(MCOperand::CreateImm("
237            << Expansion.OperandMap[MIOpNo + i].Data.Imm << "));\n";
238          break;
239        case OpData::Reg: {
240          Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
241          o << "      TmpInst.addOperand(MCOperand::CreateReg(";
242          // "zero_reg" is special.
243          if (Reg->getName() == "zero_reg")
244            o << "0";
245          else
246            o << Reg->getValueAsString("Namespace") << "::" << Reg->getName();
247          o << "));\n";
248          break;
249        }
250        }
251      }
252      MIOpNo += Dest.Operands[OpNo].MINumOperands;
253    }
254    if (Dest.Operands.isVariadic) {
255      o << "      // variable_ops\n";
256      o << "      for (unsigned i = " << MIOpNo
257        << ", e = MI->getNumOperands(); i != e; ++i)\n"
258        << "        if (lowerOperand(MI->getOperand(i), MCOp))\n"
259        << "          TmpInst.addOperand(MCOp);\n";
260    }
261    o << "      OutStreamer.EmitInstruction(TmpInst);\n"
262      << "      break;\n"
263      << "    }\n";
264  }
265  o << "  }\n  return true;\n}\n\n";
266}
267
268void PseudoLoweringEmitter::run(raw_ostream &o) {
269  Record *ExpansionClass = Records.getClass("PseudoInstExpansion");
270  Record *InstructionClass = Records.getClass("PseudoInstExpansion");
271  assert(ExpansionClass && "PseudoInstExpansion class definition missing!");
272  assert(InstructionClass && "Instruction class definition missing!");
273
274  std::vector<Record*> Insts;
275  for (std::map<std::string, Record*>::const_iterator I =
276         Records.getDefs().begin(), E = Records.getDefs().end(); I != E; ++I) {
277    if (I->second->isSubClassOf(ExpansionClass) &&
278        I->second->isSubClassOf(InstructionClass))
279      Insts.push_back(I->second);
280  }
281
282  // Process the pseudo expansion definitions, validating them as we do so.
283  for (unsigned i = 0, e = Insts.size(); i != e; ++i)
284    evaluateExpansion(Insts[i]);
285
286  // Generate expansion code to lower the pseudo to an MCInst of the real
287  // instruction.
288  emitLoweringEmitter(o);
289}
290
291namespace llvm {
292
293void EmitPseudoLowering(RecordKeeper &RK, raw_ostream &OS) {
294  PseudoLoweringEmitter(RK).run(OS);
295}
296
297} // End llvm namespace
298