RegisterInfoEmitter.cpp revision 536ab130ec95cbb7bf30530251dafa7dfecc8471
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of a target 11// register file for a code generator. It uses instances of the Register, 12// RegisterAliases, and RegisterClass classes to gather this information. 13// 14//===----------------------------------------------------------------------===// 15 16#include "RegisterInfoEmitter.h" 17#include "CodeGenTarget.h" 18#include "CodeGenRegisters.h" 19#include "Record.h" 20#include "llvm/ADT/StringExtras.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/Support/Streams.h" 23#include <set> 24#include <algorithm> 25using namespace llvm; 26 27// runEnums - Print out enum values for all of the registers. 28void RegisterInfoEmitter::runEnums(std::ostream &OS) { 29 CodeGenTarget Target; 30 const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 31 32 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace"); 33 34 EmitSourceFileHeader("Target Register Enum Values", OS); 35 OS << "namespace llvm {\n\n"; 36 37 if (!Namespace.empty()) 38 OS << "namespace " << Namespace << " {\n"; 39 OS << " enum {\n NoRegister,\n"; 40 41 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 42 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n"; 43 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 44 OS << " };\n"; 45 if (!Namespace.empty()) 46 OS << "}\n"; 47 OS << "} // End llvm namespace \n"; 48} 49 50void RegisterInfoEmitter::runHeader(std::ostream &OS) { 51 EmitSourceFileHeader("Register Information Header Fragment", OS); 52 CodeGenTarget Target; 53 const std::string &TargetName = Target.getName(); 54 std::string ClassName = TargetName + "GenRegisterInfo"; 55 56 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; 57 OS << "#include <string>\n\n"; 58 59 OS << "namespace llvm {\n\n"; 60 61 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 62 << " explicit " << ClassName 63 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" 64 << " virtual int getDwarfRegNumFull(unsigned RegNum, " 65 << "unsigned Flavour) const;\n" 66 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" 67 << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 68 << " { return false; }\n" 69 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" 70 << "};\n\n"; 71 72 const std::vector<CodeGenRegisterClass> &RegisterClasses = 73 Target.getRegisterClasses(); 74 75 if (!RegisterClasses.empty()) { 76 OS << "namespace " << RegisterClasses[0].Namespace 77 << " { // Register classes\n"; 78 79 OS << " enum {\n"; 80 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 81 if (i) OS << ",\n"; 82 OS << " " << RegisterClasses[i].getName() << "RegClassID"; 83 OS << " = " << (i+1); 84 } 85 OS << "\n };\n\n"; 86 87 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 88 const std::string &Name = RegisterClasses[i].getName(); 89 90 // Output the register class definition. 91 OS << " struct " << Name << "Class : public TargetRegisterClass {\n" 92 << " " << Name << "Class();\n" 93 << RegisterClasses[i].MethodProtos << " };\n"; 94 95 // Output the extern for the instance. 96 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; 97 // Output the extern for the pointer to the instance (should remove). 98 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" 99 << Name << "RegClass;\n"; 100 } 101 OS << "} // end of namespace " << TargetName << "\n\n"; 102 } 103 OS << "} // End llvm namespace \n"; 104} 105 106bool isSubRegisterClass(const CodeGenRegisterClass &RC, 107 std::set<Record*> &RegSet) { 108 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 109 Record *Reg = RC.Elements[i]; 110 if (!RegSet.count(Reg)) 111 return false; 112 } 113 return true; 114} 115 116static void addSuperReg(Record *R, Record *S, 117 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs, 118 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs, 119 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) { 120 if (R == S) { 121 cerr << "Error: recursive sub-register relationship between" 122 << " register " << getQualifiedName(R) 123 << " and its sub-registers?\n"; 124 abort(); 125 } 126 if (!SuperRegs[R].insert(S).second) 127 return; 128 SubRegs[S].insert(R); 129 Aliases[R].insert(S); 130 Aliases[S].insert(R); 131 if (SuperRegs.count(S)) 132 for (std::set<Record*>::iterator I = SuperRegs[S].begin(), 133 E = SuperRegs[S].end(); I != E; ++I) 134 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases); 135} 136 137static void addSubSuperReg(Record *R, Record *S, 138 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs, 139 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs, 140 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) { 141 if (R == S) { 142 cerr << "Error: recursive sub-register relationship between" 143 << " register " << getQualifiedName(R) 144 << " and its sub-registers?\n"; 145 abort(); 146 } 147 148 if (!SubRegs[R].insert(S).second) 149 return; 150 addSuperReg(S, R, SubRegs, SuperRegs, Aliases); 151 Aliases[R].insert(S); 152 Aliases[S].insert(R); 153 if (SubRegs.count(S)) 154 for (std::set<Record*>::iterator I = SubRegs[S].begin(), 155 E = SubRegs[S].end(); I != E; ++I) 156 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); 157} 158 159class RegisterSorter { 160private: 161 std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs; 162 163public: 164 RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS) 165 : RegisterSubRegs(RS) {}; 166 167 bool operator()(Record *RegA, Record *RegB) { 168 // B is sub-register of A. 169 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB); 170 } 171}; 172 173// RegisterInfoEmitter::run - Main register file description emitter. 174// 175void RegisterInfoEmitter::run(std::ostream &OS) { 176 CodeGenTarget Target; 177 EmitSourceFileHeader("Register Information Source Fragment", OS); 178 179 OS << "namespace llvm {\n\n"; 180 181 // Start out by emitting each of the register classes... to do this, we build 182 // a set of registers which belong to a register class, this is to ensure that 183 // each register is only in a single register class. 184 // 185 const std::vector<CodeGenRegisterClass> &RegisterClasses = 186 Target.getRegisterClasses(); 187 188 // Loop over all of the register classes... emitting each one. 189 OS << "namespace { // Register classes...\n"; 190 191 // RegClassesBelongedTo - Keep track of which register classes each reg 192 // belongs to. 193 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo; 194 195 // Emit the register enum value arrays for each RegisterClass 196 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 197 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 198 199 // Give the register class a legal C name if it's anonymous. 200 std::string Name = RC.TheDef->getName(); 201 202 // Emit the register list now. 203 OS << " // " << Name << " Register Class...\n" 204 << " static const unsigned " << Name 205 << "[] = {\n "; 206 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 207 Record *Reg = RC.Elements[i]; 208 OS << getQualifiedName(Reg) << ", "; 209 210 // Keep track of which regclasses this register is in. 211 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC)); 212 } 213 OS << "\n };\n\n"; 214 } 215 216 // Emit the ValueType arrays for each RegisterClass 217 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 218 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 219 220 // Give the register class a legal C name if it's anonymous. 221 std::string Name = RC.TheDef->getName() + "VTs"; 222 223 // Emit the register list now. 224 OS << " // " << Name 225 << " Register Class Value Types...\n" 226 << " static const MVT " << Name 227 << "[] = {\n "; 228 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) 229 OS << getEnumName(RC.VTs[i]) << ", "; 230 OS << "MVT::Other\n };\n\n"; 231 } 232 OS << "} // end anonymous namespace\n\n"; 233 234 // Now that all of the structs have been emitted, emit the instances. 235 if (!RegisterClasses.empty()) { 236 OS << "namespace " << RegisterClasses[0].Namespace 237 << " { // Register class instances\n"; 238 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 239 OS << " " << RegisterClasses[i].getName() << "Class\t" 240 << RegisterClasses[i].getName() << "RegClass;\n"; 241 242 std::map<unsigned, std::set<unsigned> > SuperClassMap; 243 OS << "\n"; 244 245 // Emit the sub-classes array for each RegisterClass 246 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 247 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 248 249 // Give the register class a legal C name if it's anonymous. 250 std::string Name = RC.TheDef->getName(); 251 252 std::set<Record*> RegSet; 253 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 254 Record *Reg = RC.Elements[i]; 255 RegSet.insert(Reg); 256 } 257 258 OS << " // " << Name 259 << " Register Class sub-classes...\n" 260 << " static const TargetRegisterClass* const " 261 << Name << "Subclasses [] = {\n "; 262 263 bool Empty = true; 264 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 265 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 266 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() || 267 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet)) 268 continue; 269 270 if (!Empty) OS << ", "; 271 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 272 Empty = false; 273 274 std::map<unsigned, std::set<unsigned> >::iterator SCMI = 275 SuperClassMap.find(rc2); 276 if (SCMI == SuperClassMap.end()) { 277 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>())); 278 SCMI = SuperClassMap.find(rc2); 279 } 280 SCMI->second.insert(rc); 281 } 282 283 OS << (!Empty ? ", " : "") << "NULL"; 284 OS << "\n };\n\n"; 285 } 286 287 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 288 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 289 290 // Give the register class a legal C name if it's anonymous. 291 std::string Name = RC.TheDef->getName(); 292 293 OS << " // " << Name 294 << " Register Class super-classes...\n" 295 << " static const TargetRegisterClass* const " 296 << Name << "Superclasses [] = {\n "; 297 298 bool Empty = true; 299 std::map<unsigned, std::set<unsigned> >::iterator I = 300 SuperClassMap.find(rc); 301 if (I != SuperClassMap.end()) { 302 for (std::set<unsigned>::iterator II = I->second.begin(), 303 EE = I->second.end(); II != EE; ++II) { 304 const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 305 if (!Empty) OS << ", "; 306 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 307 Empty = false; 308 } 309 } 310 311 OS << (!Empty ? ", " : "") << "NULL"; 312 OS << "\n };\n\n"; 313 } 314 315 316 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 317 const CodeGenRegisterClass &RC = RegisterClasses[i]; 318 OS << RC.MethodBodies << "\n"; 319 OS << RC.getName() << "Class::" << RC.getName() 320 << "Class() : TargetRegisterClass(" 321 << RC.getName() + "RegClassID" << ", " 322 << RC.getName() + "VTs" << ", " 323 << RC.getName() + "Subclasses" << ", " 324 << RC.getName() + "Superclasses" << ", " 325 << RC.SpillSize/8 << ", " 326 << RC.SpillAlignment/8 << ", " 327 << RC.CopyCost << ", " 328 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() 329 << ") {}\n"; 330 } 331 332 OS << "}\n"; 333 } 334 335 OS << "\nnamespace {\n"; 336 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 337 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 338 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef) 339 << "RegClass,\n"; 340 OS << " };\n"; 341 342 // Emit register sub-registers / super-registers, aliases... 343 std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs; 344 std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs; 345 std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases; 346 std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors; 347 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; 348 DwarfRegNumsMapTy DwarfRegNums; 349 350 const std::vector<CodeGenRegister> &Regs = Target.getRegisters(); 351 352 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 353 Record *R = Regs[i].TheDef; 354 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases"); 355 // Add information that R aliases all of the elements in the list... and 356 // that everything in the list aliases R. 357 for (unsigned j = 0, e = LI.size(); j != e; ++j) { 358 Record *Reg = LI[j]; 359 if (RegisterAliases[R].count(Reg)) 360 cerr << "Warning: register alias between " << getQualifiedName(R) 361 << " and " << getQualifiedName(Reg) 362 << " specified multiple times!\n"; 363 RegisterAliases[R].insert(Reg); 364 365 if (RegisterAliases[Reg].count(R)) 366 cerr << "Warning: register alias between " << getQualifiedName(R) 367 << " and " << getQualifiedName(Reg) 368 << " specified multiple times!\n"; 369 RegisterAliases[Reg].insert(R); 370 } 371 } 372 373 // Process sub-register sets. 374 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 375 Record *R = Regs[i].TheDef; 376 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs"); 377 // Process sub-register set and add aliases information. 378 for (unsigned j = 0, e = LI.size(); j != e; ++j) { 379 Record *SubReg = LI[j]; 380 if (RegisterSubRegs[R].count(SubReg)) 381 cerr << "Warning: register " << getQualifiedName(SubReg) 382 << " specified as a sub-register of " << getQualifiedName(R) 383 << " multiple times!\n"; 384 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs, 385 RegisterAliases); 386 } 387 } 388 389 // Print the SubregHashTable, a simple quadratically probed 390 // hash table for determining if a register is a subregister 391 // of another register. 392 unsigned NumSubRegs = 0; 393 std::map<Record*, unsigned> RegNo; 394 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 395 RegNo[Regs[i].TheDef] = i; 396 NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); 397 } 398 399 unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); 400 unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; 401 std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); 402 403 unsigned hashMisses = 0; 404 405 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 406 Record* R = Regs[i].TheDef; 407 for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(), 408 E = RegisterSubRegs[R].end(); I != E; ++I) { 409 Record* RJ = *I; 410 // We have to increase the indices of both registers by one when 411 // computing the hash because, in the generated code, there 412 // will be an extra empty slot at register 0. 413 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1); 414 unsigned ProbeAmt = 2; 415 while (SubregHashTable[index*2] != ~0U && 416 SubregHashTable[index*2+1] != ~0U) { 417 index = (index + ProbeAmt) & (SubregHashTableSize-1); 418 ProbeAmt += 2; 419 420 hashMisses++; 421 } 422 423 SubregHashTable[index*2] = i; 424 SubregHashTable[index*2+1] = RegNo[RJ]; 425 } 426 } 427 428 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; 429 430 if (SubregHashTableSize) { 431 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); 432 433 OS << " const unsigned SubregHashTable[] = { "; 434 for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { 435 if (i != 0) 436 // Insert spaces for nice formatting. 437 OS << " "; 438 439 if (SubregHashTable[2*i] != ~0U) { 440 OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " 441 << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; 442 } else { 443 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; 444 } 445 } 446 447 unsigned Idx = SubregHashTableSize*2-2; 448 if (SubregHashTable[Idx] != ~0U) { 449 OS << " " 450 << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", " 451 << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n"; 452 } else { 453 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; 454 } 455 456 OS << " const unsigned SubregHashTableSize = " 457 << SubregHashTableSize << ";\n"; 458 } else { 459 OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" 460 << " const unsigned SubregHashTableSize = 1;\n"; 461 } 462 463 delete [] SubregHashTable; 464 465 if (!RegisterAliases.empty()) 466 OS << "\n\n // Register Alias Sets...\n"; 467 468 // Emit the empty alias list 469 OS << " const unsigned Empty_AliasSet[] = { 0 };\n"; 470 // Loop over all of the registers which have aliases, emitting the alias list 471 // to memory. 472 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator 473 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { 474 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { "; 475 for (std::set<Record*>::iterator ASI = I->second.begin(), 476 E = I->second.end(); ASI != E; ++ASI) 477 OS << getQualifiedName(*ASI) << ", "; 478 OS << "0 };\n"; 479 } 480 481 if (!RegisterSubRegs.empty()) 482 OS << "\n\n // Register Sub-registers Sets...\n"; 483 484 // Emit the empty sub-registers list 485 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; 486 // Loop over all of the registers which have sub-registers, emitting the 487 // sub-registers list to memory. 488 for (std::map<Record*, std::set<Record*>, LessRecord>::iterator 489 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { 490 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; 491 std::vector<Record*> SubRegsVector; 492 for (std::set<Record*>::iterator ASI = I->second.begin(), 493 E = I->second.end(); ASI != E; ++ASI) 494 SubRegsVector.push_back(*ASI); 495 RegisterSorter RS(RegisterSubRegs); 496 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS); 497 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i) 498 OS << getQualifiedName(SubRegsVector[i]) << ", "; 499 OS << "0 };\n"; 500 } 501 502 if (!RegisterSuperRegs.empty()) 503 OS << "\n\n // Register Super-registers Sets...\n"; 504 505 // Emit the empty super-registers list 506 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; 507 // Loop over all of the registers which have super-registers, emitting the 508 // super-registers list to memory. 509 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator 510 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { 511 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; 512 513 std::vector<Record*> SuperRegsVector; 514 for (std::set<Record*>::iterator ASI = I->second.begin(), 515 E = I->second.end(); ASI != E; ++ASI) 516 SuperRegsVector.push_back(*ASI); 517 RegisterSorter RS(RegisterSubRegs); 518 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS); 519 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i) 520 OS << getQualifiedName(SuperRegsVector[i]) << ", "; 521 OS << "0 };\n"; 522 } 523 524 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; 525 OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n"; 526 527 // Now that register alias and sub-registers sets have been emitted, emit the 528 // register descriptors now. 529 const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 530 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 531 const CodeGenRegister &Reg = Registers[i]; 532 OS << " { \""; 533 if (!Reg.TheDef->getValueAsString("AsmName").empty()) 534 OS << Reg.TheDef->getValueAsString("AsmName"); 535 else 536 OS << Reg.getName(); 537 OS << "\",\t\""; 538 OS << Reg.getName() << "\",\t"; 539 if (RegisterAliases.count(Reg.TheDef)) 540 OS << Reg.getName() << "_AliasSet,\t"; 541 else 542 OS << "Empty_AliasSet,\t"; 543 if (RegisterSubRegs.count(Reg.TheDef)) 544 OS << Reg.getName() << "_SubRegsSet,\t"; 545 else 546 OS << "Empty_SubRegsSet,\t"; 547 if (RegisterSuperRegs.count(Reg.TheDef)) 548 OS << Reg.getName() << "_SuperRegsSet },\n"; 549 else 550 OS << "Empty_SuperRegsSet },\n"; 551 } 552 OS << " };\n"; // End of register descriptors... 553 OS << "}\n\n"; // End of anonymous namespace... 554 555 std::string ClassName = Target.getName() + "GenRegisterInfo"; 556 557 // Calculate the mapping of subregister+index pairs to physical registers. 558 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet"); 559 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) { 560 int subRegIndex = SubRegs[i]->getValueAsInt("index"); 561 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From"); 562 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To"); 563 564 if (From.size() != To.size()) { 565 cerr << "Error: register list and sub-register list not of equal length" 566 << " in SubRegSet\n"; 567 exit(1); 568 } 569 570 // For each entry in from/to vectors, insert the to register at index 571 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii) 572 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii])); 573 } 574 575 // Emit the subregister + index mapping function based on the information 576 // calculated above. 577 OS << "unsigned " << ClassName 578 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" 579 << " switch (RegNo) {\n" 580 << " default:\n return 0;\n"; 581 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator 582 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) { 583 OS << " case " << getQualifiedName(I->first) << ":\n"; 584 OS << " switch (Index) {\n"; 585 OS << " default: return 0;\n"; 586 for (unsigned i = 0, e = I->second.size(); i != e; ++i) 587 OS << " case " << (I->second)[i].first << ": return " 588 << getQualifiedName((I->second)[i].second) << ";\n"; 589 OS << " };\n" << " break;\n"; 590 } 591 OS << " };\n"; 592 OS << " return 0;\n"; 593 OS << "}\n\n"; 594 595 // Emit the constructor of the class... 596 OS << ClassName << "::" << ClassName 597 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" 598 << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1 599 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " 600 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n" 601 << " SubregHashTable, SubregHashTableSize) {\n" 602 << "}\n\n"; 603 604 // Collect all information about dwarf register numbers 605 606 // First, just pull all provided information to the map 607 unsigned maxLength = 0; 608 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 609 Record *Reg = Registers[i].TheDef; 610 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 611 maxLength = std::max((size_t)maxLength, RegNums.size()); 612 if (DwarfRegNums.count(Reg)) 613 cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg) 614 << "specified multiple times\n"; 615 DwarfRegNums[Reg] = RegNums; 616 } 617 618 // Now we know maximal length of number list. Append -1's, where needed 619 for (DwarfRegNumsMapTy::iterator 620 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 621 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 622 I->second.push_back(-1); 623 624 // Emit information about the dwarf register numbers. 625 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, " 626 << "unsigned Flavour) const {\n" 627 << " switch (Flavour) {\n" 628 << " default:\n" 629 << " assert(0 && \"Unknown DWARF flavour\");\n" 630 << " return -1;\n"; 631 632 for (unsigned i = 0, e = maxLength; i != e; ++i) { 633 OS << " case " << i << ":\n" 634 << " switch (RegNum) {\n" 635 << " default:\n" 636 << " assert(0 && \"Invalid RegNum\");\n" 637 << " return -1;\n"; 638 639 // Sort by name to get a stable order. 640 641 642 for (DwarfRegNumsMapTy::iterator 643 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 644 int RegNo = I->second[i]; 645 if (RegNo != -2) 646 OS << " case " << getQualifiedName(I->first) << ":\n" 647 << " return " << RegNo << ";\n"; 648 else 649 OS << " case " << getQualifiedName(I->first) << ":\n" 650 << " assert(0 && \"Invalid register for this mode\");\n" 651 << " return -1;\n"; 652 } 653 OS << " };\n"; 654 } 655 656 OS << " };\n}\n\n"; 657 658 OS << "} // End llvm namespace \n"; 659} 660