RegisterInfoEmitter.cpp revision 5de728cfe1a922ac9b13546dca94526b2fa693b6
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of a target 11// register file for a code generator. It uses instances of the Register, 12// RegisterAliases, and RegisterClass classes to gather this information. 13// 14//===----------------------------------------------------------------------===// 15 16#include "RegisterInfoEmitter.h" 17#include "CodeGenTarget.h" 18#include "CodeGenRegisters.h" 19#include "Record.h" 20#include "llvm/ADT/BitVector.h" 21#include "llvm/ADT/StringExtras.h" 22#include "llvm/ADT/STLExtras.h" 23#include "llvm/Support/Format.h" 24#include <algorithm> 25#include <set> 26using namespace llvm; 27 28// runEnums - Print out enum values for all of the registers. 29void 30RegisterInfoEmitter::runEnums(raw_ostream &OS, 31 CodeGenTarget &Target, CodeGenRegBank &Bank) { 32 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters(); 33 34 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); 35 36 EmitSourceFileHeader("Target Register Enum Values", OS); 37 38 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 39 OS << "#undef GET_REGINFO_ENUM\n"; 40 41 OS << "namespace llvm {\n\n"; 42 43 OS << "class MCRegisterClass;\n" 44 << "extern MCRegisterClass " << Namespace << "MCRegisterClasses[];\n\n"; 45 46 if (!Namespace.empty()) 47 OS << "namespace " << Namespace << " {\n"; 48 OS << "enum {\n NoRegister,\n"; 49 50 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 51 OS << " " << Registers[i]->getName() << " = " << 52 Registers[i]->EnumValue << ",\n"; 53 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue && 54 "Register enum value mismatch!"); 55 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 56 OS << "};\n"; 57 if (!Namespace.empty()) 58 OS << "}\n"; 59 60 const std::vector<CodeGenRegisterClass> &RegisterClasses = 61 Target.getRegisterClasses(); 62 if (!RegisterClasses.empty()) { 63 OS << "\n// Register classes\n"; 64 if (!Namespace.empty()) 65 OS << "namespace " << Namespace << " {\n"; 66 OS << "enum {\n"; 67 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 68 if (i) OS << ",\n"; 69 OS << " " << RegisterClasses[i].getName() << "RegClassID"; 70 OS << " = " << i; 71 } 72 OS << "\n };\n"; 73 if (!Namespace.empty()) 74 OS << "}\n"; 75 } 76 77 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices(); 78 // If the only definition is the default NoRegAltName, we don't need to 79 // emit anything. 80 if (RegAltNameIndices.size() > 1) { 81 OS << "\n// Register alternate name indices\n"; 82 if (!Namespace.empty()) 83 OS << "namespace " << Namespace << " {\n"; 84 OS << "enum {\n"; 85 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 86 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 87 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 88 OS << "};\n"; 89 if (!Namespace.empty()) 90 OS << "}\n"; 91 } 92 93 94 OS << "} // End llvm namespace \n"; 95 OS << "#endif // GET_REGINFO_ENUM\n\n"; 96} 97 98void 99RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS, 100 const std::vector<CodeGenRegister*> &Regs, 101 bool isCtor) { 102 103 // Collect all information about dwarf register numbers 104 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; 105 DwarfRegNumsMapTy DwarfRegNums; 106 107 // First, just pull all provided information to the map 108 unsigned maxLength = 0; 109 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 110 Record *Reg = Regs[i]->TheDef; 111 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 112 maxLength = std::max((size_t)maxLength, RegNums.size()); 113 if (DwarfRegNums.count(Reg)) 114 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg) 115 << "specified multiple times\n"; 116 DwarfRegNums[Reg] = RegNums; 117 } 118 119 if (!maxLength) 120 return; 121 122 // Now we know maximal length of number list. Append -1's, where needed 123 for (DwarfRegNumsMapTy::iterator 124 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 125 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 126 I->second.push_back(-1); 127 128 // Emit reverse information about the dwarf register numbers. 129 for (unsigned j = 0; j < 2; ++j) { 130 OS << " switch ("; 131 if (j == 0) 132 OS << "DwarfFlavour"; 133 else 134 OS << "EHFlavour"; 135 OS << ") {\n" 136 << " default:\n" 137 << " assert(0 && \"Unknown DWARF flavour\");\n" 138 << " break;\n"; 139 140 for (unsigned i = 0, e = maxLength; i != e; ++i) { 141 OS << " case " << i << ":\n"; 142 for (DwarfRegNumsMapTy::iterator 143 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 144 int DwarfRegNo = I->second[i]; 145 if (DwarfRegNo < 0) 146 continue; 147 OS << " "; 148 if (!isCtor) 149 OS << "RI->"; 150 OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", " 151 << getQualifiedName(I->first) << ", "; 152 if (j == 0) 153 OS << "false"; 154 else 155 OS << "true"; 156 OS << " );\n"; 157 } 158 OS << " break;\n"; 159 } 160 OS << " }\n"; 161 } 162 163 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 164 Record *Reg = Regs[i]->TheDef; 165 const RecordVal *V = Reg->getValue("DwarfAlias"); 166 if (!V || !V->getValue()) 167 continue; 168 169 DefInit *DI = dynamic_cast<DefInit*>(V->getValue()); 170 Record *Alias = DI->getDef(); 171 DwarfRegNums[Reg] = DwarfRegNums[Alias]; 172 } 173 174 // Emit information about the dwarf register numbers. 175 for (unsigned j = 0; j < 2; ++j) { 176 OS << " switch ("; 177 if (j == 0) 178 OS << "DwarfFlavour"; 179 else 180 OS << "EHFlavour"; 181 OS << ") {\n" 182 << " default:\n" 183 << " assert(0 && \"Unknown DWARF flavour\");\n" 184 << " break;\n"; 185 186 for (unsigned i = 0, e = maxLength; i != e; ++i) { 187 OS << " case " << i << ":\n"; 188 // Sort by name to get a stable order. 189 for (DwarfRegNumsMapTy::iterator 190 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 191 int RegNo = I->second[i]; 192 OS << " "; 193 if (!isCtor) 194 OS << "RI->"; 195 OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", " 196 << RegNo << ", "; 197 if (j == 0) 198 OS << "false"; 199 else 200 OS << "true"; 201 OS << " );\n"; 202 } 203 OS << " break;\n"; 204 } 205 OS << " }\n"; 206 } 207} 208 209// Helper to emit a set of bits into a constant byte array. 210class BitVectorEmitter { 211 BitVector Values; 212public: 213 void add(unsigned v) { 214 if (v >= Values.size()) 215 Values.resize(((v/8)+1)*8); // Round up to the next byte. 216 Values[v] = true; 217 } 218 219 void print(raw_ostream &OS) { 220 for (unsigned i = 0, e = Values.size() / 8; i != e; ++i) { 221 unsigned char out = 0; 222 for (unsigned j = 0; j != 8; ++j) 223 if (Values[i * 8 + j]) 224 out |= 1 << j; 225 OS << format("0x%02x, ", out); 226 } 227 } 228}; 229 230// 231// runMCDesc - Print out MC register descriptions. 232// 233void 234RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, 235 CodeGenRegBank &RegBank) { 236 EmitSourceFileHeader("MC Register Information", OS); 237 238 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 239 OS << "#undef GET_REGINFO_MC_DESC\n"; 240 241 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps; 242 RegBank.computeOverlaps(Overlaps); 243 244 OS << "namespace llvm {\n\n"; 245 246 const std::string &TargetName = Target.getName(); 247 std::string ClassName = TargetName + "GenMCRegisterInfo"; 248 OS << "struct " << ClassName << " : public MCRegisterInfo {\n" 249 << " explicit " << ClassName << "(const MCRegisterDesc *D);\n"; 250 OS << "};\n"; 251 252 OS << "\nnamespace {\n"; 253 254 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 255 256 // Emit an overlap list for all registers. 257 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 258 const CodeGenRegister *Reg = Regs[i]; 259 const CodeGenRegister::Set &O = Overlaps[Reg]; 260 // Move Reg to the front so TRI::getAliasSet can share the list. 261 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { " 262 << getQualifiedName(Reg->TheDef) << ", "; 263 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); 264 I != E; ++I) 265 if (*I != Reg) 266 OS << getQualifiedName((*I)->TheDef) << ", "; 267 OS << "0 };\n"; 268 } 269 270 // Emit the empty sub-registers list 271 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; 272 // Loop over all of the registers which have sub-registers, emitting the 273 // sub-registers list to memory. 274 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 275 const CodeGenRegister &Reg = *Regs[i]; 276 if (Reg.getSubRegs().empty()) 277 continue; 278 // getSubRegs() orders by SubRegIndex. We want a topological order. 279 SetVector<CodeGenRegister*> SR; 280 Reg.addSubRegsPreOrder(SR); 281 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { "; 282 for (unsigned j = 0, je = SR.size(); j != je; ++j) 283 OS << getQualifiedName(SR[j]->TheDef) << ", "; 284 OS << "0 };\n"; 285 } 286 287 // Emit the empty super-registers list 288 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; 289 // Loop over all of the registers which have super-registers, emitting the 290 // super-registers list to memory. 291 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 292 const CodeGenRegister &Reg = *Regs[i]; 293 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs(); 294 if (SR.empty()) 295 continue; 296 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { "; 297 for (unsigned j = 0, je = SR.size(); j != je; ++j) 298 OS << getQualifiedName(SR[j]->TheDef) << ", "; 299 OS << "0 };\n"; 300 } 301 OS << "}\n"; // End of anonymous namespace... 302 303 OS << "\nMCRegisterDesc " << TargetName 304 << "RegDesc[] = { // Descriptors\n"; 305 OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; 306 307 // Now that register alias and sub-registers sets have been emitted, emit the 308 // register descriptors now. 309 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 310 const CodeGenRegister &Reg = *Regs[i]; 311 OS << " { \""; 312 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; 313 if (!Reg.getSubRegs().empty()) 314 OS << Reg.getName() << "_SubRegsSet,\t"; 315 else 316 OS << "Empty_SubRegsSet,\t"; 317 if (!Reg.getSuperRegs().empty()) 318 OS << Reg.getName() << "_SuperRegsSet"; 319 else 320 OS << "Empty_SuperRegsSet"; 321 OS << " },\n"; 322 } 323 OS << "};\n\n"; // End of register descriptors... 324 325 const std::vector<CodeGenRegisterClass> &RegisterClasses = 326 Target.getRegisterClasses(); 327 328 // Loop over all of the register classes... emitting each one. 329 OS << "namespace { // Register classes...\n"; 330 331 // Emit the register enum value arrays for each RegisterClass 332 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 333 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 334 ArrayRef<Record*> Order = RC.getOrder(); 335 336 // Give the register class a legal C name if it's anonymous. 337 std::string Name = RC.getName(); 338 339 // Emit the register list now. 340 OS << " // " << Name << " Register Class...\n" 341 << " static const unsigned " << Name 342 << "[] = {\n "; 343 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 344 Record *Reg = Order[i]; 345 OS << getQualifiedName(Reg) << ", "; 346 } 347 OS << "\n };\n\n"; 348 349 OS << " // " << Name << " Bit set.\n" 350 << " static const unsigned char " << Name 351 << "Bits[] = {\n "; 352 BitVectorEmitter BVE; 353 for (unsigned i = 0, e = Order.size(); i != e; ++i) { 354 Record *Reg = Order[i]; 355 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue); 356 } 357 BVE.print(OS); 358 OS << "\n };\n\n"; 359 360 } 361 OS << "}\n\n"; 362 363 OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n"; 364 365 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 366 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 367 OS << " MCRegisterClass("; 368 if (!RC.Namespace.empty()) 369 OS << RC.Namespace << "::"; 370 OS << RC.getName() + "RegClassID" << ", " 371 << '\"' << RC.getName() << "\", " 372 << RC.SpillSize/8 << ", " 373 << RC.SpillAlignment/8 << ", " 374 << RC.CopyCost << ", " 375 << RC.Allocatable << ", " 376 << RC.getName() << ", " << RC.getName() << " + " 377 << RC.getOrder().size() << ", " 378 << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)" 379 << "),\n"; 380 } 381 382 OS << "};\n\n"; 383 384 // MCRegisterInfo initialization routine. 385 OS << "static inline void Init" << TargetName 386 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 387 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n"; 388 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 389 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, " 390 << RegisterClasses.size() << ");\n\n"; 391 392 EmitRegMapping(OS, Regs, false); 393 394 OS << "}\n\n"; 395 396 397 OS << "} // End llvm namespace \n"; 398 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 399} 400 401void 402RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, 403 CodeGenRegBank &RegBank) { 404 EmitSourceFileHeader("Register Information Header Fragment", OS); 405 406 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 407 OS << "#undef GET_REGINFO_HEADER\n"; 408 409 const std::string &TargetName = Target.getName(); 410 std::string ClassName = TargetName + "GenRegisterInfo"; 411 412 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; 413 OS << "#include <string>\n\n"; 414 415 OS << "namespace llvm {\n\n"; 416 417 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 418 << " explicit " << ClassName 419 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n" 420 << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 421 << " { return false; }\n" 422 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" 423 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n" 424 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" 425 << "};\n\n"; 426 427 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices(); 428 if (!SubRegIndices.empty()) { 429 OS << "\n// Subregister indices\n"; 430 std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace"); 431 if (!Namespace.empty()) 432 OS << "namespace " << Namespace << " {\n"; 433 OS << "enum {\n NoSubRegister,\n"; 434 for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i) 435 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; 436 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; 437 OS << "};\n"; 438 if (!Namespace.empty()) 439 OS << "}\n"; 440 } 441 442 const std::vector<CodeGenRegisterClass> &RegisterClasses = 443 Target.getRegisterClasses(); 444 445 if (!RegisterClasses.empty()) { 446 OS << "namespace " << RegisterClasses[0].Namespace 447 << " { // Register classes\n"; 448 449 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 450 const CodeGenRegisterClass &RC = RegisterClasses[i]; 451 const std::string &Name = RC.getName(); 452 453 // Output the register class definition. 454 OS << " struct " << Name << "Class : public TargetRegisterClass {\n" 455 << " " << Name << "Class();\n"; 456 if (!RC.AltOrderSelect.empty()) 457 OS << " ArrayRef<unsigned> " 458 "getRawAllocationOrder(const MachineFunction&) const;\n"; 459 OS << " };\n"; 460 461 // Output the extern for the instance. 462 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; 463 // Output the extern for the pointer to the instance (should remove). 464 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" 465 << Name << "RegClass;\n"; 466 } 467 OS << "} // end of namespace " << TargetName << "\n\n"; 468 } 469 OS << "} // End llvm namespace \n"; 470 OS << "#endif // GET_REGINFO_HEADER\n\n"; 471} 472 473// 474// runTargetDesc - Output the target register and register file descriptions. 475// 476void 477RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, 478 CodeGenRegBank &RegBank){ 479 EmitSourceFileHeader("Target Register and Register Classes Information", OS); 480 481 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 482 OS << "#undef GET_REGINFO_TARGET_DESC\n"; 483 484 OS << "namespace llvm {\n\n"; 485 486 // Get access to MCRegisterClass data. 487 OS << "extern MCRegisterClass " << Target.getName() 488 << "MCRegisterClasses[];\n"; 489 490 // Start out by emitting each of the register classes. 491 const std::vector<CodeGenRegisterClass> &RegisterClasses = 492 Target.getRegisterClasses(); 493 494 // Collect all registers belonging to any allocatable class. 495 std::set<Record*> AllocatableRegs; 496 497 // Collect allocatable registers. 498 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 499 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 500 ArrayRef<Record*> Order = RC.getOrder(); 501 502 if (RC.Allocatable) 503 AllocatableRegs.insert(Order.begin(), Order.end()); 504 } 505 506 OS << "namespace { // Register classes...\n"; 507 508 // Emit the ValueType arrays for each RegisterClass 509 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 510 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 511 512 // Give the register class a legal C name if it's anonymous. 513 std::string Name = RC.getName() + "VTs"; 514 515 // Emit the register list now. 516 OS << " // " << Name 517 << " Register Class Value Types...\n" 518 << " static const EVT " << Name 519 << "[] = {\n "; 520 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) 521 OS << getEnumName(RC.VTs[i]) << ", "; 522 OS << "MVT::Other\n };\n\n"; 523 } 524 OS << "} // end anonymous namespace\n\n"; 525 526 // Now that all of the structs have been emitted, emit the instances. 527 if (!RegisterClasses.empty()) { 528 OS << "namespace " << RegisterClasses[0].Namespace 529 << " { // Register class instances\n"; 530 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 531 OS << " " << RegisterClasses[i].getName() << "Class\t" 532 << RegisterClasses[i].getName() << "RegClass;\n"; 533 534 std::map<unsigned, std::set<unsigned> > SuperClassMap; 535 std::map<unsigned, std::set<unsigned> > SuperRegClassMap; 536 OS << "\n"; 537 538 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size(); 539 540 if (NumSubRegIndices) { 541 // Emit the sub-register classes for each RegisterClass 542 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 543 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 544 std::vector<Record*> SRC(NumSubRegIndices); 545 for (DenseMap<Record*,Record*>::const_iterator 546 i = RC.SubRegClasses.begin(), 547 e = RC.SubRegClasses.end(); i != e; ++i) { 548 // Build SRC array. 549 unsigned idx = RegBank.getSubRegIndexNo(i->first); 550 SRC.at(idx-1) = i->second; 551 552 // Find the register class number of i->second for SuperRegClassMap. 553 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 554 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 555 if (RC2.TheDef == i->second) { 556 SuperRegClassMap[rc2].insert(rc); 557 break; 558 } 559 } 560 } 561 562 // Give the register class a legal C name if it's anonymous. 563 std::string Name = RC.TheDef->getName(); 564 565 OS << " // " << Name 566 << " Sub-register Classes...\n" 567 << " static const TargetRegisterClass* const " 568 << Name << "SubRegClasses[] = {\n "; 569 570 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) { 571 if (idx) 572 OS << ", "; 573 if (SRC[idx]) 574 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass"; 575 else 576 OS << "0"; 577 } 578 OS << "\n };\n\n"; 579 } 580 581 // Emit the super-register classes for each RegisterClass 582 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 583 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 584 585 // Give the register class a legal C name if it's anonymous. 586 std::string Name = RC.TheDef->getName(); 587 588 OS << " // " << Name 589 << " Super-register Classes...\n" 590 << " static const TargetRegisterClass* const " 591 << Name << "SuperRegClasses[] = {\n "; 592 593 bool Empty = true; 594 std::map<unsigned, std::set<unsigned> >::iterator I = 595 SuperRegClassMap.find(rc); 596 if (I != SuperRegClassMap.end()) { 597 for (std::set<unsigned>::iterator II = I->second.begin(), 598 EE = I->second.end(); II != EE; ++II) { 599 const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 600 if (!Empty) 601 OS << ", "; 602 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 603 Empty = false; 604 } 605 } 606 607 OS << (!Empty ? ", " : "") << "NULL"; 608 OS << "\n };\n\n"; 609 } 610 } else { 611 // No subregindices in this target 612 OS << " static const TargetRegisterClass* const " 613 << "NullRegClasses[] = { NULL };\n\n"; 614 } 615 616 // Emit the sub-classes array for each RegisterClass 617 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 618 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 619 620 // Give the register class a legal C name if it's anonymous. 621 std::string Name = RC.TheDef->getName(); 622 623 OS << " // " << Name 624 << " Register Class sub-classes...\n" 625 << " static const TargetRegisterClass* const " 626 << Name << "Subclasses[] = {\n "; 627 628 bool Empty = true; 629 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 630 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 631 632 // Sub-classes are used to determine if a virtual register can be used 633 // as an instruction operand, or if it must be copied first. 634 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue; 635 636 if (!Empty) OS << ", "; 637 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 638 Empty = false; 639 640 std::map<unsigned, std::set<unsigned> >::iterator SCMI = 641 SuperClassMap.find(rc2); 642 if (SCMI == SuperClassMap.end()) { 643 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>())); 644 SCMI = SuperClassMap.find(rc2); 645 } 646 SCMI->second.insert(rc); 647 } 648 649 OS << (!Empty ? ", " : "") << "NULL"; 650 OS << "\n };\n\n"; 651 } 652 653 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 654 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 655 656 // Give the register class a legal C name if it's anonymous. 657 std::string Name = RC.TheDef->getName(); 658 659 OS << " // " << Name 660 << " Register Class super-classes...\n" 661 << " static const TargetRegisterClass* const " 662 << Name << "Superclasses[] = {\n "; 663 664 bool Empty = true; 665 std::map<unsigned, std::set<unsigned> >::iterator I = 666 SuperClassMap.find(rc); 667 if (I != SuperClassMap.end()) { 668 for (std::set<unsigned>::iterator II = I->second.begin(), 669 EE = I->second.end(); II != EE; ++II) { 670 const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 671 if (!Empty) OS << ", "; 672 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 673 Empty = false; 674 } 675 } 676 677 OS << (!Empty ? ", " : "") << "NULL"; 678 OS << "\n };\n\n"; 679 } 680 681 // Emit methods. 682 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 683 const CodeGenRegisterClass &RC = RegisterClasses[i]; 684 OS << RC.getName() << "Class::" << RC.getName() 685 << "Class() : TargetRegisterClass(&" 686 << Target.getName() << "MCRegisterClasses[" 687 << RC.getName() + "RegClassID" << "], " 688 << RC.getName() + "VTs" << ", " 689 << RC.getName() + "Subclasses" << ", " 690 << RC.getName() + "Superclasses" << ", " 691 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null")) 692 << "RegClasses, " 693 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null")) 694 << "RegClasses" 695 << ") {}\n"; 696 if (!RC.AltOrderSelect.empty()) { 697 OS << "\nstatic inline unsigned " << RC.getName() 698 << "AltOrderSelect(const MachineFunction &MF) {" 699 << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> " 700 << RC.getName() << "Class::" 701 << "getRawAllocationOrder(const MachineFunction &MF) const {\n"; 702 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { 703 ArrayRef<Record*> Elems = RC.getOrder(oi); 704 OS << " static const unsigned AltOrder" << oi << "[] = {"; 705 for (unsigned elem = 0; elem != Elems.size(); ++elem) 706 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 707 OS << " };\n"; 708 } 709 OS << " const MCRegisterClass &MCR = " << Target.getName() 710 << "MCRegisterClasses["; 711 if (!RC.Namespace.empty()) 712 OS << RC.Namespace << "::"; 713 OS << RC.getName() + "RegClassID];" 714 << " static const ArrayRef<unsigned> Order[] = {\n" 715 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; 716 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 717 OS << "),\n makeArrayRef(AltOrder" << oi; 718 OS << ")\n };\n const unsigned Select = " << RC.getName() 719 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() 720 << ");\n return Order[Select];\n}\n"; 721 } 722 } 723 724 OS << "}\n"; 725 } 726 727 OS << "\nnamespace {\n"; 728 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 729 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 730 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef) 731 << "RegClass,\n"; 732 OS << " };\n"; 733 OS << "}\n"; // End of anonymous namespace... 734 735 // Emit extra information about registers. 736 const std::string &TargetName = Target.getName(); 737 OS << "\n static const TargetRegisterInfoDesc " 738 << TargetName << "RegInfoDesc[] = " 739 << "{ // Extra Descriptors\n"; 740 OS << " { 0, 0 },\n"; 741 742 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); 743 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 744 const CodeGenRegister &Reg = *Regs[i]; 745 OS << " { "; 746 OS << Reg.CostPerUse << ", " 747 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; 748 } 749 OS << " };\n"; // End of register descriptors... 750 751 752 // Calculate the mapping of subregister+index pairs to physical registers. 753 // This will also create further anonymous indexes. 754 unsigned NamedIndices = RegBank.getNumNamedIndices(); 755 756 // Emit SubRegIndex names, skipping 0 757 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices(); 758 OS << "\n static const char *const " << TargetName 759 << "SubRegIndexTable[] = { \""; 760 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 761 OS << SubRegIndices[i]->getName(); 762 if (i+1 != e) 763 OS << "\", \""; 764 } 765 OS << "\" };\n\n"; 766 767 // Emit names of the anonymus subreg indexes. 768 if (SubRegIndices.size() > NamedIndices) { 769 OS << " enum {"; 770 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) { 771 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1; 772 if (i+1 != e) 773 OS << ','; 774 } 775 OS << "\n };\n\n"; 776 } 777 OS << "\n"; 778 779 std::string ClassName = Target.getName() + "GenRegisterInfo"; 780 781 // Emit the subregister + index mapping function based on the information 782 // calculated above. 783 OS << "unsigned " << ClassName 784 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" 785 << " switch (RegNo) {\n" 786 << " default:\n return 0;\n"; 787 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 788 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs(); 789 if (SRM.empty()) 790 continue; 791 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n"; 792 OS << " switch (Index) {\n"; 793 OS << " default: return 0;\n"; 794 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(), 795 ie = SRM.end(); ii != ie; ++ii) 796 OS << " case " << getQualifiedName(ii->first) 797 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n"; 798 OS << " };\n" << " break;\n"; 799 } 800 OS << " };\n"; 801 OS << " return 0;\n"; 802 OS << "}\n\n"; 803 804 OS << "unsigned " << ClassName 805 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n" 806 << " switch (RegNo) {\n" 807 << " default:\n return 0;\n"; 808 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 809 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs(); 810 if (SRM.empty()) 811 continue; 812 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n"; 813 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(), 814 ie = SRM.end(); ii != ie; ++ii) 815 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef) 816 << ") return " << getQualifiedName(ii->first) << ";\n"; 817 OS << " return 0;\n"; 818 } 819 OS << " };\n"; 820 OS << " return 0;\n"; 821 OS << "}\n\n"; 822 823 // Emit composeSubRegIndices 824 OS << "unsigned " << ClassName 825 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n" 826 << " switch (IdxA) {\n" 827 << " default:\n return IdxB;\n"; 828 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 829 bool Open = false; 830 for (unsigned j = 0; j != e; ++j) { 831 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i], 832 SubRegIndices[j])) { 833 if (!Open) { 834 OS << " case " << getQualifiedName(SubRegIndices[i]) 835 << ": switch(IdxB) {\n default: return IdxB;\n"; 836 Open = true; 837 } 838 OS << " case " << getQualifiedName(SubRegIndices[j]) 839 << ": return " << getQualifiedName(Comp) << ";\n"; 840 } 841 } 842 if (Open) 843 OS << " }\n"; 844 } 845 OS << " }\n}\n\n"; 846 847 // Emit the constructor of the class... 848 OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n"; 849 850 OS << ClassName << "::" << ClassName 851 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n" 852 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" 853 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" 854 << " " << TargetName << "SubRegIndexTable) {\n" 855 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " 856 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, " 857 << RegisterClasses.size() << ");\n\n"; 858 859 EmitRegMapping(OS, Regs, true); 860 861 OS << "}\n\n"; 862 863 OS << "} // End llvm namespace \n"; 864 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 865} 866 867void RegisterInfoEmitter::run(raw_ostream &OS) { 868 CodeGenTarget Target(Records); 869 CodeGenRegBank &RegBank = Target.getRegBank(); 870 RegBank.computeDerivedInfo(); 871 872 runEnums(OS, Target, RegBank); 873 runMCDesc(OS, Target, RegBank); 874 runTargetHeader(OS, Target, RegBank); 875 runTargetDesc(OS, Target, RegBank); 876} 877