RegisterInfoEmitter.cpp revision bf710cc23ed7a3cd3e114e122cf0f11a033d23b1
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend is responsible for emitting a description of a target 11// register file for a code generator. It uses instances of the Register, 12// RegisterAliases, and RegisterClass classes to gather this information. 13// 14//===----------------------------------------------------------------------===// 15 16#include "RegisterInfoEmitter.h" 17#include "CodeGenTarget.h" 18#include "CodeGenRegisters.h" 19#include "Record.h" 20#include "llvm/ADT/StringExtras.h" 21#include "llvm/ADT/STLExtras.h" 22#include "llvm/Support/Format.h" 23#include <algorithm> 24#include <set> 25using namespace llvm; 26 27// runEnums - Print out enum values for all of the registers. 28void RegisterInfoEmitter::runEnums(raw_ostream &OS) { 29 CodeGenTarget Target(Records); 30 CodeGenRegBank &Bank = Target.getRegBank(); 31 const std::vector<CodeGenRegister> &Registers = Target.getRegisters(); 32 33 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace"); 34 35 EmitSourceFileHeader("Target Register Enum Values", OS); 36 OS << "namespace llvm {\n\n"; 37 38 if (!Namespace.empty()) 39 OS << "namespace " << Namespace << " {\n"; 40 OS << "enum {\n NoRegister,\n"; 41 42 for (unsigned i = 0, e = Registers.size(); i != e; ++i) 43 OS << " " << Registers[i].getName() << " = " << 44 Registers[i].EnumValue << ",\n"; 45 assert(Registers.size() == Registers[Registers.size()-1].EnumValue && 46 "Register enum value mismatch!"); 47 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; 48 OS << "};\n"; 49 if (!Namespace.empty()) 50 OS << "}\n"; 51 52 const std::vector<Record*> &SubRegIndices = Bank.getSubRegIndices(); 53 if (!SubRegIndices.empty()) { 54 OS << "\n// Subregister indices\n"; 55 Namespace = SubRegIndices[0]->getValueAsString("Namespace"); 56 if (!Namespace.empty()) 57 OS << "namespace " << Namespace << " {\n"; 58 OS << "enum {\n NoSubRegister,\n"; 59 for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i) 60 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; 61 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; 62 OS << "};\n"; 63 if (!Namespace.empty()) 64 OS << "}\n"; 65 } 66 OS << "} // End llvm namespace \n"; 67} 68 69void RegisterInfoEmitter::runHeader(raw_ostream &OS) { 70 EmitSourceFileHeader("Register Information Header Fragment", OS); 71 CodeGenTarget Target(Records); 72 const std::string &TargetName = Target.getName(); 73 std::string ClassName = TargetName + "GenRegisterInfo"; 74 75 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; 76 OS << "#include <string>\n\n"; 77 78 OS << "namespace llvm {\n\n"; 79 80 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 81 << " explicit " << ClassName 82 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" 83 << " virtual int getDwarfRegNumFull(unsigned RegNum, " 84 << "unsigned Flavour) const;\n" 85 << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " 86 << "unsigned Flavour) const;\n" 87 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" 88 << " virtual bool needsStackRealignment(const MachineFunction &) const\n" 89 << " { return false; }\n" 90 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" 91 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n" 92 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" 93 << "};\n\n"; 94 95 const std::vector<CodeGenRegisterClass> &RegisterClasses = 96 Target.getRegisterClasses(); 97 98 if (!RegisterClasses.empty()) { 99 OS << "namespace " << RegisterClasses[0].Namespace 100 << " { // Register classes\n"; 101 102 OS << " enum {\n"; 103 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 104 if (i) OS << ",\n"; 105 OS << " " << RegisterClasses[i].getName() << "RegClassID"; 106 OS << " = " << i; 107 } 108 OS << "\n };\n\n"; 109 110 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 111 const std::string &Name = RegisterClasses[i].getName(); 112 113 // Output the register class definition. 114 OS << " struct " << Name << "Class : public TargetRegisterClass {\n" 115 << " " << Name << "Class();\n" 116 << RegisterClasses[i].MethodProtos << " };\n"; 117 118 // Output the extern for the instance. 119 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; 120 // Output the extern for the pointer to the instance (should remove). 121 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" 122 << Name << "RegClass;\n"; 123 } 124 OS << "} // end of namespace " << TargetName << "\n\n"; 125 } 126 OS << "} // End llvm namespace \n"; 127} 128 129typedef std::pair<unsigned, unsigned> UUPair; 130typedef std::vector<UUPair> UUVector; 131 132// Generate and print a quadratically probed hash table of unsigned pairs. 133// The pair (0,0) is used as a sentinel, so it cannot be a data point. 134static void generateHashTable(raw_ostream &OS, const char *Name, 135 const UUVector &Data) { 136 const UUPair Sentinel(0, 0); 137 unsigned HSize = Data.size(); 138 UUVector HT; 139 140 // Hashtable size must be a power of two. 141 HSize = 2 * NextPowerOf2(2 * HSize); 142 HT.assign(HSize, Sentinel); 143 144 // Insert all entries. 145 unsigned MaxProbes = 0; 146 for (unsigned i = 0, e = Data.size(); i != e; ++i) { 147 UUPair D = Data[i]; 148 unsigned Idx = (D.first + D.second * 37) & (HSize - 1); 149 unsigned ProbeAmt = 2; 150 while (HT[Idx] != Sentinel) { 151 Idx = (Idx + ProbeAmt) & (HSize - 1); 152 ProbeAmt += 2; 153 } 154 HT[Idx] = D; 155 MaxProbes = std::max(MaxProbes, ProbeAmt/2); 156 } 157 158 // Print the hash table. 159 OS << "\n\n // Max number of probes: " << MaxProbes 160 << "\n // Used entries: " << Data.size() 161 << "\n const unsigned " << Name << "Size = " << HSize << ';' 162 << "\n const unsigned " << Name << "[] = {\n"; 163 164 for (unsigned i = 0, e = HSize; i != e; ++i) { 165 UUPair D = HT[i]; 166 OS << format(" %3u,%3u,", D.first, D.second); 167 if (i % 8 == 7 && i + 1 != e) 168 OS << '\n'; 169 } 170 OS << "\n };\n"; 171} 172 173// 174// RegisterInfoEmitter::run - Main register file description emitter. 175// 176void RegisterInfoEmitter::run(raw_ostream &OS) { 177 CodeGenTarget Target(Records); 178 CodeGenRegBank &RegBank = Target.getRegBank(); 179 RegBank.computeDerivedInfo(); 180 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps; 181 RegBank.computeOverlaps(Overlaps); 182 183 EmitSourceFileHeader("Register Information Source Fragment", OS); 184 185 OS << "namespace llvm {\n\n"; 186 187 // Start out by emitting each of the register classes. 188 const std::vector<CodeGenRegisterClass> &RegisterClasses = 189 Target.getRegisterClasses(); 190 191 // Collect all registers belonging to any allocatable class. 192 std::set<Record*> AllocatableRegs; 193 194 // Loop over all of the register classes... emitting each one. 195 OS << "namespace { // Register classes...\n"; 196 197 // Emit the register enum value arrays for each RegisterClass 198 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 199 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 200 201 // Collect allocatable registers. 202 if (RC.Allocatable) 203 AllocatableRegs.insert(RC.Elements.begin(), RC.Elements.end()); 204 205 // Give the register class a legal C name if it's anonymous. 206 std::string Name = RC.TheDef->getName(); 207 208 // Emit the register list now. 209 OS << " // " << Name << " Register Class...\n" 210 << " static const unsigned " << Name 211 << "[] = {\n "; 212 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { 213 Record *Reg = RC.Elements[i]; 214 OS << getQualifiedName(Reg) << ", "; 215 } 216 OS << "\n };\n\n"; 217 } 218 219 // Emit the ValueType arrays for each RegisterClass 220 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 221 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 222 223 // Give the register class a legal C name if it's anonymous. 224 std::string Name = RC.TheDef->getName() + "VTs"; 225 226 // Emit the register list now. 227 OS << " // " << Name 228 << " Register Class Value Types...\n" 229 << " static const EVT " << Name 230 << "[] = {\n "; 231 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) 232 OS << getEnumName(RC.VTs[i]) << ", "; 233 OS << "MVT::Other\n };\n\n"; 234 } 235 OS << "} // end anonymous namespace\n\n"; 236 237 // Now that all of the structs have been emitted, emit the instances. 238 if (!RegisterClasses.empty()) { 239 OS << "namespace " << RegisterClasses[0].Namespace 240 << " { // Register class instances\n"; 241 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 242 OS << " " << RegisterClasses[i].getName() << "Class\t" 243 << RegisterClasses[i].getName() << "RegClass;\n"; 244 245 std::map<unsigned, std::set<unsigned> > SuperClassMap; 246 std::map<unsigned, std::set<unsigned> > SuperRegClassMap; 247 OS << "\n"; 248 249 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size(); 250 251 if (NumSubRegIndices) { 252 // Emit the sub-register classes for each RegisterClass 253 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 254 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 255 std::vector<Record*> SRC(NumSubRegIndices); 256 for (DenseMap<Record*,Record*>::const_iterator 257 i = RC.SubRegClasses.begin(), 258 e = RC.SubRegClasses.end(); i != e; ++i) { 259 // Build SRC array. 260 unsigned idx = RegBank.getSubRegIndexNo(i->first); 261 SRC.at(idx-1) = i->second; 262 263 // Find the register class number of i->second for SuperRegClassMap. 264 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 265 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 266 if (RC2.TheDef == i->second) { 267 SuperRegClassMap[rc2].insert(rc); 268 break; 269 } 270 } 271 } 272 273 // Give the register class a legal C name if it's anonymous. 274 std::string Name = RC.TheDef->getName(); 275 276 OS << " // " << Name 277 << " Sub-register Classes...\n" 278 << " static const TargetRegisterClass* const " 279 << Name << "SubRegClasses[] = {\n "; 280 281 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) { 282 if (idx) 283 OS << ", "; 284 if (SRC[idx]) 285 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass"; 286 else 287 OS << "0"; 288 } 289 OS << "\n };\n\n"; 290 } 291 292 // Emit the super-register classes for each RegisterClass 293 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 294 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 295 296 // Give the register class a legal C name if it's anonymous. 297 std::string Name = RC.TheDef->getName(); 298 299 OS << " // " << Name 300 << " Super-register Classes...\n" 301 << " static const TargetRegisterClass* const " 302 << Name << "SuperRegClasses[] = {\n "; 303 304 bool Empty = true; 305 std::map<unsigned, std::set<unsigned> >::iterator I = 306 SuperRegClassMap.find(rc); 307 if (I != SuperRegClassMap.end()) { 308 for (std::set<unsigned>::iterator II = I->second.begin(), 309 EE = I->second.end(); II != EE; ++II) { 310 const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 311 if (!Empty) 312 OS << ", "; 313 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 314 Empty = false; 315 } 316 } 317 318 OS << (!Empty ? ", " : "") << "NULL"; 319 OS << "\n };\n\n"; 320 } 321 } else { 322 // No subregindices in this target 323 OS << " static const TargetRegisterClass* const " 324 << "NullRegClasses[] = { NULL };\n\n"; 325 } 326 327 // Emit the sub-classes array for each RegisterClass 328 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 329 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 330 331 // Give the register class a legal C name if it's anonymous. 332 std::string Name = RC.TheDef->getName(); 333 334 OS << " // " << Name 335 << " Register Class sub-classes...\n" 336 << " static const TargetRegisterClass* const " 337 << Name << "Subclasses[] = {\n "; 338 339 bool Empty = true; 340 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { 341 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; 342 343 // Sub-classes are used to determine if a virtual register can be used 344 // as an instruction operand, or if it must be copied first. 345 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue; 346 347 if (!Empty) OS << ", "; 348 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 349 Empty = false; 350 351 std::map<unsigned, std::set<unsigned> >::iterator SCMI = 352 SuperClassMap.find(rc2); 353 if (SCMI == SuperClassMap.end()) { 354 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>())); 355 SCMI = SuperClassMap.find(rc2); 356 } 357 SCMI->second.insert(rc); 358 } 359 360 OS << (!Empty ? ", " : "") << "NULL"; 361 OS << "\n };\n\n"; 362 } 363 364 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { 365 const CodeGenRegisterClass &RC = RegisterClasses[rc]; 366 367 // Give the register class a legal C name if it's anonymous. 368 std::string Name = RC.TheDef->getName(); 369 370 OS << " // " << Name 371 << " Register Class super-classes...\n" 372 << " static const TargetRegisterClass* const " 373 << Name << "Superclasses[] = {\n "; 374 375 bool Empty = true; 376 std::map<unsigned, std::set<unsigned> >::iterator I = 377 SuperClassMap.find(rc); 378 if (I != SuperClassMap.end()) { 379 for (std::set<unsigned>::iterator II = I->second.begin(), 380 EE = I->second.end(); II != EE; ++II) { 381 const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; 382 if (!Empty) OS << ", "; 383 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; 384 Empty = false; 385 } 386 } 387 388 OS << (!Empty ? ", " : "") << "NULL"; 389 OS << "\n };\n\n"; 390 } 391 392 393 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { 394 const CodeGenRegisterClass &RC = RegisterClasses[i]; 395 OS << RC.MethodBodies << "\n"; 396 OS << RC.getName() << "Class::" << RC.getName() 397 << "Class() : TargetRegisterClass(" 398 << RC.getName() + "RegClassID" << ", " 399 << '\"' << RC.getName() << "\", " 400 << RC.getName() + "VTs" << ", " 401 << RC.getName() + "Subclasses" << ", " 402 << RC.getName() + "Superclasses" << ", " 403 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null")) 404 << "RegClasses, " 405 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null")) 406 << "RegClasses, " 407 << RC.SpillSize/8 << ", " 408 << RC.SpillAlignment/8 << ", " 409 << RC.CopyCost << ", " 410 << RC.Allocatable << ", " 411 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() 412 << ") {}\n"; 413 } 414 415 OS << "}\n"; 416 } 417 418 OS << "\nnamespace {\n"; 419 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; 420 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) 421 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef) 422 << "RegClass,\n"; 423 OS << " };\n"; 424 425 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; 426 DwarfRegNumsMapTy DwarfRegNums; 427 const std::vector<CodeGenRegister> &Regs = Target.getRegisters(); 428 429 // Print the SubregHashTable, a simple quadratically probed 430 // hash table for determining if a register is a subregister 431 // of another register. 432 UUVector HTData; 433 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 434 unsigned RegNo = Regs[i].EnumValue; 435 const CodeGenRegister::SuperRegList &SR = Regs[i].getSuperRegs(); 436 for (CodeGenRegister::SuperRegList::const_iterator I = SR.begin(), 437 E = SR.end(); I != E; ++I) 438 HTData.push_back(UUPair((*I)->EnumValue, RegNo)); 439 } 440 generateHashTable(OS, "SubregHashTable", HTData); 441 442 // Print the AliasHashTable, a simple quadratically probed 443 // hash table for determining if a register aliases another register. 444 HTData.clear(); 445 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 446 unsigned RegNo = Regs[i].EnumValue; 447 const CodeGenRegister::Set &O = Overlaps[&Regs[i]]; 448 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); 449 I != E; ++I) 450 if (*I != &Regs[i]) 451 HTData.push_back(UUPair(RegNo, (*I)->EnumValue)); 452 } 453 generateHashTable(OS, "AliasesHashTable", HTData); 454 455 // Emit an overlap list for all registers. 456 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 457 const CodeGenRegister *Reg = &Regs[i]; 458 const CodeGenRegister::Set &O = Overlaps[Reg]; 459 // Move Reg to the front so TRI::getAliasSet can share the list. 460 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { " 461 << getQualifiedName(Reg->TheDef) << ", "; 462 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); 463 I != E; ++I) 464 if (*I != Reg) 465 OS << getQualifiedName((*I)->TheDef) << ", "; 466 OS << "0 };\n"; 467 } 468 469 // Emit the empty sub-registers list 470 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; 471 // Loop over all of the registers which have sub-registers, emitting the 472 // sub-registers list to memory. 473 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 474 const CodeGenRegister &Reg = Regs[i]; 475 if (Reg.getSubRegs().empty()) 476 continue; 477 // getSubRegs() orders by SubRegIndex. We want a topological order. 478 SetVector<CodeGenRegister*> SR; 479 Reg.addSubRegsPreOrder(SR); 480 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { "; 481 for (unsigned j = 0, je = SR.size(); j != je; ++j) 482 OS << getQualifiedName(SR[j]->TheDef) << ", "; 483 OS << "0 };\n"; 484 } 485 486 // Emit the empty super-registers list 487 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; 488 // Loop over all of the registers which have super-registers, emitting the 489 // super-registers list to memory. 490 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 491 const CodeGenRegister &Reg = Regs[i]; 492 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs(); 493 if (SR.empty()) 494 continue; 495 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { "; 496 for (unsigned j = 0, je = SR.size(); j != je; ++j) 497 OS << getQualifiedName(SR[j]->TheDef) << ", "; 498 OS << "0 };\n"; 499 } 500 501 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; 502 OS << " { \"NOREG\",\t0,\t0,\t0,\t0,\t0 },\n"; 503 504 // Now that register alias and sub-registers sets have been emitted, emit the 505 // register descriptors now. 506 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 507 const CodeGenRegister &Reg = Regs[i]; 508 OS << " { \""; 509 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; 510 if (!Reg.getSubRegs().empty()) 511 OS << Reg.getName() << "_SubRegsSet,\t"; 512 else 513 OS << "Empty_SubRegsSet,\t"; 514 if (!Reg.getSuperRegs().empty()) 515 OS << Reg.getName() << "_SuperRegsSet,\t"; 516 else 517 OS << "Empty_SuperRegsSet,\t"; 518 OS << Reg.CostPerUse << ",\t" 519 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; 520 } 521 OS << " };\n"; // End of register descriptors... 522 523 // Calculate the mapping of subregister+index pairs to physical registers. 524 // This will also create further anonymous indexes. 525 unsigned NamedIndices = RegBank.getNumNamedIndices(); 526 527 // Emit SubRegIndex names, skipping 0 528 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices(); 529 OS << "\n const char *const SubRegIndexTable[] = { \""; 530 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 531 OS << SubRegIndices[i]->getName(); 532 if (i+1 != e) 533 OS << "\", \""; 534 } 535 OS << "\" };\n\n"; 536 537 // Emit names of the anonymus subreg indexes. 538 if (SubRegIndices.size() > NamedIndices) { 539 OS << " enum {"; 540 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) { 541 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1; 542 if (i+1 != e) 543 OS << ','; 544 } 545 OS << "\n };\n\n"; 546 } 547 OS << "}\n\n"; // End of anonymous namespace... 548 549 std::string ClassName = Target.getName() + "GenRegisterInfo"; 550 551 // Emit the subregister + index mapping function based on the information 552 // calculated above. 553 OS << "unsigned " << ClassName 554 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" 555 << " switch (RegNo) {\n" 556 << " default:\n return 0;\n"; 557 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 558 const CodeGenRegister::SubRegMap &SRM = Regs[i].getSubRegs(); 559 if (SRM.empty()) 560 continue; 561 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n"; 562 OS << " switch (Index) {\n"; 563 OS << " default: return 0;\n"; 564 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(), 565 ie = SRM.end(); ii != ie; ++ii) 566 OS << " case " << getQualifiedName(ii->first) 567 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n"; 568 OS << " };\n" << " break;\n"; 569 } 570 OS << " };\n"; 571 OS << " return 0;\n"; 572 OS << "}\n\n"; 573 574 OS << "unsigned " << ClassName 575 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n" 576 << " switch (RegNo) {\n" 577 << " default:\n return 0;\n"; 578 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 579 const CodeGenRegister::SubRegMap &SRM = Regs[i].getSubRegs(); 580 if (SRM.empty()) 581 continue; 582 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n"; 583 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(), 584 ie = SRM.end(); ii != ie; ++ii) 585 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef) 586 << ") return " << getQualifiedName(ii->first) << ";\n"; 587 OS << " return 0;\n"; 588 } 589 OS << " };\n"; 590 OS << " return 0;\n"; 591 OS << "}\n\n"; 592 593 // Emit composeSubRegIndices 594 OS << "unsigned " << ClassName 595 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n" 596 << " switch (IdxA) {\n" 597 << " default:\n return IdxB;\n"; 598 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { 599 bool Open = false; 600 for (unsigned j = 0; j != e; ++j) { 601 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i], 602 SubRegIndices[j])) { 603 if (!Open) { 604 OS << " case " << getQualifiedName(SubRegIndices[i]) 605 << ": switch(IdxB) {\n default: return IdxB;\n"; 606 Open = true; 607 } 608 OS << " case " << getQualifiedName(SubRegIndices[j]) 609 << ": return " << getQualifiedName(Comp) << ";\n"; 610 } 611 } 612 if (Open) 613 OS << " }\n"; 614 } 615 OS << " }\n}\n\n"; 616 617 // Emit the constructor of the class... 618 OS << ClassName << "::" << ClassName 619 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" 620 << " : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1 621 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" 622 << " SubRegIndexTable,\n" 623 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n" 624 << " SubregHashTable, SubregHashTableSize,\n" 625 << " AliasesHashTable, AliasesHashTableSize) {\n" 626 << "}\n\n"; 627 628 // Collect all information about dwarf register numbers 629 630 // First, just pull all provided information to the map 631 unsigned maxLength = 0; 632 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 633 Record *Reg = Regs[i].TheDef; 634 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 635 maxLength = std::max((size_t)maxLength, RegNums.size()); 636 if (DwarfRegNums.count(Reg)) 637 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg) 638 << "specified multiple times\n"; 639 DwarfRegNums[Reg] = RegNums; 640 } 641 642 // Now we know maximal length of number list. Append -1's, where needed 643 for (DwarfRegNumsMapTy::iterator 644 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) 645 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) 646 I->second.push_back(-1); 647 648 // Emit reverse information about the dwarf register numbers. 649 OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, " 650 << "unsigned Flavour) const {\n" 651 << " switch (Flavour) {\n" 652 << " default:\n" 653 << " assert(0 && \"Unknown DWARF flavour\");\n" 654 << " return -1;\n"; 655 656 for (unsigned i = 0, e = maxLength; i != e; ++i) { 657 OS << " case " << i << ":\n" 658 << " switch (DwarfRegNum) {\n" 659 << " default:\n" 660 << " assert(0 && \"Invalid DwarfRegNum\");\n" 661 << " return -1;\n"; 662 663 for (DwarfRegNumsMapTy::iterator 664 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 665 int DwarfRegNo = I->second[i]; 666 if (DwarfRegNo >= 0) 667 OS << " case " << DwarfRegNo << ":\n" 668 << " return " << getQualifiedName(I->first) << ";\n"; 669 } 670 OS << " };\n"; 671 } 672 673 OS << " };\n}\n\n"; 674 675 for (unsigned i = 0, e = Regs.size(); i != e; ++i) { 676 Record *Reg = Regs[i].TheDef; 677 const RecordVal *V = Reg->getValue("DwarfAlias"); 678 if (!V || !V->getValue()) 679 continue; 680 681 DefInit *DI = dynamic_cast<DefInit*>(V->getValue()); 682 Record *Alias = DI->getDef(); 683 DwarfRegNums[Reg] = DwarfRegNums[Alias]; 684 } 685 686 // Emit information about the dwarf register numbers. 687 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, " 688 << "unsigned Flavour) const {\n" 689 << " switch (Flavour) {\n" 690 << " default:\n" 691 << " assert(0 && \"Unknown DWARF flavour\");\n" 692 << " return -1;\n"; 693 694 for (unsigned i = 0, e = maxLength; i != e; ++i) { 695 OS << " case " << i << ":\n" 696 << " switch (RegNum) {\n" 697 << " default:\n" 698 << " assert(0 && \"Invalid RegNum\");\n" 699 << " return -1;\n"; 700 701 // Sort by name to get a stable order. 702 703 704 for (DwarfRegNumsMapTy::iterator 705 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { 706 int RegNo = I->second[i]; 707 OS << " case " << getQualifiedName(I->first) << ":\n" 708 << " return " << RegNo << ";\n"; 709 } 710 OS << " };\n"; 711 } 712 713 OS << " };\n}\n\n"; 714 715 OS << "} // End llvm namespace \n"; 716} 717