RegisterInfoEmitter.cpp revision f52baf72c116d9cf8680d25a8e751ce354c7d44b 
1//===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of a target
11// register file for a code generator.  It uses instances of the Register,
12// RegisterAliases, and RegisterClass classes to gather this information.
13//
14//===----------------------------------------------------------------------===//
15
16#include "RegisterInfoEmitter.h"
17#include "CodeGenTarget.h"
18#include "CodeGenRegisters.h"
19#include "SequenceToOffsetTable.h"
20#include "llvm/TableGen/Error.h"
21#include "llvm/TableGen/Record.h"
22#include "llvm/ADT/BitVector.h"
23#include "llvm/ADT/StringExtras.h"
24#include "llvm/ADT/STLExtras.h"
25#include "llvm/ADT/Twine.h"
26#include "llvm/Support/Format.h"
27#include <algorithm>
28#include <set>
29using namespace llvm;
30
31// runEnums - Print out enum values for all of the registers.
32void RegisterInfoEmitter::runEnums(raw_ostream &OS,
33                                   CodeGenTarget &Target, CodeGenRegBank &Bank) {
34  const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
35
36  // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
37  assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
38
39  std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
40
41  EmitSourceFileHeader("Target Register Enum Values", OS);
42
43  OS << "\n#ifdef GET_REGINFO_ENUM\n";
44  OS << "#undef GET_REGINFO_ENUM\n";
45
46  OS << "namespace llvm {\n\n";
47
48  OS << "class MCRegisterClass;\n"
49     << "extern const MCRegisterClass " << Namespace
50     << "MCRegisterClasses[];\n\n";
51
52  if (!Namespace.empty())
53    OS << "namespace " << Namespace << " {\n";
54  OS << "enum {\n  NoRegister,\n";
55
56  for (unsigned i = 0, e = Registers.size(); i != e; ++i)
57    OS << "  " << Registers[i]->getName() << " = " <<
58      Registers[i]->EnumValue << ",\n";
59  assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
60         "Register enum value mismatch!");
61  OS << "  NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
62  OS << "};\n";
63  if (!Namespace.empty())
64    OS << "}\n";
65
66  ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
67  if (!RegisterClasses.empty()) {
68
69    // RegisterClass enums are stored as uint16_t in the tables.
70    assert(RegisterClasses.size() <= 0xffff &&
71           "Too many register classes to fit in tables");
72
73    OS << "\n// Register classes\n";
74    if (!Namespace.empty())
75      OS << "namespace " << Namespace << " {\n";
76    OS << "enum {\n";
77    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
78      if (i) OS << ",\n";
79      OS << "  " << RegisterClasses[i]->getName() << "RegClassID";
80      OS << " = " << i;
81    }
82    OS << "\n  };\n";
83    if (!Namespace.empty())
84      OS << "}\n";
85  }
86
87  const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
88  // If the only definition is the default NoRegAltName, we don't need to
89  // emit anything.
90  if (RegAltNameIndices.size() > 1) {
91    OS << "\n// Register alternate name indices\n";
92    if (!Namespace.empty())
93      OS << "namespace " << Namespace << " {\n";
94    OS << "enum {\n";
95    for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
96      OS << "  " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
97    OS << "  NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
98    OS << "};\n";
99    if (!Namespace.empty())
100      OS << "}\n";
101  }
102
103  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
104  if (!SubRegIndices.empty()) {
105    OS << "\n// Subregister indices\n";
106    std::string Namespace =
107      SubRegIndices[0]->getNamespace();
108    if (!Namespace.empty())
109      OS << "namespace " << Namespace << " {\n";
110    OS << "enum {\n  NoSubRegister,\n";
111    for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
112      OS << "  " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
113    OS << "  NUM_TARGET_NAMED_SUBREGS\n};\n";
114    if (!Namespace.empty())
115      OS << "}\n";
116  }
117
118  OS << "} // End llvm namespace \n";
119  OS << "#endif // GET_REGINFO_ENUM\n\n";
120}
121
122void RegisterInfoEmitter::
123EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
124                    const std::string &ClassName) {
125  unsigned NumRCs = RegBank.getRegClasses().size();
126  unsigned NumSets = RegBank.getNumRegPressureSets();
127
128  OS << "/// Get the weight in units of pressure for this register class.\n"
129     << "const RegClassWeight &" << ClassName << "::\n"
130     << "getRegClassWeight(const TargetRegisterClass *RC) const {\n"
131     << "  static const RegClassWeight RCWeightTable[] = {\n";
132  for (unsigned i = 0, e = NumRCs; i != e; ++i) {
133    const CodeGenRegisterClass &RC = *RegBank.getRegClasses()[i];
134    const CodeGenRegister::Set &Regs = RC.getMembers();
135    if (Regs.empty())
136      OS << "    {0, 0";
137    else {
138      std::vector<unsigned> RegUnits;
139      RC.buildRegUnitSet(RegUnits);
140      OS << "    {" << (*Regs.begin())->getWeight(RegBank)
141         << ", " << RegBank.getRegUnitSetWeight(RegUnits);
142    }
143    OS << "},  \t// " << RC.getName() << "\n";
144  }
145  OS << "    {0, 0} };\n"
146     << "  return RCWeightTable[RC->getID()];\n"
147     << "}\n\n";
148
149  OS << "\n"
150     << "// Get the number of dimensions of register pressure.\n"
151     << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n"
152     << "  return " << NumSets << ";\n}\n\n";
153
154  OS << "// Get the name of this register unit pressure set.\n"
155     << "const char *" << ClassName << "::\n"
156     << "getRegPressureSetName(unsigned Idx) const {\n"
157     << "  static const char *PressureNameTable[] = {\n";
158  for (unsigned i = 0; i < NumSets; ++i ) {
159    OS << "    \"" << RegBank.getRegPressureSet(i).Name << "\",\n";
160  }
161  OS << "    0 };\n"
162     << "  return PressureNameTable[Idx];\n"
163     << "}\n\n";
164
165  OS << "// Get the register unit pressure limit for this dimension.\n"
166     << "// This limit must be adjusted dynamically for reserved registers.\n"
167     << "unsigned " << ClassName << "::\n"
168     << "getRegPressureSetLimit(unsigned Idx) const {\n"
169     << "  static const unsigned PressureLimitTable[] = {\n";
170  for (unsigned i = 0; i < NumSets; ++i ) {
171    const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i);
172    OS << "    " << RegBank.getRegUnitSetWeight(RegUnits.Units)
173       << ",  \t// " << i << ": " << RegUnits.Name << "\n";
174  }
175  OS << "    0 };\n"
176     << "  return PressureLimitTable[Idx];\n"
177     << "}\n\n";
178
179  OS << "/// Get the dimensions of register pressure "
180     << "impacted by this register class.\n"
181     << "/// Returns a -1 terminated array of pressure set IDs\n"
182     << "const int* " << ClassName << "::\n"
183     << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"
184     << "  static const int RCSetsTable[] = {\n    ";
185  std::vector<unsigned> RCSetStarts(NumRCs);
186  for (unsigned i = 0, StartIdx = 0, e = NumRCs; i != e; ++i) {
187    RCSetStarts[i] = StartIdx;
188    ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i);
189    for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(),
190           PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) {
191      OS << *PSetI << ",  ";
192      ++StartIdx;
193    }
194    OS << "-1,  \t// " << RegBank.getRegClasses()[i]->getName() << "\n    ";
195    ++StartIdx;
196  }
197  OS << "-1 };\n";
198  OS << "  static const unsigned RCSetStartTable[] = {\n    ";
199  for (unsigned i = 0, e = NumRCs; i != e; ++i) {
200    OS << RCSetStarts[i] << ",";
201  }
202  OS << "0 };\n"
203     << "  unsigned SetListStart = RCSetStartTable[RC->getID()];\n"
204     << "  return &RCSetsTable[SetListStart];\n"
205     << "}\n\n";
206}
207
208void
209RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
210                                       const std::vector<CodeGenRegister*> &Regs,
211                                          bool isCtor) {
212  // Collect all information about dwarf register numbers
213  typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
214  DwarfRegNumsMapTy DwarfRegNums;
215
216  // First, just pull all provided information to the map
217  unsigned maxLength = 0;
218  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
219    Record *Reg = Regs[i]->TheDef;
220    std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
221    maxLength = std::max((size_t)maxLength, RegNums.size());
222    if (DwarfRegNums.count(Reg))
223      PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") +
224                   getQualifiedName(Reg) + "specified multiple times");
225    DwarfRegNums[Reg] = RegNums;
226  }
227
228  if (!maxLength)
229    return;
230
231  // Now we know maximal length of number list. Append -1's, where needed
232  for (DwarfRegNumsMapTy::iterator
233       I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
234    for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
235      I->second.push_back(-1);
236
237  std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
238
239  OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
240
241  // Emit reverse information about the dwarf register numbers.
242  for (unsigned j = 0; j < 2; ++j) {
243    for (unsigned i = 0, e = maxLength; i != e; ++i) {
244      OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
245      OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
246      OS << i << "Dwarf2L[]";
247
248      if (!isCtor) {
249        OS << " = {\n";
250
251        // Store the mapping sorted by the LLVM reg num so lookup can be done
252        // with a binary search.
253        std::map<uint64_t, Record*> Dwarf2LMap;
254        for (DwarfRegNumsMapTy::iterator
255               I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
256          int DwarfRegNo = I->second[i];
257          if (DwarfRegNo < 0)
258            continue;
259          Dwarf2LMap[DwarfRegNo] = I->first;
260        }
261
262        for (std::map<uint64_t, Record*>::iterator
263               I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
264          OS << "  { " << I->first << "U, " << getQualifiedName(I->second)
265             << " },\n";
266
267        OS << "};\n";
268      } else {
269        OS << ";\n";
270      }
271
272      // We have to store the size in a const global, it's used in multiple
273      // places.
274      OS << "extern const unsigned " << Namespace
275         << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
276      if (!isCtor)
277        OS << " = sizeof(" << Namespace
278           << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
279           << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
280      else
281        OS << ";\n\n";
282    }
283  }
284
285  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
286    Record *Reg = Regs[i]->TheDef;
287    const RecordVal *V = Reg->getValue("DwarfAlias");
288    if (!V || !V->getValue())
289      continue;
290
291    DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
292    Record *Alias = DI->getDef();
293    DwarfRegNums[Reg] = DwarfRegNums[Alias];
294  }
295
296  // Emit information about the dwarf register numbers.
297  for (unsigned j = 0; j < 2; ++j) {
298    for (unsigned i = 0, e = maxLength; i != e; ++i) {
299      OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
300      OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
301      OS << i << "L2Dwarf[]";
302      if (!isCtor) {
303        OS << " = {\n";
304        // Store the mapping sorted by the Dwarf reg num so lookup can be done
305        // with a binary search.
306        for (DwarfRegNumsMapTy::iterator
307               I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
308          int RegNo = I->second[i];
309          if (RegNo == -1) // -1 is the default value, don't emit a mapping.
310            continue;
311
312          OS << "  { " << getQualifiedName(I->first) << ", " << RegNo
313             << "U },\n";
314        }
315        OS << "};\n";
316      } else {
317        OS << ";\n";
318      }
319
320      // We have to store the size in a const global, it's used in multiple
321      // places.
322      OS << "extern const unsigned " << Namespace
323         << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
324      if (!isCtor)
325        OS << " = sizeof(" << Namespace
326           << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
327           << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
328      else
329        OS << ";\n\n";
330    }
331  }
332}
333
334void
335RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
336                                    const std::vector<CodeGenRegister*> &Regs,
337                                    bool isCtor) {
338  // Emit the initializer so the tables from EmitRegMappingTables get wired up
339  // to the MCRegisterInfo object.
340  unsigned maxLength = 0;
341  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
342    Record *Reg = Regs[i]->TheDef;
343    maxLength = std::max((size_t)maxLength,
344                         Reg->getValueAsListOfInts("DwarfNumbers").size());
345  }
346
347  if (!maxLength)
348    return;
349
350  std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
351
352  // Emit reverse information about the dwarf register numbers.
353  for (unsigned j = 0; j < 2; ++j) {
354    OS << "  switch (";
355    if (j == 0)
356      OS << "DwarfFlavour";
357    else
358      OS << "EHFlavour";
359    OS << ") {\n"
360     << "  default:\n"
361     << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
362
363    for (unsigned i = 0, e = maxLength; i != e; ++i) {
364      OS << "  case " << i << ":\n";
365      OS << "    ";
366      if (!isCtor)
367        OS << "RI->";
368      std::string Tmp;
369      raw_string_ostream(Tmp) << Namespace
370                              << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
371                              << "Dwarf2L";
372      OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
373      if (j == 0)
374          OS << "false";
375        else
376          OS << "true";
377      OS << ");\n";
378      OS << "    break;\n";
379    }
380    OS << "  }\n";
381  }
382
383  // Emit information about the dwarf register numbers.
384  for (unsigned j = 0; j < 2; ++j) {
385    OS << "  switch (";
386    if (j == 0)
387      OS << "DwarfFlavour";
388    else
389      OS << "EHFlavour";
390    OS << ") {\n"
391       << "  default:\n"
392       << "    llvm_unreachable(\"Unknown DWARF flavour\");\n";
393
394    for (unsigned i = 0, e = maxLength; i != e; ++i) {
395      OS << "  case " << i << ":\n";
396      OS << "    ";
397      if (!isCtor)
398        OS << "RI->";
399      std::string Tmp;
400      raw_string_ostream(Tmp) << Namespace
401                              << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
402                              << "L2Dwarf";
403      OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
404      if (j == 0)
405          OS << "false";
406        else
407          OS << "true";
408      OS << ");\n";
409      OS << "    break;\n";
410    }
411    OS << "  }\n";
412  }
413}
414
415// Print a BitVector as a sequence of hex numbers using a little-endian mapping.
416// Width is the number of bits per hex number.
417static void printBitVectorAsHex(raw_ostream &OS,
418                                const BitVector &Bits,
419                                unsigned Width) {
420  assert(Width <= 32 && "Width too large");
421  unsigned Digits = (Width + 3) / 4;
422  for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
423    unsigned Value = 0;
424    for (unsigned j = 0; j != Width && i + j != e; ++j)
425      Value |= Bits.test(i + j) << j;
426    OS << format("0x%0*x, ", Digits, Value);
427  }
428}
429
430// Helper to emit a set of bits into a constant byte array.
431class BitVectorEmitter {
432  BitVector Values;
433public:
434  void add(unsigned v) {
435    if (v >= Values.size())
436      Values.resize(((v/8)+1)*8); // Round up to the next byte.
437    Values[v] = true;
438  }
439
440  void print(raw_ostream &OS) {
441    printBitVectorAsHex(OS, Values, 8);
442  }
443};
444
445static void printRegister(raw_ostream &OS, const CodeGenRegister *Reg) {
446  OS << getQualifiedName(Reg->TheDef);
447}
448
449static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
450  OS << getEnumName(VT);
451}
452
453static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) {
454  OS << Idx->getQualifiedName();
455}
456
457// Differentially encoded register and regunit lists allow for better
458// compression on regular register banks. The sequence is computed from the
459// differential list as:
460//
461//   out[0] = InitVal;
462//   out[n+1] = out[n] + diff[n]; // n = 0, 1, ...
463//
464// The initial value depends on the specific list. The list is terminated by a
465// 0 differential which means we can't encode repeated elements.
466
467typedef SmallVector<uint16_t, 4> DiffVec;
468
469// Differentially encode a sequence of numbers into V. The starting value and
470// terminating 0 are not added to V, so it will have the same size as List.
471DiffVec &diffEncode(DiffVec &V, unsigned InitVal, ArrayRef<unsigned> List) {
472  assert(V.empty() && "Clear DiffVec before diffEncode.");
473  uint16_t Val = uint16_t(InitVal);
474  for (unsigned i = 0; i != List.size(); ++i) {
475    uint16_t Cur = List[i];
476    V.push_back(Cur - Val);
477    Val = Cur;
478  }
479  return V;
480}
481
482static void printDiff16(raw_ostream &OS, uint16_t Val) {
483  OS << SignExtend32<16>(Val);
484}
485
486//
487// runMCDesc - Print out MC register descriptions.
488//
489void
490RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
491                               CodeGenRegBank &RegBank) {
492  EmitSourceFileHeader("MC Register Information", OS);
493
494  OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
495  OS << "#undef GET_REGINFO_MC_DESC\n";
496
497  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
498
499  // The lists of sub-registers, super-registers, and overlaps all go in the
500  // same array. That allows us to share suffixes.
501  typedef std::vector<const CodeGenRegister*> RegVec;
502  SmallVector<RegVec, 4> SubRegLists(Regs.size());
503  SmallVector<RegVec, 4> OverlapLists(Regs.size());
504  SequenceToOffsetTable<RegVec, CodeGenRegister::Less> RegSeqs;
505
506  // Differentially encoded lists.
507  SequenceToOffsetTable<DiffVec> DiffSeqs;
508  SmallVector<DiffVec, 4> RegUnitLists(Regs.size());
509  SmallVector<unsigned, 4> RegUnitInitScale(Regs.size());
510
511  SequenceToOffsetTable<std::string> RegStrings;
512
513  // Precompute register lists for the SequenceToOffsetTable.
514  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
515    const CodeGenRegister *Reg = Regs[i];
516
517    RegStrings.add(Reg->getName());
518
519    // Compute the ordered sub-register list.
520    SetVector<const CodeGenRegister*> SR;
521    Reg->addSubRegsPreOrder(SR, RegBank);
522    RegVec &SubRegList = SubRegLists[i];
523    SubRegList.assign(SR.begin(), SR.end());
524    RegSeqs.add(SubRegList);
525
526    // Super-registers are already computed.
527    const RegVec &SuperRegList = Reg->getSuperRegs();
528    RegSeqs.add(SuperRegList);
529
530    // The list of overlaps doesn't need to have any particular order, except
531    // Reg itself must be the first element. Pick an ordering that has one of
532    // the other lists as a suffix.
533    RegVec &OverlapList = OverlapLists[i];
534    const RegVec &Suffix = SubRegList.size() > SuperRegList.size() ?
535                           SubRegList : SuperRegList;
536    CodeGenRegister::Set Omit(Suffix.begin(), Suffix.end());
537
538    // First element is Reg itself.
539    OverlapList.push_back(Reg);
540    Omit.insert(Reg);
541
542    // Any elements not in Suffix.
543    CodeGenRegister::Set OSet;
544    Reg->computeOverlaps(OSet, RegBank);
545    std::set_difference(OSet.begin(), OSet.end(),
546                        Omit.begin(), Omit.end(),
547                        std::back_inserter(OverlapList),
548                        CodeGenRegister::Less());
549
550    // Finally, Suffix itself.
551    OverlapList.insert(OverlapList.end(), Suffix.begin(), Suffix.end());
552    RegSeqs.add(OverlapList);
553
554    // Differentially encode the register unit list, seeded by register number.
555    // First compute a scale factor that allows more diff-lists to be reused:
556    //
557    //   D0 -> (S0, S1)
558    //   D1 -> (S2, S3)
559    //
560    // A scale factor of 2 allows D0 and D1 to share a diff-list. The initial
561    // value for the differential decoder is the register number multiplied by
562    // the scale.
563    //
564    // Check the neighboring registers for arithmetic progressions.
565    unsigned ScaleA = ~0u, ScaleB = ~0u;
566    ArrayRef<unsigned> RUs = Reg->getNativeRegUnits();
567    if (i > 0 && Regs[i-1]->getNativeRegUnits().size() == RUs.size())
568      ScaleB = RUs.front() - Regs[i-1]->getNativeRegUnits().front();
569    if (i+1 != Regs.size() &&
570        Regs[i+1]->getNativeRegUnits().size() == RUs.size())
571      ScaleA = Regs[i+1]->getNativeRegUnits().front() - RUs.front();
572    unsigned Scale = std::min(ScaleB, ScaleA);
573    // Default the scale to 0 if it can't be encoded in 4 bits.
574    if (Scale >= 16)
575      Scale = 0;
576    RegUnitInitScale[i] = Scale;
577    DiffSeqs.add(diffEncode(RegUnitLists[i], Scale * Reg->EnumValue, RUs));
578  }
579
580  // Compute the final layout of the sequence table.
581  RegSeqs.layout();
582  DiffSeqs.layout();
583
584  OS << "namespace llvm {\n\n";
585
586  const std::string &TargetName = Target.getName();
587
588  // Emit the shared table of register lists.
589  OS << "extern const uint16_t " << TargetName << "RegLists[] = {\n";
590  RegSeqs.emit(OS, printRegister);
591  OS << "};\n\n";
592
593  // Emit the shared table of differential lists.
594  OS << "extern const uint16_t " << TargetName << "RegDiffLists[] = {\n";
595  DiffSeqs.emit(OS, printDiff16);
596  OS << "};\n\n";
597
598  // Emit the string table.
599  RegStrings.layout();
600  OS << "extern const char " << TargetName << "RegStrings[] = {\n";
601  RegStrings.emit(OS, printChar);
602  OS << "};\n\n";
603
604  OS << "extern const MCRegisterDesc " << TargetName
605     << "RegDesc[] = { // Descriptors\n";
606  OS << "  { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n";
607
608  // Emit the register descriptors now.
609  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
610    const CodeGenRegister *Reg = Regs[i];
611    OS << "  { " << RegStrings.get(Reg->getName()) << ", "
612       << RegSeqs.get(OverlapLists[i]) << ", "
613       << RegSeqs.get(SubRegLists[i]) << ", "
614       << RegSeqs.get(Reg->getSuperRegs()) << ", "
615       << (DiffSeqs.get(RegUnitLists[i])*16 + RegUnitInitScale[i]) << " },\n";
616  }
617  OS << "};\n\n";      // End of register descriptors...
618
619  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
620
621  // Loop over all of the register classes... emitting each one.
622  OS << "namespace {     // Register classes...\n";
623
624  // Emit the register enum value arrays for each RegisterClass
625  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
626    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
627    ArrayRef<Record*> Order = RC.getOrder();
628
629    // Give the register class a legal C name if it's anonymous.
630    std::string Name = RC.getName();
631
632    // Emit the register list now.
633    OS << "  // " << Name << " Register Class...\n"
634       << "  const uint16_t " << Name
635       << "[] = {\n    ";
636    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
637      Record *Reg = Order[i];
638      OS << getQualifiedName(Reg) << ", ";
639    }
640    OS << "\n  };\n\n";
641
642    OS << "  // " << Name << " Bit set.\n"
643       << "  const uint8_t " << Name
644       << "Bits[] = {\n    ";
645    BitVectorEmitter BVE;
646    for (unsigned i = 0, e = Order.size(); i != e; ++i) {
647      Record *Reg = Order[i];
648      BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
649    }
650    BVE.print(OS);
651    OS << "\n  };\n\n";
652
653  }
654  OS << "}\n\n";
655
656  OS << "extern const MCRegisterClass " << TargetName
657     << "MCRegisterClasses[] = {\n";
658
659  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
660    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
661
662    // Asserts to make sure values will fit in table assuming types from
663    // MCRegisterInfo.h
664    assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
665    assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
666    assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
667
668    OS << "  { " << '\"' << RC.getName() << "\", "
669       << RC.getName() << ", " << RC.getName() << "Bits, "
670       << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
671       << RC.getQualifiedName() + "RegClassID" << ", "
672       << RC.SpillSize/8 << ", "
673       << RC.SpillAlignment/8 << ", "
674       << RC.CopyCost << ", "
675       << RC.Allocatable << " },\n";
676  }
677
678  OS << "};\n\n";
679
680  // Emit the data table for getSubReg().
681  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
682  if (SubRegIndices.size()) {
683    OS << "const uint16_t " << TargetName << "SubRegTable[]["
684       << SubRegIndices.size() << "] = {\n";
685    for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
686      const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
687      OS << "  /* " << Regs[i]->TheDef->getName() << " */\n";
688      if (SRM.empty()) {
689        OS << "  {0},\n";
690        continue;
691      }
692      OS << "  {";
693      for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
694        // FIXME: We really should keep this to 80 columns...
695        CodeGenRegister::SubRegMap::const_iterator SubReg =
696          SRM.find(SubRegIndices[j]);
697        if (SubReg != SRM.end())
698          OS << getQualifiedName(SubReg->second->TheDef);
699        else
700          OS << "0";
701        if (j != je - 1)
702          OS << ", ";
703      }
704      OS << "}" << (i != e ? "," : "") << "\n";
705    }
706    OS << "};\n\n";
707    OS << "const uint16_t *get" << TargetName
708       << "SubRegTable() {\n  return (const uint16_t *)" << TargetName
709       << "SubRegTable;\n}\n\n";
710  }
711
712  EmitRegMappingTables(OS, Regs, false);
713
714  // Emit Reg encoding table
715  OS << "extern const uint16_t " << TargetName;
716  OS << "RegEncodingTable[] = {\n";
717  // Add entry for NoRegister
718  OS << "  0,\n";
719  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
720    Record *Reg = Regs[i]->TheDef;
721    BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding");
722    uint64_t Value = 0;
723    for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) {
724      if (BitInit *B = dynamic_cast<BitInit*>(BI->getBit(b)))
725      Value |= (uint64_t)B->getValue() << b;
726    }
727    OS << "  " << Value << ",\n";
728  }
729  OS << "};\n";       // End of HW encoding table
730
731  // MCRegisterInfo initialization routine.
732  OS << "static inline void Init" << TargetName
733     << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
734     << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
735  OS << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
736     << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
737     << RegisterClasses.size() << ", "
738     << RegBank.getNumNativeRegUnits() << ", "
739     << TargetName << "RegLists, "
740     << TargetName << "RegDiffLists, "
741     << TargetName << "RegStrings, ";
742  if (SubRegIndices.size() != 0)
743    OS << "(uint16_t*)" << TargetName << "SubRegTable, "
744       << SubRegIndices.size() << ",\n";
745  else
746    OS << "NULL, 0,\n";
747
748  OS << "  " << TargetName << "RegEncodingTable);\n\n";
749
750  EmitRegMapping(OS, Regs, false);
751
752  OS << "}\n\n";
753
754  OS << "} // End llvm namespace \n";
755  OS << "#endif // GET_REGINFO_MC_DESC\n\n";
756}
757
758void
759RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
760                                     CodeGenRegBank &RegBank) {
761  EmitSourceFileHeader("Register Information Header Fragment", OS);
762
763  OS << "\n#ifdef GET_REGINFO_HEADER\n";
764  OS << "#undef GET_REGINFO_HEADER\n";
765
766  const std::string &TargetName = Target.getName();
767  std::string ClassName = TargetName + "GenRegisterInfo";
768
769  OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
770
771  OS << "namespace llvm {\n\n";
772
773  OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
774     << "  explicit " << ClassName
775     << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
776     << "  virtual bool needsStackRealignment(const MachineFunction &) const\n"
777     << "     { return false; }\n";
778  if (!RegBank.getSubRegIndices().empty()) {
779    OS << "  unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
780      << "  const TargetRegisterClass *"
781      "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n";
782  }
783  OS << "  const RegClassWeight &getRegClassWeight("
784     << "const TargetRegisterClass *RC) const;\n"
785     << "  unsigned getNumRegPressureSets() const;\n"
786     << "  const char *getRegPressureSetName(unsigned Idx) const;\n"
787     << "  unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
788     << "  const int *getRegClassPressureSets("
789     << "const TargetRegisterClass *RC) const;\n"
790     << "};\n\n";
791
792  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
793
794  if (!RegisterClasses.empty()) {
795    OS << "namespace " << RegisterClasses[0]->Namespace
796       << " { // Register classes\n";
797
798    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
799      const CodeGenRegisterClass &RC = *RegisterClasses[i];
800      const std::string &Name = RC.getName();
801
802      // Output the extern for the instance.
803      OS << "  extern const TargetRegisterClass " << Name << "RegClass;\n";
804    }
805    OS << "} // end of namespace " << TargetName << "\n\n";
806  }
807  OS << "} // End llvm namespace \n";
808  OS << "#endif // GET_REGINFO_HEADER\n\n";
809}
810
811//
812// runTargetDesc - Output the target register and register file descriptions.
813//
814void
815RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
816                                   CodeGenRegBank &RegBank){
817  EmitSourceFileHeader("Target Register and Register Classes Information", OS);
818
819  OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
820  OS << "#undef GET_REGINFO_TARGET_DESC\n";
821
822  OS << "namespace llvm {\n\n";
823
824  // Get access to MCRegisterClass data.
825  OS << "extern const MCRegisterClass " << Target.getName()
826     << "MCRegisterClasses[];\n";
827
828  // Start out by emitting each of the register classes.
829  ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
830  ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
831
832  // Collect all registers belonging to any allocatable class.
833  std::set<Record*> AllocatableRegs;
834
835  // Collect allocatable registers.
836  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
837    const CodeGenRegisterClass &RC = *RegisterClasses[rc];
838    ArrayRef<Record*> Order = RC.getOrder();
839
840    if (RC.Allocatable)
841      AllocatableRegs.insert(Order.begin(), Order.end());
842  }
843
844  // Build a shared array of value types.
845  SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
846  for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
847    VTSeqs.add(RegisterClasses[rc]->VTs);
848  VTSeqs.layout();
849  OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
850  VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
851  OS << "};\n";
852
853  // Emit SubRegIndex names, skipping 0
854  OS << "\nstatic const char *const SubRegIndexTable[] = { \"";
855  for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
856    OS << SubRegIndices[i]->getName();
857    if (i+1 != e)
858      OS << "\", \"";
859  }
860  OS << "\" };\n\n";
861
862  // Emit names of the anonymous subreg indices.
863  unsigned NamedIndices = RegBank.getNumNamedIndices();
864  if (SubRegIndices.size() > NamedIndices) {
865    OS << "  enum {";
866    for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
867      OS << "\n    " << SubRegIndices[i]->getName() << " = " << i+1;
868      if (i+1 != e)
869        OS << ',';
870    }
871    OS << "\n  };\n\n";
872  }
873  OS << "\n";
874
875  // Now that all of the structs have been emitted, emit the instances.
876  if (!RegisterClasses.empty()) {
877    OS << "\nstatic const TargetRegisterClass *const "
878       << "NullRegClasses[] = { NULL };\n\n";
879
880    // Emit register class bit mask tables. The first bit mask emitted for a
881    // register class, RC, is the set of sub-classes, including RC itself.
882    //
883    // If RC has super-registers, also create a list of subreg indices and bit
884    // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass,
885    // SuperRC, that satisfies:
886    //
887    //   For all SuperReg in SuperRC: SuperReg:Idx in RC
888    //
889    // The 0-terminated list of subreg indices starts at:
890    //
891    //   RC->getSuperRegIndices() = SuperRegIdxSeqs + ...
892    //
893    // The corresponding bitmasks follow the sub-class mask in memory. Each
894    // mask has RCMaskWords uint32_t entries.
895    //
896    // Every bit mask present in the list has at least one bit set.
897
898    // Compress the sub-reg index lists.
899    typedef std::vector<const CodeGenSubRegIndex*> IdxList;
900    SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size());
901    SequenceToOffsetTable<IdxList> SuperRegIdxSeqs;
902    BitVector MaskBV(RegisterClasses.size());
903
904    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
905      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
906      OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n  ";
907      printBitVectorAsHex(OS, RC.getSubClasses(), 32);
908
909      // Emit super-reg class masks for any relevant SubRegIndices that can
910      // project into RC.
911      IdxList &SRIList = SuperRegIdxLists[rc];
912      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
913        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
914        MaskBV.reset();
915        RC.getSuperRegClasses(Idx, MaskBV);
916        if (MaskBV.none())
917          continue;
918        SRIList.push_back(Idx);
919        OS << "\n  ";
920        printBitVectorAsHex(OS, MaskBV, 32);
921        OS << "// " << Idx->getName();
922      }
923      SuperRegIdxSeqs.add(SRIList);
924      OS << "\n};\n\n";
925    }
926
927    OS << "static const uint16_t SuperRegIdxSeqs[] = {\n";
928    SuperRegIdxSeqs.layout();
929    SuperRegIdxSeqs.emit(OS, printSubRegIndex);
930    OS << "};\n\n";
931
932    // Emit NULL terminated super-class lists.
933    for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
934      const CodeGenRegisterClass &RC = *RegisterClasses[rc];
935      ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
936
937      // Skip classes without supers.  We can reuse NullRegClasses.
938      if (Supers.empty())
939        continue;
940
941      OS << "static const TargetRegisterClass *const "
942         << RC.getName() << "Superclasses[] = {\n";
943      for (unsigned i = 0; i != Supers.size(); ++i)
944        OS << "  &" << Supers[i]->getQualifiedName() << "RegClass,\n";
945      OS << "  NULL\n};\n\n";
946    }
947
948    // Emit methods.
949    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
950      const CodeGenRegisterClass &RC = *RegisterClasses[i];
951      if (!RC.AltOrderSelect.empty()) {
952        OS << "\nstatic inline unsigned " << RC.getName()
953           << "AltOrderSelect(const MachineFunction &MF) {"
954           << RC.AltOrderSelect << "}\n\n"
955           << "static ArrayRef<uint16_t> " << RC.getName()
956           << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
957        for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
958          ArrayRef<Record*> Elems = RC.getOrder(oi);
959          if (!Elems.empty()) {
960            OS << "  static const uint16_t AltOrder" << oi << "[] = {";
961            for (unsigned elem = 0; elem != Elems.size(); ++elem)
962              OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
963            OS << " };\n";
964          }
965        }
966        OS << "  const MCRegisterClass &MCR = " << Target.getName()
967           << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
968           << "  const ArrayRef<uint16_t> Order[] = {\n"
969           << "    makeArrayRef(MCR.begin(), MCR.getNumRegs()";
970        for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
971          if (RC.getOrder(oi).empty())
972            OS << "),\n    ArrayRef<uint16_t>(";
973          else
974            OS << "),\n    makeArrayRef(AltOrder" << oi;
975        OS << ")\n  };\n  const unsigned Select = " << RC.getName()
976           << "AltOrderSelect(MF);\n  assert(Select < " << RC.getNumOrders()
977           << ");\n  return Order[Select];\n}\n";
978        }
979    }
980
981    // Now emit the actual value-initialized register class instances.
982    OS << "namespace " << RegisterClasses[0]->Namespace
983       << " {   // Register class instances\n";
984
985    for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
986      const CodeGenRegisterClass &RC = *RegisterClasses[i];
987      OS << "  extern const TargetRegisterClass "
988         << RegisterClasses[i]->getName() << "RegClass = {\n    "
989         << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
990         << "RegClassID],\n    "
991         << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n    "
992         << RC.getName() << "SubClassMask,\n    SuperRegIdxSeqs + "
993         << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n    ";
994      if (RC.getSuperClasses().empty())
995        OS << "NullRegClasses,\n    ";
996      else
997        OS << RC.getName() << "Superclasses,\n    ";
998      if (RC.AltOrderSelect.empty())
999        OS << "0\n";
1000      else
1001        OS << RC.getName() << "GetRawAllocationOrder\n";
1002      OS << "  };\n\n";
1003    }
1004
1005    OS << "}\n";
1006  }
1007
1008  OS << "\nnamespace {\n";
1009  OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
1010  for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
1011    OS << "    &" << RegisterClasses[i]->getQualifiedName()
1012       << "RegClass,\n";
1013  OS << "  };\n";
1014  OS << "}\n";       // End of anonymous namespace...
1015
1016  // Emit extra information about registers.
1017  const std::string &TargetName = Target.getName();
1018  OS << "\nstatic const TargetRegisterInfoDesc "
1019     << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
1020  OS << "  { 0, 0 },\n";
1021
1022  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
1023  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1024    const CodeGenRegister &Reg = *Regs[i];
1025    OS << "  { ";
1026    OS << Reg.CostPerUse << ", "
1027       << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
1028  }
1029  OS << "};\n";      // End of register descriptors...
1030
1031
1032  std::string ClassName = Target.getName() + "GenRegisterInfo";
1033
1034  // Emit composeSubRegIndices
1035  if (!SubRegIndices.empty()) {
1036    OS << "unsigned " << ClassName
1037      << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
1038      << "  switch (IdxA) {\n"
1039      << "  default:\n    return IdxB;\n";
1040    for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
1041      bool Open = false;
1042      for (unsigned j = 0; j != e; ++j) {
1043        if (CodeGenSubRegIndex *Comp =
1044            SubRegIndices[i]->compose(SubRegIndices[j])) {
1045          if (!Open) {
1046            OS << "  case " << SubRegIndices[i]->getQualifiedName()
1047              << ": switch(IdxB) {\n    default: return IdxB;\n";
1048            Open = true;
1049          }
1050          OS << "    case " << SubRegIndices[j]->getQualifiedName()
1051            << ": return " << Comp->getQualifiedName() << ";\n";
1052        }
1053      }
1054      if (Open)
1055        OS << "    }\n";
1056    }
1057    OS << "  }\n}\n\n";
1058  }
1059
1060  // Emit getSubClassWithSubReg.
1061  if (!SubRegIndices.empty()) {
1062    OS << "const TargetRegisterClass *" << ClassName
1063       << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1064       << " const {\n";
1065    // Use the smallest type that can hold a regclass ID with room for a
1066    // sentinel.
1067    if (RegisterClasses.size() < UINT8_MAX)
1068      OS << "  static const uint8_t Table[";
1069    else if (RegisterClasses.size() < UINT16_MAX)
1070      OS << "  static const uint16_t Table[";
1071    else
1072      throw "Too many register classes.";
1073    OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
1074    for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
1075      const CodeGenRegisterClass &RC = *RegisterClasses[rci];
1076      OS << "    {\t// " << RC.getName() << "\n";
1077      for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
1078        CodeGenSubRegIndex *Idx = SubRegIndices[sri];
1079        if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
1080          OS << "      " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
1081             << " -> " << SRC->getName() << "\n";
1082        else
1083          OS << "      0,\t// " << Idx->getName() << "\n";
1084      }
1085      OS << "    },\n";
1086    }
1087    OS << "  };\n  assert(RC && \"Missing regclass\");\n"
1088       << "  if (!Idx) return RC;\n  --Idx;\n"
1089       << "  assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
1090       << "  unsigned TV = Table[RC->getID()][Idx];\n"
1091       << "  return TV ? getRegClass(TV - 1) : 0;\n}\n\n";
1092  }
1093
1094  EmitRegUnitPressure(OS, RegBank, ClassName);
1095
1096  // Emit the constructor of the class...
1097  OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
1098  OS << "extern const uint16_t " << TargetName << "RegLists[];\n";
1099  OS << "extern const uint16_t " << TargetName << "RegDiffLists[];\n";
1100  OS << "extern const char " << TargetName << "RegStrings[];\n";
1101  if (SubRegIndices.size() != 0)
1102    OS << "extern const uint16_t *get" << TargetName
1103       << "SubRegTable();\n";
1104  OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
1105
1106  EmitRegMappingTables(OS, Regs, true);
1107
1108  OS << ClassName << "::\n" << ClassName
1109     << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
1110     << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
1111     << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
1112     << "             SubRegIndexTable) {\n"
1113     << "  InitMCRegisterInfo(" << TargetName << "RegDesc, "
1114     << Regs.size()+1 << ", RA,\n                     " << TargetName
1115     << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
1116     << "                     " << RegBank.getNumNativeRegUnits() << ",\n"
1117     << "                     " << TargetName << "RegLists,\n"
1118     << "                     " << TargetName << "RegDiffLists,\n"
1119     << "                     " << TargetName << "RegStrings,\n"
1120     << "                     ";
1121  if (SubRegIndices.size() != 0)
1122    OS << "get" << TargetName << "SubRegTable(), "
1123       << SubRegIndices.size() << ",\n";
1124  else
1125    OS << "NULL, 0,\n";
1126
1127  OS << "                     " << TargetName << "RegEncodingTable);\n\n";
1128
1129  EmitRegMapping(OS, Regs, true);
1130
1131  OS << "}\n\n";
1132
1133
1134  // Emit CalleeSavedRegs information.
1135  std::vector<Record*> CSRSets =
1136    Records.getAllDerivedDefinitions("CalleeSavedRegs");
1137  for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
1138    Record *CSRSet = CSRSets[i];
1139    const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1140    assert(Regs && "Cannot expand CalleeSavedRegs instance");
1141
1142    // Emit the *_SaveList list of callee-saved registers.
1143    OS << "static const uint16_t " << CSRSet->getName()
1144       << "_SaveList[] = { ";
1145    for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1146      OS << getQualifiedName((*Regs)[r]) << ", ";
1147    OS << "0 };\n";
1148
1149    // Emit the *_RegMask bit mask of call-preserved registers.
1150    OS << "static const uint32_t " << CSRSet->getName()
1151       << "_RegMask[] = { ";
1152    printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
1153    OS << "};\n";
1154  }
1155  OS << "\n\n";
1156
1157  OS << "} // End llvm namespace \n";
1158  OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1159}
1160
1161void RegisterInfoEmitter::run(raw_ostream &OS) {
1162  CodeGenTarget Target(Records);
1163  CodeGenRegBank &RegBank = Target.getRegBank();
1164  RegBank.computeDerivedInfo();
1165
1166  runEnums(OS, Target, RegBank);
1167  runMCDesc(OS, Target, RegBank);
1168  runTargetHeader(OS, Target, RegBank);
1169  runTargetDesc(OS, Target, RegBank);
1170}
1171