nv50_program.c revision 001daf78c87b2d194b51bc650bf9f917d4224e31
1/* 2 * Copyright 2008 Ben Skeggs 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "pipe/p_context.h" 24#include "pipe/p_defines.h" 25#include "pipe/p_state.h" 26#include "pipe/p_inlines.h" 27 28#include "pipe/p_shader_tokens.h" 29#include "tgsi/tgsi_parse.h" 30#include "tgsi/tgsi_util.h" 31 32#include "nv50_context.h" 33 34#define NV50_SU_MAX_TEMP 64 35//#define NV50_PROGRAM_DUMP 36 37/* ARL - gallium craps itself on progs/vp/arl.txt 38 * 39 * MSB - Like MAD, but MUL+SUB 40 * - Fuck it off, introduce a way to negate args for ops that 41 * support it. 42 * 43 * Look into inlining IMMD for ops other than MOV (make it general?) 44 * - Maybe even relax restrictions a bit, can't do P_RESULT + P_IMMD, 45 * but can emit to P_TEMP first - then MOV later. NVIDIA does this 46 * 47 * In ops such as ADD it's possible to construct a bad opcode in the !is_long() 48 * case, if the emit_src() causes the inst to suddenly become long. 49 * 50 * Verify half-insns work where expected - and force disable them where they 51 * don't work - MUL has it forcibly disabled atm as it fixes POW.. 52 * 53 * FUCK! watch dst==src vectors, can overwrite components that are needed. 54 * ie. SUB R0, R0.yzxw, R0 55 * 56 * Things to check with renouveau: 57 * FP attr/result assignment - how? 58 * attrib 59 * - 0x16bc maps vp output onto fp hpos 60 * - 0x16c0 maps vp output onto fp col0 61 * result 62 * - colr always 0-3 63 * - depr always 4 64 * 0x16bc->0x16e8 --> some binding between vp/fp regs 65 * 0x16b8 --> VP output count 66 * 67 * 0x1298 --> "MOV rcol.x, fcol.y" "MOV depr, fcol.y" = 0x00000005 68 * "MOV rcol.x, fcol.y" = 0x00000004 69 * 0x19a8 --> as above but 0x00000100 and 0x00000000 70 * - 0x00100000 used when KIL used 71 * 0x196c --> as above but 0x00000011 and 0x00000000 72 * 73 * 0x1988 --> 0xXXNNNNNN 74 * - XX == FP high something 75 */ 76struct nv50_reg { 77 enum { 78 P_TEMP, 79 P_ATTR, 80 P_RESULT, 81 P_CONST, 82 P_IMMD 83 } type; 84 int index; 85 86 int hw; 87 int neg; 88 89 int rhw; /* result hw for FP outputs, or interpolant index */ 90 int acc; /* instruction where this reg is last read (first insn == 1) */ 91}; 92 93/* arbitrary limits */ 94#define MAX_IF_DEPTH 4 95#define MAX_LOOP_DEPTH 4 96 97struct nv50_pc { 98 struct nv50_program *p; 99 100 /* hw resources */ 101 struct nv50_reg *r_temp[NV50_SU_MAX_TEMP]; 102 103 /* tgsi resources */ 104 struct nv50_reg *temp; 105 int temp_nr; 106 struct nv50_reg *attr; 107 int attr_nr; 108 struct nv50_reg *result; 109 int result_nr; 110 struct nv50_reg *param; 111 int param_nr; 112 struct nv50_reg *immd; 113 float *immd_buf; 114 int immd_nr; 115 116 struct nv50_reg *temp_temp[16]; 117 unsigned temp_temp_nr; 118 119 /* broadcast and destination replacement regs */ 120 struct nv50_reg *r_brdc; 121 struct nv50_reg *r_dst[4]; 122 123 unsigned interp_mode[32]; 124 /* perspective interpolation registers */ 125 struct nv50_reg *iv_p; 126 struct nv50_reg *iv_c; 127 128 struct nv50_program_exec *if_cond; 129 struct nv50_program_exec *if_insn[MAX_IF_DEPTH]; 130 struct nv50_program_exec *br_join[MAX_IF_DEPTH]; 131 struct nv50_program_exec *br_loop[MAX_LOOP_DEPTH]; /* for BRK branch */ 132 int if_lvl, loop_lvl; 133 unsigned loop_pos[MAX_LOOP_DEPTH]; 134 135 /* current instruction and total number of insns */ 136 unsigned insn_cur; 137 unsigned insn_nr; 138 139 boolean allow32; 140}; 141 142static INLINE void 143ctor_reg(struct nv50_reg *reg, unsigned type, int index, int hw) 144{ 145 reg->type = type; 146 reg->index = index; 147 reg->hw = hw; 148 reg->neg = 0; 149 reg->rhw = -1; 150 reg->acc = 0; 151} 152 153static INLINE unsigned 154popcnt4(uint32_t val) 155{ 156 static const unsigned cnt[16] 157 = { 0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4 }; 158 return cnt[val & 0xf]; 159} 160 161static void 162alloc_reg(struct nv50_pc *pc, struct nv50_reg *reg) 163{ 164 int i = 0; 165 166 if (reg->type == P_RESULT) { 167 if (pc->p->cfg.high_result < (reg->hw + 1)) 168 pc->p->cfg.high_result = reg->hw + 1; 169 } 170 171 if (reg->type != P_TEMP) 172 return; 173 174 if (reg->hw >= 0) { 175 /*XXX: do this here too to catch FP temp-as-attr usage.. 176 * not clean, but works */ 177 if (pc->p->cfg.high_temp < (reg->hw + 1)) 178 pc->p->cfg.high_temp = reg->hw + 1; 179 return; 180 } 181 182 if (reg->rhw != -1) { 183 /* try to allocate temporary with index rhw first */ 184 if (!(pc->r_temp[reg->rhw])) { 185 pc->r_temp[reg->rhw] = reg; 186 reg->hw = reg->rhw; 187 if (pc->p->cfg.high_temp < (reg->rhw + 1)) 188 pc->p->cfg.high_temp = reg->rhw + 1; 189 return; 190 } 191 /* make sure we don't get things like $r0 needs to go 192 * in $r1 and $r1 in $r0 193 */ 194 i = pc->result_nr * 4; 195 } 196 197 for (; i < NV50_SU_MAX_TEMP; i++) { 198 if (!(pc->r_temp[i])) { 199 pc->r_temp[i] = reg; 200 reg->hw = i; 201 if (pc->p->cfg.high_temp < (i + 1)) 202 pc->p->cfg.high_temp = i + 1; 203 return; 204 } 205 } 206 207 assert(0); 208} 209 210/* XXX: For shaders that aren't executed linearly (e.g. shaders that 211 * contain loops), we need to assign all hw regs to TGSI TEMPs early, 212 * lest we risk temp_temps overwriting regs alloc'd "later". 213 */ 214static struct nv50_reg * 215alloc_temp(struct nv50_pc *pc, struct nv50_reg *dst) 216{ 217 struct nv50_reg *r; 218 int i; 219 220 if (dst && dst->type == P_TEMP && dst->hw == -1) 221 return dst; 222 223 for (i = 0; i < NV50_SU_MAX_TEMP; i++) { 224 if (!pc->r_temp[i]) { 225 r = MALLOC_STRUCT(nv50_reg); 226 ctor_reg(r, P_TEMP, -1, i); 227 pc->r_temp[i] = r; 228 return r; 229 } 230 } 231 232 assert(0); 233 return NULL; 234} 235 236/* Assign the hw of the discarded temporary register src 237 * to the tgsi register dst and free src. 238 */ 239static void 240assimilate_temp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 241{ 242 assert(src->index == -1 && src->hw != -1); 243 244 if (dst->hw != -1) 245 pc->r_temp[dst->hw] = NULL; 246 pc->r_temp[src->hw] = dst; 247 dst->hw = src->hw; 248 249 FREE(src); 250} 251 252/* release the hardware resource held by r */ 253static void 254release_hw(struct nv50_pc *pc, struct nv50_reg *r) 255{ 256 assert(r->type == P_TEMP); 257 if (r->hw == -1) 258 return; 259 260 assert(pc->r_temp[r->hw] == r); 261 pc->r_temp[r->hw] = NULL; 262 263 r->acc = 0; 264 if (r->index == -1) 265 FREE(r); 266} 267 268static void 269free_temp(struct nv50_pc *pc, struct nv50_reg *r) 270{ 271 if (r->index == -1) { 272 unsigned hw = r->hw; 273 274 FREE(pc->r_temp[hw]); 275 pc->r_temp[hw] = NULL; 276 } 277} 278 279static int 280alloc_temp4(struct nv50_pc *pc, struct nv50_reg *dst[4], int idx) 281{ 282 int i; 283 284 if ((idx + 4) >= NV50_SU_MAX_TEMP) 285 return 1; 286 287 if (pc->r_temp[idx] || pc->r_temp[idx + 1] || 288 pc->r_temp[idx + 2] || pc->r_temp[idx + 3]) 289 return alloc_temp4(pc, dst, idx + 4); 290 291 for (i = 0; i < 4; i++) { 292 dst[i] = MALLOC_STRUCT(nv50_reg); 293 ctor_reg(dst[i], P_TEMP, -1, idx + i); 294 pc->r_temp[idx + i] = dst[i]; 295 } 296 297 return 0; 298} 299 300static void 301free_temp4(struct nv50_pc *pc, struct nv50_reg *reg[4]) 302{ 303 int i; 304 305 for (i = 0; i < 4; i++) 306 free_temp(pc, reg[i]); 307} 308 309static struct nv50_reg * 310temp_temp(struct nv50_pc *pc) 311{ 312 if (pc->temp_temp_nr >= 16) 313 assert(0); 314 315 pc->temp_temp[pc->temp_temp_nr] = alloc_temp(pc, NULL); 316 return pc->temp_temp[pc->temp_temp_nr++]; 317} 318 319static void 320kill_temp_temp(struct nv50_pc *pc) 321{ 322 int i; 323 324 for (i = 0; i < pc->temp_temp_nr; i++) 325 free_temp(pc, pc->temp_temp[i]); 326 pc->temp_temp_nr = 0; 327} 328 329static int 330ctor_immd(struct nv50_pc *pc, float x, float y, float z, float w) 331{ 332 pc->immd_buf = REALLOC(pc->immd_buf, (pc->immd_nr * 4 * sizeof(float)), 333 (pc->immd_nr + 1) * 4 * sizeof(float)); 334 pc->immd_buf[(pc->immd_nr * 4) + 0] = x; 335 pc->immd_buf[(pc->immd_nr * 4) + 1] = y; 336 pc->immd_buf[(pc->immd_nr * 4) + 2] = z; 337 pc->immd_buf[(pc->immd_nr * 4) + 3] = w; 338 339 return pc->immd_nr++; 340} 341 342static struct nv50_reg * 343alloc_immd(struct nv50_pc *pc, float f) 344{ 345 struct nv50_reg *r = MALLOC_STRUCT(nv50_reg); 346 unsigned hw; 347 348 for (hw = 0; hw < pc->immd_nr * 4; hw++) 349 if (pc->immd_buf[hw] == f) 350 break; 351 352 if (hw == pc->immd_nr * 4) 353 hw = ctor_immd(pc, f, -f, 0.5 * f, 0) * 4; 354 355 ctor_reg(r, P_IMMD, -1, hw); 356 return r; 357} 358 359static struct nv50_program_exec * 360exec(struct nv50_pc *pc) 361{ 362 struct nv50_program_exec *e = CALLOC_STRUCT(nv50_program_exec); 363 364 e->param.index = -1; 365 return e; 366} 367 368static void 369emit(struct nv50_pc *pc, struct nv50_program_exec *e) 370{ 371 struct nv50_program *p = pc->p; 372 373 if (p->exec_tail) 374 p->exec_tail->next = e; 375 if (!p->exec_head) 376 p->exec_head = e; 377 p->exec_tail = e; 378 p->exec_size += (e->inst[0] & 1) ? 2 : 1; 379} 380 381static INLINE void set_long(struct nv50_pc *, struct nv50_program_exec *); 382 383static boolean 384is_long(struct nv50_program_exec *e) 385{ 386 if (e->inst[0] & 1) 387 return TRUE; 388 return FALSE; 389} 390 391static boolean 392is_immd(struct nv50_program_exec *e) 393{ 394 if (is_long(e) && (e->inst[1] & 3) == 3) 395 return TRUE; 396 return FALSE; 397} 398 399static INLINE void 400set_pred(struct nv50_pc *pc, unsigned pred, unsigned idx, 401 struct nv50_program_exec *e) 402{ 403 set_long(pc, e); 404 e->inst[1] &= ~((0x1f << 7) | (0x3 << 12)); 405 e->inst[1] |= (pred << 7) | (idx << 12); 406} 407 408static INLINE void 409set_pred_wr(struct nv50_pc *pc, unsigned on, unsigned idx, 410 struct nv50_program_exec *e) 411{ 412 set_long(pc, e); 413 e->inst[1] &= ~((0x3 << 4) | (1 << 6)); 414 e->inst[1] |= (idx << 4) | (on << 6); 415} 416 417static INLINE void 418set_long(struct nv50_pc *pc, struct nv50_program_exec *e) 419{ 420 if (is_long(e)) 421 return; 422 423 e->inst[0] |= 1; 424 set_pred(pc, 0xf, 0, e); 425 set_pred_wr(pc, 0, 0, e); 426} 427 428static INLINE void 429set_dst(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_program_exec *e) 430{ 431 if (dst->type == P_RESULT) { 432 set_long(pc, e); 433 e->inst[1] |= 0x00000008; 434 } 435 436 alloc_reg(pc, dst); 437 e->inst[0] |= (dst->hw << 2); 438} 439 440static INLINE void 441set_immd(struct nv50_pc *pc, struct nv50_reg *imm, struct nv50_program_exec *e) 442{ 443 float f = pc->immd_buf[imm->hw]; 444 unsigned val = fui(imm->neg ? -f : f); 445 446 set_long(pc, e); 447 /*XXX: can't be predicated - bits overlap.. catch cases where both 448 * are required and avoid them. */ 449 set_pred(pc, 0, 0, e); 450 set_pred_wr(pc, 0, 0, e); 451 452 e->inst[1] |= 0x00000002 | 0x00000001; 453 e->inst[0] |= (val & 0x3f) << 16; 454 e->inst[1] |= (val >> 6) << 2; 455} 456 457 458#define INTERP_LINEAR 0 459#define INTERP_FLAT 1 460#define INTERP_PERSPECTIVE 2 461#define INTERP_CENTROID 4 462 463/* interpolant index has been stored in dst->rhw */ 464static void 465emit_interp(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *iv, 466 unsigned mode) 467{ 468 assert(dst->rhw != -1); 469 struct nv50_program_exec *e = exec(pc); 470 471 e->inst[0] |= 0x80000000; 472 set_dst(pc, dst, e); 473 e->inst[0] |= (dst->rhw << 16); 474 475 if (mode & INTERP_FLAT) { 476 e->inst[0] |= (1 << 8); 477 } else { 478 if (mode & INTERP_PERSPECTIVE) { 479 e->inst[0] |= (1 << 25); 480 alloc_reg(pc, iv); 481 e->inst[0] |= (iv->hw << 9); 482 } 483 484 if (mode & INTERP_CENTROID) 485 e->inst[0] |= (1 << 24); 486 } 487 488 emit(pc, e); 489} 490 491static void 492set_data(struct nv50_pc *pc, struct nv50_reg *src, unsigned m, unsigned s, 493 struct nv50_program_exec *e) 494{ 495 set_long(pc, e); 496 497 e->param.index = src->hw; 498 e->param.shift = s; 499 e->param.mask = m << (s % 32); 500 501 e->inst[1] |= (((src->type == P_IMMD) ? 0 : 1) << 22); 502} 503 504static void 505emit_mov(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 506{ 507 struct nv50_program_exec *e = exec(pc); 508 509 e->inst[0] |= 0x10000000; 510 511 set_dst(pc, dst, e); 512 513 if (pc->allow32 && dst->type != P_RESULT && src->type == P_IMMD) { 514 set_immd(pc, src, e); 515 /*XXX: 32-bit, but steals part of "half" reg space - need to 516 * catch and handle this case if/when we do half-regs 517 */ 518 } else 519 if (src->type == P_IMMD || src->type == P_CONST) { 520 set_long(pc, e); 521 set_data(pc, src, 0x7f, 9, e); 522 e->inst[1] |= 0x20000000; /* src0 const? */ 523 } else { 524 if (src->type == P_ATTR) { 525 set_long(pc, e); 526 e->inst[1] |= 0x00200000; 527 } 528 529 alloc_reg(pc, src); 530 e->inst[0] |= (src->hw << 9); 531 } 532 533 if (is_long(e) && !is_immd(e)) { 534 e->inst[1] |= 0x04000000; /* 32-bit */ 535 e->inst[1] |= 0x0000c000; /* "subsubop" 0x3 */ 536 if (!(e->inst[1] & 0x20000000)) 537 e->inst[1] |= 0x00030000; /* "subsubop" 0xf */ 538 } else 539 e->inst[0] |= 0x00008000; 540 541 emit(pc, e); 542} 543 544static INLINE void 545emit_mov_immdval(struct nv50_pc *pc, struct nv50_reg *dst, float f) 546{ 547 struct nv50_reg *imm = alloc_immd(pc, f); 548 emit_mov(pc, dst, imm); 549 FREE(imm); 550} 551 552static boolean 553check_swap_src_0_1(struct nv50_pc *pc, 554 struct nv50_reg **s0, struct nv50_reg **s1) 555{ 556 struct nv50_reg *src0 = *s0, *src1 = *s1; 557 558 if (src0->type == P_CONST) { 559 if (src1->type != P_CONST) { 560 *s0 = src1; 561 *s1 = src0; 562 return TRUE; 563 } 564 } else 565 if (src1->type == P_ATTR) { 566 if (src0->type != P_ATTR) { 567 *s0 = src1; 568 *s1 = src0; 569 return TRUE; 570 } 571 } 572 573 return FALSE; 574} 575 576static void 577set_src_0_restricted(struct nv50_pc *pc, struct nv50_reg *src, 578 struct nv50_program_exec *e) 579{ 580 struct nv50_reg *temp; 581 582 if (src->type != P_TEMP) { 583 temp = temp_temp(pc); 584 emit_mov(pc, temp, src); 585 src = temp; 586 } 587 588 alloc_reg(pc, src); 589 e->inst[0] |= (src->hw << 9); 590} 591 592static void 593set_src_0(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e) 594{ 595 if (src->type == P_ATTR) { 596 set_long(pc, e); 597 e->inst[1] |= 0x00200000; 598 } else 599 if (src->type == P_CONST || src->type == P_IMMD) { 600 struct nv50_reg *temp = temp_temp(pc); 601 602 emit_mov(pc, temp, src); 603 src = temp; 604 } 605 606 alloc_reg(pc, src); 607 e->inst[0] |= (src->hw << 9); 608} 609 610static void 611set_src_1(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e) 612{ 613 if (src->type == P_ATTR) { 614 struct nv50_reg *temp = temp_temp(pc); 615 616 emit_mov(pc, temp, src); 617 src = temp; 618 } else 619 if (src->type == P_CONST || src->type == P_IMMD) { 620 assert(!(e->inst[0] & 0x00800000)); 621 if (e->inst[0] & 0x01000000) { 622 struct nv50_reg *temp = temp_temp(pc); 623 624 emit_mov(pc, temp, src); 625 src = temp; 626 } else { 627 set_data(pc, src, 0x7f, 16, e); 628 e->inst[0] |= 0x00800000; 629 } 630 } 631 632 alloc_reg(pc, src); 633 e->inst[0] |= (src->hw << 16); 634} 635 636static void 637set_src_2(struct nv50_pc *pc, struct nv50_reg *src, struct nv50_program_exec *e) 638{ 639 set_long(pc, e); 640 641 if (src->type == P_ATTR) { 642 struct nv50_reg *temp = temp_temp(pc); 643 644 emit_mov(pc, temp, src); 645 src = temp; 646 } else 647 if (src->type == P_CONST || src->type == P_IMMD) { 648 assert(!(e->inst[0] & 0x01000000)); 649 if (e->inst[0] & 0x00800000) { 650 struct nv50_reg *temp = temp_temp(pc); 651 652 emit_mov(pc, temp, src); 653 src = temp; 654 } else { 655 set_data(pc, src, 0x7f, 32+14, e); 656 e->inst[0] |= 0x01000000; 657 } 658 } 659 660 alloc_reg(pc, src); 661 e->inst[1] |= (src->hw << 14); 662} 663 664static void 665emit_mul(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0, 666 struct nv50_reg *src1) 667{ 668 struct nv50_program_exec *e = exec(pc); 669 670 e->inst[0] |= 0xc0000000; 671 672 if (!pc->allow32) 673 set_long(pc, e); 674 675 check_swap_src_0_1(pc, &src0, &src1); 676 set_dst(pc, dst, e); 677 set_src_0(pc, src0, e); 678 if (src1->type == P_IMMD && !is_long(e)) { 679 if (src0->neg) 680 e->inst[0] |= 0x00008000; 681 set_immd(pc, src1, e); 682 } else { 683 set_src_1(pc, src1, e); 684 if (src0->neg ^ src1->neg) { 685 if (is_long(e)) 686 e->inst[1] |= 0x08000000; 687 else 688 e->inst[0] |= 0x00008000; 689 } 690 } 691 692 emit(pc, e); 693} 694 695static void 696emit_add(struct nv50_pc *pc, struct nv50_reg *dst, 697 struct nv50_reg *src0, struct nv50_reg *src1) 698{ 699 struct nv50_program_exec *e = exec(pc); 700 701 e->inst[0] |= 0xb0000000; 702 703 check_swap_src_0_1(pc, &src0, &src1); 704 705 if (!pc->allow32 || src0->neg || src1->neg) { 706 set_long(pc, e); 707 e->inst[1] |= (src0->neg << 26) | (src1->neg << 27); 708 } 709 710 set_dst(pc, dst, e); 711 set_src_0(pc, src0, e); 712 if (src1->type == P_CONST || src1->type == P_ATTR || is_long(e)) 713 set_src_2(pc, src1, e); 714 else 715 if (src1->type == P_IMMD) 716 set_immd(pc, src1, e); 717 else 718 set_src_1(pc, src1, e); 719 720 emit(pc, e); 721} 722 723static void 724emit_minmax(struct nv50_pc *pc, unsigned sub, struct nv50_reg *dst, 725 struct nv50_reg *src0, struct nv50_reg *src1) 726{ 727 struct nv50_program_exec *e = exec(pc); 728 729 set_long(pc, e); 730 e->inst[0] |= 0xb0000000; 731 e->inst[1] |= (sub << 29); 732 733 check_swap_src_0_1(pc, &src0, &src1); 734 set_dst(pc, dst, e); 735 set_src_0(pc, src0, e); 736 set_src_1(pc, src1, e); 737 738 emit(pc, e); 739} 740 741static INLINE void 742emit_sub(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0, 743 struct nv50_reg *src1) 744{ 745 src1->neg ^= 1; 746 emit_add(pc, dst, src0, src1); 747 src1->neg ^= 1; 748} 749 750static void 751emit_mad(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0, 752 struct nv50_reg *src1, struct nv50_reg *src2) 753{ 754 struct nv50_program_exec *e = exec(pc); 755 756 e->inst[0] |= 0xe0000000; 757 758 check_swap_src_0_1(pc, &src0, &src1); 759 set_dst(pc, dst, e); 760 set_src_0(pc, src0, e); 761 set_src_1(pc, src1, e); 762 set_src_2(pc, src2, e); 763 764 if (src0->neg ^ src1->neg) 765 e->inst[1] |= 0x04000000; 766 if (src2->neg) 767 e->inst[1] |= 0x08000000; 768 769 emit(pc, e); 770} 771 772static INLINE void 773emit_msb(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src0, 774 struct nv50_reg *src1, struct nv50_reg *src2) 775{ 776 src2->neg ^= 1; 777 emit_mad(pc, dst, src0, src1, src2); 778 src2->neg ^= 1; 779} 780 781static void 782emit_flop(struct nv50_pc *pc, unsigned sub, 783 struct nv50_reg *dst, struct nv50_reg *src) 784{ 785 struct nv50_program_exec *e = exec(pc); 786 787 e->inst[0] |= 0x90000000; 788 if (sub) { 789 set_long(pc, e); 790 e->inst[1] |= (sub << 29); 791 } 792 793 set_dst(pc, dst, e); 794 795 if (sub == 0 || sub == 2) 796 set_src_0_restricted(pc, src, e); 797 else 798 set_src_0(pc, src, e); 799 800 emit(pc, e); 801} 802 803static void 804emit_preex2(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 805{ 806 struct nv50_program_exec *e = exec(pc); 807 808 e->inst[0] |= 0xb0000000; 809 810 set_dst(pc, dst, e); 811 set_src_0(pc, src, e); 812 set_long(pc, e); 813 e->inst[1] |= (6 << 29) | 0x00004000; 814 815 emit(pc, e); 816} 817 818static void 819emit_precossin(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 820{ 821 struct nv50_program_exec *e = exec(pc); 822 823 e->inst[0] |= 0xb0000000; 824 825 set_dst(pc, dst, e); 826 set_src_0(pc, src, e); 827 set_long(pc, e); 828 e->inst[1] |= (6 << 29); 829 830 emit(pc, e); 831} 832 833#define CVTOP_RN 0x01 834#define CVTOP_FLOOR 0x03 835#define CVTOP_CEIL 0x05 836#define CVTOP_TRUNC 0x07 837#define CVTOP_SAT 0x08 838#define CVTOP_ABS 0x10 839 840/* 0x04 == 32 bit */ 841/* 0x40 == dst is float */ 842/* 0x80 == src is float */ 843#define CVT_F32_F32 0xc4 844#define CVT_F32_S32 0x44 845#define CVT_F32_U32 0x64 846#define CVT_S32_F32 0x8c 847#define CVT_S32_S32 0x0c 848#define CVT_NEG 0x20 849#define CVT_RI 0x08 850 851static void 852emit_cvt(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src, 853 int wp, unsigned cvn, unsigned fmt) 854{ 855 struct nv50_program_exec *e; 856 857 e = exec(pc); 858 set_long(pc, e); 859 860 e->inst[0] |= 0xa0000000; 861 e->inst[1] |= 0x00004000; 862 e->inst[1] |= (cvn << 16); 863 e->inst[1] |= (fmt << 24); 864 set_src_0(pc, src, e); 865 866 if (wp >= 0) 867 set_pred_wr(pc, 1, wp, e); 868 869 if (dst) 870 set_dst(pc, dst, e); 871 else { 872 e->inst[0] |= 0x000001fc; 873 e->inst[1] |= 0x00000008; 874 } 875 876 emit(pc, e); 877} 878 879/* nv50 Condition codes: 880 * 0x1 = LT 881 * 0x2 = EQ 882 * 0x3 = LE 883 * 0x4 = GT 884 * 0x5 = NE 885 * 0x6 = GE 886 * 0x7 = set condition code ? (used before bra.lt/le/gt/ge) 887 * 0x8 = unordered bit (allows NaN) 888 */ 889static void 890emit_set(struct nv50_pc *pc, unsigned ccode, struct nv50_reg *dst, int wp, 891 struct nv50_reg *src0, struct nv50_reg *src1) 892{ 893 static const unsigned cc_swapped[8] = { 0, 4, 2, 6, 1, 5, 3, 7 }; 894 895 struct nv50_program_exec *e = exec(pc); 896 struct nv50_reg *rdst; 897 898 assert(ccode < 16); 899 if (check_swap_src_0_1(pc, &src0, &src1)) 900 ccode = cc_swapped[ccode & 7] | (ccode & 8); 901 902 rdst = dst; 903 if (dst && dst->type != P_TEMP) 904 dst = alloc_temp(pc, NULL); 905 906 /* set.u32 */ 907 set_long(pc, e); 908 e->inst[0] |= 0xb0000000; 909 e->inst[1] |= 0x60000000 | (ccode << 14); 910 911 /* XXX: decuda will disasm as .u16 and use .lo/.hi regs, but 912 * that doesn't seem to match what the hw actually does 913 e->inst[1] |= 0x04000000; << breaks things, u32 by default ? 914 */ 915 916 if (wp >= 0) 917 set_pred_wr(pc, 1, wp, e); 918 if (dst) 919 set_dst(pc, dst, e); 920 else { 921 e->inst[0] |= 0x000001fc; 922 e->inst[1] |= 0x00000008; 923 } 924 925 set_src_0(pc, src0, e); 926 set_src_1(pc, src1, e); 927 928 emit(pc, e); 929 pc->if_cond = pc->p->exec_tail; /* record for OPCODE_IF */ 930 931 /* cvt.f32.u32/s32 (?) if we didn't only write the predicate */ 932 if (rdst) 933 emit_cvt(pc, rdst, dst, -1, CVTOP_ABS | CVTOP_RN, CVT_F32_S32); 934 if (rdst && rdst != dst) 935 free_temp(pc, dst); 936} 937 938static INLINE unsigned 939map_tgsi_setop_cc(unsigned op) 940{ 941 switch (op) { 942 case TGSI_OPCODE_SLT: return 0x1; 943 case TGSI_OPCODE_SGE: return 0x6; 944 case TGSI_OPCODE_SEQ: return 0x2; 945 case TGSI_OPCODE_SGT: return 0x4; 946 case TGSI_OPCODE_SLE: return 0x3; 947 case TGSI_OPCODE_SNE: return 0xd; 948 default: 949 assert(0); 950 return 0; 951 } 952} 953 954static INLINE void 955emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 956{ 957 emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32 | CVT_RI); 958} 959 960static void 961emit_pow(struct nv50_pc *pc, struct nv50_reg *dst, 962 struct nv50_reg *v, struct nv50_reg *e) 963{ 964 struct nv50_reg *temp = alloc_temp(pc, NULL); 965 966 emit_flop(pc, 3, temp, v); 967 emit_mul(pc, temp, temp, e); 968 emit_preex2(pc, temp, temp); 969 emit_flop(pc, 6, dst, temp); 970 971 free_temp(pc, temp); 972} 973 974static INLINE void 975emit_abs(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 976{ 977 emit_cvt(pc, dst, src, -1, CVTOP_ABS, CVT_F32_F32); 978} 979 980static INLINE void 981emit_sat(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 982{ 983 emit_cvt(pc, dst, src, -1, CVTOP_SAT, CVT_F32_F32); 984} 985 986static void 987emit_lit(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask, 988 struct nv50_reg **src) 989{ 990 struct nv50_reg *one = alloc_immd(pc, 1.0); 991 struct nv50_reg *zero = alloc_immd(pc, 0.0); 992 struct nv50_reg *neg128 = alloc_immd(pc, -127.999999); 993 struct nv50_reg *pos128 = alloc_immd(pc, 127.999999); 994 struct nv50_reg *tmp[4]; 995 boolean allow32 = pc->allow32; 996 997 pc->allow32 = FALSE; 998 999 if (mask & (3 << 1)) { 1000 tmp[0] = alloc_temp(pc, NULL); 1001 emit_minmax(pc, 4, tmp[0], src[0], zero); 1002 } 1003 1004 if (mask & (1 << 2)) { 1005 set_pred_wr(pc, 1, 0, pc->p->exec_tail); 1006 1007 tmp[1] = temp_temp(pc); 1008 emit_minmax(pc, 4, tmp[1], src[1], zero); 1009 1010 tmp[3] = temp_temp(pc); 1011 emit_minmax(pc, 4, tmp[3], src[3], neg128); 1012 emit_minmax(pc, 5, tmp[3], tmp[3], pos128); 1013 1014 emit_pow(pc, dst[2], tmp[1], tmp[3]); 1015 emit_mov(pc, dst[2], zero); 1016 set_pred(pc, 3, 0, pc->p->exec_tail); 1017 } 1018 1019 if (mask & (1 << 1)) 1020 assimilate_temp(pc, dst[1], tmp[0]); 1021 else 1022 if (mask & (1 << 2)) 1023 free_temp(pc, tmp[0]); 1024 1025 pc->allow32 = allow32; 1026 1027 /* do this last, in case src[i,j] == dst[0,3] */ 1028 if (mask & (1 << 0)) 1029 emit_mov(pc, dst[0], one); 1030 1031 if (mask & (1 << 3)) 1032 emit_mov(pc, dst[3], one); 1033 1034 FREE(pos128); 1035 FREE(neg128); 1036 FREE(zero); 1037 FREE(one); 1038} 1039 1040static void 1041emit_neg(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src) 1042{ 1043 struct nv50_program_exec *e = exec(pc); 1044 1045 set_long(pc, e); 1046 e->inst[0] |= 0xa0000000; /* delta */ 1047 e->inst[1] |= (7 << 29); /* delta */ 1048 e->inst[1] |= 0x04000000; /* negate arg0? probably not */ 1049 e->inst[1] |= (1 << 14); /* src .f32 */ 1050 set_dst(pc, dst, e); 1051 set_src_0(pc, src, e); 1052 1053 emit(pc, e); 1054} 1055 1056static void 1057emit_kil(struct nv50_pc *pc, struct nv50_reg *src) 1058{ 1059 struct nv50_program_exec *e; 1060 const int r_pred = 1; 1061 1062 /* Sets predicate reg ? */ 1063 e = exec(pc); 1064 e->inst[0] = 0xa00001fd; 1065 e->inst[1] = 0xc4014788; 1066 set_src_0(pc, src, e); 1067 set_pred_wr(pc, 1, r_pred, e); 1068 if (src->neg) 1069 e->inst[1] |= 0x20000000; 1070 emit(pc, e); 1071 1072 /* This is probably KILP */ 1073 e = exec(pc); 1074 e->inst[0] = 0x000001fe; 1075 set_long(pc, e); 1076 set_pred(pc, 1 /* LT? */, r_pred, e); 1077 emit(pc, e); 1078} 1079 1080static void 1081emit_tex(struct nv50_pc *pc, struct nv50_reg **dst, unsigned mask, 1082 struct nv50_reg **src, unsigned unit, unsigned type, boolean proj) 1083{ 1084 struct nv50_reg *temp, *t[4]; 1085 struct nv50_program_exec *e; 1086 1087 unsigned c, mode, dim; 1088 1089 switch (type) { 1090 case TGSI_TEXTURE_1D: 1091 dim = 1; 1092 break; 1093 case TGSI_TEXTURE_UNKNOWN: 1094 case TGSI_TEXTURE_2D: 1095 case TGSI_TEXTURE_SHADOW1D: /* XXX: x, z */ 1096 case TGSI_TEXTURE_RECT: 1097 dim = 2; 1098 break; 1099 case TGSI_TEXTURE_3D: 1100 case TGSI_TEXTURE_CUBE: 1101 case TGSI_TEXTURE_SHADOW2D: 1102 case TGSI_TEXTURE_SHADOWRECT: /* XXX */ 1103 dim = 3; 1104 break; 1105 default: 1106 assert(0); 1107 break; 1108 } 1109 1110 /* some cards need t[0]'s hw index to be a multiple of 4 */ 1111 alloc_temp4(pc, t, 0); 1112 1113 if (proj) { 1114 if (src[0]->type == P_TEMP && src[0]->rhw != -1) { 1115 mode = pc->interp_mode[src[0]->index]; 1116 1117 t[3]->rhw = src[3]->rhw; 1118 emit_interp(pc, t[3], NULL, (mode & INTERP_CENTROID)); 1119 emit_flop(pc, 0, t[3], t[3]); 1120 1121 for (c = 0; c < dim; c++) { 1122 t[c]->rhw = src[c]->rhw; 1123 emit_interp(pc, t[c], t[3], 1124 (mode | INTERP_PERSPECTIVE)); 1125 } 1126 } else { 1127 emit_flop(pc, 0, t[3], src[3]); 1128 for (c = 0; c < dim; c++) 1129 emit_mul(pc, t[c], src[c], t[3]); 1130 1131 /* XXX: for some reason the blob sometimes uses MAD: 1132 * emit_mad(pc, t[c], src[0][c], t[3], t[3]) 1133 * pc->p->exec_tail->inst[1] |= 0x080fc000; 1134 */ 1135 } 1136 } else { 1137 if (type == TGSI_TEXTURE_CUBE) { 1138 temp = temp_temp(pc); 1139 emit_minmax(pc, 4, temp, src[0], src[1]); 1140 emit_minmax(pc, 4, temp, temp, src[2]); 1141 emit_flop(pc, 0, temp, temp); 1142 for (c = 0; c < 3; c++) 1143 emit_mul(pc, t[c], src[c], temp); 1144 } else { 1145 for (c = 0; c < dim; c++) 1146 emit_mov(pc, t[c], src[c]); 1147 } 1148 } 1149 1150 e = exec(pc); 1151 set_long(pc, e); 1152 e->inst[0] |= 0xf0000000; 1153 e->inst[1] |= 0x00000004; 1154 set_dst(pc, t[0], e); 1155 e->inst[0] |= (unit << 9); 1156 1157 if (dim == 2) 1158 e->inst[0] |= 0x00400000; 1159 else 1160 if (dim == 3) 1161 e->inst[0] |= 0x00800000; 1162 1163 e->inst[0] |= (mask & 0x3) << 25; 1164 e->inst[1] |= (mask & 0xc) << 12; 1165 1166 emit(pc, e); 1167 1168#if 1 1169 if (mask & 1) emit_mov(pc, dst[0], t[0]); 1170 if (mask & 2) emit_mov(pc, dst[1], t[1]); 1171 if (mask & 4) emit_mov(pc, dst[2], t[2]); 1172 if (mask & 8) emit_mov(pc, dst[3], t[3]); 1173 1174 free_temp4(pc, t); 1175#else 1176 /* XXX: if p.e. MUL is used directly after TEX, it would still use 1177 * the texture coordinates, not the fetched values: latency ? */ 1178 1179 for (c = 0; c < 4; c++) { 1180 if (mask & (1 << c)) 1181 assimilate_temp(pc, dst[c], t[c]); 1182 else 1183 free_temp(pc, t[c]); 1184 } 1185#endif 1186} 1187 1188static void 1189emit_branch(struct nv50_pc *pc, int pred, unsigned cc, 1190 struct nv50_program_exec **join) 1191{ 1192 struct nv50_program_exec *e = exec(pc); 1193 1194 if (join) { 1195 set_long(pc, e); 1196 e->inst[0] |= 0xa0000002; 1197 emit(pc, e); 1198 *join = e; 1199 e = exec(pc); 1200 } 1201 1202 set_long(pc, e); 1203 e->inst[0] |= 0x10000002; 1204 if (pred >= 0) 1205 set_pred(pc, cc, pred, e); 1206 emit(pc, e); 1207} 1208 1209static void 1210emit_nop(struct nv50_pc *pc) 1211{ 1212 struct nv50_program_exec *e = exec(pc); 1213 1214 e->inst[0] = 0xf0000000; 1215 set_long(pc, e); 1216 e->inst[1] = 0xe0000000; 1217 emit(pc, e); 1218} 1219 1220static void 1221convert_to_long(struct nv50_pc *pc, struct nv50_program_exec *e) 1222{ 1223 unsigned q = 0, m = ~0; 1224 1225 assert(!is_long(e)); 1226 1227 switch (e->inst[0] >> 28) { 1228 case 0x1: 1229 /* MOV */ 1230 q = 0x0403c000; 1231 m = 0xffff7fff; 1232 break; 1233 case 0x8: 1234 /* INTERP (move centroid, perspective and flat bits) */ 1235 m = ~0x03000100; 1236 q = (e->inst[0] & (3 << 24)) >> (24 - 16); 1237 q |= (e->inst[0] & (1 << 8)) << (18 - 8); 1238 break; 1239 case 0x9: 1240 /* RCP */ 1241 break; 1242 case 0xB: 1243 /* ADD */ 1244 m = ~(127 << 16); 1245 q = ((e->inst[0] & (~m)) >> 2); 1246 break; 1247 case 0xC: 1248 /* MUL */ 1249 m = ~0x00008000; 1250 q = ((e->inst[0] & (~m)) << 12); 1251 break; 1252 case 0xE: 1253 /* MAD (if src2 == dst) */ 1254 q = ((e->inst[0] & 0x1fc) << 12); 1255 break; 1256 default: 1257 assert(0); 1258 break; 1259 } 1260 1261 set_long(pc, e); 1262 pc->p->exec_size++; 1263 1264 e->inst[0] &= m; 1265 e->inst[1] |= q; 1266} 1267 1268static boolean 1269negate_supported(const struct tgsi_full_instruction *insn, int i) 1270{ 1271 switch (insn->Instruction.Opcode) { 1272 case TGSI_OPCODE_DP3: 1273 case TGSI_OPCODE_DP4: 1274 case TGSI_OPCODE_MUL: 1275 case TGSI_OPCODE_KIL: 1276 case TGSI_OPCODE_ADD: 1277 case TGSI_OPCODE_SUB: 1278 case TGSI_OPCODE_MAD: 1279 return TRUE; 1280 case TGSI_OPCODE_POW: 1281 return (i == 1) ? TRUE : FALSE; 1282 default: 1283 return FALSE; 1284 } 1285} 1286 1287/* Return a read mask for source registers deduced from opcode & write mask. */ 1288static unsigned 1289nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c) 1290{ 1291 unsigned x, mask = insn->FullDstRegisters[0].DstRegister.WriteMask; 1292 1293 switch (insn->Instruction.Opcode) { 1294 case TGSI_OPCODE_COS: 1295 case TGSI_OPCODE_SIN: 1296 return (mask & 0x8) | ((mask & 0x7) ? 0x1 : 0x0); 1297 case TGSI_OPCODE_DP3: 1298 return 0x7; 1299 case TGSI_OPCODE_DP4: 1300 case TGSI_OPCODE_DPH: 1301 case TGSI_OPCODE_KIL: /* WriteMask ignored */ 1302 return 0xf; 1303 case TGSI_OPCODE_DST: 1304 return mask & (c ? 0xa : 0x6); 1305 case TGSI_OPCODE_EX2: 1306 case TGSI_OPCODE_LG2: 1307 case TGSI_OPCODE_POW: 1308 case TGSI_OPCODE_RCP: 1309 case TGSI_OPCODE_RSQ: 1310 case TGSI_OPCODE_SCS: 1311 return 0x1; 1312 case TGSI_OPCODE_LIT: 1313 return 0xb; 1314 case TGSI_OPCODE_TEX: 1315 case TGSI_OPCODE_TXP: 1316 { 1317 const struct tgsi_instruction_ext_texture *tex; 1318 1319 assert(insn->Instruction.Extended); 1320 tex = &insn->InstructionExtTexture; 1321 1322 mask = 0x7; 1323 if (insn->Instruction.Opcode == TGSI_OPCODE_TXP) 1324 mask |= 0x8; 1325 1326 switch (tex->Texture) { 1327 case TGSI_TEXTURE_1D: 1328 mask &= 0x9; 1329 break; 1330 case TGSI_TEXTURE_2D: 1331 mask &= 0xb; 1332 break; 1333 default: 1334 break; 1335 } 1336 } 1337 return mask; 1338 case TGSI_OPCODE_XPD: 1339 x = 0; 1340 if (mask & 1) x |= 0x6; 1341 if (mask & 2) x |= 0x5; 1342 if (mask & 4) x |= 0x3; 1343 return x; 1344 default: 1345 break; 1346 } 1347 1348 return mask; 1349} 1350 1351static struct nv50_reg * 1352tgsi_dst(struct nv50_pc *pc, int c, const struct tgsi_full_dst_register *dst) 1353{ 1354 switch (dst->DstRegister.File) { 1355 case TGSI_FILE_TEMPORARY: 1356 return &pc->temp[dst->DstRegister.Index * 4 + c]; 1357 case TGSI_FILE_OUTPUT: 1358 return &pc->result[dst->DstRegister.Index * 4 + c]; 1359 case TGSI_FILE_NULL: 1360 return NULL; 1361 default: 1362 break; 1363 } 1364 1365 return NULL; 1366} 1367 1368static struct nv50_reg * 1369tgsi_src(struct nv50_pc *pc, int chan, const struct tgsi_full_src_register *src, 1370 boolean neg) 1371{ 1372 struct nv50_reg *r = NULL; 1373 struct nv50_reg *temp; 1374 unsigned sgn, c; 1375 1376 sgn = tgsi_util_get_full_src_register_sign_mode(src, chan); 1377 1378 c = tgsi_util_get_full_src_register_extswizzle(src, chan); 1379 switch (c) { 1380 case TGSI_EXTSWIZZLE_X: 1381 case TGSI_EXTSWIZZLE_Y: 1382 case TGSI_EXTSWIZZLE_Z: 1383 case TGSI_EXTSWIZZLE_W: 1384 switch (src->SrcRegister.File) { 1385 case TGSI_FILE_INPUT: 1386 r = &pc->attr[src->SrcRegister.Index * 4 + c]; 1387 break; 1388 case TGSI_FILE_TEMPORARY: 1389 r = &pc->temp[src->SrcRegister.Index * 4 + c]; 1390 break; 1391 case TGSI_FILE_CONSTANT: 1392 r = &pc->param[src->SrcRegister.Index * 4 + c]; 1393 break; 1394 case TGSI_FILE_IMMEDIATE: 1395 r = &pc->immd[src->SrcRegister.Index * 4 + c]; 1396 break; 1397 case TGSI_FILE_SAMPLER: 1398 break; 1399 default: 1400 assert(0); 1401 break; 1402 } 1403 break; 1404 case TGSI_EXTSWIZZLE_ZERO: 1405 r = alloc_immd(pc, 0.0); 1406 return r; 1407 case TGSI_EXTSWIZZLE_ONE: 1408 if (sgn == TGSI_UTIL_SIGN_TOGGLE || sgn == TGSI_UTIL_SIGN_SET) 1409 return alloc_immd(pc, -1.0); 1410 return alloc_immd(pc, 1.0); 1411 default: 1412 assert(0); 1413 break; 1414 } 1415 1416 switch (sgn) { 1417 case TGSI_UTIL_SIGN_KEEP: 1418 break; 1419 case TGSI_UTIL_SIGN_CLEAR: 1420 temp = temp_temp(pc); 1421 emit_abs(pc, temp, r); 1422 r = temp; 1423 break; 1424 case TGSI_UTIL_SIGN_TOGGLE: 1425 if (neg) 1426 r->neg = 1; 1427 else { 1428 temp = temp_temp(pc); 1429 emit_neg(pc, temp, r); 1430 r = temp; 1431 } 1432 break; 1433 case TGSI_UTIL_SIGN_SET: 1434 temp = temp_temp(pc); 1435 emit_abs(pc, temp, r); 1436 if (neg) 1437 temp->neg = 1; 1438 else 1439 emit_neg(pc, temp, temp); 1440 r = temp; 1441 break; 1442 default: 1443 assert(0); 1444 break; 1445 } 1446 1447 return r; 1448} 1449 1450/* return TRUE for ops that produce only a single result */ 1451static boolean 1452is_scalar_op(unsigned op) 1453{ 1454 switch (op) { 1455 case TGSI_OPCODE_COS: 1456 case TGSI_OPCODE_DP2: 1457 case TGSI_OPCODE_DP3: 1458 case TGSI_OPCODE_DP4: 1459 case TGSI_OPCODE_DPH: 1460 case TGSI_OPCODE_EX2: 1461 case TGSI_OPCODE_LG2: 1462 case TGSI_OPCODE_POW: 1463 case TGSI_OPCODE_RCP: 1464 case TGSI_OPCODE_RSQ: 1465 case TGSI_OPCODE_SIN: 1466 /* 1467 case TGSI_OPCODE_KIL: 1468 case TGSI_OPCODE_LIT: 1469 case TGSI_OPCODE_SCS: 1470 */ 1471 return TRUE; 1472 default: 1473 return FALSE; 1474 } 1475} 1476 1477/* Returns a bitmask indicating which dst components depend 1478 * on source s, component c (reverse of nv50_tgsi_src_mask). 1479 */ 1480static unsigned 1481nv50_tgsi_dst_revdep(unsigned op, int s, int c) 1482{ 1483 if (is_scalar_op(op)) 1484 return 0x1; 1485 1486 switch (op) { 1487 case TGSI_OPCODE_DST: 1488 return (1 << c) & (s ? 0xa : 0x6); 1489 case TGSI_OPCODE_XPD: 1490 switch (c) { 1491 case 0: return 0x6; 1492 case 1: return 0x5; 1493 case 2: return 0x3; 1494 case 3: return 0x0; 1495 default: 1496 assert(0); 1497 return 0x0; 1498 } 1499 case TGSI_OPCODE_LIT: 1500 case TGSI_OPCODE_SCS: 1501 case TGSI_OPCODE_TEX: 1502 case TGSI_OPCODE_TXP: 1503 /* these take care of dangerous swizzles themselves */ 1504 return 0x0; 1505 case TGSI_OPCODE_IF: 1506 case TGSI_OPCODE_KIL: 1507 /* don't call this function for these ops */ 1508 assert(0); 1509 return 0; 1510 default: 1511 /* linear vector instruction */ 1512 return (1 << c); 1513 } 1514} 1515 1516static INLINE boolean 1517has_pred(struct nv50_program_exec *e, unsigned cc) 1518{ 1519 if (!is_long(e) || is_immd(e)) 1520 return FALSE; 1521 return ((e->inst[1] & 0x780) == (cc << 7)); 1522} 1523 1524/* on ENDIF see if we can do "@p0.neu single_op" instead of: 1525 * join_at ENDIF 1526 * @p0.eq bra ENDIF 1527 * single_op 1528 * ENDIF: nop.join 1529 */ 1530static boolean 1531nv50_kill_branch(struct nv50_pc *pc) 1532{ 1533 int lvl = pc->if_lvl; 1534 1535 if (pc->if_insn[lvl]->next != pc->p->exec_tail) 1536 return FALSE; 1537 1538 /* if ccode == 'true', the BRA is from an ELSE and the predicate 1539 * reg may no longer be valid, since we currently always use $p0 1540 */ 1541 if (has_pred(pc->if_insn[lvl], 0xf)) 1542 return FALSE; 1543 assert(pc->if_insn[lvl] && pc->br_join[lvl]); 1544 1545 /* We'll use the exec allocated for JOIN_AT (as we can't easily 1546 * update prev's next); if exec_tail is BRK, update the pointer. 1547 */ 1548 if (pc->loop_lvl && pc->br_loop[pc->loop_lvl - 1] == pc->p->exec_tail) 1549 pc->br_loop[pc->loop_lvl - 1] = pc->br_join[lvl]; 1550 1551 pc->p->exec_size -= 4; /* remove JOIN_AT and BRA */ 1552 1553 *pc->br_join[lvl] = *pc->p->exec_tail; 1554 1555 FREE(pc->if_insn[lvl]); 1556 FREE(pc->p->exec_tail); 1557 1558 pc->p->exec_tail = pc->br_join[lvl]; 1559 pc->p->exec_tail->next = NULL; 1560 set_pred(pc, 0xd, 0, pc->p->exec_tail); 1561 1562 return TRUE; 1563} 1564 1565static boolean 1566nv50_program_tx_insn(struct nv50_pc *pc, 1567 const struct tgsi_full_instruction *inst) 1568{ 1569 struct nv50_reg *rdst[4], *dst[4], *brdc, *src[3][4], *temp; 1570 unsigned mask, sat, unit; 1571 int i, c; 1572 1573 mask = inst->FullDstRegisters[0].DstRegister.WriteMask; 1574 sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE; 1575 1576 memset(src, 0, sizeof(src)); 1577 1578 for (c = 0; c < 4; c++) { 1579 if ((mask & (1 << c)) && !pc->r_dst[c]) 1580 dst[c] = tgsi_dst(pc, c, &inst->FullDstRegisters[0]); 1581 else 1582 dst[c] = pc->r_dst[c]; 1583 rdst[c] = dst[c]; 1584 } 1585 1586 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) { 1587 const struct tgsi_full_src_register *fs = &inst->FullSrcRegisters[i]; 1588 unsigned src_mask; 1589 boolean neg_supp; 1590 1591 src_mask = nv50_tgsi_src_mask(inst, i); 1592 neg_supp = negate_supported(inst, i); 1593 1594 if (fs->SrcRegister.File == TGSI_FILE_SAMPLER) 1595 unit = fs->SrcRegister.Index; 1596 1597 for (c = 0; c < 4; c++) 1598 if (src_mask & (1 << c)) 1599 src[i][c] = tgsi_src(pc, c, fs, neg_supp); 1600 } 1601 1602 brdc = temp = pc->r_brdc; 1603 if (brdc && brdc->type != P_TEMP) { 1604 temp = temp_temp(pc); 1605 if (sat) 1606 brdc = temp; 1607 } else 1608 if (sat) { 1609 for (c = 0; c < 4; c++) { 1610 if (!(mask & (1 << c)) || dst[c]->type == P_TEMP) 1611 continue; 1612 rdst[c] = dst[c]; 1613 dst[c] = temp_temp(pc); 1614 } 1615 } 1616 1617 assert(brdc || !is_scalar_op(inst->Instruction.Opcode)); 1618 1619 switch (inst->Instruction.Opcode) { 1620 case TGSI_OPCODE_ABS: 1621 for (c = 0; c < 4; c++) { 1622 if (!(mask & (1 << c))) 1623 continue; 1624 emit_abs(pc, dst[c], src[0][c]); 1625 } 1626 break; 1627 case TGSI_OPCODE_ADD: 1628 for (c = 0; c < 4; c++) { 1629 if (!(mask & (1 << c))) 1630 continue; 1631 emit_add(pc, dst[c], src[0][c], src[1][c]); 1632 } 1633 break; 1634 case TGSI_OPCODE_BGNLOOP: 1635 pc->loop_pos[pc->loop_lvl++] = pc->p->exec_size; 1636 break; 1637 case TGSI_OPCODE_BRK: 1638 emit_branch(pc, -1, 0, NULL); 1639 assert(pc->loop_lvl > 0); 1640 pc->br_loop[pc->loop_lvl - 1] = pc->p->exec_tail; 1641 break; 1642 case TGSI_OPCODE_CEIL: 1643 for (c = 0; c < 4; c++) { 1644 if (!(mask & (1 << c))) 1645 continue; 1646 emit_cvt(pc, dst[c], src[0][c], -1, 1647 CVTOP_CEIL, CVT_F32_F32 | CVT_RI); 1648 } 1649 break; 1650 case TGSI_OPCODE_COS: 1651 if (mask & 8) { 1652 emit_precossin(pc, temp, src[0][3]); 1653 emit_flop(pc, 5, dst[3], temp); 1654 if (!(mask &= 7)) 1655 break; 1656 if (temp == dst[3]) 1657 temp = brdc = temp_temp(pc); 1658 } 1659 emit_precossin(pc, temp, src[0][0]); 1660 emit_flop(pc, 5, brdc, temp); 1661 break; 1662 case TGSI_OPCODE_DP3: 1663 emit_mul(pc, temp, src[0][0], src[1][0]); 1664 emit_mad(pc, temp, src[0][1], src[1][1], temp); 1665 emit_mad(pc, brdc, src[0][2], src[1][2], temp); 1666 break; 1667 case TGSI_OPCODE_DP4: 1668 emit_mul(pc, temp, src[0][0], src[1][0]); 1669 emit_mad(pc, temp, src[0][1], src[1][1], temp); 1670 emit_mad(pc, temp, src[0][2], src[1][2], temp); 1671 emit_mad(pc, brdc, src[0][3], src[1][3], temp); 1672 break; 1673 case TGSI_OPCODE_DPH: 1674 emit_mul(pc, temp, src[0][0], src[1][0]); 1675 emit_mad(pc, temp, src[0][1], src[1][1], temp); 1676 emit_mad(pc, temp, src[0][2], src[1][2], temp); 1677 emit_add(pc, brdc, src[1][3], temp); 1678 break; 1679 case TGSI_OPCODE_DST: 1680 if (mask & (1 << 1)) 1681 emit_mul(pc, dst[1], src[0][1], src[1][1]); 1682 if (mask & (1 << 2)) 1683 emit_mov(pc, dst[2], src[0][2]); 1684 if (mask & (1 << 3)) 1685 emit_mov(pc, dst[3], src[1][3]); 1686 if (mask & (1 << 0)) 1687 emit_mov_immdval(pc, dst[0], 1.0f); 1688 break; 1689 case TGSI_OPCODE_ELSE: 1690 emit_branch(pc, -1, 0, NULL); 1691 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size; 1692 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail; 1693 break; 1694 case TGSI_OPCODE_ENDIF: 1695 pc->if_insn[--pc->if_lvl]->param.index = pc->p->exec_size; 1696 1697 /* try to replace branch over 1 insn with a predicated insn */ 1698 if (nv50_kill_branch(pc) == TRUE) 1699 break; 1700 1701 if (pc->br_join[pc->if_lvl]) { 1702 pc->br_join[pc->if_lvl]->param.index = pc->p->exec_size; 1703 pc->br_join[pc->if_lvl] = NULL; 1704 } 1705 /* emit a NOP as join point, we could set it on the next 1706 * one, but would have to make sure it is long and !immd 1707 */ 1708 emit_nop(pc); 1709 pc->p->exec_tail->inst[1] |= 2; 1710 break; 1711 case TGSI_OPCODE_ENDLOOP: 1712 emit_branch(pc, -1, 0, NULL); 1713 pc->p->exec_tail->param.index = pc->loop_pos[--pc->loop_lvl]; 1714 pc->br_loop[pc->loop_lvl]->param.index = pc->p->exec_size; 1715 break; 1716 case TGSI_OPCODE_EX2: 1717 emit_preex2(pc, temp, src[0][0]); 1718 emit_flop(pc, 6, brdc, temp); 1719 break; 1720 case TGSI_OPCODE_FLR: 1721 for (c = 0; c < 4; c++) { 1722 if (!(mask & (1 << c))) 1723 continue; 1724 emit_flr(pc, dst[c], src[0][c]); 1725 } 1726 break; 1727 case TGSI_OPCODE_FRC: 1728 temp = temp_temp(pc); 1729 for (c = 0; c < 4; c++) { 1730 if (!(mask & (1 << c))) 1731 continue; 1732 emit_flr(pc, temp, src[0][c]); 1733 emit_sub(pc, dst[c], src[0][c], temp); 1734 } 1735 break; 1736 case TGSI_OPCODE_IF: 1737 /* emitting a join_at may not be necessary */ 1738 assert(pc->if_lvl < MAX_IF_DEPTH); 1739 set_pred_wr(pc, 1, 0, pc->if_cond); 1740 emit_branch(pc, 0, 2, &pc->br_join[pc->if_lvl]); 1741 pc->if_insn[pc->if_lvl++] = pc->p->exec_tail; 1742 break; 1743 case TGSI_OPCODE_KIL: 1744 emit_kil(pc, src[0][0]); 1745 emit_kil(pc, src[0][1]); 1746 emit_kil(pc, src[0][2]); 1747 emit_kil(pc, src[0][3]); 1748 break; 1749 case TGSI_OPCODE_LIT: 1750 emit_lit(pc, &dst[0], mask, &src[0][0]); 1751 break; 1752 case TGSI_OPCODE_LG2: 1753 emit_flop(pc, 3, brdc, src[0][0]); 1754 break; 1755 case TGSI_OPCODE_LRP: 1756 temp = temp_temp(pc); 1757 for (c = 0; c < 4; c++) { 1758 if (!(mask & (1 << c))) 1759 continue; 1760 emit_sub(pc, temp, src[1][c], src[2][c]); 1761 emit_mad(pc, dst[c], temp, src[0][c], src[2][c]); 1762 } 1763 break; 1764 case TGSI_OPCODE_MAD: 1765 for (c = 0; c < 4; c++) { 1766 if (!(mask & (1 << c))) 1767 continue; 1768 emit_mad(pc, dst[c], src[0][c], src[1][c], src[2][c]); 1769 } 1770 break; 1771 case TGSI_OPCODE_MAX: 1772 for (c = 0; c < 4; c++) { 1773 if (!(mask & (1 << c))) 1774 continue; 1775 emit_minmax(pc, 4, dst[c], src[0][c], src[1][c]); 1776 } 1777 break; 1778 case TGSI_OPCODE_MIN: 1779 for (c = 0; c < 4; c++) { 1780 if (!(mask & (1 << c))) 1781 continue; 1782 emit_minmax(pc, 5, dst[c], src[0][c], src[1][c]); 1783 } 1784 break; 1785 case TGSI_OPCODE_MOV: 1786 case TGSI_OPCODE_SWZ: 1787 for (c = 0; c < 4; c++) { 1788 if (!(mask & (1 << c))) 1789 continue; 1790 emit_mov(pc, dst[c], src[0][c]); 1791 } 1792 break; 1793 case TGSI_OPCODE_MUL: 1794 for (c = 0; c < 4; c++) { 1795 if (!(mask & (1 << c))) 1796 continue; 1797 emit_mul(pc, dst[c], src[0][c], src[1][c]); 1798 } 1799 break; 1800 case TGSI_OPCODE_POW: 1801 emit_pow(pc, brdc, src[0][0], src[1][0]); 1802 break; 1803 case TGSI_OPCODE_RCP: 1804 emit_flop(pc, 0, brdc, src[0][0]); 1805 break; 1806 case TGSI_OPCODE_RSQ: 1807 emit_flop(pc, 2, brdc, src[0][0]); 1808 break; 1809 case TGSI_OPCODE_SCS: 1810 temp = temp_temp(pc); 1811 if (mask & 3) 1812 emit_precossin(pc, temp, src[0][0]); 1813 if (mask & (1 << 0)) 1814 emit_flop(pc, 5, dst[0], temp); 1815 if (mask & (1 << 1)) 1816 emit_flop(pc, 4, dst[1], temp); 1817 if (mask & (1 << 2)) 1818 emit_mov_immdval(pc, dst[2], 0.0); 1819 if (mask & (1 << 3)) 1820 emit_mov_immdval(pc, dst[3], 1.0); 1821 break; 1822 case TGSI_OPCODE_SIN: 1823 if (mask & 8) { 1824 emit_precossin(pc, temp, src[0][3]); 1825 emit_flop(pc, 4, dst[3], temp); 1826 if (!(mask &= 7)) 1827 break; 1828 if (temp == dst[3]) 1829 temp = brdc = temp_temp(pc); 1830 } 1831 emit_precossin(pc, temp, src[0][0]); 1832 emit_flop(pc, 4, brdc, temp); 1833 break; 1834 case TGSI_OPCODE_SLT: 1835 case TGSI_OPCODE_SGE: 1836 case TGSI_OPCODE_SEQ: 1837 case TGSI_OPCODE_SGT: 1838 case TGSI_OPCODE_SLE: 1839 case TGSI_OPCODE_SNE: 1840 i = map_tgsi_setop_cc(inst->Instruction.Opcode); 1841 for (c = 0; c < 4; c++) { 1842 if (!(mask & (1 << c))) 1843 continue; 1844 emit_set(pc, i, dst[c], -1, src[0][c], src[1][c]); 1845 } 1846 break; 1847 case TGSI_OPCODE_SUB: 1848 for (c = 0; c < 4; c++) { 1849 if (!(mask & (1 << c))) 1850 continue; 1851 emit_sub(pc, dst[c], src[0][c], src[1][c]); 1852 } 1853 break; 1854 case TGSI_OPCODE_TEX: 1855 emit_tex(pc, dst, mask, src[0], unit, 1856 inst->InstructionExtTexture.Texture, FALSE); 1857 break; 1858 case TGSI_OPCODE_TXP: 1859 emit_tex(pc, dst, mask, src[0], unit, 1860 inst->InstructionExtTexture.Texture, TRUE); 1861 break; 1862 case TGSI_OPCODE_TRUNC: 1863 for (c = 0; c < 4; c++) { 1864 if (!(mask & (1 << c))) 1865 continue; 1866 emit_cvt(pc, dst[c], src[0][c], -1, 1867 CVTOP_TRUNC, CVT_F32_F32 | CVT_RI); 1868 } 1869 break; 1870 case TGSI_OPCODE_XPD: 1871 temp = temp_temp(pc); 1872 if (mask & (1 << 0)) { 1873 emit_mul(pc, temp, src[0][2], src[1][1]); 1874 emit_msb(pc, dst[0], src[0][1], src[1][2], temp); 1875 } 1876 if (mask & (1 << 1)) { 1877 emit_mul(pc, temp, src[0][0], src[1][2]); 1878 emit_msb(pc, dst[1], src[0][2], src[1][0], temp); 1879 } 1880 if (mask & (1 << 2)) { 1881 emit_mul(pc, temp, src[0][1], src[1][0]); 1882 emit_msb(pc, dst[2], src[0][0], src[1][1], temp); 1883 } 1884 if (mask & (1 << 3)) 1885 emit_mov_immdval(pc, dst[3], 1.0); 1886 break; 1887 case TGSI_OPCODE_END: 1888 break; 1889 default: 1890 NOUVEAU_ERR("invalid opcode %d\n", inst->Instruction.Opcode); 1891 return FALSE; 1892 } 1893 1894 if (brdc) { 1895 if (sat) 1896 emit_sat(pc, brdc, brdc); 1897 for (c = 0; c < 4; c++) 1898 if ((mask & (1 << c)) && dst[c] != brdc) 1899 emit_mov(pc, dst[c], brdc); 1900 } else 1901 if (sat) { 1902 for (c = 0; c < 4; c++) { 1903 if (!(mask & (1 << c))) 1904 continue; 1905 /* in this case we saturate later */ 1906 if (dst[c]->type == P_TEMP && dst[c]->index < 0) 1907 continue; 1908 emit_sat(pc, rdst[c], dst[c]); 1909 } 1910 } 1911 1912 for (i = 0; i < inst->Instruction.NumSrcRegs; i++) { 1913 for (c = 0; c < 4; c++) { 1914 if (!src[i][c]) 1915 continue; 1916 if (src[i][c]->index == -1 && src[i][c]->type == P_IMMD) 1917 FREE(src[i][c]); 1918 } 1919 } 1920 1921 kill_temp_temp(pc); 1922 return TRUE; 1923} 1924 1925static void 1926prep_inspect_insn(struct nv50_pc *pc, const struct tgsi_full_instruction *insn) 1927{ 1928 struct nv50_reg *reg = NULL; 1929 const struct tgsi_full_src_register *src; 1930 const struct tgsi_dst_register *dst; 1931 unsigned i, c, k, mask; 1932 1933 dst = &insn->FullDstRegisters[0].DstRegister; 1934 mask = dst->WriteMask; 1935 1936 if (dst->File == TGSI_FILE_TEMPORARY) 1937 reg = pc->temp; 1938 else 1939 if (dst->File == TGSI_FILE_OUTPUT) 1940 reg = pc->result; 1941 1942 if (reg) { 1943 for (c = 0; c < 4; c++) { 1944 if (!(mask & (1 << c))) 1945 continue; 1946 reg[dst->Index * 4 + c].acc = pc->insn_nr; 1947 } 1948 } 1949 1950 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) { 1951 src = &insn->FullSrcRegisters[i]; 1952 1953 if (src->SrcRegister.File == TGSI_FILE_TEMPORARY) 1954 reg = pc->temp; 1955 else 1956 if (src->SrcRegister.File == TGSI_FILE_INPUT) 1957 reg = pc->attr; 1958 else 1959 continue; 1960 1961 mask = nv50_tgsi_src_mask(insn, i); 1962 1963 for (c = 0; c < 4; c++) { 1964 if (!(mask & (1 << c))) 1965 continue; 1966 k = tgsi_util_get_full_src_register_extswizzle(src, c); 1967 1968 if (k > TGSI_EXTSWIZZLE_W) 1969 continue; 1970 1971 reg[src->SrcRegister.Index * 4 + k].acc = pc->insn_nr; 1972 } 1973 } 1974} 1975 1976/* Returns a bitmask indicating which dst components need to be 1977 * written to temporaries first to avoid 'corrupting' sources. 1978 * 1979 * m[i] (out) indicate component to write in the i-th position 1980 * rdep[c] (in) bitmasks of dst[i] that require dst[c] as source 1981 */ 1982static unsigned 1983nv50_revdep_reorder(unsigned m[4], unsigned rdep[4]) 1984{ 1985 unsigned i, c, x, unsafe; 1986 1987 for (c = 0; c < 4; c++) 1988 m[c] = c; 1989 1990 /* Swap as long as a dst component written earlier is depended on 1991 * by one written later, but the next one isn't depended on by it. 1992 */ 1993 for (c = 0; c < 3; c++) { 1994 if (rdep[m[c + 1]] & (1 << m[c])) 1995 continue; /* if next one is depended on by us */ 1996 for (i = c + 1; i < 4; i++) 1997 /* if we are depended on by a later one */ 1998 if (rdep[m[c]] & (1 << m[i])) 1999 break; 2000 if (i == 4) 2001 continue; 2002 /* now, swap */ 2003 x = m[c]; 2004 m[c] = m[c + 1]; 2005 m[c + 1] = x; 2006 2007 /* restart */ 2008 c = 0; 2009 } 2010 2011 /* mark dependencies that could not be resolved by reordering */ 2012 for (i = 0; i < 3; ++i) 2013 for (c = i + 1; c < 4; ++c) 2014 if (rdep[m[i]] & (1 << m[c])) 2015 unsafe |= (1 << i); 2016 2017 /* NOTE: $unsafe is with respect to order, not component */ 2018 return unsafe; 2019} 2020 2021/* Select a suitable dst register for broadcasting scalar results, 2022 * or return NULL if we have to allocate an extra TEMP. 2023 * 2024 * If e.g. only 1 component is written, we may also emit the final 2025 * result to a write-only register. 2026 */ 2027static struct nv50_reg * 2028tgsi_broadcast_dst(struct nv50_pc *pc, 2029 const struct tgsi_full_dst_register *fd, unsigned mask) 2030{ 2031 if (fd->DstRegister.File == TGSI_FILE_TEMPORARY) { 2032 int c = ffs(~mask & fd->DstRegister.WriteMask); 2033 if (c) 2034 return tgsi_dst(pc, c - 1, fd); 2035 } else { 2036 int c = ffs(fd->DstRegister.WriteMask) - 1; 2037 if ((1 << c) == fd->DstRegister.WriteMask) 2038 return tgsi_dst(pc, c, fd); 2039 } 2040 2041 return NULL; 2042} 2043 2044/* Scan source swizzles and return a bitmask indicating dst regs that 2045 * also occur among the src regs, and fill rdep for nv50_revdep_reoder. 2046 */ 2047static unsigned 2048nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn, 2049 unsigned rdep[4]) 2050{ 2051 const struct tgsi_full_dst_register *fd = &insn->FullDstRegisters[0]; 2052 const struct tgsi_full_src_register *fs; 2053 unsigned i, deqs = 0; 2054 2055 for (i = 0; i < 4; ++i) 2056 rdep[i] = 0; 2057 2058 for (i = 0; i < insn->Instruction.NumSrcRegs; i++) { 2059 unsigned chn, mask = nv50_tgsi_src_mask(insn, i); 2060 boolean neg_supp = negate_supported(insn, i); 2061 2062 fs = &insn->FullSrcRegisters[i]; 2063 if (fs->SrcRegister.File != fd->DstRegister.File || 2064 fs->SrcRegister.Index != fd->DstRegister.Index) 2065 continue; 2066 2067 for (chn = 0; chn < 4; ++chn) { 2068 unsigned s, c; 2069 2070 if (!(mask & (1 << chn))) /* src is not read */ 2071 continue; 2072 c = tgsi_util_get_full_src_register_extswizzle(fs, chn); 2073 s = tgsi_util_get_full_src_register_sign_mode(fs, chn); 2074 2075 if (c > TGSI_EXTSWIZZLE_W || 2076 !(fd->DstRegister.WriteMask & (1 << c))) 2077 continue; 2078 2079 /* no danger if src is copied to TEMP first */ 2080 if ((s != TGSI_UTIL_SIGN_KEEP) && 2081 (s != TGSI_UTIL_SIGN_TOGGLE || !neg_supp)) 2082 continue; 2083 2084 rdep[c] |= nv50_tgsi_dst_revdep( 2085 insn->Instruction.Opcode, i, chn); 2086 deqs |= (1 << c); 2087 } 2088 } 2089 2090 return deqs; 2091} 2092 2093static boolean 2094nv50_tgsi_insn(struct nv50_pc *pc, const union tgsi_full_token *tok) 2095{ 2096 struct tgsi_full_instruction insn = tok->FullInstruction; 2097 const struct tgsi_full_dst_register *fd; 2098 unsigned i, deqs, rdep[4], m[4]; 2099 2100 fd = &tok->FullInstruction.FullDstRegisters[0]; 2101 deqs = nv50_tgsi_scan_swizzle(&insn, rdep); 2102 2103 if (is_scalar_op(insn.Instruction.Opcode)) { 2104 pc->r_brdc = tgsi_broadcast_dst(pc, fd, deqs); 2105 if (!pc->r_brdc) 2106 pc->r_brdc = temp_temp(pc); 2107 return nv50_program_tx_insn(pc, &insn); 2108 } 2109 pc->r_brdc = NULL; 2110 2111 if (!deqs) 2112 return nv50_program_tx_insn(pc, &insn); 2113 2114 deqs = nv50_revdep_reorder(m, rdep); 2115 2116 for (i = 0; i < 4; ++i) { 2117 assert(pc->r_dst[m[i]] == NULL); 2118 2119 insn.FullDstRegisters[0].DstRegister.WriteMask = 2120 fd->DstRegister.WriteMask & (1 << m[i]); 2121 2122 if (!insn.FullDstRegisters[0].DstRegister.WriteMask) 2123 continue; 2124 2125 if (deqs & (1 << i)) 2126 pc->r_dst[m[i]] = alloc_temp(pc, NULL); 2127 2128 if (!nv50_program_tx_insn(pc, &insn)) 2129 return FALSE; 2130 } 2131 2132 for (i = 0; i < 4; i++) { 2133 struct nv50_reg *reg = pc->r_dst[i]; 2134 if (!reg) 2135 continue; 2136 pc->r_dst[i] = NULL; 2137 2138 if (insn.Instruction.Saturate == TGSI_SAT_ZERO_ONE) 2139 emit_sat(pc, tgsi_dst(pc, i, fd), reg); 2140 else 2141 emit_mov(pc, tgsi_dst(pc, i, fd), reg); 2142 free_temp(pc, reg); 2143 } 2144 2145 return TRUE; 2146} 2147 2148static void 2149load_interpolant(struct nv50_pc *pc, struct nv50_reg *reg) 2150{ 2151 struct nv50_reg *iv, **ppiv; 2152 unsigned mode = pc->interp_mode[reg->index]; 2153 2154 ppiv = (mode & INTERP_CENTROID) ? &pc->iv_c : &pc->iv_p; 2155 iv = *ppiv; 2156 2157 if ((mode & INTERP_PERSPECTIVE) && !iv) { 2158 iv = *ppiv = alloc_temp(pc, NULL); 2159 iv->rhw = popcnt4(pc->p->cfg.regs[1] >> 24) - 1; 2160 2161 emit_interp(pc, iv, NULL, mode & INTERP_CENTROID); 2162 emit_flop(pc, 0, iv, iv); 2163 2164 /* XXX: when loading interpolants dynamically, move these 2165 * to the program head, or make sure it can't be skipped. 2166 */ 2167 } 2168 2169 emit_interp(pc, reg, iv, mode); 2170} 2171 2172static boolean 2173nv50_program_tx_prep(struct nv50_pc *pc) 2174{ 2175 struct tgsi_parse_context tp; 2176 struct nv50_program *p = pc->p; 2177 boolean ret = FALSE; 2178 unsigned i, c, flat_nr = 0; 2179 2180 tgsi_parse_init(&tp, pc->p->pipe.tokens); 2181 while (!tgsi_parse_end_of_tokens(&tp)) { 2182 const union tgsi_full_token *tok = &tp.FullToken; 2183 2184 tgsi_parse_token(&tp); 2185 switch (tok->Token.Type) { 2186 case TGSI_TOKEN_TYPE_IMMEDIATE: 2187 { 2188 const struct tgsi_full_immediate *imm = 2189 &tp.FullToken.FullImmediate; 2190 2191 ctor_immd(pc, imm->u[0].Float, 2192 imm->u[1].Float, 2193 imm->u[2].Float, 2194 imm->u[3].Float); 2195 } 2196 break; 2197 case TGSI_TOKEN_TYPE_DECLARATION: 2198 { 2199 const struct tgsi_full_declaration *d; 2200 unsigned si, last, first, mode; 2201 2202 d = &tp.FullToken.FullDeclaration; 2203 first = d->DeclarationRange.First; 2204 last = d->DeclarationRange.Last; 2205 2206 switch (d->Declaration.File) { 2207 case TGSI_FILE_TEMPORARY: 2208 break; 2209 case TGSI_FILE_OUTPUT: 2210 if (!d->Declaration.Semantic || 2211 p->type == PIPE_SHADER_FRAGMENT) 2212 break; 2213 2214 si = d->Semantic.SemanticIndex; 2215 switch (d->Semantic.SemanticName) { 2216 case TGSI_SEMANTIC_BCOLOR: 2217 p->cfg.two_side[si].hw = first; 2218 if (p->cfg.io_nr > first) 2219 p->cfg.io_nr = first; 2220 break; 2221 case TGSI_SEMANTIC_PSIZE: 2222 p->cfg.psiz = first; 2223 if (p->cfg.io_nr > first) 2224 p->cfg.io_nr = first; 2225 break; 2226 /* 2227 case TGSI_SEMANTIC_CLIP_DISTANCE: 2228 p->cfg.clpd = MIN2(p->cfg.clpd, first); 2229 break; 2230 */ 2231 default: 2232 break; 2233 } 2234 break; 2235 case TGSI_FILE_INPUT: 2236 { 2237 if (p->type != PIPE_SHADER_FRAGMENT) 2238 break; 2239 2240 switch (d->Declaration.Interpolate) { 2241 case TGSI_INTERPOLATE_CONSTANT: 2242 mode = INTERP_FLAT; 2243 flat_nr++; 2244 break; 2245 case TGSI_INTERPOLATE_PERSPECTIVE: 2246 mode = INTERP_PERSPECTIVE; 2247 p->cfg.regs[1] |= 0x08 << 24; 2248 break; 2249 default: 2250 mode = INTERP_LINEAR; 2251 break; 2252 } 2253 if (d->Declaration.Centroid) 2254 mode |= INTERP_CENTROID; 2255 2256 assert(last < 32); 2257 for (i = first; i <= last; i++) 2258 pc->interp_mode[i] = mode; 2259 } 2260 break; 2261 case TGSI_FILE_CONSTANT: 2262 break; 2263 case TGSI_FILE_SAMPLER: 2264 break; 2265 default: 2266 NOUVEAU_ERR("bad decl file %d\n", 2267 d->Declaration.File); 2268 goto out_err; 2269 } 2270 } 2271 break; 2272 case TGSI_TOKEN_TYPE_INSTRUCTION: 2273 pc->insn_nr++; 2274 prep_inspect_insn(pc, &tok->FullInstruction); 2275 break; 2276 default: 2277 break; 2278 } 2279 } 2280 2281 if (p->type == PIPE_SHADER_VERTEX) { 2282 int rid = 0; 2283 2284 for (i = 0; i < pc->attr_nr * 4; ++i) { 2285 if (pc->attr[i].acc) { 2286 pc->attr[i].hw = rid++; 2287 p->cfg.attr[i / 32] |= 1 << (i % 32); 2288 } 2289 } 2290 2291 for (i = 0, rid = 0; i < pc->result_nr; ++i) { 2292 p->cfg.io[i].hw = rid; 2293 p->cfg.io[i].id_vp = i; 2294 2295 for (c = 0; c < 4; ++c) { 2296 int n = i * 4 + c; 2297 if (!pc->result[n].acc) 2298 continue; 2299 pc->result[n].hw = rid++; 2300 p->cfg.io[i].mask |= 1 << c; 2301 } 2302 } 2303 2304 for (c = 0; c < 2; ++c) 2305 if (p->cfg.two_side[c].hw < 0x40) 2306 p->cfg.two_side[c] = p->cfg.io[ 2307 p->cfg.two_side[c].hw]; 2308 2309 if (p->cfg.psiz < 0x40) 2310 p->cfg.psiz = p->cfg.io[p->cfg.psiz].hw; 2311 } else 2312 if (p->type == PIPE_SHADER_FRAGMENT) { 2313 int rid, aid; 2314 unsigned n = 0, m = pc->attr_nr - flat_nr; 2315 2316 int base = (TGSI_SEMANTIC_POSITION == 2317 p->info.input_semantic_name[0]) ? 0 : 1; 2318 2319 /* non-flat interpolants have to be mapped to 2320 * the lower hardware IDs, so sort them: 2321 */ 2322 for (i = 0; i < pc->attr_nr; i++) { 2323 if (pc->interp_mode[i] == INTERP_FLAT) { 2324 p->cfg.io[m].id_vp = i + base; 2325 p->cfg.io[m++].id_fp = i; 2326 } else { 2327 if (!(pc->interp_mode[i] & INTERP_PERSPECTIVE)) 2328 p->cfg.io[n].linear = TRUE; 2329 p->cfg.io[n].id_vp = i + base; 2330 p->cfg.io[n++].id_fp = i; 2331 } 2332 } 2333 2334 if (!base) /* set w-coordinate mask from perspective interp */ 2335 p->cfg.io[0].mask |= p->cfg.regs[1] >> 24; 2336 2337 aid = popcnt4( /* if fcrd isn't contained in cfg.io */ 2338 base ? (p->cfg.regs[1] >> 24) : p->cfg.io[0].mask); 2339 2340 for (n = 0; n < pc->attr_nr; ++n) { 2341 p->cfg.io[n].hw = rid = aid; 2342 i = p->cfg.io[n].id_fp; 2343 2344 for (c = 0; c < 4; ++c) { 2345 if (!pc->attr[i * 4 + c].acc) 2346 continue; 2347 pc->attr[i * 4 + c].rhw = rid++; 2348 p->cfg.io[n].mask |= 1 << c; 2349 2350 load_interpolant(pc, &pc->attr[i * 4 + c]); 2351 } 2352 aid += popcnt4(p->cfg.io[n].mask); 2353 } 2354 2355 if (!base) 2356 p->cfg.regs[1] |= p->cfg.io[0].mask << 24; 2357 2358 m = popcnt4(p->cfg.regs[1] >> 24); 2359 2360 /* set count of non-position inputs and of non-flat 2361 * non-position inputs for FP_INTERPOLANT_CTRL 2362 */ 2363 p->cfg.regs[1] |= aid - m; 2364 2365 if (flat_nr) { 2366 i = p->cfg.io[pc->attr_nr - flat_nr].hw; 2367 p->cfg.regs[1] |= (i - m) << 16; 2368 } else 2369 p->cfg.regs[1] |= p->cfg.regs[1] << 16; 2370 2371 /* mark color semantic for light-twoside */ 2372 n = 0x40; 2373 for (i = 0; i < pc->attr_nr; i++) { 2374 ubyte si, sn; 2375 2376 sn = p->info.input_semantic_name[p->cfg.io[i].id_fp]; 2377 si = p->info.input_semantic_index[p->cfg.io[i].id_fp]; 2378 2379 if (sn == TGSI_SEMANTIC_COLOR) { 2380 p->cfg.two_side[si] = p->cfg.io[i]; 2381 2382 /* increase colour count */ 2383 p->cfg.regs[0] += popcnt4( 2384 p->cfg.two_side[si].mask) << 16; 2385 2386 n = MIN2(n, p->cfg.io[i].hw - m); 2387 } 2388 } 2389 if (n < 0x40) 2390 p->cfg.regs[0] += n; 2391 2392 /* Initialize FP results: 2393 * FragDepth is always first TGSI and last hw output 2394 */ 2395 i = p->info.writes_z ? 4 : 0; 2396 for (rid = 0; i < pc->result_nr * 4; i++) 2397 pc->result[i].rhw = rid++; 2398 if (p->info.writes_z) 2399 pc->result[2].rhw = rid; 2400 2401 p->cfg.high_result = rid; 2402 } 2403 2404 if (pc->immd_nr) { 2405 int rid = 0; 2406 2407 pc->immd = MALLOC(pc->immd_nr * 4 * sizeof(struct nv50_reg)); 2408 if (!pc->immd) 2409 goto out_err; 2410 2411 for (i = 0; i < pc->immd_nr; i++) { 2412 for (c = 0; c < 4; c++, rid++) 2413 ctor_reg(&pc->immd[rid], P_IMMD, i, rid); 2414 } 2415 } 2416 2417 ret = TRUE; 2418out_err: 2419 if (pc->iv_p) 2420 free_temp(pc, pc->iv_p); 2421 if (pc->iv_c) 2422 free_temp(pc, pc->iv_c); 2423 2424 tgsi_parse_free(&tp); 2425 return ret; 2426} 2427 2428static void 2429free_nv50_pc(struct nv50_pc *pc) 2430{ 2431 if (pc->immd) 2432 FREE(pc->immd); 2433 if (pc->param) 2434 FREE(pc->param); 2435 if (pc->result) 2436 FREE(pc->result); 2437 if (pc->attr) 2438 FREE(pc->attr); 2439 if (pc->temp) 2440 FREE(pc->temp); 2441 2442 FREE(pc); 2443} 2444 2445static boolean 2446ctor_nv50_pc(struct nv50_pc *pc, struct nv50_program *p) 2447{ 2448 int i, c; 2449 unsigned rtype[2] = { P_ATTR, P_RESULT }; 2450 2451 pc->p = p; 2452 pc->temp_nr = p->info.file_max[TGSI_FILE_TEMPORARY] + 1; 2453 pc->attr_nr = p->info.file_max[TGSI_FILE_INPUT] + 1; 2454 pc->result_nr = p->info.file_max[TGSI_FILE_OUTPUT] + 1; 2455 pc->param_nr = p->info.file_max[TGSI_FILE_CONSTANT] + 1; 2456 2457 p->cfg.high_temp = 4; 2458 2459 p->cfg.two_side[0].hw = 0x40; 2460 p->cfg.two_side[1].hw = 0x40; 2461 2462 switch (p->type) { 2463 case PIPE_SHADER_VERTEX: 2464 p->cfg.psiz = 0x40; 2465 p->cfg.clpd = 0x40; 2466 p->cfg.io_nr = pc->result_nr; 2467 break; 2468 case PIPE_SHADER_FRAGMENT: 2469 rtype[0] = rtype[1] = P_TEMP; 2470 2471 p->cfg.regs[0] = 0x01000004; 2472 p->cfg.io_nr = pc->attr_nr; 2473 2474 if (p->info.writes_z) { 2475 p->cfg.regs[2] |= 0x00000100; 2476 p->cfg.regs[3] |= 0x00000011; 2477 } 2478 if (p->info.uses_kill) 2479 p->cfg.regs[2] |= 0x00100000; 2480 break; 2481 } 2482 2483 if (pc->temp_nr) { 2484 pc->temp = MALLOC(pc->temp_nr * 4 * sizeof(struct nv50_reg)); 2485 if (!pc->temp) 2486 return FALSE; 2487 2488 for (i = 0; i < pc->temp_nr * 4; ++i) 2489 ctor_reg(&pc->temp[i], P_TEMP, i / 4, -1); 2490 } 2491 2492 if (pc->attr_nr) { 2493 pc->attr = MALLOC(pc->attr_nr * 4 * sizeof(struct nv50_reg)); 2494 if (!pc->attr) 2495 return FALSE; 2496 2497 for (i = 0; i < pc->attr_nr * 4; ++i) 2498 ctor_reg(&pc->attr[i], rtype[0], i / 4, -1); 2499 } 2500 2501 if (pc->result_nr) { 2502 unsigned nr = pc->result_nr * 4; 2503 2504 pc->result = MALLOC(nr * sizeof(struct nv50_reg)); 2505 if (!pc->result) 2506 return FALSE; 2507 2508 for (i = 0; i < nr; ++i) 2509 ctor_reg(&pc->result[i], rtype[1], i / 4, -1); 2510 } 2511 2512 if (pc->param_nr) { 2513 int rid = 0; 2514 2515 pc->param = MALLOC(pc->param_nr * 4 * sizeof(struct nv50_reg)); 2516 if (!pc->param) 2517 return FALSE; 2518 2519 for (i = 0; i < pc->param_nr; ++i) 2520 for (c = 0; c < 4; ++c, ++rid) 2521 ctor_reg(&pc->param[rid], P_CONST, i, rid); 2522 } 2523 2524 return TRUE; 2525} 2526 2527static void 2528nv50_fp_move_results(struct nv50_pc *pc) 2529{ 2530 struct nv50_reg reg; 2531 unsigned i; 2532 2533 ctor_reg(®, P_TEMP, -1, -1); 2534 2535 for (i = 0; i < pc->result_nr * 4; ++i) { 2536 if (pc->result[i].rhw < 0 || pc->result[i].hw < 0) 2537 continue; 2538 if (pc->result[i].rhw != pc->result[i].hw) { 2539 reg.hw = pc->result[i].rhw; 2540 emit_mov(pc, ®, &pc->result[i]); 2541 } 2542 } 2543} 2544 2545static void 2546nv50_program_fixup_insns(struct nv50_pc *pc) 2547{ 2548 struct nv50_program_exec *e, *prev = NULL, **bra_list; 2549 unsigned i, n, pos; 2550 2551 bra_list = CALLOC(pc->p->exec_size, sizeof(struct nv50_program_exec *)); 2552 2553 /* Collect branch instructions, we need to adjust their offsets 2554 * when converting 32 bit instructions to 64 bit ones 2555 */ 2556 for (n = 0, e = pc->p->exec_head; e; e = e->next) 2557 if (e->param.index >= 0 && !e->param.mask) 2558 bra_list[n++] = e; 2559 2560 /* Make sure we don't have any single 32 bit instructions. */ 2561 for (e = pc->p->exec_head, pos = 0; e; e = e->next) { 2562 pos += is_long(e) ? 2 : 1; 2563 2564 if ((pos & 1) && (!e->next || is_long(e->next))) { 2565 for (i = 0; i < n; ++i) 2566 if (bra_list[i]->param.index >= pos) 2567 bra_list[i]->param.index += 1; 2568 convert_to_long(pc, e); 2569 ++pos; 2570 } 2571 if (e->next) 2572 prev = e; 2573 } 2574 2575 assert(!is_immd(pc->p->exec_head)); 2576 assert(!is_immd(pc->p->exec_tail)); 2577 2578 /* last instruction must be long so it can have the end bit set */ 2579 if (!is_long(pc->p->exec_tail)) { 2580 convert_to_long(pc, pc->p->exec_tail); 2581 if (prev) 2582 convert_to_long(pc, prev); 2583 } 2584 assert(!(pc->p->exec_tail->inst[1] & 2)); 2585 /* set the end-bit */ 2586 pc->p->exec_tail->inst[1] |= 1; 2587 2588 FREE(bra_list); 2589} 2590 2591static boolean 2592nv50_program_tx(struct nv50_program *p) 2593{ 2594 struct tgsi_parse_context parse; 2595 struct nv50_pc *pc; 2596 boolean ret; 2597 2598 pc = CALLOC_STRUCT(nv50_pc); 2599 if (!pc) 2600 return FALSE; 2601 2602 ret = ctor_nv50_pc(pc, p); 2603 if (ret == FALSE) 2604 goto out_cleanup; 2605 2606 ret = nv50_program_tx_prep(pc); 2607 if (ret == FALSE) 2608 goto out_cleanup; 2609 2610 tgsi_parse_init(&parse, pc->p->pipe.tokens); 2611 while (!tgsi_parse_end_of_tokens(&parse)) { 2612 const union tgsi_full_token *tok = &parse.FullToken; 2613 2614 /* don't allow half insn/immd on first and last instruction */ 2615 pc->allow32 = TRUE; 2616 if (pc->insn_cur == 0 || pc->insn_cur + 2 == pc->insn_nr) 2617 pc->allow32 = FALSE; 2618 2619 tgsi_parse_token(&parse); 2620 2621 switch (tok->Token.Type) { 2622 case TGSI_TOKEN_TYPE_INSTRUCTION: 2623 ++pc->insn_cur; 2624 ret = nv50_tgsi_insn(pc, tok); 2625 if (ret == FALSE) 2626 goto out_err; 2627 break; 2628 default: 2629 break; 2630 } 2631 } 2632 2633 if (pc->p->type == PIPE_SHADER_FRAGMENT) 2634 nv50_fp_move_results(pc); 2635 2636 nv50_program_fixup_insns(pc); 2637 2638 p->param_nr = pc->param_nr * 4; 2639 p->immd_nr = pc->immd_nr * 4; 2640 p->immd = pc->immd_buf; 2641 2642out_err: 2643 tgsi_parse_free(&parse); 2644 2645out_cleanup: 2646 free_nv50_pc(pc); 2647 return ret; 2648} 2649 2650static void 2651nv50_program_validate(struct nv50_context *nv50, struct nv50_program *p) 2652{ 2653 if (nv50_program_tx(p) == FALSE) 2654 assert(0); 2655 p->translated = TRUE; 2656} 2657 2658static void 2659nv50_program_upload_data(struct nv50_context *nv50, float *map, 2660 unsigned start, unsigned count, unsigned cbuf) 2661{ 2662 struct nouveau_channel *chan = nv50->screen->base.channel; 2663 struct nouveau_grobj *tesla = nv50->screen->tesla; 2664 2665 while (count) { 2666 unsigned nr = count > 2047 ? 2047 : count; 2667 2668 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1); 2669 OUT_RING (chan, (cbuf << 0) | (start << 8)); 2670 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr); 2671 OUT_RINGp (chan, map, nr); 2672 2673 map += nr; 2674 start += nr; 2675 count -= nr; 2676 } 2677} 2678 2679static void 2680nv50_program_validate_data(struct nv50_context *nv50, struct nv50_program *p) 2681{ 2682 struct pipe_screen *pscreen = nv50->pipe.screen; 2683 2684 if (!p->data[0] && p->immd_nr) { 2685 struct nouveau_resource *heap = nv50->screen->immd_heap[0]; 2686 2687 if (nouveau_resource_alloc(heap, p->immd_nr, p, &p->data[0])) { 2688 while (heap->next && heap->size < p->immd_nr) { 2689 struct nv50_program *evict = heap->next->priv; 2690 nouveau_resource_free(&evict->data[0]); 2691 } 2692 2693 if (nouveau_resource_alloc(heap, p->immd_nr, p, 2694 &p->data[0])) 2695 assert(0); 2696 } 2697 2698 /* immediates only need to be uploaded again when freed */ 2699 nv50_program_upload_data(nv50, p->immd, p->data[0]->start, 2700 p->immd_nr, NV50_CB_PMISC); 2701 } 2702 2703 assert(p->param_nr <= 128); 2704 2705 if (p->param_nr) { 2706 unsigned cb; 2707 float *map = pipe_buffer_map(pscreen, nv50->constbuf[p->type], 2708 PIPE_BUFFER_USAGE_CPU_READ); 2709 2710 if (p->type == PIPE_SHADER_VERTEX) 2711 cb = NV50_CB_PVP; 2712 else 2713 cb = NV50_CB_PFP; 2714 2715 nv50_program_upload_data(nv50, map, 0, p->param_nr, cb); 2716 pipe_buffer_unmap(pscreen, nv50->constbuf[p->type]); 2717 } 2718} 2719 2720static void 2721nv50_program_validate_code(struct nv50_context *nv50, struct nv50_program *p) 2722{ 2723 struct nouveau_channel *chan = nv50->screen->base.channel; 2724 struct nouveau_grobj *tesla = nv50->screen->tesla; 2725 struct nv50_program_exec *e; 2726 struct nouveau_stateobj *so; 2727 const unsigned flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_WR; 2728 unsigned start, count, *up, *ptr; 2729 boolean upload = FALSE; 2730 2731 if (!p->bo) { 2732 nouveau_bo_new(chan->device, NOUVEAU_BO_VRAM, 0x100, 2733 p->exec_size * 4, &p->bo); 2734 upload = TRUE; 2735 } 2736 2737 if (p->data[0] && p->data[0]->start != p->data_start[0]) 2738 upload = TRUE; 2739 2740 if (!upload) 2741 return; 2742 2743 for (e = p->exec_head; e; e = e->next) { 2744 unsigned ei, ci, bs; 2745 2746 if (e->param.index < 0) 2747 continue; 2748 2749 if (e->param.mask == 0) { 2750 assert(!(e->param.index & 1)); 2751 /* seem to be 8 byte steps */ 2752 ei = (e->param.index >> 1) + 0 /* START_ID */; 2753 2754 e->inst[0] &= 0xf0000fff; 2755 e->inst[0] |= ei << 12; 2756 continue; 2757 } 2758 2759 bs = (e->inst[1] >> 22) & 0x07; 2760 assert(bs < 2); 2761 ei = e->param.shift >> 5; 2762 ci = e->param.index; 2763 if (bs == 0) 2764 ci += p->data[bs]->start; 2765 2766 e->inst[ei] &= ~e->param.mask; 2767 e->inst[ei] |= (ci << e->param.shift); 2768 } 2769 2770 if (p->data[0]) 2771 p->data_start[0] = p->data[0]->start; 2772 2773#ifdef NV50_PROGRAM_DUMP 2774 NOUVEAU_ERR("-------\n"); 2775 for (e = p->exec_head; e; e = e->next) { 2776 NOUVEAU_ERR("0x%08x\n", e->inst[0]); 2777 if (is_long(e)) 2778 NOUVEAU_ERR("0x%08x\n", e->inst[1]); 2779 } 2780#endif 2781 2782 up = ptr = MALLOC(p->exec_size * 4); 2783 for (e = p->exec_head; e; e = e->next) { 2784 *(ptr++) = e->inst[0]; 2785 if (is_long(e)) 2786 *(ptr++) = e->inst[1]; 2787 } 2788 2789 so = so_new(4,2); 2790 so_method(so, nv50->screen->tesla, NV50TCL_CB_DEF_ADDRESS_HIGH, 3); 2791 so_reloc (so, p->bo, 0, flags | NOUVEAU_BO_HIGH, 0, 0); 2792 so_reloc (so, p->bo, 0, flags | NOUVEAU_BO_LOW, 0, 0); 2793 so_data (so, (NV50_CB_PUPLOAD << 16) | 0x0800); //(p->exec_size * 4)); 2794 2795 start = 0; count = p->exec_size; 2796 while (count) { 2797 struct nouveau_channel *chan = nv50->screen->base.channel; 2798 unsigned nr; 2799 2800 so_emit(chan, so); 2801 2802 nr = MIN2(count, 2047); 2803 nr = MIN2(chan->pushbuf->remaining, nr); 2804 if (chan->pushbuf->remaining < (nr + 3)) { 2805 FIRE_RING(chan); 2806 continue; 2807 } 2808 2809 BEGIN_RING(chan, tesla, NV50TCL_CB_ADDR, 1); 2810 OUT_RING (chan, (start << 8) | NV50_CB_PUPLOAD); 2811 BEGIN_RING(chan, tesla, NV50TCL_CB_DATA(0) | 0x40000000, nr); 2812 OUT_RINGp (chan, up + start, nr); 2813 2814 start += nr; 2815 count -= nr; 2816 } 2817 2818 FREE(up); 2819 so_ref(NULL, &so); 2820} 2821 2822void 2823nv50_vertprog_validate(struct nv50_context *nv50) 2824{ 2825 struct nouveau_grobj *tesla = nv50->screen->tesla; 2826 struct nv50_program *p = nv50->vertprog; 2827 struct nouveau_stateobj *so; 2828 2829 if (!p->translated) { 2830 nv50_program_validate(nv50, p); 2831 if (!p->translated) 2832 assert(0); 2833 } 2834 2835 nv50_program_validate_data(nv50, p); 2836 nv50_program_validate_code(nv50, p); 2837 2838 so = so_new(13, 2); 2839 so_method(so, tesla, NV50TCL_VP_ADDRESS_HIGH, 2); 2840 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | 2841 NOUVEAU_BO_HIGH, 0, 0); 2842 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | 2843 NOUVEAU_BO_LOW, 0, 0); 2844 so_method(so, tesla, NV50TCL_VP_ATTR_EN_0, 2); 2845 so_data (so, p->cfg.attr[0]); 2846 so_data (so, p->cfg.attr[1]); 2847 so_method(so, tesla, NV50TCL_VP_REG_ALLOC_RESULT, 1); 2848 so_data (so, p->cfg.high_result); 2849 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 2); 2850 so_data (so, p->cfg.high_result); //8); 2851 so_data (so, p->cfg.high_temp); 2852 so_method(so, tesla, NV50TCL_VP_START_ID, 1); 2853 so_data (so, 0); /* program start offset */ 2854 so_ref(so, &nv50->state.vertprog); 2855 so_ref(NULL, &so); 2856} 2857 2858void 2859nv50_fragprog_validate(struct nv50_context *nv50) 2860{ 2861 struct nouveau_grobj *tesla = nv50->screen->tesla; 2862 struct nv50_program *p = nv50->fragprog; 2863 struct nouveau_stateobj *so; 2864 2865 if (!p->translated) { 2866 nv50_program_validate(nv50, p); 2867 if (!p->translated) 2868 assert(0); 2869 } 2870 2871 nv50_program_validate_data(nv50, p); 2872 nv50_program_validate_code(nv50, p); 2873 2874 so = so_new(64, 2); 2875 so_method(so, tesla, NV50TCL_FP_ADDRESS_HIGH, 2); 2876 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | 2877 NOUVEAU_BO_HIGH, 0, 0); 2878 so_reloc (so, p->bo, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | 2879 NOUVEAU_BO_LOW, 0, 0); 2880 so_method(so, tesla, NV50TCL_FP_REG_ALLOC_TEMP, 1); 2881 so_data (so, p->cfg.high_temp); 2882 so_method(so, tesla, NV50TCL_FP_RESULT_COUNT, 1); 2883 so_data (so, p->cfg.high_result); 2884 so_method(so, tesla, NV50TCL_FP_CTRL_UNK19A8, 1); 2885 so_data (so, p->cfg.regs[2]); 2886 so_method(so, tesla, NV50TCL_FP_CTRL_UNK196C, 1); 2887 so_data (so, p->cfg.regs[3]); 2888 so_method(so, tesla, NV50TCL_FP_START_ID, 1); 2889 so_data (so, 0); /* program start offset */ 2890 so_ref(so, &nv50->state.fragprog); 2891 so_ref(NULL, &so); 2892} 2893 2894static void 2895nv50_pntc_replace(struct nv50_context *nv50, uint32_t pntc[8], unsigned base) 2896{ 2897 struct nv50_program *fp = nv50->fragprog; 2898 struct nv50_program *vp = nv50->vertprog; 2899 unsigned i, c, m = base; 2900 2901 /* XXX: This can't work correctly in all cases yet, we either 2902 * have to create TGSI_SEMANTIC_PNTC or sprite_coord_mode has 2903 * to be per FP input instead of per VP output 2904 */ 2905 memset(pntc, 0, 8 * sizeof(uint32_t)); 2906 2907 for (i = 0; i < fp->cfg.io_nr; i++) { 2908 uint8_t sn, si; 2909 uint8_t j = fp->cfg.io[i].id_vp, k = fp->cfg.io[i].id_fp; 2910 unsigned n = popcnt4(fp->cfg.io[i].mask); 2911 2912 if (fp->info.input_semantic_name[k] != TGSI_SEMANTIC_GENERIC) { 2913 m += n; 2914 continue; 2915 } 2916 2917 sn = vp->info.input_semantic_name[j]; 2918 si = vp->info.input_semantic_index[j]; 2919 2920 if (j < fp->cfg.io_nr && sn == TGSI_SEMANTIC_GENERIC) { 2921 ubyte mode = 2922 nv50->rasterizer->pipe.sprite_coord_mode[si]; 2923 2924 if (mode == PIPE_SPRITE_COORD_NONE) { 2925 m += n; 2926 continue; 2927 } 2928 } 2929 2930 /* this is either PointCoord or replaced by sprite coords */ 2931 for (c = 0; c < 4; c++) { 2932 if (!(fp->cfg.io[i].mask & (1 << c))) 2933 continue; 2934 pntc[m / 8] |= (c + 1) << ((m % 8) * 4); 2935 ++m; 2936 } 2937 } 2938} 2939 2940static int 2941nv50_sreg4_map(uint32_t *p_map, int mid, uint32_t lin[4], 2942 struct nv50_sreg4 *fpi, struct nv50_sreg4 *vpo) 2943{ 2944 int c; 2945 uint8_t mv = vpo->mask, mf = fpi->mask, oid = vpo->hw; 2946 uint8_t *map = (uint8_t *)p_map; 2947 2948 for (c = 0; c < 4; ++c) { 2949 if (mf & 1) { 2950 if (fpi->linear == TRUE) 2951 lin[mid / 32] |= 1 << (mid % 32); 2952 map[mid++] = (mv & 1) ? oid : ((c == 3) ? 0x41 : 0x40); 2953 } 2954 2955 oid += mv & 1; 2956 mf >>= 1; 2957 mv >>= 1; 2958 } 2959 2960 return mid; 2961} 2962 2963void 2964nv50_linkage_validate(struct nv50_context *nv50) 2965{ 2966 struct nouveau_grobj *tesla = nv50->screen->tesla; 2967 struct nv50_program *vp = nv50->vertprog; 2968 struct nv50_program *fp = nv50->fragprog; 2969 struct nouveau_stateobj *so; 2970 struct nv50_sreg4 dummy, *vpo; 2971 int i, n, c, m = 0; 2972 uint32_t map[16], lin[4], reg[5], pcrd[8]; 2973 2974 memset(map, 0, sizeof(map)); 2975 memset(lin, 0, sizeof(lin)); 2976 2977 reg[1] = 0x00000004; /* low and high clip distance map ids */ 2978 reg[2] = 0x00000000; /* layer index map id (disabled, GP only) */ 2979 reg[3] = 0x00000000; /* point size map id & enable */ 2980 reg[0] = fp->cfg.regs[0]; /* colour semantic reg */ 2981 reg[4] = fp->cfg.regs[1]; /* interpolant info */ 2982 2983 dummy.linear = FALSE; 2984 dummy.mask = 0xf; /* map all components of HPOS */ 2985 m = nv50_sreg4_map(map, m, lin, &dummy, &vp->cfg.io[0]); 2986 2987 dummy.mask = 0x0; 2988 2989 if (vp->cfg.clpd < 0x40) { 2990 for (c = 0; c < vp->cfg.clpd_nr; ++c) 2991 map[m++] = vp->cfg.clpd + c; 2992 reg[1] = (m << 8); 2993 } 2994 2995 reg[0] |= m << 8; /* adjust BFC0 id */ 2996 2997 /* if light_twoside is active, it seems FFC0_ID == BFC0_ID is bad */ 2998 if (nv50->rasterizer->pipe.light_twoside) { 2999 vpo = &vp->cfg.two_side[0]; 3000 3001 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[0], &vpo[0]); 3002 m = nv50_sreg4_map(map, m, lin, &fp->cfg.two_side[1], &vpo[1]); 3003 } 3004 3005 reg[0] += m - 4; /* adjust FFC0 id */ 3006 reg[4] |= m << 8; /* set mid where 'normal' FP inputs start */ 3007 3008 i = 0; 3009 if (fp->info.input_semantic_name[0] == TGSI_SEMANTIC_POSITION) 3010 i = 1; 3011 for (; i < fp->cfg.io_nr; i++) { 3012 ubyte sn = fp->info.input_semantic_name[fp->cfg.io[i].id_fp]; 3013 ubyte si = fp->info.input_semantic_index[fp->cfg.io[i].id_fp]; 3014 3015 n = fp->cfg.io[i].id_vp; 3016 if (n >= vp->cfg.io_nr || 3017 vp->info.output_semantic_name[n] != sn || 3018 vp->info.output_semantic_index[n] != si) 3019 vpo = &dummy; 3020 else 3021 vpo = &vp->cfg.io[n]; 3022 3023 m = nv50_sreg4_map(map, m, lin, &fp->cfg.io[i], vpo); 3024 } 3025 3026 if (nv50->rasterizer->pipe.point_size_per_vertex) { 3027 map[m / 4] |= vp->cfg.psiz << ((m % 4) * 8); 3028 reg[3] = (m++ << 4) | 1; 3029 } 3030 3031 /* now fill the stateobj */ 3032 so = so_new(64, 0); 3033 3034 n = (m + 3) / 4; 3035 so_method(so, tesla, NV50TCL_VP_RESULT_MAP_SIZE, 1); 3036 so_data (so, m); 3037 so_method(so, tesla, NV50TCL_VP_RESULT_MAP(0), n); 3038 so_datap (so, map, n); 3039 3040 so_method(so, tesla, NV50TCL_MAP_SEMANTIC_0, 4); 3041 so_datap (so, reg, 4); 3042 3043 so_method(so, tesla, NV50TCL_FP_INTERPOLANT_CTRL, 1); 3044 so_data (so, reg[4]); 3045 3046 so_method(so, tesla, 0x1540, 4); 3047 so_datap (so, lin, 4); 3048 3049 if (nv50->rasterizer->pipe.point_sprite) { 3050 nv50_pntc_replace(nv50, pcrd, (reg[4] >> 8) & 0xff); 3051 3052 so_method(so, tesla, NV50TCL_POINT_COORD_REPLACE_MAP(0), 8); 3053 so_datap (so, pcrd, 8); 3054 } 3055 3056 so_ref(so, &nv50->state.programs); 3057 so_ref(NULL, &so); 3058} 3059 3060void 3061nv50_program_destroy(struct nv50_context *nv50, struct nv50_program *p) 3062{ 3063 while (p->exec_head) { 3064 struct nv50_program_exec *e = p->exec_head; 3065 3066 p->exec_head = e->next; 3067 FREE(e); 3068 } 3069 p->exec_tail = NULL; 3070 p->exec_size = 0; 3071 3072 nouveau_bo_ref(NULL, &p->bo); 3073 3074 nouveau_resource_free(&p->data[0]); 3075 3076 p->translated = 0; 3077} 3078