nv50_screen.c revision 51ba1c1ae1ea6eff0e0c727aeec48d3433ec5bce
1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "util/u_format.h" 24#include "util/u_format_s3tc.h" 25#include "pipe/p_screen.h" 26 27#include "nv50_context.h" 28#include "nv50_screen.h" 29 30#include "nouveau/nv_object.xml.h" 31#include <errno.h> 32 33#ifndef NOUVEAU_GETPARAM_GRAPH_UNITS 34# define NOUVEAU_GETPARAM_GRAPH_UNITS 13 35#endif 36 37/* affected by LOCAL_WARPS_LOG_ALLOC / LOCAL_WARPS_NO_CLAMP */ 38#define LOCAL_WARPS_ALLOC 32 39/* affected by STACK_WARPS_LOG_ALLOC / STACK_WARPS_NO_CLAMP */ 40#define STACK_WARPS_ALLOC 32 41 42#define THREADS_IN_WARP 32 43 44#define ONE_TEMP_SIZE (4/*vector*/ * sizeof(float)) 45 46static boolean 47nv50_screen_is_format_supported(struct pipe_screen *pscreen, 48 enum pipe_format format, 49 enum pipe_texture_target target, 50 unsigned sample_count, 51 unsigned bindings) 52{ 53 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ 54 return FALSE; 55 if (sample_count == 8 && util_format_get_blocksizebits(format) >= 128) 56 return FALSE; 57 58 if (!util_format_is_supported(format, bindings)) 59 return FALSE; 60 61 switch (format) { 62 case PIPE_FORMAT_Z16_UNORM: 63 if (nv50_screen(pscreen)->tesla->oclass < NVA0_3D_CLASS) 64 return FALSE; 65 break; 66 case PIPE_FORMAT_R8G8B8A8_UNORM: 67 case PIPE_FORMAT_R8G8B8X8_UNORM: 68 /* HACK: GL requires equal formats for MS resolve and window is BGRA */ 69 if (bindings & PIPE_BIND_RENDER_TARGET) 70 return FALSE; 71 default: 72 break; 73 } 74 75 /* transfers & shared are always supported */ 76 bindings &= ~(PIPE_BIND_TRANSFER_READ | 77 PIPE_BIND_TRANSFER_WRITE | 78 PIPE_BIND_SHARED); 79 80 return (nv50_format_table[format].usage & bindings) == bindings; 81} 82 83static int 84nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 85{ 86 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d; 87 88 switch (param) { 89 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 90 return 64; 91 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 92 return 14; 93 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 94 return 12; 95 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 96 return 14; 97 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 98 return 512; 99 case PIPE_CAP_MIN_TEXEL_OFFSET: 100 return -8; 101 case PIPE_CAP_MAX_TEXEL_OFFSET: 102 return 7; 103 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 104 case PIPE_CAP_TEXTURE_SWIZZLE: 105 case PIPE_CAP_TEXTURE_SHADOW_MAP: 106 case PIPE_CAP_NPOT_TEXTURES: 107 case PIPE_CAP_ANISOTROPIC_FILTER: 108 case PIPE_CAP_SCALED_RESOLVE: 109 return 1; 110 case PIPE_CAP_SEAMLESS_CUBE_MAP: 111 return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS; 112 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 113 return 0; 114 case PIPE_CAP_TWO_SIDED_STENCIL: 115 case PIPE_CAP_DEPTH_CLIP_DISABLE: 116 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 117 case PIPE_CAP_POINT_SPRITE: 118 return 1; 119 case PIPE_CAP_SM3: 120 return 1; 121 case PIPE_CAP_GLSL_FEATURE_LEVEL: 122 return 130; 123 case PIPE_CAP_MAX_RENDER_TARGETS: 124 return 8; 125 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 126 return 1; 127 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 128 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 129 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 130 return 1; 131 case PIPE_CAP_QUERY_TIMESTAMP: 132 case PIPE_CAP_TIMER_QUERY: 133 case PIPE_CAP_OCCLUSION_QUERY: 134 return 1; 135 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 136 return 4; 137 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 138 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 139 return 64; 140 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 141 return (class_3d >= NVA0_3D_CLASS) ? 1 : 0; 142 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 143 case PIPE_CAP_INDEP_BLEND_ENABLE: 144 return 1; 145 case PIPE_CAP_INDEP_BLEND_FUNC: 146 return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS; 147 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 148 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 149 return 1; 150 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 151 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 152 return 0; 153 case PIPE_CAP_SHADER_STENCIL_EXPORT: 154 return 0; 155 case PIPE_CAP_PRIMITIVE_RESTART: 156 case PIPE_CAP_TGSI_INSTANCEID: 157 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 158 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 159 case PIPE_CAP_CONDITIONAL_RENDER: 160 case PIPE_CAP_TEXTURE_BARRIER: 161 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 162 case PIPE_CAP_START_INSTANCE: 163 return 1; 164 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 165 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 166 return 0; /* state trackers will know better */ 167 case PIPE_CAP_USER_CONSTANT_BUFFERS: 168 case PIPE_CAP_USER_INDEX_BUFFERS: 169 case PIPE_CAP_USER_VERTEX_BUFFERS: 170 return 1; 171 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 172 return 256; 173 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 174 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 175 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 176 return 0; 177 default: 178 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 179 return 0; 180 } 181} 182 183static int 184nv50_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, 185 enum pipe_shader_cap param) 186{ 187 switch (shader) { 188 case PIPE_SHADER_VERTEX: 189 case PIPE_SHADER_GEOMETRY: 190 case PIPE_SHADER_FRAGMENT: 191 break; 192 default: 193 return 0; 194 } 195 196 switch (param) { 197 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 198 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 199 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 200 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 201 return 16384; 202 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 203 return 4; 204 case PIPE_SHADER_CAP_MAX_INPUTS: 205 if (shader == PIPE_SHADER_VERTEX) 206 return 32; 207 return 0x300 / 16; 208 case PIPE_SHADER_CAP_MAX_CONSTS: 209 return 65536 / 16; 210 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 211 return NV50_MAX_PIPE_CONSTBUFS; 212 case PIPE_SHADER_CAP_MAX_ADDRS: 213 return 1; 214 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 215 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 216 return shader != PIPE_SHADER_FRAGMENT; 217 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 218 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 219 return 1; 220 case PIPE_SHADER_CAP_MAX_PREDS: 221 return 0; 222 case PIPE_SHADER_CAP_MAX_TEMPS: 223 return nv50_screen(pscreen)->max_tls_space / ONE_TEMP_SIZE; 224 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 225 return 1; 226 case PIPE_SHADER_CAP_SUBROUTINES: 227 return 0; /* please inline, or provide function declarations */ 228 case PIPE_SHADER_CAP_INTEGERS: 229 return 1; 230 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 231 return 32; 232 default: 233 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); 234 return 0; 235 } 236} 237 238static float 239nv50_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 240{ 241 switch (param) { 242 case PIPE_CAPF_MAX_LINE_WIDTH: 243 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 244 return 10.0f; 245 case PIPE_CAPF_MAX_POINT_WIDTH: 246 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 247 return 64.0f; 248 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 249 return 16.0f; 250 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 251 return 4.0f; 252 default: 253 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 254 return 0.0f; 255 } 256} 257 258static void 259nv50_screen_destroy(struct pipe_screen *pscreen) 260{ 261 struct nv50_screen *screen = nv50_screen(pscreen); 262 263 if (screen->base.fence.current) { 264 nouveau_fence_wait(screen->base.fence.current); 265 nouveau_fence_ref (NULL, &screen->base.fence.current); 266 } 267 if (screen->base.pushbuf) 268 screen->base.pushbuf->user_priv = NULL; 269 270 if (screen->blitctx) 271 FREE(screen->blitctx); 272 273 nouveau_bo_ref(NULL, &screen->code); 274 nouveau_bo_ref(NULL, &screen->tls_bo); 275 nouveau_bo_ref(NULL, &screen->stack_bo); 276 nouveau_bo_ref(NULL, &screen->txc); 277 nouveau_bo_ref(NULL, &screen->uniforms); 278 nouveau_bo_ref(NULL, &screen->fence.bo); 279 280 nouveau_heap_destroy(&screen->vp_code_heap); 281 nouveau_heap_destroy(&screen->gp_code_heap); 282 nouveau_heap_destroy(&screen->fp_code_heap); 283 284 if (screen->tic.entries) 285 FREE(screen->tic.entries); 286 287 nouveau_object_del(&screen->tesla); 288 nouveau_object_del(&screen->eng2d); 289 nouveau_object_del(&screen->m2mf); 290 nouveau_object_del(&screen->sync); 291 292 nouveau_screen_fini(&screen->base); 293 294 FREE(screen); 295} 296 297static void 298nv50_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence) 299{ 300 struct nv50_screen *screen = nv50_screen(pscreen); 301 struct nouveau_pushbuf *push = screen->base.pushbuf; 302 303 /* we need to do it after possible flush in MARK_RING */ 304 *sequence = ++screen->base.fence.sequence; 305 306 PUSH_DATA (push, NV50_FIFO_PKHDR(NV50_3D(QUERY_ADDRESS_HIGH), 4)); 307 PUSH_DATAh(push, screen->fence.bo->offset); 308 PUSH_DATA (push, screen->fence.bo->offset); 309 PUSH_DATA (push, *sequence); 310 PUSH_DATA (push, NV50_3D_QUERY_GET_MODE_WRITE_UNK0 | 311 NV50_3D_QUERY_GET_UNK4 | 312 NV50_3D_QUERY_GET_UNIT_CROP | 313 NV50_3D_QUERY_GET_TYPE_QUERY | 314 NV50_3D_QUERY_GET_QUERY_SELECT_ZERO | 315 NV50_3D_QUERY_GET_SHORT); 316} 317 318static u32 319nv50_screen_fence_update(struct pipe_screen *pscreen) 320{ 321 return nv50_screen(pscreen)->fence.map[0]; 322} 323 324static void 325nv50_screen_init_hwctx(struct nv50_screen *screen) 326{ 327 struct nouveau_pushbuf *push = screen->base.pushbuf; 328 struct nv04_fifo *fifo; 329 unsigned i; 330 331 fifo = (struct nv04_fifo *)screen->base.channel->data; 332 333 BEGIN_NV04(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1); 334 PUSH_DATA (push, screen->m2mf->handle); 335 BEGIN_NV04(push, SUBC_M2MF(NV03_M2MF_DMA_NOTIFY), 3); 336 PUSH_DATA (push, screen->sync->handle); 337 PUSH_DATA (push, fifo->vram); 338 PUSH_DATA (push, fifo->vram); 339 340 BEGIN_NV04(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1); 341 PUSH_DATA (push, screen->eng2d->handle); 342 BEGIN_NV04(push, NV50_2D(DMA_NOTIFY), 4); 343 PUSH_DATA (push, screen->sync->handle); 344 PUSH_DATA (push, fifo->vram); 345 PUSH_DATA (push, fifo->vram); 346 PUSH_DATA (push, fifo->vram); 347 BEGIN_NV04(push, NV50_2D(OPERATION), 1); 348 PUSH_DATA (push, NV50_2D_OPERATION_SRCCOPY); 349 BEGIN_NV04(push, NV50_2D(CLIP_ENABLE), 1); 350 PUSH_DATA (push, 0); 351 BEGIN_NV04(push, NV50_2D(COLOR_KEY_ENABLE), 1); 352 PUSH_DATA (push, 0); 353 BEGIN_NV04(push, SUBC_2D(0x0888), 1); 354 PUSH_DATA (push, 1); 355 356 BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1); 357 PUSH_DATA (push, screen->tesla->handle); 358 359 BEGIN_NV04(push, NV50_3D(COND_MODE), 1); 360 PUSH_DATA (push, NV50_3D_COND_MODE_ALWAYS); 361 362 BEGIN_NV04(push, NV50_3D(DMA_NOTIFY), 1); 363 PUSH_DATA (push, screen->sync->handle); 364 BEGIN_NV04(push, NV50_3D(DMA_ZETA), 11); 365 for (i = 0; i < 11; ++i) 366 PUSH_DATA(push, fifo->vram); 367 BEGIN_NV04(push, NV50_3D(DMA_COLOR(0)), NV50_3D_DMA_COLOR__LEN); 368 for (i = 0; i < NV50_3D_DMA_COLOR__LEN; ++i) 369 PUSH_DATA(push, fifo->vram); 370 371 BEGIN_NV04(push, NV50_3D(REG_MODE), 1); 372 PUSH_DATA (push, NV50_3D_REG_MODE_STRIPED); 373 BEGIN_NV04(push, NV50_3D(UNK1400_LANES), 1); 374 PUSH_DATA (push, 0xf); 375 376 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) { 377 BEGIN_NV04(push, NV50_3D(WATCHDOG_TIMER), 1); 378 PUSH_DATA (push, 0x18); 379 } 380 381 BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1); 382 PUSH_DATA (push, 1); 383 384 BEGIN_NV04(push, NV50_3D(CSAA_ENABLE), 1); 385 PUSH_DATA (push, 0); 386 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_ENABLE), 1); 387 PUSH_DATA (push, 0); 388 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_MODE), 1); 389 PUSH_DATA (push, NV50_3D_MULTISAMPLE_MODE_MS1); 390 BEGIN_NV04(push, NV50_3D(MULTISAMPLE_CTRL), 1); 391 PUSH_DATA (push, 0); 392 BEGIN_NV04(push, NV50_3D(LINE_LAST_PIXEL), 1); 393 PUSH_DATA (push, 0); 394 BEGIN_NV04(push, NV50_3D(BLEND_SEPARATE_ALPHA), 1); 395 PUSH_DATA (push, 1); 396 397 if (screen->tesla->oclass >= NVA0_3D_CLASS) { 398 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1); 399 PUSH_DATA (push, NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP); 400 } 401 402 BEGIN_NV04(push, NV50_3D(SCREEN_Y_CONTROL), 1); 403 PUSH_DATA (push, 0); 404 BEGIN_NV04(push, NV50_3D(WINDOW_OFFSET_X), 2); 405 PUSH_DATA (push, 0); 406 PUSH_DATA (push, 0); 407 BEGIN_NV04(push, NV50_3D(ZCULL_REGION), 1); 408 PUSH_DATA (push, 0x3f); 409 410 BEGIN_NV04(push, NV50_3D(VP_ADDRESS_HIGH), 2); 411 PUSH_DATAh(push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2)); 412 PUSH_DATA (push, screen->code->offset + (0 << NV50_CODE_BO_SIZE_LOG2)); 413 414 BEGIN_NV04(push, NV50_3D(FP_ADDRESS_HIGH), 2); 415 PUSH_DATAh(push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2)); 416 PUSH_DATA (push, screen->code->offset + (1 << NV50_CODE_BO_SIZE_LOG2)); 417 418 BEGIN_NV04(push, NV50_3D(GP_ADDRESS_HIGH), 2); 419 PUSH_DATAh(push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2)); 420 PUSH_DATA (push, screen->code->offset + (2 << NV50_CODE_BO_SIZE_LOG2)); 421 422 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3); 423 PUSH_DATAh(push, screen->tls_bo->offset); 424 PUSH_DATA (push, screen->tls_bo->offset); 425 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8)); 426 427 BEGIN_NV04(push, NV50_3D(STACK_ADDRESS_HIGH), 3); 428 PUSH_DATAh(push, screen->stack_bo->offset); 429 PUSH_DATA (push, screen->stack_bo->offset); 430 PUSH_DATA (push, 4); 431 432 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); 433 PUSH_DATAh(push, screen->uniforms->offset + (0 << 16)); 434 PUSH_DATA (push, screen->uniforms->offset + (0 << 16)); 435 PUSH_DATA (push, (NV50_CB_PVP << 16) | 0x0000); 436 437 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); 438 PUSH_DATAh(push, screen->uniforms->offset + (1 << 16)); 439 PUSH_DATA (push, screen->uniforms->offset + (1 << 16)); 440 PUSH_DATA (push, (NV50_CB_PGP << 16) | 0x0000); 441 442 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); 443 PUSH_DATAh(push, screen->uniforms->offset + (2 << 16)); 444 PUSH_DATA (push, screen->uniforms->offset + (2 << 16)); 445 PUSH_DATA (push, (NV50_CB_PFP << 16) | 0x0000); 446 447 BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3); 448 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16)); 449 PUSH_DATA (push, screen->uniforms->offset + (3 << 16)); 450 PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200); 451 452 BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3); 453 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01); 454 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21); 455 PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31); 456 457 /* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */ 458 BEGIN_NV04(push, NV50_3D(CB_ADDR), 1); 459 PUSH_DATA (push, ((1 << 9) << 6) | NV50_CB_AUX); 460 BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4); 461 PUSH_DATAf(push, 0.0f); 462 PUSH_DATAf(push, 0.0f); 463 PUSH_DATAf(push, 0.0f); 464 PUSH_DATAf(push, 0.0f); 465 BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2); 466 PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + (1 << 9)); 467 PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + (1 << 9)); 468 469 /* max TIC (bits 4:8) & TSC bindings, per program type */ 470 for (i = 0; i < 3; ++i) { 471 BEGIN_NV04(push, NV50_3D(TEX_LIMITS(i)), 1); 472 PUSH_DATA (push, 0x54); 473 } 474 475 BEGIN_NV04(push, NV50_3D(TIC_ADDRESS_HIGH), 3); 476 PUSH_DATAh(push, screen->txc->offset); 477 PUSH_DATA (push, screen->txc->offset); 478 PUSH_DATA (push, NV50_TIC_MAX_ENTRIES - 1); 479 480 BEGIN_NV04(push, NV50_3D(TSC_ADDRESS_HIGH), 3); 481 PUSH_DATAh(push, screen->txc->offset + 65536); 482 PUSH_DATA (push, screen->txc->offset + 65536); 483 PUSH_DATA (push, NV50_TSC_MAX_ENTRIES - 1); 484 485 BEGIN_NV04(push, NV50_3D(LINKED_TSC), 1); 486 PUSH_DATA (push, 0); 487 488 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_EN), 1); 489 PUSH_DATA (push, 0); 490 BEGIN_NV04(push, NV50_3D(CLIP_RECTS_MODE), 1); 491 PUSH_DATA (push, NV50_3D_CLIP_RECTS_MODE_INSIDE_ANY); 492 BEGIN_NV04(push, NV50_3D(CLIP_RECT_HORIZ(0)), 8 * 2); 493 for (i = 0; i < 8 * 2; ++i) 494 PUSH_DATA(push, 0); 495 BEGIN_NV04(push, NV50_3D(CLIPID_ENABLE), 1); 496 PUSH_DATA (push, 0); 497 498 BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1); 499 PUSH_DATA (push, 1); 500 BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2); 501 PUSH_DATAf(push, 0.0f); 502 PUSH_DATAf(push, 1.0f); 503 504 BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1); 505#ifdef NV50_SCISSORS_CLIPPING 506 PUSH_DATA (push, 0x0000); 507#else 508 PUSH_DATA (push, 0x1080); 509#endif 510 511 BEGIN_NV04(push, NV50_3D(CLEAR_FLAGS), 1); 512 PUSH_DATA (push, NV50_3D_CLEAR_FLAGS_CLEAR_RECT_VIEWPORT); 513 514 /* We use scissors instead of exact view volume clipping, 515 * so they're always enabled. 516 */ 517 BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3); 518 PUSH_DATA (push, 1); 519 PUSH_DATA (push, 8192 << 16); 520 PUSH_DATA (push, 8192 << 16); 521 522 BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1); 523 PUSH_DATA (push, 1); 524 BEGIN_NV04(push, NV50_3D(POINT_RASTER_RULES), 1); 525 PUSH_DATA (push, NV50_3D_POINT_RASTER_RULES_OGL); 526 BEGIN_NV04(push, NV50_3D(FRAG_COLOR_CLAMP_EN), 1); 527 PUSH_DATA (push, 0x11111111); 528 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1); 529 PUSH_DATA (push, 1); 530 531 PUSH_KICK (push); 532} 533 534static int nv50_tls_alloc(struct nv50_screen *screen, unsigned tls_space, 535 uint64_t *tls_size) 536{ 537 struct nouveau_device *dev = screen->base.device; 538 int ret; 539 540 screen->cur_tls_space = util_next_power_of_two(tls_space / ONE_TEMP_SIZE) * 541 ONE_TEMP_SIZE; 542 if (nouveau_mesa_debug) 543 debug_printf("allocating space for %u temps\n", 544 util_next_power_of_two(tls_space / ONE_TEMP_SIZE)); 545 *tls_size = screen->cur_tls_space * util_next_power_of_two(screen->TPs) * 546 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP; 547 548 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 549 *tls_size, NULL, &screen->tls_bo); 550 if (ret) { 551 NOUVEAU_ERR("Failed to allocate local bo: %d\n", ret); 552 return ret; 553 } 554 555 return 0; 556} 557 558int nv50_tls_realloc(struct nv50_screen *screen, unsigned tls_space) 559{ 560 struct nouveau_pushbuf *push = screen->base.pushbuf; 561 int ret; 562 uint64_t tls_size; 563 564 if (tls_space < screen->cur_tls_space) 565 return 0; 566 if (tls_space > screen->max_tls_space) { 567 /* fixable by limiting number of warps (LOCAL_WARPS_LOG_ALLOC / 568 * LOCAL_WARPS_NO_CLAMP) */ 569 NOUVEAU_ERR("Unsupported number of temporaries (%u > %u). Fixable if someone cares.\n", 570 (unsigned)(tls_space / ONE_TEMP_SIZE), 571 (unsigned)(screen->max_tls_space / ONE_TEMP_SIZE)); 572 return -ENOMEM; 573 } 574 575 nouveau_bo_ref(NULL, &screen->tls_bo); 576 ret = nv50_tls_alloc(screen, tls_space, &tls_size); 577 if (ret) 578 return ret; 579 580 BEGIN_NV04(push, NV50_3D(LOCAL_ADDRESS_HIGH), 3); 581 PUSH_DATAh(push, screen->tls_bo->offset); 582 PUSH_DATA (push, screen->tls_bo->offset); 583 PUSH_DATA (push, util_logbase2(screen->cur_tls_space / 8)); 584 585 return 1; 586} 587 588struct pipe_screen * 589nv50_screen_create(struct nouveau_device *dev) 590{ 591 struct nv50_screen *screen; 592 struct pipe_screen *pscreen; 593 struct nouveau_object *chan; 594 uint64_t value; 595 uint32_t tesla_class; 596 unsigned stack_size; 597 int ret; 598 599 screen = CALLOC_STRUCT(nv50_screen); 600 if (!screen) 601 return NULL; 602 pscreen = &screen->base.base; 603 604 ret = nouveau_screen_init(&screen->base, dev); 605 if (ret) { 606 NOUVEAU_ERR("nouveau_screen_init failed: %d\n", ret); 607 goto fail; 608 } 609 610 /* TODO: Prevent FIFO prefetch before transfer of index buffers and 611 * admit them to VRAM. 612 */ 613 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER | 614 PIPE_BIND_VERTEX_BUFFER; 615 screen->base.sysmem_bindings |= 616 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER; 617 618 screen->base.pushbuf->user_priv = screen; 619 screen->base.pushbuf->rsvd_kick = 5; 620 621 chan = screen->base.channel; 622 623 pscreen->destroy = nv50_screen_destroy; 624 pscreen->context_create = nv50_create; 625 pscreen->is_format_supported = nv50_screen_is_format_supported; 626 pscreen->get_param = nv50_screen_get_param; 627 pscreen->get_shader_param = nv50_screen_get_shader_param; 628 pscreen->get_paramf = nv50_screen_get_paramf; 629 630 nv50_screen_init_resource_functions(pscreen); 631 632 nouveau_screen_init_vdec(&screen->base); 633 634 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, 635 NULL, &screen->fence.bo); 636 if (ret) { 637 NOUVEAU_ERR("Failed to allocate fence bo: %d\n", ret); 638 goto fail; 639 } 640 641 nouveau_bo_map(screen->fence.bo, 0, NULL); 642 screen->fence.map = screen->fence.bo->map; 643 screen->base.fence.emit = nv50_screen_fence_emit; 644 screen->base.fence.update = nv50_screen_fence_update; 645 646 ret = nouveau_object_new(chan, 0xbeef0301, NOUVEAU_NOTIFIER_CLASS, 647 &(struct nv04_notify){ .length = 32 }, 648 sizeof(struct nv04_notify), &screen->sync); 649 if (ret) { 650 NOUVEAU_ERR("Failed to allocate notifier: %d\n", ret); 651 goto fail; 652 } 653 654 ret = nouveau_object_new(chan, 0xbeef5039, NV50_M2MF_CLASS, 655 NULL, 0, &screen->m2mf); 656 if (ret) { 657 NOUVEAU_ERR("Failed to allocate PGRAPH context for M2MF: %d\n", ret); 658 goto fail; 659 } 660 661 ret = nouveau_object_new(chan, 0xbeef502d, NV50_2D_CLASS, 662 NULL, 0, &screen->eng2d); 663 if (ret) { 664 NOUVEAU_ERR("Failed to allocate PGRAPH context for 2D: %d\n", ret); 665 goto fail; 666 } 667 668 switch (dev->chipset & 0xf0) { 669 case 0x50: 670 tesla_class = NV50_3D_CLASS; 671 break; 672 case 0x80: 673 case 0x90: 674 tesla_class = NV84_3D_CLASS; 675 break; 676 case 0xa0: 677 switch (dev->chipset) { 678 case 0xa0: 679 case 0xaa: 680 case 0xac: 681 tesla_class = NVA0_3D_CLASS; 682 break; 683 case 0xaf: 684 tesla_class = NVAF_3D_CLASS; 685 break; 686 default: 687 tesla_class = NVA3_3D_CLASS; 688 break; 689 } 690 break; 691 default: 692 NOUVEAU_ERR("Not a known NV50 chipset: NV%02x\n", dev->chipset); 693 goto fail; 694 } 695 screen->base.class_3d = tesla_class; 696 697 ret = nouveau_object_new(chan, 0xbeef5097, tesla_class, 698 NULL, 0, &screen->tesla); 699 if (ret) { 700 NOUVEAU_ERR("Failed to allocate PGRAPH context for 3D: %d\n", ret); 701 goto fail; 702 } 703 704 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 705 3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code); 706 if (ret) { 707 NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret); 708 goto fail; 709 } 710 711 nouveau_heap_init(&screen->vp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 712 nouveau_heap_init(&screen->gp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 713 nouveau_heap_init(&screen->fp_code_heap, 0, 1 << NV50_CODE_BO_SIZE_LOG2); 714 715 nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value); 716 717 screen->TPs = util_bitcount(value & 0xffff); 718 screen->MPsInTP = util_bitcount((value >> 24) & 0xf); 719 720 stack_size = util_next_power_of_two(screen->TPs) * screen->MPsInTP * 721 STACK_WARPS_ALLOC * 64 * 8; 722 723 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, stack_size, NULL, 724 &screen->stack_bo); 725 if (ret) { 726 NOUVEAU_ERR("Failed to allocate stack bo: %d\n", ret); 727 goto fail; 728 } 729 730 uint64_t size_of_one_temp = util_next_power_of_two(screen->TPs) * 731 screen->MPsInTP * LOCAL_WARPS_ALLOC * THREADS_IN_WARP * 732 ONE_TEMP_SIZE; 733 screen->max_tls_space = dev->vram_size / size_of_one_temp * ONE_TEMP_SIZE; 734 screen->max_tls_space /= 2; /* half of vram */ 735 736 /* hw can address max 64 KiB */ 737 screen->max_tls_space = MIN2(screen->max_tls_space, 64 << 10); 738 739 uint64_t tls_size; 740 unsigned tls_space = 4/*temps*/ * ONE_TEMP_SIZE; 741 ret = nv50_tls_alloc(screen, tls_space, &tls_size); 742 if (ret) 743 goto fail; 744 745 if (nouveau_mesa_debug) 746 debug_printf("TPs = %u, MPsInTP = %u, VRAM = %"PRIu64" MiB, tls_size = %"PRIu64" KiB\n", 747 screen->TPs, screen->MPsInTP, dev->vram_size >> 20, tls_size >> 10); 748 749 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 4 << 16, NULL, 750 &screen->uniforms); 751 if (ret) { 752 NOUVEAU_ERR("Failed to allocate uniforms bo: %d\n", ret); 753 goto fail; 754 } 755 756 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16, 3 << 16, NULL, 757 &screen->txc); 758 if (ret) { 759 NOUVEAU_ERR("Failed to allocate TIC/TSC bo: %d\n", ret); 760 goto fail; 761 } 762 763 screen->tic.entries = CALLOC(4096, sizeof(void *)); 764 screen->tsc.entries = screen->tic.entries + 2048; 765 766 if (!nv50_blitctx_create(screen)) 767 goto fail; 768 769 nv50_screen_init_hwctx(screen); 770 771 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); 772 773 return pscreen; 774 775fail: 776 nv50_screen_destroy(pscreen); 777 return NULL; 778} 779 780int 781nv50_screen_tic_alloc(struct nv50_screen *screen, void *entry) 782{ 783 int i = screen->tic.next; 784 785 while (screen->tic.lock[i / 32] & (1 << (i % 32))) 786 i = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); 787 788 screen->tic.next = (i + 1) & (NV50_TIC_MAX_ENTRIES - 1); 789 790 if (screen->tic.entries[i]) 791 nv50_tic_entry(screen->tic.entries[i])->id = -1; 792 793 screen->tic.entries[i] = entry; 794 return i; 795} 796 797int 798nv50_screen_tsc_alloc(struct nv50_screen *screen, void *entry) 799{ 800 int i = screen->tsc.next; 801 802 while (screen->tsc.lock[i / 32] & (1 << (i % 32))) 803 i = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); 804 805 screen->tsc.next = (i + 1) & (NV50_TSC_MAX_ENTRIES - 1); 806 807 if (screen->tsc.entries[i]) 808 nv50_tsc_entry(screen->tsc.entries[i])->id = -1; 809 810 screen->tsc.entries[i] = entry; 811 return i; 812} 813