nv50_tex.c revision 09bf09cf92c3958c3b8268f38387804084ca30e2
1/* 2 * Copyright 2008 Ben Skeggs 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "nv50_context.h" 24#include "nv50_texture.h" 25#include "nv50_resource.h" 26 27#include "nouveau/nouveau_stateobj.h" 28#include "nouveau/nouveau_reloc.h" 29 30#include "util/u_format.h" 31 32#define _MIXED(pf, t0, t1, t2, t3, cr, cg, cb, ca, f) \ 33[PIPE_FORMAT_##pf] = ( \ 34 NV50TIC_0_0_MAPR_##cr | NV50TIC_0_0_TYPER_##t0 | \ 35 NV50TIC_0_0_MAPG_##cg | NV50TIC_0_0_TYPEG_##t1 | \ 36 NV50TIC_0_0_MAPB_##cb | NV50TIC_0_0_TYPEB_##t2 | \ 37 NV50TIC_0_0_MAPA_##ca | NV50TIC_0_0_TYPEA_##t3 | \ 38 NV50TIC_0_0_FMT_##f) 39 40#define _(pf, t, cr, cg, cb, ca, f) _MIXED(pf, t, t, t, t, cr, cg, cb, ca, f) 41 42static const uint32_t nv50_texture_formats[PIPE_FORMAT_COUNT] = 43{ 44 _(B8G8R8A8_UNORM, UNORM, C2, C1, C0, C3, 8_8_8_8), 45 _(B8G8R8A8_SRGB, UNORM, C2, C1, C0, C3, 8_8_8_8), 46 _(B8G8R8X8_UNORM, UNORM, C2, C1, C0, ONE, 8_8_8_8), 47 _(B8G8R8X8_SRGB, UNORM, C2, C1, C0, ONE, 8_8_8_8), 48 _(B5G5R5A1_UNORM, UNORM, C2, C1, C0, C3, 1_5_5_5), 49 _(B4G4R4A4_UNORM, UNORM, C2, C1, C0, C3, 4_4_4_4), 50 51 _(B5G6R5_UNORM, UNORM, C2, C1, C0, ONE, 5_6_5), 52 53 _(L8_UNORM, UNORM, C0, C0, C0, ONE, 8), 54 _(L8_SRGB, UNORM, C0, C0, C0, ONE, 8), 55 _(A8_UNORM, UNORM, ZERO, ZERO, ZERO, C0, 8), 56 _(I8_UNORM, UNORM, C0, C0, C0, C0, 8), 57 58 _(L8A8_UNORM, UNORM, C0, C0, C0, C1, 8_8), 59 _(L8A8_SRGB, UNORM, C0, C0, C0, C1, 8_8), 60 61 _(DXT1_RGB, UNORM, C0, C1, C2, ONE, DXT1), 62 _(DXT1_RGBA, UNORM, C0, C1, C2, C3, DXT1), 63 _(DXT3_RGBA, UNORM, C0, C1, C2, C3, DXT3), 64 _(DXT5_RGBA, UNORM, C0, C1, C2, C3, DXT5), 65 66 _MIXED(S8_USCALED_Z24_UNORM, UINT, UNORM, UINT, UINT, C1, C1, C1, ONE, 24_8), 67 _MIXED(Z24_UNORM_S8_USCALED, UNORM, UINT, UINT, UINT, C0, C0, C0, ONE, 8_24), 68 69 _(R16G16B16A16_SNORM, UNORM, C0, C1, C2, C3, 16_16_16_16), 70 _(R16G16B16A16_UNORM, SNORM, C0, C1, C2, C3, 16_16_16_16), 71 _(R32G32B32A32_FLOAT, FLOAT, C0, C1, C2, C3, 32_32_32_32), 72 73 _(R16G16_SNORM, SNORM, C0, C1, ZERO, ONE, 16_16), 74 _(R16G16_UNORM, UNORM, C0, C1, ZERO, ONE, 16_16), 75 76 _MIXED(Z32_FLOAT, FLOAT, UINT, UINT, UINT, C0, C0, C0, ONE, 32_DEPTH) 77}; 78 79#undef _ 80#undef _MIXED 81 82static INLINE uint32_t 83nv50_tic_swizzle(uint32_t tc, unsigned swz) 84{ 85 switch (swz) { 86 case PIPE_SWIZZLE_RED: 87 return (tc & NV50TIC_0_0_MAPR_MASK) >> NV50TIC_0_0_MAPR_SHIFT; 88 case PIPE_SWIZZLE_GREEN: 89 return (tc & NV50TIC_0_0_MAPG_MASK) >> NV50TIC_0_0_MAPG_SHIFT; 90 case PIPE_SWIZZLE_BLUE: 91 return (tc & NV50TIC_0_0_MAPB_MASK) >> NV50TIC_0_0_MAPB_SHIFT; 92 case PIPE_SWIZZLE_ALPHA: 93 return (tc & NV50TIC_0_0_MAPA_MASK) >> NV50TIC_0_0_MAPA_SHIFT; 94 case PIPE_SWIZZLE_ONE: 95 return 7; 96 case PIPE_SWIZZLE_ZERO: 97 default: 98 return 0; 99 } 100} 101 102boolean 103nv50_tex_construct(struct nv50_sampler_view *view) 104{ 105 const struct util_format_description *desc; 106 struct nv50_miptree *mt = nv50_miptree(view->pipe.texture); 107 uint32_t swz[4], *tic = view->tic; 108 109 tic[0] = nv50_texture_formats[view->pipe.format]; 110 111 swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r); 112 swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g); 113 swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b); 114 swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a); 115 view->tic[0] = (tic[0] & ~NV50TIC_0_0_SWIZZLE_MASK) | 116 (swz[0] << NV50TIC_0_0_MAPR_SHIFT) | 117 (swz[1] << NV50TIC_0_0_MAPG_SHIFT) | 118 (swz[2] << NV50TIC_0_0_MAPB_SHIFT) | 119 (swz[3] << NV50TIC_0_0_MAPA_SHIFT); 120 121 tic[2] = 0x50001000; 122 tic[2] |= ((mt->base.bo->tile_mode & 0x0f) << 22) | 123 ((mt->base.bo->tile_mode & 0xf0) << 21); 124 125 desc = util_format_description(mt->base.base.format); 126 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 127 tic[2] |= NV50TIC_0_2_COLORSPACE_SRGB; 128 129 switch (mt->base.base.target) { 130 case PIPE_TEXTURE_1D: 131 tic[2] |= NV50TIC_0_2_TARGET_1D; 132 break; 133 case PIPE_TEXTURE_2D: 134 tic[2] |= NV50TIC_0_2_TARGET_2D; 135 break; 136 case PIPE_TEXTURE_RECT: 137 tic[2] |= NV50TIC_0_2_TARGET_RECT; 138 break; 139 case PIPE_TEXTURE_3D: 140 tic[2] |= NV50TIC_0_2_TARGET_3D; 141 break; 142 case PIPE_TEXTURE_CUBE: 143 tic[2] |= NV50TIC_0_2_TARGET_CUBE; 144 break; 145 default: 146 NOUVEAU_ERR("invalid texture target: %d\n", 147 mt->base.base.target); 148 return FALSE; 149 } 150 151 tic[3] = 0x00300000; 152 153 tic[4] = (1 << 31) | mt->base.base.width0; 154 tic[5] = (mt->base.base.last_level << 28) | 155 (mt->base.base.depth0 << 16) | mt->base.base.height0; 156 157 tic[6] = 0x03000000; 158 159 tic[7] = (view->pipe.last_level << 4) | view->pipe.first_level; 160 161 return TRUE; 162} 163 164static int 165nv50_validate_textures(struct nv50_context *nv50, struct nouveau_stateobj *so, 166 unsigned p) 167{ 168 struct nouveau_grobj *eng2d = nv50->screen->eng2d; 169 struct nouveau_grobj *tesla = nv50->screen->tesla; 170 unsigned unit, j; 171 172 const unsigned rll = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_LOW; 173 const unsigned rlh = NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | NOUVEAU_BO_HIGH 174 | NOUVEAU_BO_OR; 175 176 nv50_so_init_sifc(nv50, so, nv50->screen->tic, NOUVEAU_BO_VRAM, 177 p * (32 * 8 * 4), nv50->sampler_view_nr[p] * 8 * 4); 178 179 for (unit = 0; unit < nv50->sampler_view_nr[p]; ++unit) { 180 struct nv50_sampler_view *view = 181 nv50_sampler_view(nv50->sampler_views[p][unit]); 182 183 so_method(so, eng2d, NV50_2D_SIFC_DATA | (2 << 29), 8); 184 if (view) { 185 uint32_t tic2 = view->tic[2]; 186 struct nv50_miptree *mt = 187 nv50_miptree(view->pipe.texture); 188 189 tic2 &= ~NV50TIC_0_2_NORMALIZED_COORDS; 190 if (nv50->sampler[p][unit]->normalized) 191 tic2 |= NV50TIC_0_2_NORMALIZED_COORDS; 192 view->tic[2] = tic2; 193 194 so_data (so, view->tic[0]); 195 so_reloc (so, mt->base.bo, 0, rll, 0, 0); 196 so_reloc (so, mt->base.bo, 0, rlh, tic2, tic2); 197 so_datap (so, &view->tic[3], 5); 198 199 /* Set TEX insn $t src binding $unit in program type p 200 * to TIC, TSC entry (32 * p + unit), mark valid (1). 201 */ 202 so_method(so, tesla, NV50TCL_BIND_TIC(p), 1); 203 so_data (so, ((32 * p + unit) << 9) | (unit << 1) | 1); 204 } else { 205 for (j = 0; j < 8; ++j) 206 so_data(so, 0); 207 so_method(so, tesla, NV50TCL_BIND_TIC(p), 1); 208 so_data (so, (unit << 1) | 0); 209 } 210 } 211 212 for (; unit < nv50->state.sampler_view_nr[p]; unit++) { 213 /* Make other bindings invalid. */ 214 so_method(so, tesla, NV50TCL_BIND_TIC(p), 1); 215 so_data (so, (unit << 1) | 0); 216 } 217 218 nv50->state.sampler_view_nr[p] = nv50->sampler_view_nr[p]; 219 return TRUE; 220} 221 222static void 223nv50_emit_texture_relocs(struct nv50_context *nv50, int prog) 224{ 225 struct nouveau_channel *chan = nv50->screen->base.channel; 226 struct nouveau_bo *tic = nv50->screen->tic; 227 int unit; 228 229 for (unit = 0; unit < nv50->sampler_view_nr[prog]; unit++) { 230 struct nv50_sampler_view *view; 231 struct nv50_miptree *mt; 232 const unsigned base = ((prog * 32) + unit) * 32; 233 234 view = nv50_sampler_view(nv50->sampler_views[prog][unit]); 235 if (!view) 236 continue; 237 mt = nv50_miptree(view->pipe.texture); 238 239 nouveau_reloc_emit(chan, tic, base + 4, NULL, mt->base.bo, 0, 0, 240 NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | 241 NOUVEAU_BO_LOW, 0, 0); 242 nouveau_reloc_emit(chan, tic, base + 8, NULL, mt->base.bo, 0, 0, 243 NOUVEAU_BO_VRAM | NOUVEAU_BO_RD | 244 NOUVEAU_BO_HIGH, view->tic[2], view->tic[2]); 245 } 246} 247 248void 249nv50_tex_relocs(struct nv50_context *nv50) 250{ 251 nv50_emit_texture_relocs(nv50, 2); /* FP */ 252 nv50_emit_texture_relocs(nv50, 0); /* VP */ 253} 254 255struct nouveau_stateobj * 256nv50_tex_validate(struct nv50_context *nv50) 257{ 258 struct nouveau_stateobj *so; 259 struct nouveau_grobj *tesla = nv50->screen->tesla; 260 unsigned p, m = 0, d = 0, r = 0; 261 262 for (p = 0; p < 3; ++p) { 263 unsigned nr = MAX2(nv50->sampler_view_nr[p], 264 nv50->state.sampler_view_nr[p]); 265 m += nr; 266 d += nr; 267 r += nv50->sampler_view_nr[p]; 268 } 269 m = m * 2 + 3 * 4 + 1; 270 d = d * 9 + 3 * 19 + 1; 271 r = r * 2 + 3 * 2; 272 273 so = so_new(m, d, r); 274 275 if (nv50_validate_textures(nv50, so, 0) == FALSE || 276 nv50_validate_textures(nv50, so, 2) == FALSE) { 277 so_ref(NULL, &so); 278 279 NOUVEAU_ERR("failed tex validate\n"); 280 return NULL; 281 } 282 283 so_method(so, tesla, 0x1330, 1); /* flush TIC */ 284 so_data (so, 0); 285 286 return so; 287} 288