nvc0_screen.c revision 854b8099c3120f3b12624faccf768b2afaff88c8
1/* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 18 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 19 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 20 * SOFTWARE. 21 */ 22 23#include "util/u_format.h" 24#include "util/u_format_s3tc.h" 25#include "pipe/p_screen.h" 26 27#include "vl/vl_decoder.h" 28#include "vl/vl_video_buffer.h" 29 30#include "nvc0_context.h" 31#include "nvc0_screen.h" 32 33#include "nvc0_graph_macros.h" 34 35static boolean 36nvc0_screen_is_format_supported(struct pipe_screen *pscreen, 37 enum pipe_format format, 38 enum pipe_texture_target target, 39 unsigned sample_count, 40 unsigned bindings) 41{ 42 if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */ 43 return FALSE; 44 45 if (!util_format_is_supported(format, bindings)) 46 return FALSE; 47 48 switch (format) { 49 case PIPE_FORMAT_R8G8B8A8_UNORM: 50 case PIPE_FORMAT_R8G8B8X8_UNORM: 51 /* HACK: GL requires equal formats for MS resolve and window is BGRA */ 52 if (bindings & PIPE_BIND_RENDER_TARGET) 53 return FALSE; 54 default: 55 break; 56 } 57 58 /* transfers & shared are always supported */ 59 bindings &= ~(PIPE_BIND_TRANSFER_READ | 60 PIPE_BIND_TRANSFER_WRITE | 61 PIPE_BIND_SHARED); 62 63 return (nvc0_format_table[format].usage & bindings) == bindings; 64} 65 66static int 67nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) 68{ 69 const uint16_t class_3d = nouveau_screen(pscreen)->class_3d; 70 71 switch (param) { 72 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 73 return 16 * PIPE_SHADER_TYPES; /* NOTE: should not count COMPUTE */ 74 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 75 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 76 return 15; 77 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 78 return 12; 79 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 80 return 2048; 81 case PIPE_CAP_MIN_TEXEL_OFFSET: 82 return -8; 83 case PIPE_CAP_MAX_TEXEL_OFFSET: 84 return 7; 85 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 86 case PIPE_CAP_TEXTURE_SWIZZLE: 87 case PIPE_CAP_TEXTURE_SHADOW_MAP: 88 case PIPE_CAP_NPOT_TEXTURES: 89 case PIPE_CAP_ANISOTROPIC_FILTER: 90 case PIPE_CAP_SEAMLESS_CUBE_MAP: 91 return 1; 92 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 93 return (class_3d >= NVE4_3D_CLASS) ? 1 : 0; 94 case PIPE_CAP_TWO_SIDED_STENCIL: 95 case PIPE_CAP_DEPTH_CLIP_DISABLE: 96 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 97 case PIPE_CAP_POINT_SPRITE: 98 return 1; 99 case PIPE_CAP_SM3: 100 return 1; 101 case PIPE_CAP_GLSL_FEATURE_LEVEL: 102 return 150; 103 case PIPE_CAP_MAX_RENDER_TARGETS: 104 return 8; 105 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 106 return 1; 107 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 108 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 109 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 110 return 1; 111 case PIPE_CAP_QUERY_TIMESTAMP: 112 case PIPE_CAP_TIMER_QUERY: 113 case PIPE_CAP_OCCLUSION_QUERY: 114 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 115 return 1; 116 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 117 return 4; 118 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 119 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 120 return 128; 121 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 122 case PIPE_CAP_INDEP_BLEND_ENABLE: 123 case PIPE_CAP_INDEP_BLEND_FUNC: 124 return 1; 125 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 126 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 127 return 1; 128 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 129 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 130 return 0; 131 case PIPE_CAP_SHADER_STENCIL_EXPORT: 132 return 0; 133 case PIPE_CAP_PRIMITIVE_RESTART: 134 case PIPE_CAP_TGSI_INSTANCEID: 135 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 136 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 137 case PIPE_CAP_CONDITIONAL_RENDER: 138 case PIPE_CAP_TEXTURE_BARRIER: 139 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 140 case PIPE_CAP_START_INSTANCE: 141 return 1; 142 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 143 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 144 return 0; /* state trackers will know better */ 145 case PIPE_CAP_USER_CONSTANT_BUFFERS: 146 case PIPE_CAP_USER_INDEX_BUFFERS: 147 case PIPE_CAP_USER_VERTEX_BUFFERS: 148 return 1; 149 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 150 return 256; 151 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 152 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 153 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 154 return 0; 155 default: 156 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 157 return 0; 158 } 159} 160 161static int 162nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, 163 enum pipe_shader_cap param) 164{ 165 switch (shader) { 166 case PIPE_SHADER_VERTEX: 167 /* 168 case PIPE_SHADER_TESSELLATION_CONTROL: 169 case PIPE_SHADER_TESSELLATION_EVALUATION: 170 */ 171 case PIPE_SHADER_GEOMETRY: 172 case PIPE_SHADER_FRAGMENT: 173 break; 174 default: 175 return 0; 176 } 177 178 switch (param) { 179 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 180 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 181 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 182 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 183 return 16384; 184 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 185 return 16; 186 case PIPE_SHADER_CAP_MAX_INPUTS: 187 if (shader == PIPE_SHADER_VERTEX) 188 return 32; 189 if (shader == PIPE_SHADER_FRAGMENT) 190 return (0x200 + 0x20 + 0x80) / 16; /* generic + colors + TexCoords */ 191 return (0x200 + 0x40 + 0x80) / 16; /* without 0x60 for per-patch inputs */ 192 case PIPE_SHADER_CAP_MAX_CONSTS: 193 return 65536 / 16; 194 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 195 return NVC0_MAX_PIPE_CONSTBUFS; 196 case PIPE_SHADER_CAP_MAX_ADDRS: 197 return 1; 198 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 199 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 200 return shader != PIPE_SHADER_FRAGMENT; 201 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 202 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 203 return 1; 204 case PIPE_SHADER_CAP_MAX_PREDS: 205 return 0; 206 case PIPE_SHADER_CAP_MAX_TEMPS: 207 return NVC0_CAP_MAX_PROGRAM_TEMPS; 208 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 209 return 1; 210 case PIPE_SHADER_CAP_SUBROUTINES: 211 return 1; /* but inlining everything, we need function declarations */ 212 case PIPE_SHADER_CAP_INTEGERS: 213 return 1; 214 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 215 return 16; /* would be 32 in linked (OpenGL-style) mode */ 216 /* 217 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS: 218 return 32; 219 */ 220 default: 221 NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param); 222 return 0; 223 } 224} 225 226static float 227nvc0_screen_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param) 228{ 229 switch (param) { 230 case PIPE_CAPF_MAX_LINE_WIDTH: 231 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 232 return 10.0f; 233 case PIPE_CAPF_MAX_POINT_WIDTH: 234 return 63.0f; 235 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 236 return 63.375f; 237 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 238 return 16.0f; 239 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 240 return 15.0f; 241 default: 242 NOUVEAU_ERR("unknown PIPE_CAP %d\n", param); 243 return 0.0f; 244 } 245} 246 247static void 248nvc0_screen_destroy(struct pipe_screen *pscreen) 249{ 250 struct nvc0_screen *screen = nvc0_screen(pscreen); 251 252 if (screen->base.fence.current) { 253 nouveau_fence_wait(screen->base.fence.current); 254 nouveau_fence_ref(NULL, &screen->base.fence.current); 255 } 256 if (screen->base.pushbuf) 257 screen->base.pushbuf->user_priv = NULL; 258 259 if (screen->blitctx) 260 FREE(screen->blitctx); 261 262 nouveau_bo_ref(NULL, &screen->text); 263 nouveau_bo_ref(NULL, &screen->uniform_bo); 264 nouveau_bo_ref(NULL, &screen->tls); 265 nouveau_bo_ref(NULL, &screen->txc); 266 nouveau_bo_ref(NULL, &screen->fence.bo); 267 nouveau_bo_ref(NULL, &screen->poly_cache); 268 269 nouveau_heap_destroy(&screen->lib_code); 270 nouveau_heap_destroy(&screen->text_heap); 271 272 if (screen->tic.entries) 273 FREE(screen->tic.entries); 274 275 nouveau_mm_destroy(screen->mm_VRAM_fe0); 276 277 nouveau_object_del(&screen->eng3d); 278 nouveau_object_del(&screen->eng2d); 279 nouveau_object_del(&screen->m2mf); 280 281 nouveau_screen_fini(&screen->base); 282 283 FREE(screen); 284} 285 286static int 287nvc0_graph_set_macro(struct nvc0_screen *screen, uint32_t m, unsigned pos, 288 unsigned size, const uint32_t *data) 289{ 290 struct nouveau_pushbuf *push = screen->base.pushbuf; 291 292 size /= 4; 293 294 BEGIN_NVC0(push, SUBC_3D(NVC0_GRAPH_MACRO_ID), 2); 295 PUSH_DATA (push, (m - 0x3800) / 8); 296 PUSH_DATA (push, pos); 297 BEGIN_1IC0(push, SUBC_3D(NVC0_GRAPH_MACRO_UPLOAD_POS), size + 1); 298 PUSH_DATA (push, pos); 299 PUSH_DATAp(push, data, size); 300 301 return pos + size; 302} 303 304static void 305nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class) 306{ 307 BEGIN_NVC0(push, SUBC_3D(0x10cc), 1); 308 PUSH_DATA (push, 0xff); 309 BEGIN_NVC0(push, SUBC_3D(0x10e0), 2); 310 PUSH_DATA (push, 0xff); 311 PUSH_DATA (push, 0xff); 312 BEGIN_NVC0(push, SUBC_3D(0x10ec), 2); 313 PUSH_DATA (push, 0xff); 314 PUSH_DATA (push, 0xff); 315 BEGIN_NVC0(push, SUBC_3D(0x074c), 1); 316 PUSH_DATA (push, 0x3f); 317 318 BEGIN_NVC0(push, SUBC_3D(0x16a8), 1); 319 PUSH_DATA (push, (3 << 16) | 3); 320 BEGIN_NVC0(push, SUBC_3D(0x1794), 1); 321 PUSH_DATA (push, (2 << 16) | 2); 322 BEGIN_NVC0(push, SUBC_3D(0x0de8), 1); 323 PUSH_DATA (push, 1); 324 325 BEGIN_NVC0(push, SUBC_3D(0x12ac), 1); 326 PUSH_DATA (push, 0); 327 BEGIN_NVC0(push, SUBC_3D(0x0218), 1); 328 PUSH_DATA (push, 0x10); 329 BEGIN_NVC0(push, SUBC_3D(0x10fc), 1); 330 PUSH_DATA (push, 0x10); 331 BEGIN_NVC0(push, SUBC_3D(0x1290), 1); 332 PUSH_DATA (push, 0x10); 333 BEGIN_NVC0(push, SUBC_3D(0x12d8), 2); 334 PUSH_DATA (push, 0x10); 335 PUSH_DATA (push, 0x10); 336 BEGIN_NVC0(push, SUBC_3D(0x1140), 1); 337 PUSH_DATA (push, 0x10); 338 BEGIN_NVC0(push, SUBC_3D(0x1610), 1); 339 PUSH_DATA (push, 0xe); 340 341 BEGIN_NVC0(push, SUBC_3D(0x164c), 1); 342 PUSH_DATA (push, 1 << 12); 343 BEGIN_NVC0(push, SUBC_3D(0x030c), 1); 344 PUSH_DATA (push, 0); 345 BEGIN_NVC0(push, SUBC_3D(0x0300), 1); 346 PUSH_DATA (push, 3); 347 348 BEGIN_NVC0(push, SUBC_3D(0x02d0), 1); 349 PUSH_DATA (push, 0x3fffff); 350 BEGIN_NVC0(push, SUBC_3D(0x0fdc), 1); 351 PUSH_DATA (push, 1); 352 BEGIN_NVC0(push, SUBC_3D(0x19c0), 1); 353 PUSH_DATA (push, 1); 354 BEGIN_NVC0(push, SUBC_3D(0x075c), 1); 355 PUSH_DATA (push, 3); 356 357 if (obj_class >= NVE4_3D_CLASS) { 358 BEGIN_NVC0(push, SUBC_3D(0x07fc), 1); 359 PUSH_DATA (push, 1); 360 } 361 362 /* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc 363 * are supposed to do */ 364} 365 366static void 367nvc0_screen_fence_emit(struct pipe_screen *pscreen, u32 *sequence) 368{ 369 struct nvc0_screen *screen = nvc0_screen(pscreen); 370 struct nouveau_pushbuf *push = screen->base.pushbuf; 371 372 /* we need to do it after possible flush in MARK_RING */ 373 *sequence = ++screen->base.fence.sequence; 374 375 BEGIN_NVC0(push, NVC0_3D(QUERY_ADDRESS_HIGH), 4); 376 PUSH_DATAh(push, screen->fence.bo->offset); 377 PUSH_DATA (push, screen->fence.bo->offset); 378 PUSH_DATA (push, *sequence); 379 PUSH_DATA (push, NVC0_3D_QUERY_GET_FENCE | NVC0_3D_QUERY_GET_SHORT | 380 (0xf << NVC0_3D_QUERY_GET_UNIT__SHIFT)); 381} 382 383static u32 384nvc0_screen_fence_update(struct pipe_screen *pscreen) 385{ 386 struct nvc0_screen *screen = nvc0_screen(pscreen); 387 return screen->fence.map[0]; 388} 389 390#define FAIL_SCREEN_INIT(str, err) \ 391 do { \ 392 NOUVEAU_ERR(str, err); \ 393 nvc0_screen_destroy(pscreen); \ 394 return NULL; \ 395 } while(0) 396 397struct pipe_screen * 398nvc0_screen_create(struct nouveau_device *dev) 399{ 400 struct nvc0_screen *screen; 401 struct pipe_screen *pscreen; 402 struct nouveau_object *chan; 403 struct nouveau_pushbuf *push; 404 uint32_t obj_class; 405 int ret; 406 unsigned i; 407 union nouveau_bo_config mm_config; 408 409 switch (dev->chipset & ~0xf) { 410 case 0xc0: 411 case 0xd0: 412 case 0xe0: 413 break; 414 default: 415 return NULL; 416 } 417 418 screen = CALLOC_STRUCT(nvc0_screen); 419 if (!screen) 420 return NULL; 421 pscreen = &screen->base.base; 422 423 ret = nouveau_screen_init(&screen->base, dev); 424 if (ret) { 425 nvc0_screen_destroy(pscreen); 426 return NULL; 427 } 428 chan = screen->base.channel; 429 push = screen->base.pushbuf; 430 push->user_priv = screen; 431 432 screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER | 433 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER; 434 screen->base.sysmem_bindings |= 435 PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER; 436 437 pscreen->destroy = nvc0_screen_destroy; 438 pscreen->context_create = nvc0_create; 439 pscreen->is_format_supported = nvc0_screen_is_format_supported; 440 pscreen->get_param = nvc0_screen_get_param; 441 pscreen->get_shader_param = nvc0_screen_get_shader_param; 442 pscreen->get_paramf = nvc0_screen_get_paramf; 443 444 nvc0_screen_init_resource_functions(pscreen); 445 446 nouveau_screen_init_vdec(&screen->base); 447 448 ret = nouveau_bo_new(dev, NOUVEAU_BO_GART | NOUVEAU_BO_MAP, 0, 4096, NULL, 449 &screen->fence.bo); 450 if (ret) 451 goto fail; 452 nouveau_bo_map(screen->fence.bo, 0, NULL); 453 screen->fence.map = screen->fence.bo->map; 454 screen->base.fence.emit = nvc0_screen_fence_emit; 455 screen->base.fence.update = nvc0_screen_fence_update; 456 457 switch (dev->chipset & 0xf0) { 458 case 0xe0: 459 obj_class = NVE4_P2MF_CLASS; 460 break; 461 default: 462 obj_class = NVC0_M2MF_CLASS; 463 break; 464 } 465 ret = nouveau_object_new(chan, 0xbeef323f, obj_class, NULL, 0, 466 &screen->m2mf); 467 if (ret) 468 FAIL_SCREEN_INIT("Error allocating PGRAPH context for M2MF: %d\n", ret); 469 470 BEGIN_NVC0(push, SUBC_M2MF(NV01_SUBCHAN_OBJECT), 1); 471 PUSH_DATA (push, screen->m2mf->oclass); 472 if (screen->m2mf->oclass == NVE4_P2MF_CLASS) { 473 BEGIN_NVC0(push, SUBC_COPY(NV01_SUBCHAN_OBJECT), 1); 474 PUSH_DATA (push, 0xa0b5); 475 } 476 477 ret = nouveau_object_new(chan, 0xbeef902d, NVC0_2D_CLASS, NULL, 0, 478 &screen->eng2d); 479 if (ret) 480 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 2D: %d\n", ret); 481 482 BEGIN_NVC0(push, SUBC_2D(NV01_SUBCHAN_OBJECT), 1); 483 PUSH_DATA (push, screen->eng2d->oclass); 484 BEGIN_NVC0(push, NVC0_2D(OPERATION), 1); 485 PUSH_DATA (push, NVC0_2D_OPERATION_SRCCOPY); 486 BEGIN_NVC0(push, NVC0_2D(CLIP_ENABLE), 1); 487 PUSH_DATA (push, 0); 488 BEGIN_NVC0(push, NVC0_2D(COLOR_KEY_ENABLE), 1); 489 PUSH_DATA (push, 0); 490 BEGIN_NVC0(push, SUBC_2D(0x0884), 1); 491 PUSH_DATA (push, 0x3f); 492 BEGIN_NVC0(push, SUBC_2D(0x0888), 1); 493 PUSH_DATA (push, 1); 494 495 BEGIN_NVC0(push, SUBC_2D(NVC0_GRAPH_NOTIFY_ADDRESS_HIGH), 2); 496 PUSH_DATAh(push, screen->fence.bo->offset + 16); 497 PUSH_DATA (push, screen->fence.bo->offset + 16); 498 499 switch (dev->chipset & 0xf0) { 500 case 0xe0: 501 obj_class = NVE4_3D_CLASS; 502 break; 503 case 0xd0: 504 case 0xc0: 505 default: 506 switch (dev->chipset) { 507 case 0xd9: 508 case 0xc8: 509 obj_class = NVC8_3D_CLASS; 510 break; 511 case 0xc1: 512 obj_class = NVC1_3D_CLASS; 513 break; 514 default: 515 obj_class = NVC0_3D_CLASS; 516 break; 517 } 518 break; 519 } 520 ret = nouveau_object_new(chan, 0xbeef003d, obj_class, NULL, 0, 521 &screen->eng3d); 522 if (ret) 523 FAIL_SCREEN_INIT("Error allocating PGRAPH context for 3D: %d\n", ret); 524 screen->base.class_3d = obj_class; 525 526 BEGIN_NVC0(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1); 527 PUSH_DATA (push, screen->eng3d->oclass); 528 529 BEGIN_NVC0(push, NVC0_3D(COND_MODE), 1); 530 PUSH_DATA (push, NVC0_3D_COND_MODE_ALWAYS); 531 532 if (debug_get_bool_option("NOUVEAU_SHADER_WATCHDOG", TRUE)) { 533 /* kill shaders after about 1 second (at 100 MHz) */ 534 BEGIN_NVC0(push, NVC0_3D(WATCHDOG_TIMER), 1); 535 PUSH_DATA (push, 0x17); 536 } 537 538 BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1); 539 PUSH_DATA (push, 1); 540 541 BEGIN_NVC0(push, NVC0_3D(CSAA_ENABLE), 1); 542 PUSH_DATA (push, 0); 543 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_ENABLE), 1); 544 PUSH_DATA (push, 0); 545 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_MODE), 1); 546 PUSH_DATA (push, NVC0_3D_MULTISAMPLE_MODE_MS1); 547 BEGIN_NVC0(push, NVC0_3D(MULTISAMPLE_CTRL), 1); 548 PUSH_DATA (push, 0); 549 BEGIN_NVC0(push, NVC0_3D(LINE_WIDTH_SEPARATE), 1); 550 PUSH_DATA (push, 1); 551 BEGIN_NVC0(push, NVC0_3D(LINE_LAST_PIXEL), 1); 552 PUSH_DATA (push, 0); 553 BEGIN_NVC0(push, NVC0_3D(BLEND_SEPARATE_ALPHA), 1); 554 PUSH_DATA (push, 1); 555 BEGIN_NVC0(push, NVC0_3D(BLEND_ENABLE_COMMON), 1); 556 PUSH_DATA (push, 0); 557 if (screen->eng3d->oclass < NVE4_3D_CLASS) { 558 BEGIN_NVC0(push, NVC0_3D(TEX_MISC), 1); 559 PUSH_DATA (push, NVC0_3D_TEX_MISC_SEAMLESS_CUBE_MAP); 560 } else { 561 BEGIN_NVC0(push, NVE4_3D(TEX_CB_INDEX), 1); 562 PUSH_DATA (push, 15); 563 } 564 BEGIN_NVC0(push, NVC0_3D(CALL_LIMIT_LOG), 1); 565 PUSH_DATA (push, 8); /* 128 */ 566 BEGIN_NVC0(push, NVC0_3D(ZCULL_STATCTRS_ENABLE), 1); 567 PUSH_DATA (push, 1); 568 if (screen->eng3d->oclass >= NVC1_3D_CLASS) { 569 BEGIN_NVC0(push, NVC0_3D(CACHE_SPLIT), 1); 570 PUSH_DATA (push, NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1); 571 } 572 573 nvc0_magic_3d_init(push, screen->eng3d->oclass); 574 575 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL, 576 &screen->text); 577 if (ret) 578 goto fail; 579 580 /* XXX: getting a page fault at the end of the code buffer every few 581 * launches, don't use the last 256 bytes to work around them - prefetch ? 582 */ 583 nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100); 584 585 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 12, 6 << 16, NULL, 586 &screen->uniform_bo); 587 if (ret) 588 goto fail; 589 590 for (i = 0; i < 5; ++i) { 591 /* TIC and TSC entries for each unit (nve4+ only) */ 592 /* auxiliary constants (6 user clip planes, base instance id) */ 593 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); 594 PUSH_DATA (push, 512); 595 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (i << 9)); 596 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (i << 9)); 597 BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1); 598 PUSH_DATA (push, (15 << 4) | 1); 599 if (screen->eng3d->oclass >= NVE4_3D_CLASS) { 600 unsigned j; 601 BEGIN_1IC0(push, NVC0_3D(CB_POS), 9); 602 PUSH_DATA (push, 0); 603 for (j = 0; j < 8; ++j) 604 PUSH_DATA(push, j); 605 } else { 606 BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1); 607 PUSH_DATA (push, 0x54); 608 } 609 } 610 BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1); 611 PUSH_DATA (push, 0); 612 613 /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */ 614 BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3); 615 PUSH_DATA (push, 256); 616 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9)); 617 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9)); 618 BEGIN_1IC0(push, NVC0_3D(CB_POS), 5); 619 PUSH_DATA (push, 0); 620 PUSH_DATAf(push, 0.0f); 621 PUSH_DATAf(push, 0.0f); 622 PUSH_DATAf(push, 0.0f); 623 PUSH_DATAf(push, 0.0f); 624 BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2); 625 PUSH_DATAh(push, screen->uniform_bo->offset + (5 << 16) + (6 << 9)); 626 PUSH_DATA (push, screen->uniform_bo->offset + (5 << 16) + (6 << 9)); 627 628 /* max MPs * max warps per MP (TODO: ask kernel) */ 629 if (screen->eng3d->oclass >= NVE4_3D_CLASS) 630 screen->tls_size = 8 * 64; 631 else 632 screen->tls_size = 16 * 48; 633 screen->tls_size *= NVC0_CAP_MAX_PROGRAM_TEMPS * 16; 634 screen->tls_size = align(screen->tls_size, 1 << 17); 635 636 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 637 screen->tls_size, NULL, &screen->tls); 638 if (ret) 639 goto fail; 640 641 BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2); 642 PUSH_DATAh(push, screen->text->offset); 643 PUSH_DATA (push, screen->text->offset); 644 BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4); 645 PUSH_DATAh(push, screen->tls->offset); 646 PUSH_DATA (push, screen->tls->offset); 647 PUSH_DATA (push, screen->tls_size >> 32); 648 PUSH_DATA (push, screen->tls_size); 649 BEGIN_NVC0(push, NVC0_3D(WARP_TEMP_ALLOC), 1); 650 PUSH_DATA (push, 0); 651 BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1); 652 PUSH_DATA (push, 0); 653 654 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL, 655 &screen->poly_cache); 656 if (ret) 657 goto fail; 658 659 BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3); 660 PUSH_DATAh(push, screen->poly_cache->offset); 661 PUSH_DATA (push, screen->poly_cache->offset); 662 PUSH_DATA (push, 3); 663 664 ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL, 665 &screen->txc); 666 if (ret) 667 goto fail; 668 669 BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3); 670 PUSH_DATAh(push, screen->txc->offset); 671 PUSH_DATA (push, screen->txc->offset); 672 PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1); 673 674 BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3); 675 PUSH_DATAh(push, screen->txc->offset + 65536); 676 PUSH_DATA (push, screen->txc->offset + 65536); 677 PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1); 678 679 BEGIN_NVC0(push, NVC0_3D(SCREEN_Y_CONTROL), 1); 680 PUSH_DATA (push, 0); 681 BEGIN_NVC0(push, NVC0_3D(WINDOW_OFFSET_X), 2); 682 PUSH_DATA (push, 0); 683 PUSH_DATA (push, 0); 684 BEGIN_NVC0(push, NVC0_3D(ZCULL_REGION), 1); /* deactivate ZCULL */ 685 PUSH_DATA (push, 0x3f); 686 687 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_MODE), 1); 688 PUSH_DATA (push, NVC0_3D_CLIP_RECTS_MODE_INSIDE_ANY); 689 BEGIN_NVC0(push, NVC0_3D(CLIP_RECT_HORIZ(0)), 8 * 2); 690 for (i = 0; i < 8 * 2; ++i) 691 PUSH_DATA(push, 0); 692 BEGIN_NVC0(push, NVC0_3D(CLIP_RECTS_EN), 1); 693 PUSH_DATA (push, 0); 694 BEGIN_NVC0(push, NVC0_3D(CLIPID_ENABLE), 1); 695 PUSH_DATA (push, 0); 696 697 /* neither scissors, viewport nor stencil mask should affect clears */ 698 BEGIN_NVC0(push, NVC0_3D(CLEAR_FLAGS), 1); 699 PUSH_DATA (push, 0); 700 701 BEGIN_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1); 702 PUSH_DATA (push, 1); 703 BEGIN_NVC0(push, NVC0_3D(DEPTH_RANGE_NEAR(0)), 2); 704 PUSH_DATAf(push, 0.0f); 705 PUSH_DATAf(push, 1.0f); 706 BEGIN_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 1); 707 PUSH_DATA (push, NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK1); 708 709 /* We use scissors instead of exact view volume clipping, 710 * so they're always enabled. 711 */ 712 BEGIN_NVC0(push, NVC0_3D(SCISSOR_ENABLE(0)), 3); 713 PUSH_DATA (push, 1); 714 PUSH_DATA (push, 8192 << 16); 715 PUSH_DATA (push, 8192 << 16); 716 717#define MK_MACRO(m, n) i = nvc0_graph_set_macro(screen, m, i, sizeof(n), n); 718 719 i = 0; 720 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_PER_INSTANCE, nvc0_9097_per_instance_bf); 721 MK_MACRO(NVC0_3D_MACRO_BLEND_ENABLES, nvc0_9097_blend_enables); 722 MK_MACRO(NVC0_3D_MACRO_VERTEX_ARRAY_SELECT, nvc0_9097_vertex_array_select); 723 MK_MACRO(NVC0_3D_MACRO_TEP_SELECT, nvc0_9097_tep_select); 724 MK_MACRO(NVC0_3D_MACRO_GP_SELECT, nvc0_9097_gp_select); 725 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_FRONT, nvc0_9097_poly_mode_front); 726 MK_MACRO(NVC0_3D_MACRO_POLYGON_MODE_BACK, nvc0_9097_poly_mode_back); 727 728 BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1); 729 PUSH_DATA (push, 1); 730 BEGIN_NVC0(push, NVC0_3D(RT_SEPARATE_FRAG_DATA), 1); 731 PUSH_DATA (push, 1); 732 BEGIN_NVC0(push, NVC0_3D(MACRO_GP_SELECT), 1); 733 PUSH_DATA (push, 0x40); 734 BEGIN_NVC0(push, NVC0_3D(LAYER), 1); 735 PUSH_DATA (push, 0); 736 BEGIN_NVC0(push, NVC0_3D(MACRO_TEP_SELECT), 1); 737 PUSH_DATA (push, 0x30); 738 BEGIN_NVC0(push, NVC0_3D(PATCH_VERTICES), 1); 739 PUSH_DATA (push, 3); 740 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(2)), 1); 741 PUSH_DATA (push, 0x20); 742 BEGIN_NVC0(push, NVC0_3D(SP_SELECT(0)), 1); 743 PUSH_DATA (push, 0x00); 744 745 BEGIN_NVC0(push, NVC0_3D(POINT_COORD_REPLACE), 1); 746 PUSH_DATA (push, 0); 747 BEGIN_NVC0(push, NVC0_3D(POINT_RASTER_RULES), 1); 748 PUSH_DATA (push, NVC0_3D_POINT_RASTER_RULES_OGL); 749 750 IMMED_NVC0(push, NVC0_3D(EDGEFLAG), 1); 751 752 PUSH_KICK (push); 753 754 screen->tic.entries = CALLOC(4096, sizeof(void *)); 755 screen->tsc.entries = screen->tic.entries + 2048; 756 757 mm_config.nvc0.tile_mode = 0; 758 mm_config.nvc0.memtype = 0xfe0; 759 screen->mm_VRAM_fe0 = nouveau_mm_create(dev, NOUVEAU_BO_VRAM, &mm_config); 760 761 if (!nvc0_blitctx_create(screen)) 762 goto fail; 763 764 nouveau_fence_new(&screen->base, &screen->base.fence.current, FALSE); 765 766 return pscreen; 767 768fail: 769 nvc0_screen_destroy(pscreen); 770 return NULL; 771} 772 773int 774nvc0_screen_tic_alloc(struct nvc0_screen *screen, void *entry) 775{ 776 int i = screen->tic.next; 777 778 while (screen->tic.lock[i / 32] & (1 << (i % 32))) 779 i = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1); 780 781 screen->tic.next = (i + 1) & (NVC0_TIC_MAX_ENTRIES - 1); 782 783 if (screen->tic.entries[i]) 784 nv50_tic_entry(screen->tic.entries[i])->id = -1; 785 786 screen->tic.entries[i] = entry; 787 return i; 788} 789 790int 791nvc0_screen_tsc_alloc(struct nvc0_screen *screen, void *entry) 792{ 793 int i = screen->tsc.next; 794 795 while (screen->tsc.lock[i / 32] & (1 << (i % 32))) 796 i = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1); 797 798 screen->tsc.next = (i + 1) & (NVC0_TSC_MAX_ENTRIES - 1); 799 800 if (screen->tsc.entries[i]) 801 nv50_tsc_entry(screen->tsc.entries[i])->id = -1; 802 803 screen->tsc.entries[i] = entry; 804 return i; 805} 806