evergreen_state.c revision 26cb887ea213be2445e0fd64364d9264ed4fbfd2 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "evergreend.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31#include "evergreen_compute.h"
32
33static uint32_t eg_num_banks(uint32_t nbanks)
34{
35	switch (nbanks) {
36	case 2:
37		return 0;
38	case 4:
39		return 1;
40	case 8:
41	default:
42		return 2;
43	case 16:
44		return 3;
45	}
46}
47
48
49static unsigned eg_tile_split(unsigned tile_split)
50{
51	switch (tile_split) {
52	case 64:	tile_split = 0;	break;
53	case 128:	tile_split = 1;	break;
54	case 256:	tile_split = 2;	break;
55	case 512:	tile_split = 3;	break;
56	default:
57	case 1024:	tile_split = 4;	break;
58	case 2048:	tile_split = 5;	break;
59	case 4096:	tile_split = 6;	break;
60	}
61	return tile_split;
62}
63
64static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65{
66	switch (macro_tile_aspect) {
67	default:
68	case 1:	macro_tile_aspect = 0;	break;
69	case 2:	macro_tile_aspect = 1;	break;
70	case 4:	macro_tile_aspect = 2;	break;
71	case 8:	macro_tile_aspect = 3;	break;
72	}
73	return macro_tile_aspect;
74}
75
76static unsigned eg_bank_wh(unsigned bankwh)
77{
78	switch (bankwh) {
79	default:
80	case 1:	bankwh = 0;	break;
81	case 2:	bankwh = 1;	break;
82	case 4:	bankwh = 2;	break;
83	case 8:	bankwh = 3;	break;
84	}
85	return bankwh;
86}
87
88static uint32_t r600_translate_blend_function(int blend_func)
89{
90	switch (blend_func) {
91	case PIPE_BLEND_ADD:
92		return V_028780_COMB_DST_PLUS_SRC;
93	case PIPE_BLEND_SUBTRACT:
94		return V_028780_COMB_SRC_MINUS_DST;
95	case PIPE_BLEND_REVERSE_SUBTRACT:
96		return V_028780_COMB_DST_MINUS_SRC;
97	case PIPE_BLEND_MIN:
98		return V_028780_COMB_MIN_DST_SRC;
99	case PIPE_BLEND_MAX:
100		return V_028780_COMB_MAX_DST_SRC;
101	default:
102		R600_ERR("Unknown blend function %d\n", blend_func);
103		assert(0);
104		break;
105	}
106	return 0;
107}
108
109static uint32_t r600_translate_blend_factor(int blend_fact)
110{
111	switch (blend_fact) {
112	case PIPE_BLENDFACTOR_ONE:
113		return V_028780_BLEND_ONE;
114	case PIPE_BLENDFACTOR_SRC_COLOR:
115		return V_028780_BLEND_SRC_COLOR;
116	case PIPE_BLENDFACTOR_SRC_ALPHA:
117		return V_028780_BLEND_SRC_ALPHA;
118	case PIPE_BLENDFACTOR_DST_ALPHA:
119		return V_028780_BLEND_DST_ALPHA;
120	case PIPE_BLENDFACTOR_DST_COLOR:
121		return V_028780_BLEND_DST_COLOR;
122	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123		return V_028780_BLEND_SRC_ALPHA_SATURATE;
124	case PIPE_BLENDFACTOR_CONST_COLOR:
125		return V_028780_BLEND_CONST_COLOR;
126	case PIPE_BLENDFACTOR_CONST_ALPHA:
127		return V_028780_BLEND_CONST_ALPHA;
128	case PIPE_BLENDFACTOR_ZERO:
129		return V_028780_BLEND_ZERO;
130	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131		return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133		return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135		return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136	case PIPE_BLENDFACTOR_INV_DST_COLOR:
137		return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139		return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141		return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142	case PIPE_BLENDFACTOR_SRC1_COLOR:
143		return V_028780_BLEND_SRC1_COLOR;
144	case PIPE_BLENDFACTOR_SRC1_ALPHA:
145		return V_028780_BLEND_SRC1_ALPHA;
146	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147		return V_028780_BLEND_INV_SRC1_COLOR;
148	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149		return V_028780_BLEND_INV_SRC1_ALPHA;
150	default:
151		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152		assert(0);
153		break;
154	}
155	return 0;
156}
157
158static unsigned r600_tex_dim(unsigned dim)
159{
160	switch (dim) {
161	default:
162	case PIPE_TEXTURE_1D:
163		return V_030000_SQ_TEX_DIM_1D;
164	case PIPE_TEXTURE_1D_ARRAY:
165		return V_030000_SQ_TEX_DIM_1D_ARRAY;
166	case PIPE_TEXTURE_2D:
167	case PIPE_TEXTURE_RECT:
168		return V_030000_SQ_TEX_DIM_2D;
169	case PIPE_TEXTURE_2D_ARRAY:
170		return V_030000_SQ_TEX_DIM_2D_ARRAY;
171	case PIPE_TEXTURE_3D:
172		return V_030000_SQ_TEX_DIM_3D;
173	case PIPE_TEXTURE_CUBE:
174		return V_030000_SQ_TEX_DIM_CUBEMAP;
175	}
176}
177
178static uint32_t r600_translate_dbformat(enum pipe_format format)
179{
180	switch (format) {
181	case PIPE_FORMAT_Z16_UNORM:
182		return V_028040_Z_16;
183	case PIPE_FORMAT_Z24X8_UNORM:
184	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
185		return V_028040_Z_24;
186	case PIPE_FORMAT_Z32_FLOAT:
187	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
188		return V_028040_Z_32_FLOAT;
189	default:
190		return ~0U;
191	}
192}
193
194static uint32_t r600_translate_colorswap(enum pipe_format format)
195{
196	switch (format) {
197	/* 8-bit buffers. */
198	case PIPE_FORMAT_L4A4_UNORM:
199	case PIPE_FORMAT_A4R4_UNORM:
200		return V_028C70_SWAP_ALT;
201
202	case PIPE_FORMAT_A8_UNORM:
203	case PIPE_FORMAT_A8_SNORM:
204	case PIPE_FORMAT_A8_UINT:
205	case PIPE_FORMAT_A8_SINT:
206	case PIPE_FORMAT_A16_UNORM:
207	case PIPE_FORMAT_A16_SNORM:
208	case PIPE_FORMAT_A16_UINT:
209	case PIPE_FORMAT_A16_SINT:
210	case PIPE_FORMAT_A16_FLOAT:
211	case PIPE_FORMAT_A32_UINT:
212	case PIPE_FORMAT_A32_SINT:
213	case PIPE_FORMAT_A32_FLOAT:
214	case PIPE_FORMAT_R4A4_UNORM:
215		return V_028C70_SWAP_ALT_REV;
216	case PIPE_FORMAT_I8_UNORM:
217	case PIPE_FORMAT_I8_SNORM:
218	case PIPE_FORMAT_I8_UINT:
219	case PIPE_FORMAT_I8_SINT:
220	case PIPE_FORMAT_I16_UNORM:
221	case PIPE_FORMAT_I16_SNORM:
222	case PIPE_FORMAT_I16_UINT:
223	case PIPE_FORMAT_I16_SINT:
224	case PIPE_FORMAT_I16_FLOAT:
225	case PIPE_FORMAT_I32_UINT:
226	case PIPE_FORMAT_I32_SINT:
227	case PIPE_FORMAT_I32_FLOAT:
228	case PIPE_FORMAT_L8_UNORM:
229	case PIPE_FORMAT_L8_SNORM:
230	case PIPE_FORMAT_L8_UINT:
231	case PIPE_FORMAT_L8_SINT:
232	case PIPE_FORMAT_L8_SRGB:
233	case PIPE_FORMAT_L16_UNORM:
234	case PIPE_FORMAT_L16_SNORM:
235	case PIPE_FORMAT_L16_UINT:
236	case PIPE_FORMAT_L16_SINT:
237	case PIPE_FORMAT_L16_FLOAT:
238	case PIPE_FORMAT_L32_UINT:
239	case PIPE_FORMAT_L32_SINT:
240	case PIPE_FORMAT_L32_FLOAT:
241	case PIPE_FORMAT_R8_UNORM:
242	case PIPE_FORMAT_R8_SNORM:
243	case PIPE_FORMAT_R8_UINT:
244	case PIPE_FORMAT_R8_SINT:
245		return V_028C70_SWAP_STD;
246
247	/* 16-bit buffers. */
248	case PIPE_FORMAT_B5G6R5_UNORM:
249		return V_028C70_SWAP_STD_REV;
250
251	case PIPE_FORMAT_B5G5R5A1_UNORM:
252	case PIPE_FORMAT_B5G5R5X1_UNORM:
253		return V_028C70_SWAP_ALT;
254
255	case PIPE_FORMAT_B4G4R4A4_UNORM:
256	case PIPE_FORMAT_B4G4R4X4_UNORM:
257		return V_028C70_SWAP_ALT;
258
259	case PIPE_FORMAT_Z16_UNORM:
260		return V_028C70_SWAP_STD;
261
262	case PIPE_FORMAT_L8A8_UNORM:
263	case PIPE_FORMAT_L8A8_SNORM:
264	case PIPE_FORMAT_L8A8_UINT:
265	case PIPE_FORMAT_L8A8_SINT:
266	case PIPE_FORMAT_L8A8_SRGB:
267	case PIPE_FORMAT_L16A16_UNORM:
268	case PIPE_FORMAT_L16A16_SNORM:
269	case PIPE_FORMAT_L16A16_UINT:
270	case PIPE_FORMAT_L16A16_SINT:
271	case PIPE_FORMAT_L16A16_FLOAT:
272	case PIPE_FORMAT_L32A32_UINT:
273	case PIPE_FORMAT_L32A32_SINT:
274	case PIPE_FORMAT_L32A32_FLOAT:
275		return V_028C70_SWAP_ALT;
276	case PIPE_FORMAT_R8G8_UNORM:
277	case PIPE_FORMAT_R8G8_SNORM:
278	case PIPE_FORMAT_R8G8_UINT:
279	case PIPE_FORMAT_R8G8_SINT:
280		return V_028C70_SWAP_STD;
281
282	case PIPE_FORMAT_R16_UNORM:
283	case PIPE_FORMAT_R16_SNORM:
284	case PIPE_FORMAT_R16_UINT:
285	case PIPE_FORMAT_R16_SINT:
286	case PIPE_FORMAT_R16_FLOAT:
287		return V_028C70_SWAP_STD;
288
289	/* 32-bit buffers. */
290	case PIPE_FORMAT_A8B8G8R8_SRGB:
291		return V_028C70_SWAP_STD_REV;
292	case PIPE_FORMAT_B8G8R8A8_SRGB:
293		return V_028C70_SWAP_ALT;
294
295	case PIPE_FORMAT_B8G8R8A8_UNORM:
296	case PIPE_FORMAT_B8G8R8X8_UNORM:
297		return V_028C70_SWAP_ALT;
298
299	case PIPE_FORMAT_A8R8G8B8_UNORM:
300	case PIPE_FORMAT_X8R8G8B8_UNORM:
301		return V_028C70_SWAP_ALT_REV;
302	case PIPE_FORMAT_R8G8B8A8_SNORM:
303	case PIPE_FORMAT_R8G8B8A8_UNORM:
304	case PIPE_FORMAT_R8G8B8A8_SINT:
305	case PIPE_FORMAT_R8G8B8A8_UINT:
306	case PIPE_FORMAT_R8G8B8X8_UNORM:
307		return V_028C70_SWAP_STD;
308
309	case PIPE_FORMAT_A8B8G8R8_UNORM:
310	case PIPE_FORMAT_X8B8G8R8_UNORM:
311	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
312		return V_028C70_SWAP_STD_REV;
313
314	case PIPE_FORMAT_Z24X8_UNORM:
315	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
316		return V_028C70_SWAP_STD;
317
318	case PIPE_FORMAT_X8Z24_UNORM:
319	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
320		return V_028C70_SWAP_STD;
321
322	case PIPE_FORMAT_R10G10B10A2_UNORM:
323	case PIPE_FORMAT_R10G10B10X2_SNORM:
324	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
325		return V_028C70_SWAP_STD;
326
327	case PIPE_FORMAT_B10G10R10A2_UNORM:
328	case PIPE_FORMAT_B10G10R10A2_UINT:
329		return V_028C70_SWAP_ALT;
330
331	case PIPE_FORMAT_R11G11B10_FLOAT:
332	case PIPE_FORMAT_R32_FLOAT:
333	case PIPE_FORMAT_R32_UINT:
334	case PIPE_FORMAT_R32_SINT:
335	case PIPE_FORMAT_Z32_FLOAT:
336	case PIPE_FORMAT_R16G16_FLOAT:
337	case PIPE_FORMAT_R16G16_UNORM:
338	case PIPE_FORMAT_R16G16_SNORM:
339	case PIPE_FORMAT_R16G16_UINT:
340	case PIPE_FORMAT_R16G16_SINT:
341		return V_028C70_SWAP_STD;
342
343	/* 64-bit buffers. */
344	case PIPE_FORMAT_R32G32_FLOAT:
345	case PIPE_FORMAT_R32G32_UINT:
346	case PIPE_FORMAT_R32G32_SINT:
347	case PIPE_FORMAT_R16G16B16A16_UNORM:
348	case PIPE_FORMAT_R16G16B16A16_SNORM:
349	case PIPE_FORMAT_R16G16B16A16_UINT:
350	case PIPE_FORMAT_R16G16B16A16_SINT:
351	case PIPE_FORMAT_R16G16B16A16_FLOAT:
352	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
353
354	/* 128-bit buffers. */
355	case PIPE_FORMAT_R32G32B32A32_FLOAT:
356	case PIPE_FORMAT_R32G32B32A32_SNORM:
357	case PIPE_FORMAT_R32G32B32A32_UNORM:
358	case PIPE_FORMAT_R32G32B32A32_SINT:
359	case PIPE_FORMAT_R32G32B32A32_UINT:
360		return V_028C70_SWAP_STD;
361	default:
362		R600_ERR("unsupported colorswap format %d\n", format);
363		return ~0U;
364	}
365	return ~0U;
366}
367
368static uint32_t r600_translate_colorformat(enum pipe_format format)
369{
370	switch (format) {
371	/* 8-bit buffers. */
372	case PIPE_FORMAT_A8_UNORM:
373	case PIPE_FORMAT_A8_SNORM:
374	case PIPE_FORMAT_A8_UINT:
375	case PIPE_FORMAT_A8_SINT:
376	case PIPE_FORMAT_I8_UNORM:
377	case PIPE_FORMAT_I8_SNORM:
378	case PIPE_FORMAT_I8_UINT:
379	case PIPE_FORMAT_I8_SINT:
380	case PIPE_FORMAT_L8_UNORM:
381	case PIPE_FORMAT_L8_SNORM:
382	case PIPE_FORMAT_L8_UINT:
383	case PIPE_FORMAT_L8_SINT:
384	case PIPE_FORMAT_L8_SRGB:
385	case PIPE_FORMAT_R8_UNORM:
386	case PIPE_FORMAT_R8_SNORM:
387	case PIPE_FORMAT_R8_UINT:
388	case PIPE_FORMAT_R8_SINT:
389		return V_028C70_COLOR_8;
390
391	/* 16-bit buffers. */
392	case PIPE_FORMAT_B5G6R5_UNORM:
393		return V_028C70_COLOR_5_6_5;
394
395	case PIPE_FORMAT_B5G5R5A1_UNORM:
396	case PIPE_FORMAT_B5G5R5X1_UNORM:
397		return V_028C70_COLOR_1_5_5_5;
398
399	case PIPE_FORMAT_B4G4R4A4_UNORM:
400	case PIPE_FORMAT_B4G4R4X4_UNORM:
401		return V_028C70_COLOR_4_4_4_4;
402
403	case PIPE_FORMAT_Z16_UNORM:
404		return V_028C70_COLOR_16;
405
406	case PIPE_FORMAT_L8A8_UNORM:
407	case PIPE_FORMAT_L8A8_SNORM:
408	case PIPE_FORMAT_L8A8_UINT:
409	case PIPE_FORMAT_L8A8_SINT:
410	case PIPE_FORMAT_L8A8_SRGB:
411	case PIPE_FORMAT_R8G8_UNORM:
412	case PIPE_FORMAT_R8G8_SNORM:
413	case PIPE_FORMAT_R8G8_UINT:
414	case PIPE_FORMAT_R8G8_SINT:
415		return V_028C70_COLOR_8_8;
416
417	case PIPE_FORMAT_R16_UNORM:
418	case PIPE_FORMAT_R16_SNORM:
419	case PIPE_FORMAT_R16_UINT:
420	case PIPE_FORMAT_R16_SINT:
421	case PIPE_FORMAT_A16_UNORM:
422	case PIPE_FORMAT_A16_SNORM:
423	case PIPE_FORMAT_A16_UINT:
424	case PIPE_FORMAT_A16_SINT:
425	case PIPE_FORMAT_L16_UNORM:
426	case PIPE_FORMAT_L16_SNORM:
427	case PIPE_FORMAT_L16_UINT:
428	case PIPE_FORMAT_L16_SINT:
429	case PIPE_FORMAT_I16_UNORM:
430	case PIPE_FORMAT_I16_SNORM:
431	case PIPE_FORMAT_I16_UINT:
432	case PIPE_FORMAT_I16_SINT:
433		return V_028C70_COLOR_16;
434
435	case PIPE_FORMAT_R16_FLOAT:
436	case PIPE_FORMAT_A16_FLOAT:
437	case PIPE_FORMAT_L16_FLOAT:
438	case PIPE_FORMAT_I16_FLOAT:
439		return V_028C70_COLOR_16_FLOAT;
440
441	/* 32-bit buffers. */
442	case PIPE_FORMAT_A8B8G8R8_SRGB:
443	case PIPE_FORMAT_A8B8G8R8_UNORM:
444	case PIPE_FORMAT_A8R8G8B8_UNORM:
445	case PIPE_FORMAT_B8G8R8A8_SRGB:
446	case PIPE_FORMAT_B8G8R8A8_UNORM:
447	case PIPE_FORMAT_B8G8R8X8_UNORM:
448	case PIPE_FORMAT_R8G8B8A8_SNORM:
449	case PIPE_FORMAT_R8G8B8A8_UNORM:
450	case PIPE_FORMAT_R8G8B8X8_UNORM:
451	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
452	case PIPE_FORMAT_X8B8G8R8_UNORM:
453	case PIPE_FORMAT_X8R8G8B8_UNORM:
454	case PIPE_FORMAT_R8G8B8_UNORM:
455	case PIPE_FORMAT_R8G8B8A8_SINT:
456	case PIPE_FORMAT_R8G8B8A8_UINT:
457		return V_028C70_COLOR_8_8_8_8;
458
459	case PIPE_FORMAT_R10G10B10A2_UNORM:
460	case PIPE_FORMAT_R10G10B10X2_SNORM:
461	case PIPE_FORMAT_B10G10R10A2_UNORM:
462	case PIPE_FORMAT_B10G10R10A2_UINT:
463	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
464		return V_028C70_COLOR_2_10_10_10;
465
466	case PIPE_FORMAT_Z24X8_UNORM:
467	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
468		return V_028C70_COLOR_8_24;
469
470	case PIPE_FORMAT_X8Z24_UNORM:
471	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
472		return V_028C70_COLOR_24_8;
473
474	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
475		return V_028C70_COLOR_X24_8_32_FLOAT;
476
477	case PIPE_FORMAT_R32_UINT:
478	case PIPE_FORMAT_R32_SINT:
479	case PIPE_FORMAT_A32_UINT:
480	case PIPE_FORMAT_A32_SINT:
481	case PIPE_FORMAT_L32_UINT:
482	case PIPE_FORMAT_L32_SINT:
483	case PIPE_FORMAT_I32_UINT:
484	case PIPE_FORMAT_I32_SINT:
485		return V_028C70_COLOR_32;
486
487	case PIPE_FORMAT_R32_FLOAT:
488	case PIPE_FORMAT_A32_FLOAT:
489	case PIPE_FORMAT_L32_FLOAT:
490	case PIPE_FORMAT_I32_FLOAT:
491	case PIPE_FORMAT_Z32_FLOAT:
492		return V_028C70_COLOR_32_FLOAT;
493
494	case PIPE_FORMAT_R16G16_FLOAT:
495	case PIPE_FORMAT_L16A16_FLOAT:
496		return V_028C70_COLOR_16_16_FLOAT;
497
498	case PIPE_FORMAT_R16G16_UNORM:
499	case PIPE_FORMAT_R16G16_SNORM:
500	case PIPE_FORMAT_R16G16_UINT:
501	case PIPE_FORMAT_R16G16_SINT:
502	case PIPE_FORMAT_L16A16_UNORM:
503	case PIPE_FORMAT_L16A16_SNORM:
504	case PIPE_FORMAT_L16A16_UINT:
505	case PIPE_FORMAT_L16A16_SINT:
506		return V_028C70_COLOR_16_16;
507
508	case PIPE_FORMAT_R11G11B10_FLOAT:
509		return V_028C70_COLOR_10_11_11_FLOAT;
510
511	/* 64-bit buffers. */
512	case PIPE_FORMAT_R16G16B16A16_UINT:
513	case PIPE_FORMAT_R16G16B16A16_SINT:
514	case PIPE_FORMAT_R16G16B16A16_UNORM:
515	case PIPE_FORMAT_R16G16B16A16_SNORM:
516		return V_028C70_COLOR_16_16_16_16;
517
518	case PIPE_FORMAT_R16G16B16A16_FLOAT:
519		return V_028C70_COLOR_16_16_16_16_FLOAT;
520
521	case PIPE_FORMAT_R32G32_FLOAT:
522	case PIPE_FORMAT_L32A32_FLOAT:
523		return V_028C70_COLOR_32_32_FLOAT;
524
525	case PIPE_FORMAT_R32G32_SINT:
526	case PIPE_FORMAT_R32G32_UINT:
527	case PIPE_FORMAT_L32A32_UINT:
528	case PIPE_FORMAT_L32A32_SINT:
529		return V_028C70_COLOR_32_32;
530
531	/* 128-bit buffers. */
532	case PIPE_FORMAT_R32G32B32A32_SNORM:
533	case PIPE_FORMAT_R32G32B32A32_UNORM:
534	case PIPE_FORMAT_R32G32B32A32_SINT:
535	case PIPE_FORMAT_R32G32B32A32_UINT:
536		return V_028C70_COLOR_32_32_32_32;
537	case PIPE_FORMAT_R32G32B32A32_FLOAT:
538		return V_028C70_COLOR_32_32_32_32_FLOAT;
539
540	/* YUV buffers. */
541	case PIPE_FORMAT_UYVY:
542	case PIPE_FORMAT_YUYV:
543	default:
544		return ~0U; /* Unsupported. */
545	}
546}
547
548static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
549{
550	if (R600_BIG_ENDIAN) {
551		switch(colorformat) {
552
553		/* 8-bit buffers. */
554		case V_028C70_COLOR_8:
555			return ENDIAN_NONE;
556
557		/* 16-bit buffers. */
558		case V_028C70_COLOR_5_6_5:
559		case V_028C70_COLOR_1_5_5_5:
560		case V_028C70_COLOR_4_4_4_4:
561		case V_028C70_COLOR_16:
562		case V_028C70_COLOR_8_8:
563			return ENDIAN_8IN16;
564
565		/* 32-bit buffers. */
566		case V_028C70_COLOR_8_8_8_8:
567		case V_028C70_COLOR_2_10_10_10:
568		case V_028C70_COLOR_8_24:
569		case V_028C70_COLOR_24_8:
570		case V_028C70_COLOR_32_FLOAT:
571		case V_028C70_COLOR_16_16_FLOAT:
572		case V_028C70_COLOR_16_16:
573			return ENDIAN_8IN32;
574
575		/* 64-bit buffers. */
576		case V_028C70_COLOR_16_16_16_16:
577		case V_028C70_COLOR_16_16_16_16_FLOAT:
578			return ENDIAN_8IN16;
579
580		case V_028C70_COLOR_32_32_FLOAT:
581		case V_028C70_COLOR_32_32:
582		case V_028C70_COLOR_X24_8_32_FLOAT:
583			return ENDIAN_8IN32;
584
585		/* 96-bit buffers. */
586		case V_028C70_COLOR_32_32_32_FLOAT:
587		/* 128-bit buffers. */
588		case V_028C70_COLOR_32_32_32_32_FLOAT:
589		case V_028C70_COLOR_32_32_32_32:
590			return ENDIAN_8IN32;
591		default:
592			return ENDIAN_NONE; /* Unsupported. */
593		}
594	} else {
595		return ENDIAN_NONE;
596	}
597}
598
599static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
600{
601	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
602}
603
604static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
605{
606	return r600_translate_colorformat(format) != ~0U &&
607		r600_translate_colorswap(format) != ~0U;
608}
609
610static bool r600_is_zs_format_supported(enum pipe_format format)
611{
612	return r600_translate_dbformat(format) != ~0U;
613}
614
615boolean evergreen_is_format_supported(struct pipe_screen *screen,
616				      enum pipe_format format,
617				      enum pipe_texture_target target,
618				      unsigned sample_count,
619				      unsigned usage)
620{
621	unsigned retval = 0;
622
623	if (target >= PIPE_MAX_TEXTURE_TYPES) {
624		R600_ERR("r600: unsupported texture type %d\n", target);
625		return FALSE;
626	}
627
628	if (!util_format_is_supported(format, usage))
629		return FALSE;
630
631	/* Multisample */
632	if (sample_count > 1)
633		return FALSE;
634
635	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
636	    r600_is_sampler_format_supported(screen, format)) {
637		retval |= PIPE_BIND_SAMPLER_VIEW;
638	}
639
640	if ((usage & (PIPE_BIND_RENDER_TARGET |
641		      PIPE_BIND_DISPLAY_TARGET |
642		      PIPE_BIND_SCANOUT |
643		      PIPE_BIND_SHARED)) &&
644	    r600_is_colorbuffer_format_supported(format)) {
645		retval |= usage &
646			  (PIPE_BIND_RENDER_TARGET |
647			   PIPE_BIND_DISPLAY_TARGET |
648			   PIPE_BIND_SCANOUT |
649			   PIPE_BIND_SHARED);
650	}
651
652	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
653	    r600_is_zs_format_supported(format)) {
654		retval |= PIPE_BIND_DEPTH_STENCIL;
655	}
656
657	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
658	    r600_is_vertex_format_supported(format)) {
659		retval |= PIPE_BIND_VERTEX_BUFFER;
660	}
661
662	if (usage & PIPE_BIND_TRANSFER_READ)
663		retval |= PIPE_BIND_TRANSFER_READ;
664	if (usage & PIPE_BIND_TRANSFER_WRITE)
665		retval |= PIPE_BIND_TRANSFER_WRITE;
666
667	return retval == usage;
668}
669
670static void *evergreen_create_blend_state(struct pipe_context *ctx,
671					const struct pipe_blend_state *state)
672{
673	struct r600_context *rctx = (struct r600_context *)ctx;
674	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
675	struct r600_pipe_state *rstate;
676	uint32_t color_control = 0, target_mask;
677	/* XXX there is more then 8 framebuffer */
678	unsigned blend_cntl[8];
679
680	if (blend == NULL) {
681		return NULL;
682	}
683
684	rstate = &blend->rstate;
685
686	rstate->id = R600_PIPE_STATE_BLEND;
687
688	target_mask = 0;
689	if (state->logicop_enable) {
690		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
691	} else {
692		color_control |= (0xcc << 16);
693	}
694	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
695	if (state->independent_blend_enable) {
696		for (int i = 0; i < 8; i++) {
697			target_mask |= (state->rt[i].colormask << (4 * i));
698		}
699	} else {
700		for (int i = 0; i < 8; i++) {
701			target_mask |= (state->rt[0].colormask << (4 * i));
702		}
703	}
704	blend->cb_target_mask = target_mask;
705
706	if (target_mask)
707		color_control |= S_028808_MODE(V_028808_CB_NORMAL);
708	else
709		color_control |= S_028808_MODE(V_028808_CB_DISABLE);
710
711	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
712				color_control);
713	/* only have dual source on MRT0 */
714	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
715	for (int i = 0; i < 8; i++) {
716		/* state->rt entries > 0 only written if independent blending */
717		const int j = state->independent_blend_enable ? i : 0;
718
719		unsigned eqRGB = state->rt[j].rgb_func;
720		unsigned srcRGB = state->rt[j].rgb_src_factor;
721		unsigned dstRGB = state->rt[j].rgb_dst_factor;
722		unsigned eqA = state->rt[j].alpha_func;
723		unsigned srcA = state->rt[j].alpha_src_factor;
724		unsigned dstA = state->rt[j].alpha_dst_factor;
725
726		blend_cntl[i] = 0;
727		if (!state->rt[j].blend_enable)
728			continue;
729
730		blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
731		blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
732		blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
733		blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
734
735		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
736			blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
737			blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
738			blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
739			blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
740		}
741	}
742	for (int i = 0; i < 8; i++) {
743		r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
744	}
745
746	blend->alpha_to_one = state->alpha_to_one;
747	return rstate;
748}
749
750static void *evergreen_create_dsa_state(struct pipe_context *ctx,
751				   const struct pipe_depth_stencil_alpha_state *state)
752{
753	struct r600_context *rctx = (struct r600_context *)ctx;
754	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
755	unsigned db_depth_control, alpha_test_control, alpha_ref;
756	struct r600_pipe_state *rstate;
757
758	if (dsa == NULL) {
759		return NULL;
760	}
761
762	dsa->valuemask[0] = state->stencil[0].valuemask;
763	dsa->valuemask[1] = state->stencil[1].valuemask;
764	dsa->writemask[0] = state->stencil[0].writemask;
765	dsa->writemask[1] = state->stencil[1].writemask;
766
767	rstate = &dsa->rstate;
768
769	rstate->id = R600_PIPE_STATE_DSA;
770	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
771		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
772		S_028800_ZFUNC(state->depth.func);
773
774	/* stencil */
775	if (state->stencil[0].enabled) {
776		db_depth_control |= S_028800_STENCIL_ENABLE(1);
777		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
778		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
779		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
780		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
781
782		if (state->stencil[1].enabled) {
783			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
784			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
785			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
786			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
787			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
788		}
789	}
790
791	/* alpha */
792	alpha_test_control = 0;
793	alpha_ref = 0;
794	if (state->alpha.enabled) {
795		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
796		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
797		alpha_ref = fui(state->alpha.ref_value);
798	}
799	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
800	dsa->alpha_ref = alpha_ref;
801
802	/* misc */
803	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
804	return rstate;
805}
806
807static void *evergreen_create_rs_state(struct pipe_context *ctx,
808					const struct pipe_rasterizer_state *state)
809{
810	struct r600_context *rctx = (struct r600_context *)ctx;
811	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
812	struct r600_pipe_state *rstate;
813	unsigned tmp;
814	unsigned prov_vtx = 1, polygon_dual_mode;
815	float psize_min, psize_max;
816
817	if (rs == NULL) {
818		return NULL;
819	}
820
821	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
822				state->fill_back != PIPE_POLYGON_MODE_FILL);
823
824	if (state->flatshade_first)
825		prov_vtx = 0;
826
827	rstate = &rs->rstate;
828	rs->flatshade = state->flatshade;
829	rs->sprite_coord_enable = state->sprite_coord_enable;
830	rs->two_side = state->light_twoside;
831	rs->clip_plane_enable = state->clip_plane_enable;
832	rs->pa_sc_line_stipple = state->line_stipple_enable ?
833				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
834				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
835	rs->pa_cl_clip_cntl =
836		S_028810_PS_UCP_MODE(3) |
837		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
838		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
839		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
840	rs->multisample_enable = state->multisample;
841
842	/* offset */
843	rs->offset_units = state->offset_units;
844	rs->offset_scale = state->offset_scale * 12.0f;
845
846	rstate->id = R600_PIPE_STATE_RASTERIZER;
847	tmp = S_0286D4_FLAT_SHADE_ENA(1);
848	if (state->sprite_coord_enable) {
849		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
850			S_0286D4_PNT_SPRITE_OVRD_X(2) |
851			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
852			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
853			S_0286D4_PNT_SPRITE_OVRD_W(1);
854		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
855			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
856		}
857	}
858	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
859
860	/* point size 12.4 fixed point */
861	tmp = (unsigned)(state->point_size * 8.0);
862	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
863
864	if (state->point_size_per_vertex) {
865		psize_min = util_get_min_point_size(state);
866		psize_max = 8192;
867	} else {
868		/* Force the point size to be as if the vertex output was disabled. */
869		psize_min = state->point_size;
870		psize_max = state->point_size;
871	}
872	/* Divide by two, because 0.5 = 1 pixel. */
873	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
874				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
875				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
876
877	tmp = (unsigned)state->line_width * 8;
878	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
879	r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
880				S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
881				S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
882
883	if (rctx->chip_class == CAYMAN) {
884		r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
885					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
886	} else {
887		r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
888					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
889	}
890	r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
891	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
892				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
893				S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
894				S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
895				S_028814_FACE(!state->front_ccw) |
896				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
897				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
898				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
899				S_028814_POLY_MODE(polygon_dual_mode) |
900				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
901				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
902	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
903	return rstate;
904}
905
906static void *evergreen_create_sampler_state(struct pipe_context *ctx,
907					const struct pipe_sampler_state *state)
908{
909	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
910	union util_color uc;
911	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
912
913	if (ss == NULL) {
914		return NULL;
915	}
916
917	/* directly into sampler avoid r6xx code to emit useless reg */
918	ss->seamless_cube_map = false;
919	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
920	ss->border_color_use = false;
921	/* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
922	ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
923				S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
924				S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
925				S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
926				S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
927				S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
928				S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
929				S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
930				S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
931	/* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
932	ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
933				S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
934	/* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
935	ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
936				(state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
937				S_03C008_TYPE(1);
938	if (uc.ui) {
939		ss->border_color_use = true;
940		/* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
941		ss->border_color[0] = fui(state->border_color.f[0]);
942		/* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
943		ss->border_color[1] = fui(state->border_color.f[1]);
944		/* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
945		ss->border_color[2] = fui(state->border_color.f[2]);
946		/* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
947		ss->border_color[3] = fui(state->border_color.f[3]);
948	}
949	return ss;
950}
951
952static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
953							struct pipe_resource *texture,
954							const struct pipe_sampler_view *state)
955{
956	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
957	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
958	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
959	unsigned format, endian;
960	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
961	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
962	unsigned height, depth, width;
963	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
964
965	if (view == NULL)
966		return NULL;
967
968	/* initialize base object */
969	view->base = *state;
970	view->base.texture = NULL;
971	pipe_reference(NULL, &texture->reference);
972	view->base.texture = texture;
973	view->base.reference.count = 1;
974	view->base.context = ctx;
975
976	swizzle[0] = state->swizzle_r;
977	swizzle[1] = state->swizzle_g;
978	swizzle[2] = state->swizzle_b;
979	swizzle[3] = state->swizzle_a;
980
981	format = r600_translate_texformat(ctx->screen, state->format,
982					  swizzle,
983					  &word4, &yuv_format);
984	assert(format != ~0);
985	if (format == ~0) {
986		FREE(view);
987		return NULL;
988	}
989
990	if (tmp->is_depth && !tmp->is_flushing_texture) {
991		if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
992			FREE(view);
993			return NULL;
994		}
995		tmp = tmp->flushed_depth_texture;
996	}
997
998	endian = r600_colorformat_endian_swap(format);
999
1000	width = tmp->surface.level[0].npix_x;
1001	height = tmp->surface.level[0].npix_y;
1002	depth = tmp->surface.level[0].npix_z;
1003	pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1004	tile_type = tmp->tile_type;
1005
1006	switch (tmp->surface.level[0].mode) {
1007	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1008		array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1009		break;
1010	case RADEON_SURF_MODE_2D:
1011		array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1012		break;
1013	case RADEON_SURF_MODE_1D:
1014		array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1015		break;
1016	case RADEON_SURF_MODE_LINEAR:
1017	default:
1018		array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1019		break;
1020	}
1021	tile_split = tmp->surface.tile_split;
1022	macro_aspect = tmp->surface.mtilea;
1023	bankw = tmp->surface.bankw;
1024	bankh = tmp->surface.bankh;
1025	tile_split = eg_tile_split(tile_split);
1026	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1027	bankw = eg_bank_wh(bankw);
1028	bankh = eg_bank_wh(bankh);
1029
1030	/* 128 bit formats require tile type = 1 */
1031	if (rscreen->chip_class == CAYMAN) {
1032		if (util_format_get_blocksize(state->format) >= 16)
1033			tile_type = 1;
1034	}
1035	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1036
1037	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1038	        height = 1;
1039		depth = texture->array_size;
1040	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1041		depth = texture->array_size;
1042	}
1043
1044	view->tex_resource = &tmp->resource;
1045	view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1046				       S_030000_PITCH((pitch / 8) - 1) |
1047				       S_030000_TEX_WIDTH(width - 1));
1048	if (rscreen->chip_class == CAYMAN)
1049		view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1050	else
1051		view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1052	view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1053				       S_030004_TEX_DEPTH(depth - 1) |
1054				       S_030004_ARRAY_MODE(array_mode));
1055	view->tex_resource_words[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1056	if (state->u.tex.last_level) {
1057		view->tex_resource_words[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1058	} else {
1059		view->tex_resource_words[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1060	}
1061	view->tex_resource_words[4] = (word4 |
1062				       S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1063				       S_030010_ENDIAN_SWAP(endian) |
1064				       S_030010_BASE_LEVEL(state->u.tex.first_level));
1065	view->tex_resource_words[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1066				       S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1067				       S_030014_LAST_ARRAY(state->u.tex.last_layer));
1068	/* aniso max 16 samples */
1069	view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1070				      (S_030018_TILE_SPLIT(tile_split));
1071	view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1072				      S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1073				      S_03001C_BANK_WIDTH(bankw) |
1074				      S_03001C_BANK_HEIGHT(bankh) |
1075				      S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1076				      S_03001C_NUM_BANKS(nbanks);
1077	return &view->base;
1078}
1079
1080static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1081					   struct pipe_sampler_view **views)
1082{
1083	struct r600_context *rctx = (struct r600_context *)ctx;
1084	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
1085}
1086
1087static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1088					   struct pipe_sampler_view **views)
1089{
1090	struct r600_context *rctx = (struct r600_context *)ctx;
1091	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
1092}
1093
1094static void evergreen_set_clip_state(struct pipe_context *ctx,
1095				const struct pipe_clip_state *state)
1096{
1097	struct r600_context *rctx = (struct r600_context *)ctx;
1098	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1099	struct pipe_constant_buffer cb;
1100
1101	if (rstate == NULL)
1102		return;
1103
1104	rctx->clip = *state;
1105	rstate->id = R600_PIPE_STATE_CLIP;
1106	for (int i = 0; i < 6; i++) {
1107		r600_pipe_state_add_reg(rstate,
1108					R_0285BC_PA_CL_UCP0_X + i * 16,
1109					fui(state->ucp[i][0]));
1110		r600_pipe_state_add_reg(rstate,
1111					R_0285C0_PA_CL_UCP0_Y + i * 16,
1112					fui(state->ucp[i][1]) );
1113		r600_pipe_state_add_reg(rstate,
1114					R_0285C4_PA_CL_UCP0_Z + i * 16,
1115					fui(state->ucp[i][2]));
1116		r600_pipe_state_add_reg(rstate,
1117					R_0285C8_PA_CL_UCP0_W + i * 16,
1118					fui(state->ucp[i][3]));
1119	}
1120
1121	free(rctx->states[R600_PIPE_STATE_CLIP]);
1122	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1123	r600_context_pipe_state_set(rctx, rstate);
1124
1125	cb.buffer = NULL;
1126	cb.user_buffer = state->ucp;
1127	cb.buffer_offset = 0;
1128	cb.buffer_size = 4*4*8;
1129	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1130	pipe_resource_reference(&cb.buffer, NULL);
1131}
1132
1133static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1134					 const struct pipe_poly_stipple *state)
1135{
1136}
1137
1138static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1139{
1140}
1141
1142static void evergreen_get_scissor_rect(struct r600_context *rctx,
1143				       unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1144				       uint32_t *tl, uint32_t *br)
1145{
1146	/* EG hw workaround */
1147	if (br_x == 0)
1148		tl_x = 1;
1149	if (br_y == 0)
1150		tl_y = 1;
1151
1152	/* cayman hw workaround */
1153	if (rctx->chip_class == CAYMAN) {
1154		if (br_x == 1 && br_y == 1)
1155			br_x = 2;
1156	}
1157
1158	*tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1159	*br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1160}
1161
1162static void evergreen_set_scissor_state(struct pipe_context *ctx,
1163					const struct pipe_scissor_state *state)
1164{
1165	struct r600_context *rctx = (struct r600_context *)ctx;
1166	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1167	uint32_t tl, br;
1168
1169	if (rstate == NULL)
1170		return;
1171
1172	evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1173
1174	rstate->id = R600_PIPE_STATE_SCISSOR;
1175	r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1176	r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1177
1178	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1179	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1180	r600_context_pipe_state_set(rctx, rstate);
1181}
1182
1183static void evergreen_set_viewport_state(struct pipe_context *ctx,
1184					const struct pipe_viewport_state *state)
1185{
1186	struct r600_context *rctx = (struct r600_context *)ctx;
1187	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1188
1189	if (rstate == NULL)
1190		return;
1191
1192	rctx->viewport = *state;
1193	rstate->id = R600_PIPE_STATE_VIEWPORT;
1194	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1195	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1196	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1197	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1198	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1199	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1200
1201	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1202	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1203	r600_context_pipe_state_set(rctx, rstate);
1204}
1205
1206void evergreen_init_color_surface(struct r600_context *rctx,
1207				  struct r600_surface *surf)
1208{
1209	struct r600_screen *rscreen = rctx->screen;
1210	struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1211	struct pipe_resource *pipe_tex = surf->base.texture;
1212	unsigned level = surf->base.u.tex.level;
1213	unsigned pitch, slice;
1214	unsigned color_info, color_attrib, color_dim = 0;
1215	unsigned format, swap, ntype, endian;
1216	uint64_t offset;
1217	unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1218	const struct util_format_description *desc;
1219	int i;
1220	bool blend_clamp = 0, blend_bypass = 0;
1221
1222	if (rtex->is_depth && !rtex->is_flushing_texture) {
1223		r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1224		rtex = rtex->flushed_depth_texture;
1225		assert(rtex);
1226	}
1227
1228	offset = rtex->surface.level[level].offset;
1229	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1230		offset += rtex->surface.level[level].slice_size *
1231			  surf->base.u.tex.first_layer;
1232	}
1233	pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1234	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1235	if (slice) {
1236		slice = slice - 1;
1237	}
1238	color_info = 0;
1239	switch (rtex->surface.level[level].mode) {
1240	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1241		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1242		tile_type = 1;
1243		break;
1244	case RADEON_SURF_MODE_1D:
1245		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1246		tile_type = rtex->tile_type;
1247		break;
1248	case RADEON_SURF_MODE_2D:
1249		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1250		tile_type = rtex->tile_type;
1251		break;
1252	case RADEON_SURF_MODE_LINEAR:
1253	default:
1254		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1255		tile_type = 1;
1256		break;
1257	}
1258	tile_split = rtex->surface.tile_split;
1259	macro_aspect = rtex->surface.mtilea;
1260	bankw = rtex->surface.bankw;
1261	bankh = rtex->surface.bankh;
1262	tile_split = eg_tile_split(tile_split);
1263	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1264	bankw = eg_bank_wh(bankw);
1265	bankh = eg_bank_wh(bankh);
1266
1267	/* 128 bit formats require tile type = 1 */
1268	if (rscreen->chip_class == CAYMAN) {
1269		if (util_format_get_blocksize(surf->base.format) >= 16)
1270			tile_type = 1;
1271	}
1272	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1273	desc = util_format_description(surf->base.format);
1274	for (i = 0; i < 4; i++) {
1275		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1276			break;
1277		}
1278	}
1279
1280	color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1281			S_028C74_NUM_BANKS(nbanks) |
1282			S_028C74_BANK_WIDTH(bankw) |
1283			S_028C74_BANK_HEIGHT(bankh) |
1284			S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1285			S_028C74_NON_DISP_TILING_ORDER(tile_type);
1286
1287	ntype = V_028C70_NUMBER_UNORM;
1288	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1289		ntype = V_028C70_NUMBER_SRGB;
1290	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1291		if (desc->channel[i].normalized)
1292			ntype = V_028C70_NUMBER_SNORM;
1293		else if (desc->channel[i].pure_integer)
1294			ntype = V_028C70_NUMBER_SINT;
1295	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1296		if (desc->channel[i].normalized)
1297			ntype = V_028C70_NUMBER_UNORM;
1298		else if (desc->channel[i].pure_integer)
1299			ntype = V_028C70_NUMBER_UINT;
1300	}
1301
1302	format = r600_translate_colorformat(surf->base.format);
1303	assert(format != ~0);
1304
1305	swap = r600_translate_colorswap(surf->base.format);
1306	assert(swap != ~0);
1307
1308	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1309		endian = ENDIAN_NONE;
1310	} else {
1311		endian = r600_colorformat_endian_swap(format);
1312	}
1313
1314	/* blend clamp should be set for all NORM/SRGB types */
1315	if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1316	    ntype == V_028C70_NUMBER_SRGB)
1317		blend_clamp = 1;
1318
1319	/* set blend bypass according to docs if SINT/UINT or
1320	   8/24 COLOR variants */
1321	if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1322	    format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1323	    format == V_028C70_COLOR_X24_8_32_FLOAT) {
1324		blend_clamp = 0;
1325		blend_bypass = 1;
1326	}
1327
1328	surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1329
1330	color_info |= S_028C70_FORMAT(format) |
1331		S_028C70_COMP_SWAP(swap) |
1332		S_028C70_BLEND_CLAMP(blend_clamp) |
1333		S_028C70_BLEND_BYPASS(blend_bypass) |
1334		S_028C70_NUMBER_TYPE(ntype) |
1335		S_028C70_ENDIAN(endian);
1336
1337	if (rtex->is_rat) {
1338		color_info |= S_028C70_RAT(1);
1339		color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1340				| S_028C78_HEIGHT_MAX(pipe_tex->height0);
1341	}
1342
1343	/* EXPORT_NORM is an optimzation that can be enabled for better
1344	 * performance in certain cases.
1345	 * EXPORT_NORM can be enabled if:
1346	 * - 11-bit or smaller UNORM/SNORM/SRGB
1347	 * - 16-bit or smaller FLOAT
1348	 */
1349	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1350	    ((desc->channel[i].size < 12 &&
1351	      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1352	      ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1353	     (desc->channel[i].size < 17 &&
1354	      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1355		color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1356		surf->export_16bpc = true;
1357	}
1358
1359	offset += r600_resource_va(rctx->context.screen, pipe_tex);
1360	offset >>= 8;
1361
1362	/* XXX handle enabling of CB beyond BASE8 which has different offset */
1363	surf->cb_color_base = offset;
1364	surf->cb_color_dim = color_dim;
1365	surf->cb_color_info = color_info;
1366	surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1367	surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1368	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1369		surf->cb_color_view = 0;
1370	} else {
1371		surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1372				      S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1373	}
1374	surf->cb_color_attrib = color_attrib;
1375
1376	surf->color_initialized = true;
1377}
1378
1379static void evergreen_init_depth_surface(struct r600_context *rctx,
1380					 struct r600_surface *surf)
1381{
1382	struct r600_screen *rscreen = rctx->screen;
1383	struct pipe_screen *screen = &rscreen->screen;
1384	struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1385	uint64_t offset;
1386	unsigned level, pitch, slice, format, array_mode;
1387	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1388
1389	level = surf->base.u.tex.level;
1390	format = r600_translate_dbformat(surf->base.format);
1391	assert(format != ~0);
1392
1393	offset = r600_resource_va(screen, surf->base.texture);
1394	offset += rtex->surface.level[level].offset;
1395	pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1396	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1397	if (slice) {
1398		slice = slice - 1;
1399	}
1400	switch (rtex->surface.level[level].mode) {
1401	case RADEON_SURF_MODE_2D:
1402		array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1403		break;
1404	case RADEON_SURF_MODE_1D:
1405	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1406	case RADEON_SURF_MODE_LINEAR:
1407	default:
1408		array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1409		break;
1410	}
1411	tile_split = rtex->surface.tile_split;
1412	macro_aspect = rtex->surface.mtilea;
1413	bankw = rtex->surface.bankw;
1414	bankh = rtex->surface.bankh;
1415	tile_split = eg_tile_split(tile_split);
1416	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1417	bankw = eg_bank_wh(bankw);
1418	bankh = eg_bank_wh(bankh);
1419	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1420	offset >>= 8;
1421
1422	surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1423			      S_028040_FORMAT(format) |
1424			      S_028040_TILE_SPLIT(tile_split)|
1425			      S_028040_NUM_BANKS(nbanks) |
1426			      S_028040_BANK_WIDTH(bankw) |
1427			      S_028040_BANK_HEIGHT(bankh) |
1428			      S_028040_MACRO_TILE_ASPECT(macro_aspect);
1429	surf->db_depth_base = offset;
1430	surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1431			      S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1432	surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1433	surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1434
1435	if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1436		uint64_t stencil_offset = rtex->surface.stencil_offset;
1437		unsigned stile_split = rtex->surface.stencil_tile_split;
1438
1439		stile_split = eg_tile_split(stile_split);
1440		stencil_offset += r600_resource_va(screen, surf->base.texture);
1441		stencil_offset += rtex->surface.level[level].offset / 4;
1442		stencil_offset >>= 8;
1443
1444		surf->db_stencil_base = stencil_offset;
1445		surf->db_stencil_info = 1 | S_028044_TILE_SPLIT(stile_split);
1446	} else {
1447		surf->db_stencil_base = offset;
1448		surf->db_stencil_info = 1;
1449	}
1450
1451	surf->depth_initialized = true;
1452}
1453
1454static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1455					    const struct pipe_framebuffer_state *state)
1456{
1457	struct r600_context *rctx = (struct r600_context *)ctx;
1458	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1459	struct r600_surface *surf;
1460	struct r600_resource *res;
1461	uint32_t tl, br;
1462	int i;
1463
1464	if (rstate == NULL)
1465		return;
1466
1467	r600_flush_framebuffer(rctx, false);
1468
1469	/* unreference old buffer and reference new one */
1470	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1471
1472	util_copy_framebuffer_state(&rctx->framebuffer, state);
1473
1474	/* build states */
1475	rctx->export_16bpc = true;
1476	rctx->nr_cbufs = state->nr_cbufs;
1477	rctx->cb0_is_integer = state->nr_cbufs &&
1478			       util_format_is_pure_integer(state->cbufs[0]->format);
1479
1480	for (i = 0; i < state->nr_cbufs; i++) {
1481		surf = (struct r600_surface*)state->cbufs[i];
1482		res = (struct r600_resource*)surf->base.texture;
1483
1484		if (!surf->color_initialized) {
1485			evergreen_init_color_surface(rctx, surf);
1486		}
1487
1488		if (!surf->export_16bpc) {
1489			rctx->export_16bpc = false;
1490		}
1491
1492		r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C,
1493					   surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1494		r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + i * 0x3C,
1495					surf->cb_color_dim);
1496		r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1497					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1498		r600_pipe_state_add_reg(rstate, R_028C64_CB_COLOR0_PITCH + i * 0x3C,
1499					surf->cb_color_pitch);
1500		r600_pipe_state_add_reg(rstate, R_028C68_CB_COLOR0_SLICE + i * 0x3C,
1501					surf->cb_color_slice);
1502		r600_pipe_state_add_reg(rstate, R_028C6C_CB_COLOR0_VIEW + i * 0x3C,
1503					surf->cb_color_view);
1504		r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C,
1505					   surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
1506	}
1507	/* set CB_COLOR1_INFO for possible dual-src blending */
1508	if (i == 1 && !((struct r600_resource_texture*)res)->is_rat) {
1509		r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1510					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1511		i++;
1512	}
1513	for (; i < 8 ; i++) {
1514		r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1515	}
1516
1517	/* Update alpha-test state dependencies.
1518	 * Alpha-test is done on the first colorbuffer only. */
1519	if (state->nr_cbufs) {
1520		surf = (struct r600_surface*)state->cbufs[0];
1521		if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1522			rctx->alphatest_state.bypass = surf->alphatest_bypass;
1523			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1524		}
1525		if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1526			rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1527			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1528		}
1529	}
1530
1531	if (state->zsbuf) {
1532		surf = (struct r600_surface*)state->zsbuf;
1533		res = (struct r600_resource*)surf->base.texture;
1534
1535		if (!surf->depth_initialized) {
1536			evergreen_init_depth_surface(rctx, surf);
1537		}
1538
1539		r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1540					   res, RADEON_USAGE_READWRITE);
1541		r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1542					   res, RADEON_USAGE_READWRITE);
1543		r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1544
1545		r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1546					   res, RADEON_USAGE_READWRITE);
1547		r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1548					   res, RADEON_USAGE_READWRITE);
1549		r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1550					   res, RADEON_USAGE_READWRITE);
1551
1552		r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1553					   res, RADEON_USAGE_READWRITE);
1554		r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1555		r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
1556	}
1557
1558	evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1559
1560	r600_pipe_state_add_reg(rstate,
1561				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1562	r600_pipe_state_add_reg(rstate,
1563				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1564
1565	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1566	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1567	r600_context_pipe_state_set(rctx, rstate);
1568
1569	if (state->zsbuf) {
1570		evergreen_polygon_offset_update(rctx);
1571	}
1572
1573	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1574		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1575		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1576	}
1577
1578	if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1579		rctx->alphatest_state.bypass = false;
1580		r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1581	}
1582}
1583
1584static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1585{
1586	struct radeon_winsys_cs *cs = rctx->cs;
1587	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1588	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1589	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1590
1591	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1592	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1593	/* Always enable the first colorbuffer in CB_SHADER_MASK. This
1594	 * will assure that the alpha-test will work even if there is
1595	 * no colorbuffer bound. */
1596	r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1597}
1598
1599static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1600{
1601	struct radeon_winsys_cs *cs = rctx->cs;
1602	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1603	unsigned db_render_control = 0;
1604	unsigned db_count_control = 0;
1605	unsigned db_render_override =
1606		S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1607		S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1608		S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1609
1610	if (a->occlusion_query_enabled) {
1611		db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1612		db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1613	}
1614
1615	if (a->flush_depthstencil_through_cb) {
1616		assert(a->copy_depth || a->copy_stencil);
1617
1618		db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1619				     S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1620				     S_028000_COPY_CENTROID(1);
1621	}
1622
1623	r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1624	r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1625	r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1626	r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1627}
1628
1629static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1630					  struct r600_vertexbuf_state *state,
1631					  unsigned resource_offset,
1632					  unsigned pkt_flags)
1633{
1634	struct radeon_winsys_cs *cs = rctx->cs;
1635	uint32_t dirty_mask = state->dirty_mask;
1636
1637	while (dirty_mask) {
1638		struct pipe_vertex_buffer *vb;
1639		struct r600_resource *rbuffer;
1640		uint64_t va;
1641		unsigned buffer_index = u_bit_scan(&dirty_mask);
1642
1643		vb = &state->vb[buffer_index];
1644		rbuffer = (struct r600_resource*)vb->buffer;
1645		assert(rbuffer);
1646
1647		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1648		va += vb->buffer_offset;
1649
1650		/* fetch resources start at index 992 */
1651		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1652		r600_write_value(cs, (resource_offset + buffer_index) * 8);
1653		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1654		r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1655		r600_write_value(cs, /* RESOURCEi_WORD2 */
1656				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1657				 S_030008_STRIDE(vb->stride) |
1658				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1659		r600_write_value(cs, /* RESOURCEi_WORD3 */
1660				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1661				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1662				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1663				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1664		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1665		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1666		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1667		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1668
1669		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1670		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1671	}
1672	state->dirty_mask = 0;
1673}
1674
1675static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1676{
1677	evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1678}
1679
1680static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1681{
1682	evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1683				      RADEON_CP_PACKET3_COMPUTE_MODE);
1684}
1685
1686static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1687					    struct r600_constbuf_state *state,
1688					    unsigned buffer_id_base,
1689					    unsigned reg_alu_constbuf_size,
1690					    unsigned reg_alu_const_cache)
1691{
1692	struct radeon_winsys_cs *cs = rctx->cs;
1693	uint32_t dirty_mask = state->dirty_mask;
1694
1695	while (dirty_mask) {
1696		struct pipe_constant_buffer *cb;
1697		struct r600_resource *rbuffer;
1698		uint64_t va;
1699		unsigned buffer_index = ffs(dirty_mask) - 1;
1700
1701		cb = &state->cb[buffer_index];
1702		rbuffer = (struct r600_resource*)cb->buffer;
1703		assert(rbuffer);
1704
1705		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1706		va += cb->buffer_offset;
1707
1708		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1709				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1710		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1711
1712		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1713		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1714
1715		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1716		r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1717		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1718		r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1719		r600_write_value(cs, /* RESOURCEi_WORD2 */
1720				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1721				 S_030008_STRIDE(16) |
1722				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1723		r600_write_value(cs, /* RESOURCEi_WORD3 */
1724				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1725				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1726				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1727				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1728		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1729		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1730		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1731		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1732
1733		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1734		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1735
1736		dirty_mask &= ~(1 << buffer_index);
1737	}
1738	state->dirty_mask = 0;
1739}
1740
1741static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1742{
1743	evergreen_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 176,
1744					R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1745					R_028980_ALU_CONST_CACHE_VS_0);
1746}
1747
1748static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1749{
1750	evergreen_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1751				       R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1752				       R_028940_ALU_CONST_CACHE_PS_0);
1753}
1754
1755static void evergreen_emit_sampler_views(struct r600_context *rctx,
1756					 struct r600_samplerview_state *state,
1757					 unsigned resource_id_base)
1758{
1759	struct radeon_winsys_cs *cs = rctx->cs;
1760	uint32_t dirty_mask = state->dirty_mask;
1761
1762	while (dirty_mask) {
1763		struct r600_pipe_sampler_view *rview;
1764		unsigned resource_index = u_bit_scan(&dirty_mask);
1765		unsigned reloc;
1766
1767		rview = state->views[resource_index];
1768		assert(rview);
1769
1770		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1771		r600_write_value(cs, (resource_id_base + resource_index) * 8);
1772		r600_write_array(cs, 8, rview->tex_resource_words);
1773
1774		/* XXX The kernel needs two relocations. This is stupid. */
1775		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1776					      RADEON_USAGE_READ);
1777		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1778		r600_write_value(cs, reloc);
1779		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1780		r600_write_value(cs, reloc);
1781	}
1782	state->dirty_mask = 0;
1783}
1784
1785static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1786{
1787	evergreen_emit_sampler_views(rctx, &rctx->vs_samplers.views, 176 + R600_MAX_CONST_BUFFERS);
1788}
1789
1790static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1791{
1792	evergreen_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1793}
1794
1795static void evergreen_emit_sampler(struct r600_context *rctx,
1796				struct r600_textures_info *texinfo,
1797				unsigned resource_id_base,
1798				unsigned border_index_reg)
1799{
1800	struct radeon_winsys_cs *cs = rctx->cs;
1801	unsigned i;
1802
1803	for (i = 0; i < texinfo->n_samplers; i++) {
1804
1805		if (texinfo->samplers[i] == NULL) {
1806			continue;
1807		}
1808		r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1809		r600_write_value(cs, (resource_id_base + i) * 3);
1810		r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1811
1812		if (texinfo->samplers[i]->border_color_use) {
1813			r600_write_config_reg_seq(cs, border_index_reg, 5);
1814			r600_write_value(cs, i);
1815			r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
1816		}
1817	}
1818}
1819
1820static void evergreen_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
1821{
1822	evergreen_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
1823}
1824
1825static void evergreen_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
1826{
1827	evergreen_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
1828}
1829
1830void evergreen_init_state_functions(struct r600_context *rctx)
1831{
1832	r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
1833	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1834	r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 7, 0);
1835	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1836	r600_init_atom(&rctx->vertex_buffer_state.atom, evergreen_fs_emit_vertex_buffers, 0, 0);
1837	r600_init_atom(&rctx->cs_vertex_buffer_state.atom, evergreen_cs_emit_vertex_buffers, 0, 0);
1838	r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
1839	r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
1840	r600_init_atom(&rctx->vs_samplers.views.atom, evergreen_emit_vs_sampler_views, 0, 0);
1841	r600_init_atom(&rctx->ps_samplers.views.atom, evergreen_emit_ps_sampler_views, 0, 0);
1842	r600_init_atom(&rctx->cs_shader_state.atom, evergreen_emit_cs_shader, 0, 0);
1843	r600_init_atom(&rctx->vs_samplers.atom_sampler, evergreen_emit_vs_sampler, 0, 0);
1844	r600_init_atom(&rctx->ps_samplers.atom_sampler, evergreen_emit_ps_sampler, 0, 0);
1845
1846	rctx->context.create_blend_state = evergreen_create_blend_state;
1847	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1848	rctx->context.create_fs_state = r600_create_shader_state_ps;
1849	rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1850	rctx->context.create_sampler_state = evergreen_create_sampler_state;
1851	rctx->context.create_sampler_view = evergreen_create_sampler_view;
1852	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1853	rctx->context.create_vs_state = r600_create_shader_state_vs;
1854	rctx->context.bind_blend_state = r600_bind_blend_state;
1855	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1856	rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1857	rctx->context.bind_fs_state = r600_bind_ps_shader;
1858	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1859	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1860	rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1861	rctx->context.bind_vs_state = r600_bind_vs_shader;
1862	rctx->context.delete_blend_state = r600_delete_state;
1863	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1864	rctx->context.delete_fs_state = r600_delete_ps_shader;
1865	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1866	rctx->context.delete_sampler_state = r600_delete_sampler;
1867	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1868	rctx->context.delete_vs_state = r600_delete_vs_shader;
1869	rctx->context.set_blend_color = r600_set_blend_color;
1870	rctx->context.set_clip_state = evergreen_set_clip_state;
1871	rctx->context.set_constant_buffer = r600_set_constant_buffer;
1872	rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_views;
1873	rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1874	rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1875	rctx->context.set_sample_mask = evergreen_set_sample_mask;
1876	rctx->context.set_scissor_state = evergreen_set_scissor_state;
1877	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1878	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1879	rctx->context.set_index_buffer = r600_set_index_buffer;
1880	rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_views;
1881	rctx->context.set_viewport_state = evergreen_set_viewport_state;
1882	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1883	rctx->context.texture_barrier = r600_texture_barrier;
1884	rctx->context.create_stream_output_target = r600_create_so_target;
1885	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1886	rctx->context.set_stream_output_targets = r600_set_so_targets;
1887	evergreen_init_compute_state_functions(rctx);
1888}
1889
1890static void cayman_init_atom_start_cs(struct r600_context *rctx)
1891{
1892	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1893
1894	r600_init_command_buffer(cb, 256, EMIT_EARLY);
1895
1896	/* This must be first. */
1897	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1898	r600_store_value(cb, 0x80000000);
1899	r600_store_value(cb, 0x80000000);
1900
1901	r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1902	r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1903	/* always set the temp clauses */
1904	r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1905
1906	r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1907	r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1908	r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1909
1910	r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1911
1912	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1913
1914	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1915	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1916	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1917	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1918	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1919	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1920	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1921	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1922	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1923	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1924	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1925	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1926	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1927	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1928
1929	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1930	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1931	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1932
1933	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1934	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1935	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1936
1937	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1938
1939	r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1940
1941	r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1942	r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1943	r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1944
1945	r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1946	r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1947	r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1948
1949	r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1950
1951	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1952	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1953	r600_store_value(cb, 0);
1954	r600_store_value(cb, 0);
1955	r600_store_value(cb, 0);
1956	r600_store_value(cb, 0);
1957	r600_store_value(cb, 0);
1958	r600_store_value(cb, 0);
1959	r600_store_value(cb, 0);
1960	r600_store_value(cb, 0);
1961	r600_store_value(cb, 0);
1962	r600_store_value(cb, 0);
1963	r600_store_value(cb, 0);
1964	r600_store_value(cb, 0);
1965	r600_store_value(cb, 0);
1966	r600_store_value(cb, 0);
1967	r600_store_value(cb, 0);
1968	r600_store_value(cb, 0);
1969	r600_store_value(cb, 0);
1970	r600_store_value(cb, 0);
1971	r600_store_value(cb, 0);
1972	r600_store_value(cb, 0);
1973	r600_store_value(cb, 0);
1974	r600_store_value(cb, 0);
1975	r600_store_value(cb, 0);
1976	r600_store_value(cb, 0);
1977	r600_store_value(cb, 0);
1978	r600_store_value(cb, 0);
1979	r600_store_value(cb, 0);
1980	r600_store_value(cb, 0);
1981	r600_store_value(cb, 0);
1982	r600_store_value(cb, 0);
1983	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1984	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1985	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
1986
1987	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
1988
1989	r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
1990	r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1991	r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1992
1993	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
1994	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
1995	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
1996
1997	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
1998
1999	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2000	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2001	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2002	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2003
2004	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2005	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2006
2007	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2008	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2009	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2010
2011	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2012	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2013	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2014	r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2015
2016	r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2017	r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2018	r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2019
2020	r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2021	r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2022	r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2023	r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2024	r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2025
2026	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2027	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2028	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2029
2030	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2031	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2032	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2033
2034	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2035	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2036	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2037
2038	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2039	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2040	if (rctx->screen->has_streamout) {
2041		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2042	}
2043
2044	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2045	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2046}
2047
2048void evergreen_init_atom_start_cs(struct r600_context *rctx)
2049{
2050	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2051	int ps_prio;
2052	int vs_prio;
2053	int gs_prio;
2054	int es_prio;
2055	int hs_prio, cs_prio, ls_prio;
2056	int num_ps_gprs;
2057	int num_vs_gprs;
2058	int num_gs_gprs;
2059	int num_es_gprs;
2060	int num_hs_gprs;
2061	int num_ls_gprs;
2062	int num_temp_gprs;
2063	int num_ps_threads;
2064	int num_vs_threads;
2065	int num_gs_threads;
2066	int num_es_threads;
2067	int num_hs_threads;
2068	int num_ls_threads;
2069	int num_ps_stack_entries;
2070	int num_vs_stack_entries;
2071	int num_gs_stack_entries;
2072	int num_es_stack_entries;
2073	int num_hs_stack_entries;
2074	int num_ls_stack_entries;
2075	enum radeon_family family;
2076	unsigned tmp;
2077
2078	if (rctx->chip_class == CAYMAN) {
2079		cayman_init_atom_start_cs(rctx);
2080		return;
2081	}
2082
2083	r600_init_command_buffer(cb, 256, EMIT_EARLY);
2084
2085	/* This must be first. */
2086	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2087	r600_store_value(cb, 0x80000000);
2088	r600_store_value(cb, 0x80000000);
2089
2090	family = rctx->family;
2091	ps_prio = 0;
2092	vs_prio = 1;
2093	gs_prio = 2;
2094	es_prio = 3;
2095	hs_prio = 0;
2096	ls_prio = 0;
2097	cs_prio = 0;
2098
2099	switch (family) {
2100	case CHIP_CEDAR:
2101	default:
2102		num_ps_gprs = 93;
2103		num_vs_gprs = 46;
2104		num_temp_gprs = 4;
2105		num_gs_gprs = 31;
2106		num_es_gprs = 31;
2107		num_hs_gprs = 23;
2108		num_ls_gprs = 23;
2109		num_ps_threads = 96;
2110		num_vs_threads = 16;
2111		num_gs_threads = 16;
2112		num_es_threads = 16;
2113		num_hs_threads = 16;
2114		num_ls_threads = 16;
2115		num_ps_stack_entries = 42;
2116		num_vs_stack_entries = 42;
2117		num_gs_stack_entries = 42;
2118		num_es_stack_entries = 42;
2119		num_hs_stack_entries = 42;
2120		num_ls_stack_entries = 42;
2121		break;
2122	case CHIP_REDWOOD:
2123		num_ps_gprs = 93;
2124		num_vs_gprs = 46;
2125		num_temp_gprs = 4;
2126		num_gs_gprs = 31;
2127		num_es_gprs = 31;
2128		num_hs_gprs = 23;
2129		num_ls_gprs = 23;
2130		num_ps_threads = 128;
2131		num_vs_threads = 20;
2132		num_gs_threads = 20;
2133		num_es_threads = 20;
2134		num_hs_threads = 20;
2135		num_ls_threads = 20;
2136		num_ps_stack_entries = 42;
2137		num_vs_stack_entries = 42;
2138		num_gs_stack_entries = 42;
2139		num_es_stack_entries = 42;
2140		num_hs_stack_entries = 42;
2141		num_ls_stack_entries = 42;
2142		break;
2143	case CHIP_JUNIPER:
2144		num_ps_gprs = 93;
2145		num_vs_gprs = 46;
2146		num_temp_gprs = 4;
2147		num_gs_gprs = 31;
2148		num_es_gprs = 31;
2149		num_hs_gprs = 23;
2150		num_ls_gprs = 23;
2151		num_ps_threads = 128;
2152		num_vs_threads = 20;
2153		num_gs_threads = 20;
2154		num_es_threads = 20;
2155		num_hs_threads = 20;
2156		num_ls_threads = 20;
2157		num_ps_stack_entries = 85;
2158		num_vs_stack_entries = 85;
2159		num_gs_stack_entries = 85;
2160		num_es_stack_entries = 85;
2161		num_hs_stack_entries = 85;
2162		num_ls_stack_entries = 85;
2163		break;
2164	case CHIP_CYPRESS:
2165	case CHIP_HEMLOCK:
2166		num_ps_gprs = 93;
2167		num_vs_gprs = 46;
2168		num_temp_gprs = 4;
2169		num_gs_gprs = 31;
2170		num_es_gprs = 31;
2171		num_hs_gprs = 23;
2172		num_ls_gprs = 23;
2173		num_ps_threads = 128;
2174		num_vs_threads = 20;
2175		num_gs_threads = 20;
2176		num_es_threads = 20;
2177		num_hs_threads = 20;
2178		num_ls_threads = 20;
2179		num_ps_stack_entries = 85;
2180		num_vs_stack_entries = 85;
2181		num_gs_stack_entries = 85;
2182		num_es_stack_entries = 85;
2183		num_hs_stack_entries = 85;
2184		num_ls_stack_entries = 85;
2185		break;
2186	case CHIP_PALM:
2187		num_ps_gprs = 93;
2188		num_vs_gprs = 46;
2189		num_temp_gprs = 4;
2190		num_gs_gprs = 31;
2191		num_es_gprs = 31;
2192		num_hs_gprs = 23;
2193		num_ls_gprs = 23;
2194		num_ps_threads = 96;
2195		num_vs_threads = 16;
2196		num_gs_threads = 16;
2197		num_es_threads = 16;
2198		num_hs_threads = 16;
2199		num_ls_threads = 16;
2200		num_ps_stack_entries = 42;
2201		num_vs_stack_entries = 42;
2202		num_gs_stack_entries = 42;
2203		num_es_stack_entries = 42;
2204		num_hs_stack_entries = 42;
2205		num_ls_stack_entries = 42;
2206		break;
2207	case CHIP_SUMO:
2208		num_ps_gprs = 93;
2209		num_vs_gprs = 46;
2210		num_temp_gprs = 4;
2211		num_gs_gprs = 31;
2212		num_es_gprs = 31;
2213		num_hs_gprs = 23;
2214		num_ls_gprs = 23;
2215		num_ps_threads = 96;
2216		num_vs_threads = 25;
2217		num_gs_threads = 25;
2218		num_es_threads = 25;
2219		num_hs_threads = 25;
2220		num_ls_threads = 25;
2221		num_ps_stack_entries = 42;
2222		num_vs_stack_entries = 42;
2223		num_gs_stack_entries = 42;
2224		num_es_stack_entries = 42;
2225		num_hs_stack_entries = 42;
2226		num_ls_stack_entries = 42;
2227		break;
2228	case CHIP_SUMO2:
2229		num_ps_gprs = 93;
2230		num_vs_gprs = 46;
2231		num_temp_gprs = 4;
2232		num_gs_gprs = 31;
2233		num_es_gprs = 31;
2234		num_hs_gprs = 23;
2235		num_ls_gprs = 23;
2236		num_ps_threads = 96;
2237		num_vs_threads = 25;
2238		num_gs_threads = 25;
2239		num_es_threads = 25;
2240		num_hs_threads = 25;
2241		num_ls_threads = 25;
2242		num_ps_stack_entries = 85;
2243		num_vs_stack_entries = 85;
2244		num_gs_stack_entries = 85;
2245		num_es_stack_entries = 85;
2246		num_hs_stack_entries = 85;
2247		num_ls_stack_entries = 85;
2248		break;
2249	case CHIP_BARTS:
2250		num_ps_gprs = 93;
2251		num_vs_gprs = 46;
2252		num_temp_gprs = 4;
2253		num_gs_gprs = 31;
2254		num_es_gprs = 31;
2255		num_hs_gprs = 23;
2256		num_ls_gprs = 23;
2257		num_ps_threads = 128;
2258		num_vs_threads = 20;
2259		num_gs_threads = 20;
2260		num_es_threads = 20;
2261		num_hs_threads = 20;
2262		num_ls_threads = 20;
2263		num_ps_stack_entries = 85;
2264		num_vs_stack_entries = 85;
2265		num_gs_stack_entries = 85;
2266		num_es_stack_entries = 85;
2267		num_hs_stack_entries = 85;
2268		num_ls_stack_entries = 85;
2269		break;
2270	case CHIP_TURKS:
2271		num_ps_gprs = 93;
2272		num_vs_gprs = 46;
2273		num_temp_gprs = 4;
2274		num_gs_gprs = 31;
2275		num_es_gprs = 31;
2276		num_hs_gprs = 23;
2277		num_ls_gprs = 23;
2278		num_ps_threads = 128;
2279		num_vs_threads = 20;
2280		num_gs_threads = 20;
2281		num_es_threads = 20;
2282		num_hs_threads = 20;
2283		num_ls_threads = 20;
2284		num_ps_stack_entries = 42;
2285		num_vs_stack_entries = 42;
2286		num_gs_stack_entries = 42;
2287		num_es_stack_entries = 42;
2288		num_hs_stack_entries = 42;
2289		num_ls_stack_entries = 42;
2290		break;
2291	case CHIP_CAICOS:
2292		num_ps_gprs = 93;
2293		num_vs_gprs = 46;
2294		num_temp_gprs = 4;
2295		num_gs_gprs = 31;
2296		num_es_gprs = 31;
2297		num_hs_gprs = 23;
2298		num_ls_gprs = 23;
2299		num_ps_threads = 128;
2300		num_vs_threads = 10;
2301		num_gs_threads = 10;
2302		num_es_threads = 10;
2303		num_hs_threads = 10;
2304		num_ls_threads = 10;
2305		num_ps_stack_entries = 42;
2306		num_vs_stack_entries = 42;
2307		num_gs_stack_entries = 42;
2308		num_es_stack_entries = 42;
2309		num_hs_stack_entries = 42;
2310		num_ls_stack_entries = 42;
2311		break;
2312	}
2313
2314	tmp = 0;
2315	switch (family) {
2316	case CHIP_CEDAR:
2317	case CHIP_PALM:
2318	case CHIP_SUMO:
2319	case CHIP_SUMO2:
2320	case CHIP_CAICOS:
2321		break;
2322	default:
2323		tmp |= S_008C00_VC_ENABLE(1);
2324		break;
2325	}
2326	tmp |= S_008C00_EXPORT_SRC_C(1);
2327	tmp |= S_008C00_CS_PRIO(cs_prio);
2328	tmp |= S_008C00_LS_PRIO(ls_prio);
2329	tmp |= S_008C00_HS_PRIO(hs_prio);
2330	tmp |= S_008C00_PS_PRIO(ps_prio);
2331	tmp |= S_008C00_VS_PRIO(vs_prio);
2332	tmp |= S_008C00_GS_PRIO(gs_prio);
2333	tmp |= S_008C00_ES_PRIO(es_prio);
2334
2335	/* enable dynamic GPR resource management */
2336	if (rctx->screen->info.drm_minor >= 7) {
2337		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2338		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2339		/* always set temp clauses */
2340		r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2341		r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2342		r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2343		r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2344		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2345		r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2346					S_028838_PS_GPRS(0x1e) |
2347					S_028838_VS_GPRS(0x1e) |
2348					S_028838_GS_GPRS(0x1e) |
2349					S_028838_ES_GPRS(0x1e) |
2350					S_028838_HS_GPRS(0x1e) |
2351					S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2352	} else {
2353		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2354		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2355
2356		tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2357		tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2358		tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2359		r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2360
2361		tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2362		tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2363		r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2364
2365		tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2366		tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2367		r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2368	}
2369
2370	tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2371	tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2372	tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2373	tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2374	r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2375	r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2376
2377	tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2378	tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2379	r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2380
2381	tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2382	tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2383	r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2384
2385	tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2386	tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2387	r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2388
2389	tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2390	tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2391	r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2392
2393	r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2394			      S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2395
2396	r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2397	r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2398
2399	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2400
2401	r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2402	r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2403	r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2404	r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2405	r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2406	r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2407	r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2408
2409	r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2410	r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2411	r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2412	r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2413	r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2414
2415	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2416	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2417	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2418	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2419	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2420	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2421	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2422	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2423	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2424	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2425	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2426	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2427	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2428	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2429
2430	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2431	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2432	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2433
2434	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2435	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2436	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2437
2438	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2439
2440	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2441	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2442	r600_store_value(cb, 0);
2443	r600_store_value(cb, 0);
2444	r600_store_value(cb, 0);
2445	r600_store_value(cb, 0);
2446	r600_store_value(cb, 0);
2447	r600_store_value(cb, 0);
2448	r600_store_value(cb, 0);
2449	r600_store_value(cb, 0);
2450	r600_store_value(cb, 0);
2451	r600_store_value(cb, 0);
2452	r600_store_value(cb, 0);
2453	r600_store_value(cb, 0);
2454	r600_store_value(cb, 0);
2455	r600_store_value(cb, 0);
2456	r600_store_value(cb, 0);
2457	r600_store_value(cb, 0);
2458	r600_store_value(cb, 0);
2459	r600_store_value(cb, 0);
2460	r600_store_value(cb, 0);
2461	r600_store_value(cb, 0);
2462	r600_store_value(cb, 0);
2463	r600_store_value(cb, 0);
2464	r600_store_value(cb, 0);
2465	r600_store_value(cb, 0);
2466	r600_store_value(cb, 0);
2467	r600_store_value(cb, 0);
2468	r600_store_value(cb, 0);
2469	r600_store_value(cb, 0);
2470	r600_store_value(cb, 0);
2471	r600_store_value(cb, 0);
2472	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2473	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2474	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2475
2476	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2477
2478	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2479	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2480	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2481
2482	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2483	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2484	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2485
2486	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2487	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2488	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2489
2490	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2491	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2492	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2493
2494	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2495	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2496	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2497	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2498
2499	r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2500
2501	r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2502	r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2503	r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2504
2505	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2506	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2507	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2508	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2509	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2510	r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2511
2512	r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2513
2514	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2515	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2516	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2517
2518	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2519	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2520	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2521
2522	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2523	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2524	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2525
2526	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2527	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2528	if (rctx->screen->has_streamout) {
2529		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2530	}
2531
2532	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2533	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2534}
2535
2536void evergreen_polygon_offset_update(struct r600_context *rctx)
2537{
2538	struct r600_pipe_state state;
2539
2540	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2541	state.nregs = 0;
2542	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2543		float offset_units = rctx->rasterizer->offset_units;
2544		unsigned offset_db_fmt_cntl = 0, depth;
2545
2546		switch (rctx->framebuffer.zsbuf->format) {
2547		case PIPE_FORMAT_Z24X8_UNORM:
2548		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2549			depth = -24;
2550			offset_units *= 2.0f;
2551			break;
2552		case PIPE_FORMAT_Z32_FLOAT:
2553		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2554			depth = -23;
2555			offset_units *= 1.0f;
2556			offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2557			break;
2558		case PIPE_FORMAT_Z16_UNORM:
2559			depth = -16;
2560			offset_units *= 4.0f;
2561			break;
2562		default:
2563			return;
2564		}
2565		/* XXX some of those reg can be computed with cso */
2566		offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2567		r600_pipe_state_add_reg(&state,
2568				R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2569				fui(rctx->rasterizer->offset_scale));
2570		r600_pipe_state_add_reg(&state,
2571				R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2572				fui(offset_units));
2573		r600_pipe_state_add_reg(&state,
2574				R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2575				fui(rctx->rasterizer->offset_scale));
2576		r600_pipe_state_add_reg(&state,
2577				R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2578				fui(offset_units));
2579		r600_pipe_state_add_reg(&state,
2580				R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2581				offset_db_fmt_cntl);
2582		r600_context_pipe_state_set(rctx, &state);
2583	}
2584}
2585
2586void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2587{
2588	struct r600_context *rctx = (struct r600_context *)ctx;
2589	struct r600_pipe_state *rstate = &shader->rstate;
2590	struct r600_shader *rshader = &shader->shader;
2591	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2592	int pos_index = -1, face_index = -1;
2593	int ninterp = 0;
2594	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2595	unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2596	unsigned z_export = 0, stencil_export = 0;
2597
2598	rstate->nregs = 0;
2599
2600	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2601	for (i = 0; i < rshader->ninput; i++) {
2602		/* evergreen NUM_INTERP only contains values interpolated into the LDS,
2603		   POSITION goes via GPRs from the SC so isn't counted */
2604		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2605			pos_index = i;
2606		else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2607			face_index = i;
2608		else {
2609			ninterp++;
2610			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2611				have_linear = TRUE;
2612			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2613				have_perspective = TRUE;
2614			if (rshader->input[i].centroid)
2615				have_centroid = TRUE;
2616		}
2617
2618		sid = rshader->input[i].spi_sid;
2619
2620		if (sid) {
2621
2622			tmp = S_028644_SEMANTIC(sid);
2623
2624			if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2625				rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2626				(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2627					rctx->rasterizer && rctx->rasterizer->flatshade)) {
2628				tmp |= S_028644_FLAT_SHADE(1);
2629			}
2630
2631			if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2632					(rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2633				tmp |= S_028644_PT_SPRITE_TEX(1);
2634			}
2635
2636			r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2637					tmp);
2638
2639			idx++;
2640		}
2641	}
2642
2643	for (i = 0; i < rshader->noutput; i++) {
2644		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2645			z_export = 1;
2646		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2647			stencil_export = 1;
2648	}
2649	if (rshader->uses_kill)
2650		db_shader_control |= S_02880C_KILL_ENABLE(1);
2651
2652	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2653	db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2654
2655	exports_ps = 0;
2656	for (i = 0; i < rshader->noutput; i++) {
2657		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2658		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2659			exports_ps |= 1;
2660	}
2661
2662	num_cout = rshader->nr_ps_color_exports;
2663
2664	exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2665	if (!exports_ps) {
2666		/* always at least export 1 component per pixel */
2667		exports_ps = 2;
2668	}
2669	shader->nr_ps_color_outputs = num_cout;
2670	if (ninterp == 0) {
2671		ninterp = 1;
2672		have_perspective = TRUE;
2673	}
2674
2675	if (!have_perspective && !have_linear)
2676		have_perspective = TRUE;
2677
2678	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2679		              S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2680		              S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2681	spi_input_z = 0;
2682	if (pos_index != -1) {
2683		spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
2684			S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2685			S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2686		spi_input_z |= 1;
2687	}
2688
2689	spi_ps_in_control_1 = 0;
2690	if (face_index != -1) {
2691		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2692			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2693	}
2694
2695	spi_baryc_cntl = 0;
2696	if (have_perspective)
2697		spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2698				  S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2699	if (have_linear)
2700		spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2701				  S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2702
2703	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2704				spi_ps_in_control_0);
2705	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2706				spi_ps_in_control_1);
2707	r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2708				0);
2709	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2710	r600_pipe_state_add_reg(rstate,
2711				R_0286E0_SPI_BARYC_CNTL,
2712				spi_baryc_cntl);
2713
2714	r600_pipe_state_add_reg_bo(rstate,
2715				R_028840_SQ_PGM_START_PS,
2716				r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2717				shader->bo, RADEON_USAGE_READ);
2718	r600_pipe_state_add_reg(rstate,
2719				R_028844_SQ_PGM_RESOURCES_PS,
2720				S_028844_NUM_GPRS(rshader->bc.ngpr) |
2721				S_028844_PRIME_CACHE_ON_DRAW(1) |
2722				S_028844_STACK_SIZE(rshader->bc.nstack));
2723	r600_pipe_state_add_reg(rstate,
2724				R_02884C_SQ_PGM_EXPORTS_PS,
2725				exports_ps);
2726
2727	shader->db_shader_control = db_shader_control;
2728	shader->ps_depth_export = z_export | stencil_export;
2729
2730	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2731	if (rctx->rasterizer)
2732		shader->flatshade = rctx->rasterizer->flatshade;
2733}
2734
2735void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2736{
2737	struct r600_context *rctx = (struct r600_context *)ctx;
2738	struct r600_pipe_state *rstate = &shader->rstate;
2739	struct r600_shader *rshader = &shader->shader;
2740	unsigned spi_vs_out_id[10] = {};
2741	unsigned i, tmp, nparams = 0;
2742
2743	/* clear previous register */
2744	rstate->nregs = 0;
2745
2746	for (i = 0; i < rshader->noutput; i++) {
2747		if (rshader->output[i].spi_sid) {
2748			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2749			spi_vs_out_id[nparams / 4] |= tmp;
2750			nparams++;
2751		}
2752	}
2753
2754	for (i = 0; i < 10; i++) {
2755		r600_pipe_state_add_reg(rstate,
2756					R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2757					spi_vs_out_id[i]);
2758	}
2759
2760	/* Certain attributes (position, psize, etc.) don't count as params.
2761	 * VS is required to export at least one param and r600_shader_from_tgsi()
2762	 * takes care of adding a dummy export.
2763	 */
2764	if (nparams < 1)
2765		nparams = 1;
2766
2767	r600_pipe_state_add_reg(rstate,
2768			R_0286C4_SPI_VS_OUT_CONFIG,
2769			S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2770	r600_pipe_state_add_reg(rstate,
2771			R_028860_SQ_PGM_RESOURCES_VS,
2772			S_028860_NUM_GPRS(rshader->bc.ngpr) |
2773			S_028860_STACK_SIZE(rshader->bc.nstack));
2774	r600_pipe_state_add_reg_bo(rstate,
2775			R_02885C_SQ_PGM_START_VS,
2776			r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2777			shader->bo, RADEON_USAGE_READ);
2778
2779	shader->pa_cl_vs_out_cntl =
2780		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2781		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2782		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2783		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2784}
2785
2786void evergreen_fetch_shader(struct pipe_context *ctx,
2787			    struct r600_vertex_element *ve)
2788{
2789	struct r600_context *rctx = (struct r600_context *)ctx;
2790	struct r600_pipe_state *rstate = &ve->rstate;
2791	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2792	rstate->nregs = 0;
2793	r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
2794				r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2795				ve->fetch_shader, RADEON_USAGE_READ);
2796}
2797
2798void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2799{
2800	struct pipe_depth_stencil_alpha_state dsa = {{0}};
2801
2802	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2803}
2804
2805void evergreen_update_dual_export_state(struct r600_context * rctx)
2806{
2807	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2808			!rctx->ps_shader->current->ps_depth_export;
2809
2810	unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
2811			V_02880C_EXPORT_DB_FULL;
2812
2813	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2814			S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
2815			S_02880C_DB_SOURCE_FORMAT(db_source_format);
2816
2817	if (db_shader_control != rctx->db_shader_control) {
2818		struct r600_pipe_state rstate;
2819
2820		rctx->db_shader_control = db_shader_control;
2821
2822		rstate.nregs = 0;
2823		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2824		r600_context_pipe_state_set(rctx, &rstate);
2825	}
2826}
2827