evergreen_state.c revision 4b78df9c81f1ca8af2b750616de8ff440e99c3c1 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "evergreend.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31#include "evergreen_compute.h"
32
33static uint32_t eg_num_banks(uint32_t nbanks)
34{
35	switch (nbanks) {
36	case 2:
37		return 0;
38	case 4:
39		return 1;
40	case 8:
41	default:
42		return 2;
43	case 16:
44		return 3;
45	}
46}
47
48
49static unsigned eg_tile_split(unsigned tile_split)
50{
51	switch (tile_split) {
52	case 64:	tile_split = 0;	break;
53	case 128:	tile_split = 1;	break;
54	case 256:	tile_split = 2;	break;
55	case 512:	tile_split = 3;	break;
56	default:
57	case 1024:	tile_split = 4;	break;
58	case 2048:	tile_split = 5;	break;
59	case 4096:	tile_split = 6;	break;
60	}
61	return tile_split;
62}
63
64static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65{
66	switch (macro_tile_aspect) {
67	default:
68	case 1:	macro_tile_aspect = 0;	break;
69	case 2:	macro_tile_aspect = 1;	break;
70	case 4:	macro_tile_aspect = 2;	break;
71	case 8:	macro_tile_aspect = 3;	break;
72	}
73	return macro_tile_aspect;
74}
75
76static unsigned eg_bank_wh(unsigned bankwh)
77{
78	switch (bankwh) {
79	default:
80	case 1:	bankwh = 0;	break;
81	case 2:	bankwh = 1;	break;
82	case 4:	bankwh = 2;	break;
83	case 8:	bankwh = 3;	break;
84	}
85	return bankwh;
86}
87
88static uint32_t r600_translate_blend_function(int blend_func)
89{
90	switch (blend_func) {
91	case PIPE_BLEND_ADD:
92		return V_028780_COMB_DST_PLUS_SRC;
93	case PIPE_BLEND_SUBTRACT:
94		return V_028780_COMB_SRC_MINUS_DST;
95	case PIPE_BLEND_REVERSE_SUBTRACT:
96		return V_028780_COMB_DST_MINUS_SRC;
97	case PIPE_BLEND_MIN:
98		return V_028780_COMB_MIN_DST_SRC;
99	case PIPE_BLEND_MAX:
100		return V_028780_COMB_MAX_DST_SRC;
101	default:
102		R600_ERR("Unknown blend function %d\n", blend_func);
103		assert(0);
104		break;
105	}
106	return 0;
107}
108
109static uint32_t r600_translate_blend_factor(int blend_fact)
110{
111	switch (blend_fact) {
112	case PIPE_BLENDFACTOR_ONE:
113		return V_028780_BLEND_ONE;
114	case PIPE_BLENDFACTOR_SRC_COLOR:
115		return V_028780_BLEND_SRC_COLOR;
116	case PIPE_BLENDFACTOR_SRC_ALPHA:
117		return V_028780_BLEND_SRC_ALPHA;
118	case PIPE_BLENDFACTOR_DST_ALPHA:
119		return V_028780_BLEND_DST_ALPHA;
120	case PIPE_BLENDFACTOR_DST_COLOR:
121		return V_028780_BLEND_DST_COLOR;
122	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123		return V_028780_BLEND_SRC_ALPHA_SATURATE;
124	case PIPE_BLENDFACTOR_CONST_COLOR:
125		return V_028780_BLEND_CONST_COLOR;
126	case PIPE_BLENDFACTOR_CONST_ALPHA:
127		return V_028780_BLEND_CONST_ALPHA;
128	case PIPE_BLENDFACTOR_ZERO:
129		return V_028780_BLEND_ZERO;
130	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131		return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133		return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135		return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136	case PIPE_BLENDFACTOR_INV_DST_COLOR:
137		return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139		return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141		return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142	case PIPE_BLENDFACTOR_SRC1_COLOR:
143		return V_028780_BLEND_SRC1_COLOR;
144	case PIPE_BLENDFACTOR_SRC1_ALPHA:
145		return V_028780_BLEND_SRC1_ALPHA;
146	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147		return V_028780_BLEND_INV_SRC1_COLOR;
148	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149		return V_028780_BLEND_INV_SRC1_ALPHA;
150	default:
151		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152		assert(0);
153		break;
154	}
155	return 0;
156}
157
158static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
159{
160	switch (dim) {
161	default:
162	case PIPE_TEXTURE_1D:
163		return V_030000_SQ_TEX_DIM_1D;
164	case PIPE_TEXTURE_1D_ARRAY:
165		return V_030000_SQ_TEX_DIM_1D_ARRAY;
166	case PIPE_TEXTURE_2D:
167	case PIPE_TEXTURE_RECT:
168		return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
169					V_030000_SQ_TEX_DIM_2D;
170	case PIPE_TEXTURE_2D_ARRAY:
171		return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
172					V_030000_SQ_TEX_DIM_2D_ARRAY;
173	case PIPE_TEXTURE_3D:
174		return V_030000_SQ_TEX_DIM_3D;
175	case PIPE_TEXTURE_CUBE:
176		return V_030000_SQ_TEX_DIM_CUBEMAP;
177	}
178}
179
180static uint32_t r600_translate_dbformat(enum pipe_format format)
181{
182	switch (format) {
183	case PIPE_FORMAT_Z16_UNORM:
184		return V_028040_Z_16;
185	case PIPE_FORMAT_Z24X8_UNORM:
186	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
187		return V_028040_Z_24;
188	case PIPE_FORMAT_Z32_FLOAT:
189	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
190		return V_028040_Z_32_FLOAT;
191	default:
192		return ~0U;
193	}
194}
195
196static uint32_t r600_translate_colorswap(enum pipe_format format)
197{
198	switch (format) {
199	/* 8-bit buffers. */
200	case PIPE_FORMAT_L4A4_UNORM:
201	case PIPE_FORMAT_A4R4_UNORM:
202		return V_028C70_SWAP_ALT;
203
204	case PIPE_FORMAT_A8_UNORM:
205	case PIPE_FORMAT_A8_SNORM:
206	case PIPE_FORMAT_A8_UINT:
207	case PIPE_FORMAT_A8_SINT:
208	case PIPE_FORMAT_A16_UNORM:
209	case PIPE_FORMAT_A16_SNORM:
210	case PIPE_FORMAT_A16_UINT:
211	case PIPE_FORMAT_A16_SINT:
212	case PIPE_FORMAT_A16_FLOAT:
213	case PIPE_FORMAT_A32_UINT:
214	case PIPE_FORMAT_A32_SINT:
215	case PIPE_FORMAT_A32_FLOAT:
216	case PIPE_FORMAT_R4A4_UNORM:
217		return V_028C70_SWAP_ALT_REV;
218	case PIPE_FORMAT_I8_UNORM:
219	case PIPE_FORMAT_I8_SNORM:
220	case PIPE_FORMAT_I8_UINT:
221	case PIPE_FORMAT_I8_SINT:
222	case PIPE_FORMAT_I16_UNORM:
223	case PIPE_FORMAT_I16_SNORM:
224	case PIPE_FORMAT_I16_UINT:
225	case PIPE_FORMAT_I16_SINT:
226	case PIPE_FORMAT_I16_FLOAT:
227	case PIPE_FORMAT_I32_UINT:
228	case PIPE_FORMAT_I32_SINT:
229	case PIPE_FORMAT_I32_FLOAT:
230	case PIPE_FORMAT_L8_UNORM:
231	case PIPE_FORMAT_L8_SNORM:
232	case PIPE_FORMAT_L8_UINT:
233	case PIPE_FORMAT_L8_SINT:
234	case PIPE_FORMAT_L8_SRGB:
235	case PIPE_FORMAT_L16_UNORM:
236	case PIPE_FORMAT_L16_SNORM:
237	case PIPE_FORMAT_L16_UINT:
238	case PIPE_FORMAT_L16_SINT:
239	case PIPE_FORMAT_L16_FLOAT:
240	case PIPE_FORMAT_L32_UINT:
241	case PIPE_FORMAT_L32_SINT:
242	case PIPE_FORMAT_L32_FLOAT:
243	case PIPE_FORMAT_R8_UNORM:
244	case PIPE_FORMAT_R8_SNORM:
245	case PIPE_FORMAT_R8_UINT:
246	case PIPE_FORMAT_R8_SINT:
247		return V_028C70_SWAP_STD;
248
249	/* 16-bit buffers. */
250	case PIPE_FORMAT_B5G6R5_UNORM:
251		return V_028C70_SWAP_STD_REV;
252
253	case PIPE_FORMAT_B5G5R5A1_UNORM:
254	case PIPE_FORMAT_B5G5R5X1_UNORM:
255		return V_028C70_SWAP_ALT;
256
257	case PIPE_FORMAT_B4G4R4A4_UNORM:
258	case PIPE_FORMAT_B4G4R4X4_UNORM:
259		return V_028C70_SWAP_ALT;
260
261	case PIPE_FORMAT_Z16_UNORM:
262		return V_028C70_SWAP_STD;
263
264	case PIPE_FORMAT_L8A8_UNORM:
265	case PIPE_FORMAT_L8A8_SNORM:
266	case PIPE_FORMAT_L8A8_UINT:
267	case PIPE_FORMAT_L8A8_SINT:
268	case PIPE_FORMAT_L8A8_SRGB:
269	case PIPE_FORMAT_L16A16_UNORM:
270	case PIPE_FORMAT_L16A16_SNORM:
271	case PIPE_FORMAT_L16A16_UINT:
272	case PIPE_FORMAT_L16A16_SINT:
273	case PIPE_FORMAT_L16A16_FLOAT:
274	case PIPE_FORMAT_L32A32_UINT:
275	case PIPE_FORMAT_L32A32_SINT:
276	case PIPE_FORMAT_L32A32_FLOAT:
277		return V_028C70_SWAP_ALT;
278	case PIPE_FORMAT_R8G8_UNORM:
279	case PIPE_FORMAT_R8G8_SNORM:
280	case PIPE_FORMAT_R8G8_UINT:
281	case PIPE_FORMAT_R8G8_SINT:
282		return V_028C70_SWAP_STD;
283
284	case PIPE_FORMAT_R16_UNORM:
285	case PIPE_FORMAT_R16_SNORM:
286	case PIPE_FORMAT_R16_UINT:
287	case PIPE_FORMAT_R16_SINT:
288	case PIPE_FORMAT_R16_FLOAT:
289		return V_028C70_SWAP_STD;
290
291	/* 32-bit buffers. */
292	case PIPE_FORMAT_A8B8G8R8_SRGB:
293		return V_028C70_SWAP_STD_REV;
294	case PIPE_FORMAT_B8G8R8A8_SRGB:
295		return V_028C70_SWAP_ALT;
296
297	case PIPE_FORMAT_B8G8R8A8_UNORM:
298	case PIPE_FORMAT_B8G8R8X8_UNORM:
299		return V_028C70_SWAP_ALT;
300
301	case PIPE_FORMAT_A8R8G8B8_UNORM:
302	case PIPE_FORMAT_X8R8G8B8_UNORM:
303		return V_028C70_SWAP_ALT_REV;
304	case PIPE_FORMAT_R8G8B8A8_SNORM:
305	case PIPE_FORMAT_R8G8B8A8_UNORM:
306	case PIPE_FORMAT_R8G8B8A8_SINT:
307	case PIPE_FORMAT_R8G8B8A8_UINT:
308	case PIPE_FORMAT_R8G8B8X8_UNORM:
309		return V_028C70_SWAP_STD;
310
311	case PIPE_FORMAT_A8B8G8R8_UNORM:
312	case PIPE_FORMAT_X8B8G8R8_UNORM:
313	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314		return V_028C70_SWAP_STD_REV;
315
316	case PIPE_FORMAT_Z24X8_UNORM:
317	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318		return V_028C70_SWAP_STD;
319
320	case PIPE_FORMAT_X8Z24_UNORM:
321	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
322		return V_028C70_SWAP_STD;
323
324	case PIPE_FORMAT_R10G10B10A2_UNORM:
325	case PIPE_FORMAT_R10G10B10X2_SNORM:
326	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
327		return V_028C70_SWAP_STD;
328
329	case PIPE_FORMAT_B10G10R10A2_UNORM:
330	case PIPE_FORMAT_B10G10R10A2_UINT:
331		return V_028C70_SWAP_ALT;
332
333	case PIPE_FORMAT_R11G11B10_FLOAT:
334	case PIPE_FORMAT_R32_FLOAT:
335	case PIPE_FORMAT_R32_UINT:
336	case PIPE_FORMAT_R32_SINT:
337	case PIPE_FORMAT_Z32_FLOAT:
338	case PIPE_FORMAT_R16G16_FLOAT:
339	case PIPE_FORMAT_R16G16_UNORM:
340	case PIPE_FORMAT_R16G16_SNORM:
341	case PIPE_FORMAT_R16G16_UINT:
342	case PIPE_FORMAT_R16G16_SINT:
343		return V_028C70_SWAP_STD;
344
345	/* 64-bit buffers. */
346	case PIPE_FORMAT_R32G32_FLOAT:
347	case PIPE_FORMAT_R32G32_UINT:
348	case PIPE_FORMAT_R32G32_SINT:
349	case PIPE_FORMAT_R16G16B16A16_UNORM:
350	case PIPE_FORMAT_R16G16B16A16_SNORM:
351	case PIPE_FORMAT_R16G16B16A16_UINT:
352	case PIPE_FORMAT_R16G16B16A16_SINT:
353	case PIPE_FORMAT_R16G16B16A16_FLOAT:
354	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356	/* 128-bit buffers. */
357	case PIPE_FORMAT_R32G32B32A32_FLOAT:
358	case PIPE_FORMAT_R32G32B32A32_SNORM:
359	case PIPE_FORMAT_R32G32B32A32_UNORM:
360	case PIPE_FORMAT_R32G32B32A32_SINT:
361	case PIPE_FORMAT_R32G32B32A32_UINT:
362		return V_028C70_SWAP_STD;
363	default:
364		R600_ERR("unsupported colorswap format %d\n", format);
365		return ~0U;
366	}
367	return ~0U;
368}
369
370static uint32_t r600_translate_colorformat(enum pipe_format format)
371{
372	switch (format) {
373	/* 8-bit buffers. */
374	case PIPE_FORMAT_A8_UNORM:
375	case PIPE_FORMAT_A8_SNORM:
376	case PIPE_FORMAT_A8_UINT:
377	case PIPE_FORMAT_A8_SINT:
378	case PIPE_FORMAT_I8_UNORM:
379	case PIPE_FORMAT_I8_SNORM:
380	case PIPE_FORMAT_I8_UINT:
381	case PIPE_FORMAT_I8_SINT:
382	case PIPE_FORMAT_L8_UNORM:
383	case PIPE_FORMAT_L8_SNORM:
384	case PIPE_FORMAT_L8_UINT:
385	case PIPE_FORMAT_L8_SINT:
386	case PIPE_FORMAT_L8_SRGB:
387	case PIPE_FORMAT_R8_UNORM:
388	case PIPE_FORMAT_R8_SNORM:
389	case PIPE_FORMAT_R8_UINT:
390	case PIPE_FORMAT_R8_SINT:
391		return V_028C70_COLOR_8;
392
393	/* 16-bit buffers. */
394	case PIPE_FORMAT_B5G6R5_UNORM:
395		return V_028C70_COLOR_5_6_5;
396
397	case PIPE_FORMAT_B5G5R5A1_UNORM:
398	case PIPE_FORMAT_B5G5R5X1_UNORM:
399		return V_028C70_COLOR_1_5_5_5;
400
401	case PIPE_FORMAT_B4G4R4A4_UNORM:
402	case PIPE_FORMAT_B4G4R4X4_UNORM:
403		return V_028C70_COLOR_4_4_4_4;
404
405	case PIPE_FORMAT_Z16_UNORM:
406		return V_028C70_COLOR_16;
407
408	case PIPE_FORMAT_L8A8_UNORM:
409	case PIPE_FORMAT_L8A8_SNORM:
410	case PIPE_FORMAT_L8A8_UINT:
411	case PIPE_FORMAT_L8A8_SINT:
412	case PIPE_FORMAT_L8A8_SRGB:
413	case PIPE_FORMAT_R8G8_UNORM:
414	case PIPE_FORMAT_R8G8_SNORM:
415	case PIPE_FORMAT_R8G8_UINT:
416	case PIPE_FORMAT_R8G8_SINT:
417		return V_028C70_COLOR_8_8;
418
419	case PIPE_FORMAT_R16_UNORM:
420	case PIPE_FORMAT_R16_SNORM:
421	case PIPE_FORMAT_R16_UINT:
422	case PIPE_FORMAT_R16_SINT:
423	case PIPE_FORMAT_A16_UNORM:
424	case PIPE_FORMAT_A16_SNORM:
425	case PIPE_FORMAT_A16_UINT:
426	case PIPE_FORMAT_A16_SINT:
427	case PIPE_FORMAT_L16_UNORM:
428	case PIPE_FORMAT_L16_SNORM:
429	case PIPE_FORMAT_L16_UINT:
430	case PIPE_FORMAT_L16_SINT:
431	case PIPE_FORMAT_I16_UNORM:
432	case PIPE_FORMAT_I16_SNORM:
433	case PIPE_FORMAT_I16_UINT:
434	case PIPE_FORMAT_I16_SINT:
435		return V_028C70_COLOR_16;
436
437	case PIPE_FORMAT_R16_FLOAT:
438	case PIPE_FORMAT_A16_FLOAT:
439	case PIPE_FORMAT_L16_FLOAT:
440	case PIPE_FORMAT_I16_FLOAT:
441		return V_028C70_COLOR_16_FLOAT;
442
443	/* 32-bit buffers. */
444	case PIPE_FORMAT_A8B8G8R8_SRGB:
445	case PIPE_FORMAT_A8B8G8R8_UNORM:
446	case PIPE_FORMAT_A8R8G8B8_UNORM:
447	case PIPE_FORMAT_B8G8R8A8_SRGB:
448	case PIPE_FORMAT_B8G8R8A8_UNORM:
449	case PIPE_FORMAT_B8G8R8X8_UNORM:
450	case PIPE_FORMAT_R8G8B8A8_SNORM:
451	case PIPE_FORMAT_R8G8B8A8_UNORM:
452	case PIPE_FORMAT_R8G8B8X8_UNORM:
453	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454	case PIPE_FORMAT_X8B8G8R8_UNORM:
455	case PIPE_FORMAT_X8R8G8B8_UNORM:
456	case PIPE_FORMAT_R8G8B8_UNORM:
457	case PIPE_FORMAT_R8G8B8A8_SINT:
458	case PIPE_FORMAT_R8G8B8A8_UINT:
459		return V_028C70_COLOR_8_8_8_8;
460
461	case PIPE_FORMAT_R10G10B10A2_UNORM:
462	case PIPE_FORMAT_R10G10B10X2_SNORM:
463	case PIPE_FORMAT_B10G10R10A2_UNORM:
464	case PIPE_FORMAT_B10G10R10A2_UINT:
465	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466		return V_028C70_COLOR_2_10_10_10;
467
468	case PIPE_FORMAT_Z24X8_UNORM:
469	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470		return V_028C70_COLOR_8_24;
471
472	case PIPE_FORMAT_X8Z24_UNORM:
473	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474		return V_028C70_COLOR_24_8;
475
476	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477		return V_028C70_COLOR_X24_8_32_FLOAT;
478
479	case PIPE_FORMAT_R32_UINT:
480	case PIPE_FORMAT_R32_SINT:
481	case PIPE_FORMAT_A32_UINT:
482	case PIPE_FORMAT_A32_SINT:
483	case PIPE_FORMAT_L32_UINT:
484	case PIPE_FORMAT_L32_SINT:
485	case PIPE_FORMAT_I32_UINT:
486	case PIPE_FORMAT_I32_SINT:
487		return V_028C70_COLOR_32;
488
489	case PIPE_FORMAT_R32_FLOAT:
490	case PIPE_FORMAT_A32_FLOAT:
491	case PIPE_FORMAT_L32_FLOAT:
492	case PIPE_FORMAT_I32_FLOAT:
493	case PIPE_FORMAT_Z32_FLOAT:
494		return V_028C70_COLOR_32_FLOAT;
495
496	case PIPE_FORMAT_R16G16_FLOAT:
497	case PIPE_FORMAT_L16A16_FLOAT:
498		return V_028C70_COLOR_16_16_FLOAT;
499
500	case PIPE_FORMAT_R16G16_UNORM:
501	case PIPE_FORMAT_R16G16_SNORM:
502	case PIPE_FORMAT_R16G16_UINT:
503	case PIPE_FORMAT_R16G16_SINT:
504	case PIPE_FORMAT_L16A16_UNORM:
505	case PIPE_FORMAT_L16A16_SNORM:
506	case PIPE_FORMAT_L16A16_UINT:
507	case PIPE_FORMAT_L16A16_SINT:
508		return V_028C70_COLOR_16_16;
509
510	case PIPE_FORMAT_R11G11B10_FLOAT:
511		return V_028C70_COLOR_10_11_11_FLOAT;
512
513	/* 64-bit buffers. */
514	case PIPE_FORMAT_R16G16B16A16_UINT:
515	case PIPE_FORMAT_R16G16B16A16_SINT:
516	case PIPE_FORMAT_R16G16B16A16_UNORM:
517	case PIPE_FORMAT_R16G16B16A16_SNORM:
518		return V_028C70_COLOR_16_16_16_16;
519
520	case PIPE_FORMAT_R16G16B16A16_FLOAT:
521		return V_028C70_COLOR_16_16_16_16_FLOAT;
522
523	case PIPE_FORMAT_R32G32_FLOAT:
524	case PIPE_FORMAT_L32A32_FLOAT:
525		return V_028C70_COLOR_32_32_FLOAT;
526
527	case PIPE_FORMAT_R32G32_SINT:
528	case PIPE_FORMAT_R32G32_UINT:
529	case PIPE_FORMAT_L32A32_UINT:
530	case PIPE_FORMAT_L32A32_SINT:
531		return V_028C70_COLOR_32_32;
532
533	/* 128-bit buffers. */
534	case PIPE_FORMAT_R32G32B32A32_SNORM:
535	case PIPE_FORMAT_R32G32B32A32_UNORM:
536	case PIPE_FORMAT_R32G32B32A32_SINT:
537	case PIPE_FORMAT_R32G32B32A32_UINT:
538		return V_028C70_COLOR_32_32_32_32;
539	case PIPE_FORMAT_R32G32B32A32_FLOAT:
540		return V_028C70_COLOR_32_32_32_32_FLOAT;
541
542	/* YUV buffers. */
543	case PIPE_FORMAT_UYVY:
544	case PIPE_FORMAT_YUYV:
545	default:
546		return ~0U; /* Unsupported. */
547	}
548}
549
550static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
551{
552	if (R600_BIG_ENDIAN) {
553		switch(colorformat) {
554
555		/* 8-bit buffers. */
556		case V_028C70_COLOR_8:
557			return ENDIAN_NONE;
558
559		/* 16-bit buffers. */
560		case V_028C70_COLOR_5_6_5:
561		case V_028C70_COLOR_1_5_5_5:
562		case V_028C70_COLOR_4_4_4_4:
563		case V_028C70_COLOR_16:
564		case V_028C70_COLOR_8_8:
565			return ENDIAN_8IN16;
566
567		/* 32-bit buffers. */
568		case V_028C70_COLOR_8_8_8_8:
569		case V_028C70_COLOR_2_10_10_10:
570		case V_028C70_COLOR_8_24:
571		case V_028C70_COLOR_24_8:
572		case V_028C70_COLOR_32_FLOAT:
573		case V_028C70_COLOR_16_16_FLOAT:
574		case V_028C70_COLOR_16_16:
575			return ENDIAN_8IN32;
576
577		/* 64-bit buffers. */
578		case V_028C70_COLOR_16_16_16_16:
579		case V_028C70_COLOR_16_16_16_16_FLOAT:
580			return ENDIAN_8IN16;
581
582		case V_028C70_COLOR_32_32_FLOAT:
583		case V_028C70_COLOR_32_32:
584		case V_028C70_COLOR_X24_8_32_FLOAT:
585			return ENDIAN_8IN32;
586
587		/* 96-bit buffers. */
588		case V_028C70_COLOR_32_32_32_FLOAT:
589		/* 128-bit buffers. */
590		case V_028C70_COLOR_32_32_32_32_FLOAT:
591		case V_028C70_COLOR_32_32_32_32:
592			return ENDIAN_8IN32;
593		default:
594			return ENDIAN_NONE; /* Unsupported. */
595		}
596	} else {
597		return ENDIAN_NONE;
598	}
599}
600
601static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
602{
603	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
604}
605
606static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
607{
608	return r600_translate_colorformat(format) != ~0U &&
609		r600_translate_colorswap(format) != ~0U;
610}
611
612static bool r600_is_zs_format_supported(enum pipe_format format)
613{
614	return r600_translate_dbformat(format) != ~0U;
615}
616
617boolean evergreen_is_format_supported(struct pipe_screen *screen,
618				      enum pipe_format format,
619				      enum pipe_texture_target target,
620				      unsigned sample_count,
621				      unsigned usage)
622{
623	unsigned retval = 0;
624
625	if (target >= PIPE_MAX_TEXTURE_TYPES) {
626		R600_ERR("r600: unsupported texture type %d\n", target);
627		return FALSE;
628	}
629
630	if (!util_format_is_supported(format, usage))
631		return FALSE;
632
633	/* Multisample */
634	if (sample_count > 1)
635		return FALSE;
636
637	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
638	    r600_is_sampler_format_supported(screen, format)) {
639		retval |= PIPE_BIND_SAMPLER_VIEW;
640	}
641
642	if ((usage & (PIPE_BIND_RENDER_TARGET |
643		      PIPE_BIND_DISPLAY_TARGET |
644		      PIPE_BIND_SCANOUT |
645		      PIPE_BIND_SHARED)) &&
646	    r600_is_colorbuffer_format_supported(format)) {
647		retval |= usage &
648			  (PIPE_BIND_RENDER_TARGET |
649			   PIPE_BIND_DISPLAY_TARGET |
650			   PIPE_BIND_SCANOUT |
651			   PIPE_BIND_SHARED);
652	}
653
654	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
655	    r600_is_zs_format_supported(format)) {
656		retval |= PIPE_BIND_DEPTH_STENCIL;
657	}
658
659	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
660	    r600_is_vertex_format_supported(format)) {
661		retval |= PIPE_BIND_VERTEX_BUFFER;
662	}
663
664	if (usage & PIPE_BIND_TRANSFER_READ)
665		retval |= PIPE_BIND_TRANSFER_READ;
666	if (usage & PIPE_BIND_TRANSFER_WRITE)
667		retval |= PIPE_BIND_TRANSFER_WRITE;
668
669	return retval == usage;
670}
671
672static void *evergreen_create_blend_state(struct pipe_context *ctx,
673					const struct pipe_blend_state *state)
674{
675	struct r600_context *rctx = (struct r600_context *)ctx;
676	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
677	struct r600_pipe_state *rstate;
678	uint32_t color_control = 0, target_mask;
679	/* XXX there is more then 8 framebuffer */
680	unsigned blend_cntl[8];
681
682	if (blend == NULL) {
683		return NULL;
684	}
685
686	rstate = &blend->rstate;
687
688	rstate->id = R600_PIPE_STATE_BLEND;
689
690	target_mask = 0;
691	if (state->logicop_enable) {
692		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
693	} else {
694		color_control |= (0xcc << 16);
695	}
696	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
697	if (state->independent_blend_enable) {
698		for (int i = 0; i < 8; i++) {
699			target_mask |= (state->rt[i].colormask << (4 * i));
700		}
701	} else {
702		for (int i = 0; i < 8; i++) {
703			target_mask |= (state->rt[0].colormask << (4 * i));
704		}
705	}
706	blend->cb_target_mask = target_mask;
707
708	if (target_mask)
709		color_control |= S_028808_MODE(V_028808_CB_NORMAL);
710	else
711		color_control |= S_028808_MODE(V_028808_CB_DISABLE);
712
713	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
714				color_control);
715	/* only have dual source on MRT0 */
716	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
717	for (int i = 0; i < 8; i++) {
718		/* state->rt entries > 0 only written if independent blending */
719		const int j = state->independent_blend_enable ? i : 0;
720
721		unsigned eqRGB = state->rt[j].rgb_func;
722		unsigned srcRGB = state->rt[j].rgb_src_factor;
723		unsigned dstRGB = state->rt[j].rgb_dst_factor;
724		unsigned eqA = state->rt[j].alpha_func;
725		unsigned srcA = state->rt[j].alpha_src_factor;
726		unsigned dstA = state->rt[j].alpha_dst_factor;
727
728		blend_cntl[i] = 0;
729		if (!state->rt[j].blend_enable)
730			continue;
731
732		blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
733		blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
734		blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
735		blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
736
737		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
738			blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
739			blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
740			blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
741			blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
742		}
743	}
744	for (int i = 0; i < 8; i++) {
745		r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
746	}
747
748	r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
749				S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
750				S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
751				S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
752				S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
753				S_028B70_ALPHA_TO_MASK_OFFSET3(2));
754
755	blend->alpha_to_one = state->alpha_to_one;
756	return rstate;
757}
758
759static void *evergreen_create_dsa_state(struct pipe_context *ctx,
760				   const struct pipe_depth_stencil_alpha_state *state)
761{
762	struct r600_context *rctx = (struct r600_context *)ctx;
763	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
764	unsigned db_depth_control, alpha_test_control, alpha_ref;
765	struct r600_pipe_state *rstate;
766
767	if (dsa == NULL) {
768		return NULL;
769	}
770
771	dsa->valuemask[0] = state->stencil[0].valuemask;
772	dsa->valuemask[1] = state->stencil[1].valuemask;
773	dsa->writemask[0] = state->stencil[0].writemask;
774	dsa->writemask[1] = state->stencil[1].writemask;
775
776	rstate = &dsa->rstate;
777
778	rstate->id = R600_PIPE_STATE_DSA;
779	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
780		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
781		S_028800_ZFUNC(state->depth.func);
782
783	/* stencil */
784	if (state->stencil[0].enabled) {
785		db_depth_control |= S_028800_STENCIL_ENABLE(1);
786		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
787		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
788		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
789		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
790
791		if (state->stencil[1].enabled) {
792			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
793			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
794			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
795			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
796			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
797		}
798	}
799
800	/* alpha */
801	alpha_test_control = 0;
802	alpha_ref = 0;
803	if (state->alpha.enabled) {
804		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
805		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
806		alpha_ref = fui(state->alpha.ref_value);
807	}
808	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
809	dsa->alpha_ref = alpha_ref;
810
811	/* misc */
812	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
813	return rstate;
814}
815
816static void *evergreen_create_rs_state(struct pipe_context *ctx,
817					const struct pipe_rasterizer_state *state)
818{
819	struct r600_context *rctx = (struct r600_context *)ctx;
820	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
821	struct r600_pipe_state *rstate;
822	unsigned tmp;
823	unsigned prov_vtx = 1, polygon_dual_mode;
824	float psize_min, psize_max;
825
826	if (rs == NULL) {
827		return NULL;
828	}
829
830	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
831				state->fill_back != PIPE_POLYGON_MODE_FILL);
832
833	if (state->flatshade_first)
834		prov_vtx = 0;
835
836	rstate = &rs->rstate;
837	rs->flatshade = state->flatshade;
838	rs->sprite_coord_enable = state->sprite_coord_enable;
839	rs->two_side = state->light_twoside;
840	rs->clip_plane_enable = state->clip_plane_enable;
841	rs->pa_sc_line_stipple = state->line_stipple_enable ?
842				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
843				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
844	rs->pa_cl_clip_cntl =
845		S_028810_PS_UCP_MODE(3) |
846		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
847		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
848		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
849	rs->multisample_enable = state->multisample;
850
851	/* offset */
852	rs->offset_units = state->offset_units;
853	rs->offset_scale = state->offset_scale * 12.0f;
854
855	rstate->id = R600_PIPE_STATE_RASTERIZER;
856	tmp = S_0286D4_FLAT_SHADE_ENA(1);
857	if (state->sprite_coord_enable) {
858		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
859			S_0286D4_PNT_SPRITE_OVRD_X(2) |
860			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
861			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
862			S_0286D4_PNT_SPRITE_OVRD_W(1);
863		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
864			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
865		}
866	}
867	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
868
869	/* point size 12.4 fixed point */
870	tmp = (unsigned)(state->point_size * 8.0);
871	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
872
873	if (state->point_size_per_vertex) {
874		psize_min = util_get_min_point_size(state);
875		psize_max = 8192;
876	} else {
877		/* Force the point size to be as if the vertex output was disabled. */
878		psize_min = state->point_size;
879		psize_max = state->point_size;
880	}
881	/* Divide by two, because 0.5 = 1 pixel. */
882	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
883				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
884				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
885
886	tmp = (unsigned)state->line_width * 8;
887	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
888	r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
889				S_028A48_MSAA_ENABLE(state->multisample) |
890				S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
891				S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
892
893	if (rctx->chip_class == CAYMAN) {
894		r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
895					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
896	} else {
897		r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
898					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
899	}
900	r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
901	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
902				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
903				S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
904				S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
905				S_028814_FACE(!state->front_ccw) |
906				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
907				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
908				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
909				S_028814_POLY_MODE(polygon_dual_mode) |
910				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
911				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
912	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
913	return rstate;
914}
915
916static void *evergreen_create_sampler_state(struct pipe_context *ctx,
917					const struct pipe_sampler_state *state)
918{
919	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
920	union util_color uc;
921	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
922
923	if (ss == NULL) {
924		return NULL;
925	}
926
927	/* directly into sampler avoid r6xx code to emit useless reg */
928	ss->seamless_cube_map = false;
929	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
930	ss->border_color_use = false;
931	/* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
932	ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
933				S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
934				S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
935				S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
936				S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
937				S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
938				S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
939				S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
940				S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
941	/* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
942	ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
943				S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
944	/* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
945	ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
946				(state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
947				S_03C008_TYPE(1);
948	if (uc.ui) {
949		ss->border_color_use = true;
950		/* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
951		ss->border_color[0] = fui(state->border_color.f[0]);
952		/* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
953		ss->border_color[1] = fui(state->border_color.f[1]);
954		/* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
955		ss->border_color[2] = fui(state->border_color.f[2]);
956		/* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
957		ss->border_color[3] = fui(state->border_color.f[3]);
958	}
959	return ss;
960}
961
962static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
963							struct pipe_resource *texture,
964							const struct pipe_sampler_view *state)
965{
966	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
967	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
968	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
969	unsigned format, endian;
970	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
971	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
972	unsigned height, depth, width;
973	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
974
975	if (view == NULL)
976		return NULL;
977
978	/* initialize base object */
979	view->base = *state;
980	view->base.texture = NULL;
981	pipe_reference(NULL, &texture->reference);
982	view->base.texture = texture;
983	view->base.reference.count = 1;
984	view->base.context = ctx;
985
986	swizzle[0] = state->swizzle_r;
987	swizzle[1] = state->swizzle_g;
988	swizzle[2] = state->swizzle_b;
989	swizzle[3] = state->swizzle_a;
990
991	format = r600_translate_texformat(ctx->screen, state->format,
992					  swizzle,
993					  &word4, &yuv_format);
994	assert(format != ~0);
995	if (format == ~0) {
996		FREE(view);
997		return NULL;
998	}
999
1000	if (tmp->is_depth && !tmp->is_flushing_texture) {
1001		if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1002			FREE(view);
1003			return NULL;
1004		}
1005		tmp = tmp->flushed_depth_texture;
1006	}
1007
1008	endian = r600_colorformat_endian_swap(format);
1009
1010	width = tmp->surface.level[0].npix_x;
1011	height = tmp->surface.level[0].npix_y;
1012	depth = tmp->surface.level[0].npix_z;
1013	pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1014	tile_type = tmp->tile_type;
1015
1016	switch (tmp->surface.level[0].mode) {
1017	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1018		array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1019		break;
1020	case RADEON_SURF_MODE_2D:
1021		array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1022		break;
1023	case RADEON_SURF_MODE_1D:
1024		array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1025		break;
1026	case RADEON_SURF_MODE_LINEAR:
1027	default:
1028		array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1029		break;
1030	}
1031	tile_split = tmp->surface.tile_split;
1032	macro_aspect = tmp->surface.mtilea;
1033	bankw = tmp->surface.bankw;
1034	bankh = tmp->surface.bankh;
1035	tile_split = eg_tile_split(tile_split);
1036	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1037	bankw = eg_bank_wh(bankw);
1038	bankh = eg_bank_wh(bankh);
1039
1040	/* 128 bit formats require tile type = 1 */
1041	if (rscreen->chip_class == CAYMAN) {
1042		if (util_format_get_blocksize(state->format) >= 16)
1043			tile_type = 1;
1044	}
1045	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1046
1047	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1048	        height = 1;
1049		depth = texture->array_size;
1050	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1051		depth = texture->array_size;
1052	}
1053
1054	view->tex_resource = &tmp->resource;
1055	view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1056				       S_030000_PITCH((pitch / 8) - 1) |
1057				       S_030000_TEX_WIDTH(width - 1));
1058	if (rscreen->chip_class == CAYMAN)
1059		view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1060	else
1061		view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1062	view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1063				       S_030004_TEX_DEPTH(depth - 1) |
1064				       S_030004_ARRAY_MODE(array_mode));
1065	view->tex_resource_words[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1066	if (state->u.tex.last_level && texture->nr_samples <= 1) {
1067		view->tex_resource_words[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1068	} else {
1069		view->tex_resource_words[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1070	}
1071	view->tex_resource_words[4] = (word4 |
1072				       S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1073				       S_030010_ENDIAN_SWAP(endian));
1074	view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1075				      S_030014_LAST_ARRAY(state->u.tex.last_layer);
1076	if (texture->nr_samples > 1) {
1077		/* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1078		view->tex_resource_words[5] |= S_030014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1079	} else {
1080		view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1081		view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1082	}
1083	/* aniso max 16 samples */
1084	view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1085				      (S_030018_TILE_SPLIT(tile_split));
1086	view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1087				      S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1088				      S_03001C_BANK_WIDTH(bankw) |
1089				      S_03001C_BANK_HEIGHT(bankh) |
1090				      S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1091				      S_03001C_NUM_BANKS(nbanks);
1092	return &view->base;
1093}
1094
1095static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1096					   struct pipe_sampler_view **views)
1097{
1098	struct r600_context *rctx = (struct r600_context *)ctx;
1099	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
1100}
1101
1102static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1103					   struct pipe_sampler_view **views)
1104{
1105	struct r600_context *rctx = (struct r600_context *)ctx;
1106	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
1107}
1108
1109static void evergreen_set_clip_state(struct pipe_context *ctx,
1110				const struct pipe_clip_state *state)
1111{
1112	struct r600_context *rctx = (struct r600_context *)ctx;
1113	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1114	struct pipe_constant_buffer cb;
1115
1116	if (rstate == NULL)
1117		return;
1118
1119	rctx->clip = *state;
1120	rstate->id = R600_PIPE_STATE_CLIP;
1121	for (int i = 0; i < 6; i++) {
1122		r600_pipe_state_add_reg(rstate,
1123					R_0285BC_PA_CL_UCP0_X + i * 16,
1124					fui(state->ucp[i][0]));
1125		r600_pipe_state_add_reg(rstate,
1126					R_0285C0_PA_CL_UCP0_Y + i * 16,
1127					fui(state->ucp[i][1]) );
1128		r600_pipe_state_add_reg(rstate,
1129					R_0285C4_PA_CL_UCP0_Z + i * 16,
1130					fui(state->ucp[i][2]));
1131		r600_pipe_state_add_reg(rstate,
1132					R_0285C8_PA_CL_UCP0_W + i * 16,
1133					fui(state->ucp[i][3]));
1134	}
1135
1136	free(rctx->states[R600_PIPE_STATE_CLIP]);
1137	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1138	r600_context_pipe_state_set(rctx, rstate);
1139
1140	cb.buffer = NULL;
1141	cb.user_buffer = state->ucp;
1142	cb.buffer_offset = 0;
1143	cb.buffer_size = 4*4*8;
1144	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1145	pipe_resource_reference(&cb.buffer, NULL);
1146}
1147
1148static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1149					 const struct pipe_poly_stipple *state)
1150{
1151}
1152
1153static void evergreen_get_scissor_rect(struct r600_context *rctx,
1154				       unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1155				       uint32_t *tl, uint32_t *br)
1156{
1157	/* EG hw workaround */
1158	if (br_x == 0)
1159		tl_x = 1;
1160	if (br_y == 0)
1161		tl_y = 1;
1162
1163	/* cayman hw workaround */
1164	if (rctx->chip_class == CAYMAN) {
1165		if (br_x == 1 && br_y == 1)
1166			br_x = 2;
1167	}
1168
1169	*tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1170	*br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1171}
1172
1173static void evergreen_set_scissor_state(struct pipe_context *ctx,
1174					const struct pipe_scissor_state *state)
1175{
1176	struct r600_context *rctx = (struct r600_context *)ctx;
1177	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1178	uint32_t tl, br;
1179
1180	if (rstate == NULL)
1181		return;
1182
1183	evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1184
1185	rstate->id = R600_PIPE_STATE_SCISSOR;
1186	r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1187	r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1188
1189	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1190	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1191	r600_context_pipe_state_set(rctx, rstate);
1192}
1193
1194static void evergreen_set_viewport_state(struct pipe_context *ctx,
1195					const struct pipe_viewport_state *state)
1196{
1197	struct r600_context *rctx = (struct r600_context *)ctx;
1198	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1199
1200	if (rstate == NULL)
1201		return;
1202
1203	rctx->viewport = *state;
1204	rstate->id = R600_PIPE_STATE_VIEWPORT;
1205	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1206	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1207	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1208	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1209	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1210	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1211
1212	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1213	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1214	r600_context_pipe_state_set(rctx, rstate);
1215}
1216
1217void evergreen_init_color_surface(struct r600_context *rctx,
1218				  struct r600_surface *surf)
1219{
1220	struct r600_screen *rscreen = rctx->screen;
1221	struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1222	struct pipe_resource *pipe_tex = surf->base.texture;
1223	unsigned level = surf->base.u.tex.level;
1224	unsigned pitch, slice;
1225	unsigned color_info, color_attrib, color_dim = 0;
1226	unsigned format, swap, ntype, endian;
1227	uint64_t offset;
1228	unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1229	const struct util_format_description *desc;
1230	int i;
1231	bool blend_clamp = 0, blend_bypass = 0;
1232
1233	if (rtex->is_depth && !rtex->is_flushing_texture) {
1234		r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1235		rtex = rtex->flushed_depth_texture;
1236		assert(rtex);
1237	}
1238
1239	offset = rtex->surface.level[level].offset;
1240	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1241		offset += rtex->surface.level[level].slice_size *
1242			  surf->base.u.tex.first_layer;
1243	}
1244	pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1245	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1246	if (slice) {
1247		slice = slice - 1;
1248	}
1249	color_info = 0;
1250	switch (rtex->surface.level[level].mode) {
1251	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1252		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1253		tile_type = 1;
1254		break;
1255	case RADEON_SURF_MODE_1D:
1256		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1257		tile_type = rtex->tile_type;
1258		break;
1259	case RADEON_SURF_MODE_2D:
1260		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1261		tile_type = rtex->tile_type;
1262		break;
1263	case RADEON_SURF_MODE_LINEAR:
1264	default:
1265		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1266		tile_type = 1;
1267		break;
1268	}
1269	tile_split = rtex->surface.tile_split;
1270	macro_aspect = rtex->surface.mtilea;
1271	bankw = rtex->surface.bankw;
1272	bankh = rtex->surface.bankh;
1273	tile_split = eg_tile_split(tile_split);
1274	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1275	bankw = eg_bank_wh(bankw);
1276	bankh = eg_bank_wh(bankh);
1277
1278	/* 128 bit formats require tile type = 1 */
1279	if (rscreen->chip_class == CAYMAN) {
1280		if (util_format_get_blocksize(surf->base.format) >= 16)
1281			tile_type = 1;
1282	}
1283	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1284	desc = util_format_description(surf->base.format);
1285	for (i = 0; i < 4; i++) {
1286		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1287			break;
1288		}
1289	}
1290
1291	color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1292			S_028C74_NUM_BANKS(nbanks) |
1293			S_028C74_BANK_WIDTH(bankw) |
1294			S_028C74_BANK_HEIGHT(bankh) |
1295			S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1296			S_028C74_NON_DISP_TILING_ORDER(tile_type);
1297
1298	ntype = V_028C70_NUMBER_UNORM;
1299	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1300		ntype = V_028C70_NUMBER_SRGB;
1301	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1302		if (desc->channel[i].normalized)
1303			ntype = V_028C70_NUMBER_SNORM;
1304		else if (desc->channel[i].pure_integer)
1305			ntype = V_028C70_NUMBER_SINT;
1306	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1307		if (desc->channel[i].normalized)
1308			ntype = V_028C70_NUMBER_UNORM;
1309		else if (desc->channel[i].pure_integer)
1310			ntype = V_028C70_NUMBER_UINT;
1311	}
1312
1313	format = r600_translate_colorformat(surf->base.format);
1314	assert(format != ~0);
1315
1316	swap = r600_translate_colorswap(surf->base.format);
1317	assert(swap != ~0);
1318
1319	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1320		endian = ENDIAN_NONE;
1321	} else {
1322		endian = r600_colorformat_endian_swap(format);
1323	}
1324
1325	/* blend clamp should be set for all NORM/SRGB types */
1326	if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1327	    ntype == V_028C70_NUMBER_SRGB)
1328		blend_clamp = 1;
1329
1330	/* set blend bypass according to docs if SINT/UINT or
1331	   8/24 COLOR variants */
1332	if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1333	    format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1334	    format == V_028C70_COLOR_X24_8_32_FLOAT) {
1335		blend_clamp = 0;
1336		blend_bypass = 1;
1337	}
1338
1339	surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1340
1341	color_info |= S_028C70_FORMAT(format) |
1342		S_028C70_COMP_SWAP(swap) |
1343		S_028C70_BLEND_CLAMP(blend_clamp) |
1344		S_028C70_BLEND_BYPASS(blend_bypass) |
1345		S_028C70_NUMBER_TYPE(ntype) |
1346		S_028C70_ENDIAN(endian);
1347
1348	if (rtex->is_rat) {
1349		color_info |= S_028C70_RAT(1);
1350		color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1351				| S_028C78_HEIGHT_MAX(pipe_tex->height0);
1352	}
1353
1354	/* EXPORT_NORM is an optimzation that can be enabled for better
1355	 * performance in certain cases.
1356	 * EXPORT_NORM can be enabled if:
1357	 * - 11-bit or smaller UNORM/SNORM/SRGB
1358	 * - 16-bit or smaller FLOAT
1359	 */
1360	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1361	    ((desc->channel[i].size < 12 &&
1362	      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1363	      ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1364	     (desc->channel[i].size < 17 &&
1365	      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1366		color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1367		surf->export_16bpc = true;
1368	}
1369
1370	offset += r600_resource_va(rctx->context.screen, pipe_tex);
1371	offset >>= 8;
1372
1373	/* XXX handle enabling of CB beyond BASE8 which has different offset */
1374	surf->cb_color_base = offset;
1375	surf->cb_color_dim = color_dim;
1376	surf->cb_color_info = color_info;
1377	surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1378	surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1379	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1380		surf->cb_color_view = 0;
1381	} else {
1382		surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1383				      S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1384	}
1385	surf->cb_color_attrib = color_attrib;
1386
1387	surf->color_initialized = true;
1388}
1389
1390static void evergreen_init_depth_surface(struct r600_context *rctx,
1391					 struct r600_surface *surf)
1392{
1393	struct r600_screen *rscreen = rctx->screen;
1394	struct pipe_screen *screen = &rscreen->screen;
1395	struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1396	uint64_t offset;
1397	unsigned level, pitch, slice, format, array_mode;
1398	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1399
1400	level = surf->base.u.tex.level;
1401	format = r600_translate_dbformat(surf->base.format);
1402	assert(format != ~0);
1403
1404	offset = r600_resource_va(screen, surf->base.texture);
1405	offset += rtex->surface.level[level].offset;
1406	pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1407	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1408	if (slice) {
1409		slice = slice - 1;
1410	}
1411	switch (rtex->surface.level[level].mode) {
1412	case RADEON_SURF_MODE_2D:
1413		array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1414		break;
1415	case RADEON_SURF_MODE_1D:
1416	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1417	case RADEON_SURF_MODE_LINEAR:
1418	default:
1419		array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1420		break;
1421	}
1422	tile_split = rtex->surface.tile_split;
1423	macro_aspect = rtex->surface.mtilea;
1424	bankw = rtex->surface.bankw;
1425	bankh = rtex->surface.bankh;
1426	tile_split = eg_tile_split(tile_split);
1427	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1428	bankw = eg_bank_wh(bankw);
1429	bankh = eg_bank_wh(bankh);
1430	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1431	offset >>= 8;
1432
1433	surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1434			      S_028040_FORMAT(format) |
1435			      S_028040_TILE_SPLIT(tile_split)|
1436			      S_028040_NUM_BANKS(nbanks) |
1437			      S_028040_BANK_WIDTH(bankw) |
1438			      S_028040_BANK_HEIGHT(bankh) |
1439			      S_028040_MACRO_TILE_ASPECT(macro_aspect);
1440	surf->db_depth_base = offset;
1441	surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1442			      S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1443	surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1444	surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1445
1446	if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1447		uint64_t stencil_offset = rtex->surface.stencil_offset;
1448		unsigned stile_split = rtex->surface.stencil_tile_split;
1449
1450		stile_split = eg_tile_split(stile_split);
1451		stencil_offset += r600_resource_va(screen, surf->base.texture);
1452		stencil_offset += rtex->surface.level[level].offset / 4;
1453		stencil_offset >>= 8;
1454
1455		surf->db_stencil_base = stencil_offset;
1456		surf->db_stencil_info = 1 | S_028044_TILE_SPLIT(stile_split);
1457	} else {
1458		surf->db_stencil_base = offset;
1459		surf->db_stencil_info = 1;
1460	}
1461
1462	surf->depth_initialized = true;
1463}
1464
1465#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
1466	(((s0x) & 0xf) | (((s0y) & 0xf) << 4) |		   \
1467	(((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |	   \
1468	(((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |	   \
1469	 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1470
1471static uint32_t evergreen_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1472{
1473	/* 2xMSAA
1474	 * There are two locations (-4, 4), (4, -4). */
1475	static uint32_t sample_locs_2x[] = {
1476		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1477		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1478		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1479		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1480	};
1481	static unsigned max_dist_2x = 4;
1482	/* 4xMSAA
1483	 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1484	static uint32_t sample_locs_4x[] = {
1485		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1486		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1487		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1488		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1489	};
1490	static unsigned max_dist_4x = 6;
1491	/* 8xMSAA */
1492	static uint32_t eg_sample_locs_8x[] = {
1493		FILL_SREG(-2, -5, 4, -4,  1, 6, -6, -2),
1494		FILL_SREG( 6,  1, 0,  0, -5, 4,  7, -8),
1495		FILL_SREG(-2, -5, 4, -4,  1, 6, -6, -2),
1496		FILL_SREG( 6,  1, 0,  0, -5, 4,  7, -8),
1497		FILL_SREG(-2, -5, 4, -4,  1, 6, -6, -2),
1498		FILL_SREG( 6,  1, 0,  0, -5, 4,  7, -8),
1499		FILL_SREG(-2, -5, 4, -4,  1, 6, -6, -2),
1500		FILL_SREG( 6,  1, 0,  0, -5, 4,  7, -8),
1501	};
1502	static uint32_t cm_sample_locs_8x[] = {
1503		FILL_SREG(-2, -5, 4, -4,  1, 6, -6, -2),
1504		FILL_SREG(-2, -5, 4, -4,  1, 6, -6, -2),
1505		FILL_SREG(-2, -5, 4, -4,  1, 6, -6, -2),
1506		FILL_SREG(-2, -5, 4, -4,  1, 6, -6, -2),
1507		FILL_SREG( 6,  1, 0,  0, -5, 4,  7, -8),
1508		FILL_SREG( 6,  1, 0,  0, -5, 4,  7, -8),
1509		FILL_SREG( 6,  1, 0,  0, -5, 4,  7, -8),
1510		FILL_SREG( 6,  1, 0,  0, -5, 4,  7, -8),
1511	};
1512	static unsigned max_dist_8x = 8;
1513	/* 16xMSAA */
1514	static uint32_t cm_sample_locs_16x[] = {
1515		FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1516		FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1517		FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1518		FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1519		FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1520		FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1521		FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1522		FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1523		FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1524		FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1525		FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1526		FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1527		FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1528		FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1529		FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1530		FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1531	};
1532	static unsigned max_dist_16x = 8;
1533	struct r600_context *rctx = (struct r600_context *)ctx;
1534	uint32_t max_dist, num_regs, *sample_locs, i;
1535
1536	switch (nsample) {
1537	case 2:
1538		sample_locs = sample_locs_2x;
1539		num_regs = Elements(sample_locs_2x);
1540		max_dist = max_dist_2x;
1541		break;
1542	case 4:
1543		sample_locs = sample_locs_4x;
1544		num_regs = Elements(sample_locs_4x);
1545		max_dist = max_dist_4x;
1546		break;
1547	case 8:
1548		if (rctx->chip_class == CAYMAN) {
1549			sample_locs = cm_sample_locs_8x;
1550			num_regs = Elements(cm_sample_locs_8x);
1551		} else {
1552			sample_locs = eg_sample_locs_8x;
1553			num_regs = Elements(eg_sample_locs_8x);
1554		}
1555		max_dist = max_dist_8x;
1556		break;
1557	case 16:
1558		if (rctx->chip_class == CAYMAN) {
1559			sample_locs = cm_sample_locs_16x;
1560			num_regs = Elements(cm_sample_locs_16x);
1561			max_dist = max_dist_16x;
1562			break;
1563		}
1564		/* fall through */
1565	default:
1566		R600_ERR("Invalid nr_samples %i\n", nsample);
1567		return 0;
1568	}
1569
1570	/* All the regs must be initialized. Otherwise weird rendering may occur. */
1571	if (rctx->chip_class == CAYMAN) {
1572		r600_pipe_state_add_reg(rstate, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs[0]);
1573		r600_pipe_state_add_reg(rstate, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs[1]);
1574		r600_pipe_state_add_reg(rstate, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs[2]);
1575		r600_pipe_state_add_reg(rstate, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs[3]);
1576		if (num_regs <= 8) {
1577			r600_pipe_state_add_reg(rstate, CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs[4]);
1578			r600_pipe_state_add_reg(rstate, CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs[5]);
1579			r600_pipe_state_add_reg(rstate, CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs[6]);
1580			r600_pipe_state_add_reg(rstate, CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs[7]);
1581		}
1582		if (num_regs <= 16) {
1583			r600_pipe_state_add_reg(rstate, CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, sample_locs[8]);
1584			r600_pipe_state_add_reg(rstate, CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, sample_locs[9]);
1585			r600_pipe_state_add_reg(rstate, CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, sample_locs[10]);
1586			r600_pipe_state_add_reg(rstate, CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, sample_locs[11]);
1587			r600_pipe_state_add_reg(rstate, CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, sample_locs[12]);
1588			r600_pipe_state_add_reg(rstate, CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, sample_locs[13]);
1589			r600_pipe_state_add_reg(rstate, CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, sample_locs[14]);
1590			r600_pipe_state_add_reg(rstate, CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, sample_locs[15]);
1591		}
1592	} else {
1593		for (i = 0; i < num_regs; i++) {
1594			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1595						sample_locs[i]);
1596		}
1597	}
1598	return max_dist;
1599}
1600
1601static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1602					    const struct pipe_framebuffer_state *state)
1603{
1604	struct r600_context *rctx = (struct r600_context *)ctx;
1605	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1606	struct r600_surface *surf;
1607	struct r600_resource *res;
1608	uint32_t tl, br, i, nr_samples;
1609
1610	if (rstate == NULL)
1611		return;
1612
1613	r600_flush_framebuffer(rctx, false);
1614
1615	/* unreference old buffer and reference new one */
1616	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1617
1618	util_copy_framebuffer_state(&rctx->framebuffer, state);
1619
1620	/* Colorbuffers. */
1621	rctx->export_16bpc = true;
1622	rctx->nr_cbufs = state->nr_cbufs;
1623	rctx->cb0_is_integer = state->nr_cbufs &&
1624			       util_format_is_pure_integer(state->cbufs[0]->format);
1625
1626	for (i = 0; i < state->nr_cbufs; i++) {
1627		surf = (struct r600_surface*)state->cbufs[i];
1628		res = (struct r600_resource*)surf->base.texture;
1629
1630		if (!surf->color_initialized) {
1631			evergreen_init_color_surface(rctx, surf);
1632		}
1633
1634		if (!surf->export_16bpc) {
1635			rctx->export_16bpc = false;
1636		}
1637
1638		r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C,
1639					   surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1640		r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + i * 0x3C,
1641					surf->cb_color_dim);
1642		r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1643					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1644		r600_pipe_state_add_reg(rstate, R_028C64_CB_COLOR0_PITCH + i * 0x3C,
1645					surf->cb_color_pitch);
1646		r600_pipe_state_add_reg(rstate, R_028C68_CB_COLOR0_SLICE + i * 0x3C,
1647					surf->cb_color_slice);
1648		r600_pipe_state_add_reg(rstate, R_028C6C_CB_COLOR0_VIEW + i * 0x3C,
1649					surf->cb_color_view);
1650		r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C,
1651					   surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
1652	}
1653	/* set CB_COLOR1_INFO for possible dual-src blending */
1654	if (i == 1 && !((struct r600_resource_texture*)res)->is_rat) {
1655		r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1656					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1657		i++;
1658	}
1659	for (; i < 8 ; i++) {
1660		r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1661	}
1662
1663	/* Update alpha-test state dependencies.
1664	 * Alpha-test is done on the first colorbuffer only. */
1665	if (state->nr_cbufs) {
1666		surf = (struct r600_surface*)state->cbufs[0];
1667		if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1668			rctx->alphatest_state.bypass = surf->alphatest_bypass;
1669			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1670		}
1671		if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1672			rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1673			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1674		}
1675	}
1676
1677	/* ZS buffer. */
1678	if (state->zsbuf) {
1679		surf = (struct r600_surface*)state->zsbuf;
1680		res = (struct r600_resource*)surf->base.texture;
1681
1682		if (!surf->depth_initialized) {
1683			evergreen_init_depth_surface(rctx, surf);
1684		}
1685
1686		r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1687					   res, RADEON_USAGE_READWRITE);
1688		r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1689					   res, RADEON_USAGE_READWRITE);
1690		r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1691
1692		r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1693					   res, RADEON_USAGE_READWRITE);
1694		r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1695					   res, RADEON_USAGE_READWRITE);
1696		r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1697					   res, RADEON_USAGE_READWRITE);
1698
1699		r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1700					   res, RADEON_USAGE_READWRITE);
1701		r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1702		r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
1703	}
1704
1705	/* Framebuffer dimensions. */
1706	evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1707
1708	r600_pipe_state_add_reg(rstate,
1709				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1710	r600_pipe_state_add_reg(rstate,
1711				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1712
1713	/* Multisampling */
1714	if (state->nr_cbufs)
1715		nr_samples = state->cbufs[0]->texture->nr_samples;
1716	else if (state->zsbuf)
1717		nr_samples = state->zsbuf->texture->nr_samples;
1718	else
1719		nr_samples = 0;
1720
1721	if (nr_samples > 1) {
1722		unsigned log_samples = util_logbase2(nr_samples);
1723		unsigned max_dist, line_cntl, aa_config;
1724
1725		max_dist = evergreen_set_ms_pos(ctx, rstate, nr_samples);
1726
1727		line_cntl = S_028C00_LAST_PIXEL(1) |
1728			    S_028C00_EXPAND_LINE_WIDTH(1);
1729		aa_config = S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1730			    S_028C04_MAX_SAMPLE_DIST(max_dist);
1731
1732		if (rctx->chip_class == CAYMAN) {
1733			r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, line_cntl);
1734			r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG, aa_config);
1735		} else {
1736			r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, line_cntl);
1737			r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, aa_config);
1738		}
1739	} else {
1740		if (rctx->chip_class == CAYMAN) {
1741			r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1742			r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG, 0);
1743		} else {
1744			r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1745			r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1746		}
1747	}
1748
1749	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1750	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1751	r600_context_pipe_state_set(rctx, rstate);
1752
1753	if (state->zsbuf) {
1754		evergreen_polygon_offset_update(rctx);
1755	}
1756
1757	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1758		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1759		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1760	}
1761
1762	if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1763		rctx->alphatest_state.bypass = false;
1764		r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1765	}
1766}
1767
1768static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1769{
1770	struct radeon_winsys_cs *cs = rctx->cs;
1771	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1772	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1773	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1774
1775	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1776	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1777	/* Always enable the first colorbuffer in CB_SHADER_MASK. This
1778	 * will assure that the alpha-test will work even if there is
1779	 * no colorbuffer bound. */
1780	r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1781}
1782
1783static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1784{
1785	struct radeon_winsys_cs *cs = rctx->cs;
1786	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1787	unsigned db_render_control = 0;
1788	unsigned db_count_control = 0;
1789	unsigned db_render_override =
1790		S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1791		S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1792		S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1793
1794	if (a->occlusion_query_enabled) {
1795		db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1796		db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1797	}
1798
1799	if (a->flush_depthstencil_through_cb) {
1800		assert(a->copy_depth || a->copy_stencil);
1801
1802		db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1803				     S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1804				     S_028000_COPY_CENTROID(1);
1805	}
1806
1807	r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1808	r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1809	r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1810	r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1811}
1812
1813static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1814					  struct r600_vertexbuf_state *state,
1815					  unsigned resource_offset,
1816					  unsigned pkt_flags)
1817{
1818	struct radeon_winsys_cs *cs = rctx->cs;
1819	uint32_t dirty_mask = state->dirty_mask;
1820
1821	while (dirty_mask) {
1822		struct pipe_vertex_buffer *vb;
1823		struct r600_resource *rbuffer;
1824		uint64_t va;
1825		unsigned buffer_index = u_bit_scan(&dirty_mask);
1826
1827		vb = &state->vb[buffer_index];
1828		rbuffer = (struct r600_resource*)vb->buffer;
1829		assert(rbuffer);
1830
1831		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1832		va += vb->buffer_offset;
1833
1834		/* fetch resources start at index 992 */
1835		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1836		r600_write_value(cs, (resource_offset + buffer_index) * 8);
1837		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1838		r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1839		r600_write_value(cs, /* RESOURCEi_WORD2 */
1840				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1841				 S_030008_STRIDE(vb->stride) |
1842				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1843		r600_write_value(cs, /* RESOURCEi_WORD3 */
1844				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1845				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1846				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1847				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1848		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1849		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1850		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1851		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1852
1853		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1854		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1855	}
1856	state->dirty_mask = 0;
1857}
1858
1859static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1860{
1861	evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1862}
1863
1864static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1865{
1866	evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1867				      RADEON_CP_PACKET3_COMPUTE_MODE);
1868}
1869
1870static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1871					    struct r600_constbuf_state *state,
1872					    unsigned buffer_id_base,
1873					    unsigned reg_alu_constbuf_size,
1874					    unsigned reg_alu_const_cache)
1875{
1876	struct radeon_winsys_cs *cs = rctx->cs;
1877	uint32_t dirty_mask = state->dirty_mask;
1878
1879	while (dirty_mask) {
1880		struct pipe_constant_buffer *cb;
1881		struct r600_resource *rbuffer;
1882		uint64_t va;
1883		unsigned buffer_index = ffs(dirty_mask) - 1;
1884
1885		cb = &state->cb[buffer_index];
1886		rbuffer = (struct r600_resource*)cb->buffer;
1887		assert(rbuffer);
1888
1889		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1890		va += cb->buffer_offset;
1891
1892		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1893				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1894		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1895
1896		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1897		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1898
1899		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1900		r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1901		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1902		r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1903		r600_write_value(cs, /* RESOURCEi_WORD2 */
1904				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1905				 S_030008_STRIDE(16) |
1906				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1907		r600_write_value(cs, /* RESOURCEi_WORD3 */
1908				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1909				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1910				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1911				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1912		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1913		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1914		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1915		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1916
1917		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1918		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1919
1920		dirty_mask &= ~(1 << buffer_index);
1921	}
1922	state->dirty_mask = 0;
1923}
1924
1925static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1926{
1927	evergreen_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 176,
1928					R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1929					R_028980_ALU_CONST_CACHE_VS_0);
1930}
1931
1932static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1933{
1934	evergreen_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1935				       R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1936				       R_028940_ALU_CONST_CACHE_PS_0);
1937}
1938
1939static void evergreen_emit_sampler_views(struct r600_context *rctx,
1940					 struct r600_samplerview_state *state,
1941					 unsigned resource_id_base)
1942{
1943	struct radeon_winsys_cs *cs = rctx->cs;
1944	uint32_t dirty_mask = state->dirty_mask;
1945
1946	while (dirty_mask) {
1947		struct r600_pipe_sampler_view *rview;
1948		unsigned resource_index = u_bit_scan(&dirty_mask);
1949		unsigned reloc;
1950
1951		rview = state->views[resource_index];
1952		assert(rview);
1953
1954		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1955		r600_write_value(cs, (resource_id_base + resource_index) * 8);
1956		r600_write_array(cs, 8, rview->tex_resource_words);
1957
1958		/* XXX The kernel needs two relocations. This is stupid. */
1959		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1960					      RADEON_USAGE_READ);
1961		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1962		r600_write_value(cs, reloc);
1963		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1964		r600_write_value(cs, reloc);
1965	}
1966	state->dirty_mask = 0;
1967}
1968
1969static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1970{
1971	evergreen_emit_sampler_views(rctx, &rctx->vs_samplers.views, 176 + R600_MAX_CONST_BUFFERS);
1972}
1973
1974static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1975{
1976	evergreen_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1977}
1978
1979static void evergreen_emit_sampler(struct r600_context *rctx,
1980				struct r600_textures_info *texinfo,
1981				unsigned resource_id_base,
1982				unsigned border_index_reg)
1983{
1984	struct radeon_winsys_cs *cs = rctx->cs;
1985	unsigned i;
1986
1987	for (i = 0; i < texinfo->n_samplers; i++) {
1988
1989		if (texinfo->samplers[i] == NULL) {
1990			continue;
1991		}
1992		r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1993		r600_write_value(cs, (resource_id_base + i) * 3);
1994		r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1995
1996		if (texinfo->samplers[i]->border_color_use) {
1997			r600_write_config_reg_seq(cs, border_index_reg, 5);
1998			r600_write_value(cs, i);
1999			r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
2000		}
2001	}
2002}
2003
2004static void evergreen_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
2005{
2006	evergreen_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2007}
2008
2009static void evergreen_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
2010{
2011	evergreen_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2012}
2013
2014static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2015{
2016	struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2017	uint8_t mask = s->sample_mask;
2018
2019	r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2020			       mask | (mask << 8) | (mask << 16) | (mask << 24));
2021}
2022
2023static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2024{
2025	struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2026	struct radeon_winsys_cs *cs = rctx->cs;
2027	uint16_t mask = s->sample_mask;
2028
2029	r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2030	r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2031	r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2032}
2033
2034void evergreen_init_state_functions(struct r600_context *rctx)
2035{
2036	r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
2037	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2038	r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 7, 0);
2039	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
2040	r600_init_atom(&rctx->vertex_buffer_state.atom, evergreen_fs_emit_vertex_buffers, 0, 0);
2041	r600_init_atom(&rctx->cs_vertex_buffer_state.atom, evergreen_cs_emit_vertex_buffers, 0, 0);
2042	r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
2043	r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
2044	r600_init_atom(&rctx->vs_samplers.views.atom, evergreen_emit_vs_sampler_views, 0, 0);
2045	r600_init_atom(&rctx->ps_samplers.views.atom, evergreen_emit_ps_sampler_views, 0, 0);
2046	r600_init_atom(&rctx->cs_shader_state.atom, evergreen_emit_cs_shader, 0, 0);
2047	r600_init_atom(&rctx->vs_samplers.atom_sampler, evergreen_emit_vs_sampler, 0, 0);
2048	r600_init_atom(&rctx->ps_samplers.atom_sampler, evergreen_emit_ps_sampler, 0, 0);
2049
2050	if (rctx->chip_class == EVERGREEN)
2051		r600_init_atom(&rctx->sample_mask.atom, evergreen_emit_sample_mask, 3, 0);
2052	else
2053		r600_init_atom(&rctx->sample_mask.atom, cayman_emit_sample_mask, 4, 0);
2054	rctx->sample_mask.sample_mask = ~0;
2055	r600_atom_dirty(rctx, &rctx->sample_mask.atom);
2056
2057	rctx->context.create_blend_state = evergreen_create_blend_state;
2058	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2059	rctx->context.create_fs_state = r600_create_shader_state_ps;
2060	rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2061	rctx->context.create_sampler_state = evergreen_create_sampler_state;
2062	rctx->context.create_sampler_view = evergreen_create_sampler_view;
2063	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
2064	rctx->context.create_vs_state = r600_create_shader_state_vs;
2065	rctx->context.bind_blend_state = r600_bind_blend_state;
2066	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2067	rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
2068	rctx->context.bind_fs_state = r600_bind_ps_shader;
2069	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
2070	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
2071	rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
2072	rctx->context.bind_vs_state = r600_bind_vs_shader;
2073	rctx->context.delete_blend_state = r600_delete_state;
2074	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
2075	rctx->context.delete_fs_state = r600_delete_ps_shader;
2076	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
2077	rctx->context.delete_sampler_state = r600_delete_sampler;
2078	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
2079	rctx->context.delete_vs_state = r600_delete_vs_shader;
2080	rctx->context.set_blend_color = r600_set_blend_color;
2081	rctx->context.set_clip_state = evergreen_set_clip_state;
2082	rctx->context.set_constant_buffer = r600_set_constant_buffer;
2083	rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_views;
2084	rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2085	rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2086	rctx->context.set_sample_mask = r600_set_sample_mask;
2087	rctx->context.set_scissor_state = evergreen_set_scissor_state;
2088	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
2089	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
2090	rctx->context.set_index_buffer = r600_set_index_buffer;
2091	rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_views;
2092	rctx->context.set_viewport_state = evergreen_set_viewport_state;
2093	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
2094	rctx->context.texture_barrier = r600_texture_barrier;
2095	rctx->context.create_stream_output_target = r600_create_so_target;
2096	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
2097	rctx->context.set_stream_output_targets = r600_set_so_targets;
2098	evergreen_init_compute_state_functions(rctx);
2099}
2100
2101static void cayman_init_atom_start_cs(struct r600_context *rctx)
2102{
2103	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2104
2105	r600_init_command_buffer(cb, 256, EMIT_EARLY);
2106
2107	/* This must be first. */
2108	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2109	r600_store_value(cb, 0x80000000);
2110	r600_store_value(cb, 0x80000000);
2111
2112	r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2113	r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2114	/* always set the temp clauses */
2115	r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2116
2117	r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2118	r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2119	r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2120
2121	r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2122
2123	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2124
2125	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2126	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2127	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2128	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2129	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2130	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2131	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2132	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2133	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2134	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2135	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2136	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2137	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2138	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2139
2140	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2141	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2142	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2143
2144	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2145	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2146	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2147
2148	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2149
2150	r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2151
2152	r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2153	r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2154	r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2155
2156	r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2157	r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2158	r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2159
2160	r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
2161
2162	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2163	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2164	r600_store_value(cb, 0);
2165	r600_store_value(cb, 0);
2166	r600_store_value(cb, 0);
2167	r600_store_value(cb, 0);
2168	r600_store_value(cb, 0);
2169	r600_store_value(cb, 0);
2170	r600_store_value(cb, 0);
2171	r600_store_value(cb, 0);
2172	r600_store_value(cb, 0);
2173	r600_store_value(cb, 0);
2174	r600_store_value(cb, 0);
2175	r600_store_value(cb, 0);
2176	r600_store_value(cb, 0);
2177	r600_store_value(cb, 0);
2178	r600_store_value(cb, 0);
2179	r600_store_value(cb, 0);
2180	r600_store_value(cb, 0);
2181	r600_store_value(cb, 0);
2182	r600_store_value(cb, 0);
2183	r600_store_value(cb, 0);
2184	r600_store_value(cb, 0);
2185	r600_store_value(cb, 0);
2186	r600_store_value(cb, 0);
2187	r600_store_value(cb, 0);
2188	r600_store_value(cb, 0);
2189	r600_store_value(cb, 0);
2190	r600_store_value(cb, 0);
2191	r600_store_value(cb, 0);
2192	r600_store_value(cb, 0);
2193	r600_store_value(cb, 0);
2194	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2195	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2196	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2197
2198	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2199
2200	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2201	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2202	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2203
2204	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2205
2206	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2207	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2208	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2209	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2210
2211	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2212	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2213
2214	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2215	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2216	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2217
2218	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2219	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2220	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2221
2222	r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2223	r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2224	r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2225	r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2226	r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2227
2228	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2229	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2230	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2231
2232	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2233	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2234	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2235
2236	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2237	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2238	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2239
2240	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2241	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2242	if (rctx->screen->has_streamout) {
2243		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2244	}
2245
2246	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2247	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2248}
2249
2250void evergreen_init_atom_start_cs(struct r600_context *rctx)
2251{
2252	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2253	int ps_prio;
2254	int vs_prio;
2255	int gs_prio;
2256	int es_prio;
2257	int hs_prio, cs_prio, ls_prio;
2258	int num_ps_gprs;
2259	int num_vs_gprs;
2260	int num_gs_gprs;
2261	int num_es_gprs;
2262	int num_hs_gprs;
2263	int num_ls_gprs;
2264	int num_temp_gprs;
2265	int num_ps_threads;
2266	int num_vs_threads;
2267	int num_gs_threads;
2268	int num_es_threads;
2269	int num_hs_threads;
2270	int num_ls_threads;
2271	int num_ps_stack_entries;
2272	int num_vs_stack_entries;
2273	int num_gs_stack_entries;
2274	int num_es_stack_entries;
2275	int num_hs_stack_entries;
2276	int num_ls_stack_entries;
2277	enum radeon_family family;
2278	unsigned tmp;
2279
2280	if (rctx->chip_class == CAYMAN) {
2281		cayman_init_atom_start_cs(rctx);
2282		return;
2283	}
2284
2285	r600_init_command_buffer(cb, 256, EMIT_EARLY);
2286
2287	/* This must be first. */
2288	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2289	r600_store_value(cb, 0x80000000);
2290	r600_store_value(cb, 0x80000000);
2291
2292	family = rctx->family;
2293	ps_prio = 0;
2294	vs_prio = 1;
2295	gs_prio = 2;
2296	es_prio = 3;
2297	hs_prio = 0;
2298	ls_prio = 0;
2299	cs_prio = 0;
2300
2301	switch (family) {
2302	case CHIP_CEDAR:
2303	default:
2304		num_ps_gprs = 93;
2305		num_vs_gprs = 46;
2306		num_temp_gprs = 4;
2307		num_gs_gprs = 31;
2308		num_es_gprs = 31;
2309		num_hs_gprs = 23;
2310		num_ls_gprs = 23;
2311		num_ps_threads = 96;
2312		num_vs_threads = 16;
2313		num_gs_threads = 16;
2314		num_es_threads = 16;
2315		num_hs_threads = 16;
2316		num_ls_threads = 16;
2317		num_ps_stack_entries = 42;
2318		num_vs_stack_entries = 42;
2319		num_gs_stack_entries = 42;
2320		num_es_stack_entries = 42;
2321		num_hs_stack_entries = 42;
2322		num_ls_stack_entries = 42;
2323		break;
2324	case CHIP_REDWOOD:
2325		num_ps_gprs = 93;
2326		num_vs_gprs = 46;
2327		num_temp_gprs = 4;
2328		num_gs_gprs = 31;
2329		num_es_gprs = 31;
2330		num_hs_gprs = 23;
2331		num_ls_gprs = 23;
2332		num_ps_threads = 128;
2333		num_vs_threads = 20;
2334		num_gs_threads = 20;
2335		num_es_threads = 20;
2336		num_hs_threads = 20;
2337		num_ls_threads = 20;
2338		num_ps_stack_entries = 42;
2339		num_vs_stack_entries = 42;
2340		num_gs_stack_entries = 42;
2341		num_es_stack_entries = 42;
2342		num_hs_stack_entries = 42;
2343		num_ls_stack_entries = 42;
2344		break;
2345	case CHIP_JUNIPER:
2346		num_ps_gprs = 93;
2347		num_vs_gprs = 46;
2348		num_temp_gprs = 4;
2349		num_gs_gprs = 31;
2350		num_es_gprs = 31;
2351		num_hs_gprs = 23;
2352		num_ls_gprs = 23;
2353		num_ps_threads = 128;
2354		num_vs_threads = 20;
2355		num_gs_threads = 20;
2356		num_es_threads = 20;
2357		num_hs_threads = 20;
2358		num_ls_threads = 20;
2359		num_ps_stack_entries = 85;
2360		num_vs_stack_entries = 85;
2361		num_gs_stack_entries = 85;
2362		num_es_stack_entries = 85;
2363		num_hs_stack_entries = 85;
2364		num_ls_stack_entries = 85;
2365		break;
2366	case CHIP_CYPRESS:
2367	case CHIP_HEMLOCK:
2368		num_ps_gprs = 93;
2369		num_vs_gprs = 46;
2370		num_temp_gprs = 4;
2371		num_gs_gprs = 31;
2372		num_es_gprs = 31;
2373		num_hs_gprs = 23;
2374		num_ls_gprs = 23;
2375		num_ps_threads = 128;
2376		num_vs_threads = 20;
2377		num_gs_threads = 20;
2378		num_es_threads = 20;
2379		num_hs_threads = 20;
2380		num_ls_threads = 20;
2381		num_ps_stack_entries = 85;
2382		num_vs_stack_entries = 85;
2383		num_gs_stack_entries = 85;
2384		num_es_stack_entries = 85;
2385		num_hs_stack_entries = 85;
2386		num_ls_stack_entries = 85;
2387		break;
2388	case CHIP_PALM:
2389		num_ps_gprs = 93;
2390		num_vs_gprs = 46;
2391		num_temp_gprs = 4;
2392		num_gs_gprs = 31;
2393		num_es_gprs = 31;
2394		num_hs_gprs = 23;
2395		num_ls_gprs = 23;
2396		num_ps_threads = 96;
2397		num_vs_threads = 16;
2398		num_gs_threads = 16;
2399		num_es_threads = 16;
2400		num_hs_threads = 16;
2401		num_ls_threads = 16;
2402		num_ps_stack_entries = 42;
2403		num_vs_stack_entries = 42;
2404		num_gs_stack_entries = 42;
2405		num_es_stack_entries = 42;
2406		num_hs_stack_entries = 42;
2407		num_ls_stack_entries = 42;
2408		break;
2409	case CHIP_SUMO:
2410		num_ps_gprs = 93;
2411		num_vs_gprs = 46;
2412		num_temp_gprs = 4;
2413		num_gs_gprs = 31;
2414		num_es_gprs = 31;
2415		num_hs_gprs = 23;
2416		num_ls_gprs = 23;
2417		num_ps_threads = 96;
2418		num_vs_threads = 25;
2419		num_gs_threads = 25;
2420		num_es_threads = 25;
2421		num_hs_threads = 25;
2422		num_ls_threads = 25;
2423		num_ps_stack_entries = 42;
2424		num_vs_stack_entries = 42;
2425		num_gs_stack_entries = 42;
2426		num_es_stack_entries = 42;
2427		num_hs_stack_entries = 42;
2428		num_ls_stack_entries = 42;
2429		break;
2430	case CHIP_SUMO2:
2431		num_ps_gprs = 93;
2432		num_vs_gprs = 46;
2433		num_temp_gprs = 4;
2434		num_gs_gprs = 31;
2435		num_es_gprs = 31;
2436		num_hs_gprs = 23;
2437		num_ls_gprs = 23;
2438		num_ps_threads = 96;
2439		num_vs_threads = 25;
2440		num_gs_threads = 25;
2441		num_es_threads = 25;
2442		num_hs_threads = 25;
2443		num_ls_threads = 25;
2444		num_ps_stack_entries = 85;
2445		num_vs_stack_entries = 85;
2446		num_gs_stack_entries = 85;
2447		num_es_stack_entries = 85;
2448		num_hs_stack_entries = 85;
2449		num_ls_stack_entries = 85;
2450		break;
2451	case CHIP_BARTS:
2452		num_ps_gprs = 93;
2453		num_vs_gprs = 46;
2454		num_temp_gprs = 4;
2455		num_gs_gprs = 31;
2456		num_es_gprs = 31;
2457		num_hs_gprs = 23;
2458		num_ls_gprs = 23;
2459		num_ps_threads = 128;
2460		num_vs_threads = 20;
2461		num_gs_threads = 20;
2462		num_es_threads = 20;
2463		num_hs_threads = 20;
2464		num_ls_threads = 20;
2465		num_ps_stack_entries = 85;
2466		num_vs_stack_entries = 85;
2467		num_gs_stack_entries = 85;
2468		num_es_stack_entries = 85;
2469		num_hs_stack_entries = 85;
2470		num_ls_stack_entries = 85;
2471		break;
2472	case CHIP_TURKS:
2473		num_ps_gprs = 93;
2474		num_vs_gprs = 46;
2475		num_temp_gprs = 4;
2476		num_gs_gprs = 31;
2477		num_es_gprs = 31;
2478		num_hs_gprs = 23;
2479		num_ls_gprs = 23;
2480		num_ps_threads = 128;
2481		num_vs_threads = 20;
2482		num_gs_threads = 20;
2483		num_es_threads = 20;
2484		num_hs_threads = 20;
2485		num_ls_threads = 20;
2486		num_ps_stack_entries = 42;
2487		num_vs_stack_entries = 42;
2488		num_gs_stack_entries = 42;
2489		num_es_stack_entries = 42;
2490		num_hs_stack_entries = 42;
2491		num_ls_stack_entries = 42;
2492		break;
2493	case CHIP_CAICOS:
2494		num_ps_gprs = 93;
2495		num_vs_gprs = 46;
2496		num_temp_gprs = 4;
2497		num_gs_gprs = 31;
2498		num_es_gprs = 31;
2499		num_hs_gprs = 23;
2500		num_ls_gprs = 23;
2501		num_ps_threads = 128;
2502		num_vs_threads = 10;
2503		num_gs_threads = 10;
2504		num_es_threads = 10;
2505		num_hs_threads = 10;
2506		num_ls_threads = 10;
2507		num_ps_stack_entries = 42;
2508		num_vs_stack_entries = 42;
2509		num_gs_stack_entries = 42;
2510		num_es_stack_entries = 42;
2511		num_hs_stack_entries = 42;
2512		num_ls_stack_entries = 42;
2513		break;
2514	}
2515
2516	tmp = 0;
2517	switch (family) {
2518	case CHIP_CEDAR:
2519	case CHIP_PALM:
2520	case CHIP_SUMO:
2521	case CHIP_SUMO2:
2522	case CHIP_CAICOS:
2523		break;
2524	default:
2525		tmp |= S_008C00_VC_ENABLE(1);
2526		break;
2527	}
2528	tmp |= S_008C00_EXPORT_SRC_C(1);
2529	tmp |= S_008C00_CS_PRIO(cs_prio);
2530	tmp |= S_008C00_LS_PRIO(ls_prio);
2531	tmp |= S_008C00_HS_PRIO(hs_prio);
2532	tmp |= S_008C00_PS_PRIO(ps_prio);
2533	tmp |= S_008C00_VS_PRIO(vs_prio);
2534	tmp |= S_008C00_GS_PRIO(gs_prio);
2535	tmp |= S_008C00_ES_PRIO(es_prio);
2536
2537	/* enable dynamic GPR resource management */
2538	if (rctx->screen->info.drm_minor >= 7) {
2539		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2540		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2541		/* always set temp clauses */
2542		r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2543		r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2544		r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2545		r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2546		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2547		r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2548					S_028838_PS_GPRS(0x1e) |
2549					S_028838_VS_GPRS(0x1e) |
2550					S_028838_GS_GPRS(0x1e) |
2551					S_028838_ES_GPRS(0x1e) |
2552					S_028838_HS_GPRS(0x1e) |
2553					S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2554	} else {
2555		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2556		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2557
2558		tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2559		tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2560		tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2561		r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2562
2563		tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2564		tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2565		r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2566
2567		tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2568		tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2569		r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2570	}
2571
2572	tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2573	tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2574	tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2575	tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2576	r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2577	r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2578
2579	tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2580	tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2581	r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2582
2583	tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2584	tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2585	r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2586
2587	tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2588	tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2589	r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2590
2591	tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2592	tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2593	r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2594
2595	r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2596			      S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2597
2598	r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2599	r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2600
2601	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2602
2603	r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2604	r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2605	r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2606	r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2607	r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2608	r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2609	r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2610
2611	r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2612	r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2613	r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2614	r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2615	r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2616
2617	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2618	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2619	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2620	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2621	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2622	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2623	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2624	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2625	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2626	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2627	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2628	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2629	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2630	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2631
2632	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2633	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2634	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2635
2636	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2637	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2638	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2639
2640	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2641
2642	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2643	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2644	r600_store_value(cb, 0);
2645	r600_store_value(cb, 0);
2646	r600_store_value(cb, 0);
2647	r600_store_value(cb, 0);
2648	r600_store_value(cb, 0);
2649	r600_store_value(cb, 0);
2650	r600_store_value(cb, 0);
2651	r600_store_value(cb, 0);
2652	r600_store_value(cb, 0);
2653	r600_store_value(cb, 0);
2654	r600_store_value(cb, 0);
2655	r600_store_value(cb, 0);
2656	r600_store_value(cb, 0);
2657	r600_store_value(cb, 0);
2658	r600_store_value(cb, 0);
2659	r600_store_value(cb, 0);
2660	r600_store_value(cb, 0);
2661	r600_store_value(cb, 0);
2662	r600_store_value(cb, 0);
2663	r600_store_value(cb, 0);
2664	r600_store_value(cb, 0);
2665	r600_store_value(cb, 0);
2666	r600_store_value(cb, 0);
2667	r600_store_value(cb, 0);
2668	r600_store_value(cb, 0);
2669	r600_store_value(cb, 0);
2670	r600_store_value(cb, 0);
2671	r600_store_value(cb, 0);
2672	r600_store_value(cb, 0);
2673	r600_store_value(cb, 0);
2674	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2675	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2676	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2677
2678	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2679
2680	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2681	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2682	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2683
2684	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2685	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2686	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2687
2688	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2689	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2690	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2691
2692	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2693	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2694	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2695
2696	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2697	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2698	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2699	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2700
2701	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2702	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2703	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2704	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2705	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2706
2707	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2708	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2709	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2710
2711	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2712	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2713	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2714
2715	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2716	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2717	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2718
2719	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2720	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2721	if (rctx->screen->has_streamout) {
2722		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2723	}
2724
2725	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2726	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2727}
2728
2729void evergreen_polygon_offset_update(struct r600_context *rctx)
2730{
2731	struct r600_pipe_state state;
2732
2733	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2734	state.nregs = 0;
2735	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2736		float offset_units = rctx->rasterizer->offset_units;
2737		unsigned offset_db_fmt_cntl = 0, depth;
2738
2739		switch (rctx->framebuffer.zsbuf->format) {
2740		case PIPE_FORMAT_Z24X8_UNORM:
2741		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2742			depth = -24;
2743			offset_units *= 2.0f;
2744			break;
2745		case PIPE_FORMAT_Z32_FLOAT:
2746		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2747			depth = -23;
2748			offset_units *= 1.0f;
2749			offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2750			break;
2751		case PIPE_FORMAT_Z16_UNORM:
2752			depth = -16;
2753			offset_units *= 4.0f;
2754			break;
2755		default:
2756			return;
2757		}
2758		/* XXX some of those reg can be computed with cso */
2759		offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2760		r600_pipe_state_add_reg(&state,
2761				R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2762				fui(rctx->rasterizer->offset_scale));
2763		r600_pipe_state_add_reg(&state,
2764				R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2765				fui(offset_units));
2766		r600_pipe_state_add_reg(&state,
2767				R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2768				fui(rctx->rasterizer->offset_scale));
2769		r600_pipe_state_add_reg(&state,
2770				R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2771				fui(offset_units));
2772		r600_pipe_state_add_reg(&state,
2773				R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2774				offset_db_fmt_cntl);
2775		r600_context_pipe_state_set(rctx, &state);
2776	}
2777}
2778
2779void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2780{
2781	struct r600_context *rctx = (struct r600_context *)ctx;
2782	struct r600_pipe_state *rstate = &shader->rstate;
2783	struct r600_shader *rshader = &shader->shader;
2784	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2785	int pos_index = -1, face_index = -1;
2786	int ninterp = 0;
2787	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2788	unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2789	unsigned z_export = 0, stencil_export = 0;
2790
2791	rstate->nregs = 0;
2792
2793	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2794	for (i = 0; i < rshader->ninput; i++) {
2795		/* evergreen NUM_INTERP only contains values interpolated into the LDS,
2796		   POSITION goes via GPRs from the SC so isn't counted */
2797		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2798			pos_index = i;
2799		else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2800			face_index = i;
2801		else {
2802			ninterp++;
2803			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2804				have_linear = TRUE;
2805			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2806				have_perspective = TRUE;
2807			if (rshader->input[i].centroid)
2808				have_centroid = TRUE;
2809		}
2810
2811		sid = rshader->input[i].spi_sid;
2812
2813		if (sid) {
2814
2815			tmp = S_028644_SEMANTIC(sid);
2816
2817			if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2818				rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2819				(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2820					rctx->rasterizer && rctx->rasterizer->flatshade)) {
2821				tmp |= S_028644_FLAT_SHADE(1);
2822			}
2823
2824			if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2825					(rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2826				tmp |= S_028644_PT_SPRITE_TEX(1);
2827			}
2828
2829			r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2830					tmp);
2831
2832			idx++;
2833		}
2834	}
2835
2836	for (i = 0; i < rshader->noutput; i++) {
2837		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2838			z_export = 1;
2839		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2840			stencil_export = 1;
2841	}
2842	if (rshader->uses_kill)
2843		db_shader_control |= S_02880C_KILL_ENABLE(1);
2844
2845	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2846	db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2847
2848	exports_ps = 0;
2849	for (i = 0; i < rshader->noutput; i++) {
2850		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2851		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2852			exports_ps |= 1;
2853	}
2854
2855	num_cout = rshader->nr_ps_color_exports;
2856
2857	exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2858	if (!exports_ps) {
2859		/* always at least export 1 component per pixel */
2860		exports_ps = 2;
2861	}
2862	shader->nr_ps_color_outputs = num_cout;
2863	if (ninterp == 0) {
2864		ninterp = 1;
2865		have_perspective = TRUE;
2866	}
2867
2868	if (!have_perspective && !have_linear)
2869		have_perspective = TRUE;
2870
2871	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2872		              S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2873		              S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2874	spi_input_z = 0;
2875	if (pos_index != -1) {
2876		spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
2877			S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2878			S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2879		spi_input_z |= 1;
2880	}
2881
2882	spi_ps_in_control_1 = 0;
2883	if (face_index != -1) {
2884		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2885			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2886	}
2887
2888	spi_baryc_cntl = 0;
2889	if (have_perspective)
2890		spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2891				  S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2892	if (have_linear)
2893		spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2894				  S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2895
2896	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2897				spi_ps_in_control_0);
2898	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2899				spi_ps_in_control_1);
2900	r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2901				0);
2902	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2903	r600_pipe_state_add_reg(rstate,
2904				R_0286E0_SPI_BARYC_CNTL,
2905				spi_baryc_cntl);
2906
2907	r600_pipe_state_add_reg_bo(rstate,
2908				R_028840_SQ_PGM_START_PS,
2909				r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2910				shader->bo, RADEON_USAGE_READ);
2911	r600_pipe_state_add_reg(rstate,
2912				R_028844_SQ_PGM_RESOURCES_PS,
2913				S_028844_NUM_GPRS(rshader->bc.ngpr) |
2914				S_028844_PRIME_CACHE_ON_DRAW(1) |
2915				S_028844_STACK_SIZE(rshader->bc.nstack));
2916	r600_pipe_state_add_reg(rstate,
2917				R_02884C_SQ_PGM_EXPORTS_PS,
2918				exports_ps);
2919
2920	shader->db_shader_control = db_shader_control;
2921	shader->ps_depth_export = z_export | stencil_export;
2922
2923	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2924	if (rctx->rasterizer)
2925		shader->flatshade = rctx->rasterizer->flatshade;
2926}
2927
2928void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2929{
2930	struct r600_context *rctx = (struct r600_context *)ctx;
2931	struct r600_pipe_state *rstate = &shader->rstate;
2932	struct r600_shader *rshader = &shader->shader;
2933	unsigned spi_vs_out_id[10] = {};
2934	unsigned i, tmp, nparams = 0;
2935
2936	/* clear previous register */
2937	rstate->nregs = 0;
2938
2939	for (i = 0; i < rshader->noutput; i++) {
2940		if (rshader->output[i].spi_sid) {
2941			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2942			spi_vs_out_id[nparams / 4] |= tmp;
2943			nparams++;
2944		}
2945	}
2946
2947	for (i = 0; i < 10; i++) {
2948		r600_pipe_state_add_reg(rstate,
2949					R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2950					spi_vs_out_id[i]);
2951	}
2952
2953	/* Certain attributes (position, psize, etc.) don't count as params.
2954	 * VS is required to export at least one param and r600_shader_from_tgsi()
2955	 * takes care of adding a dummy export.
2956	 */
2957	if (nparams < 1)
2958		nparams = 1;
2959
2960	r600_pipe_state_add_reg(rstate,
2961			R_0286C4_SPI_VS_OUT_CONFIG,
2962			S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2963	r600_pipe_state_add_reg(rstate,
2964			R_028860_SQ_PGM_RESOURCES_VS,
2965			S_028860_NUM_GPRS(rshader->bc.ngpr) |
2966			S_028860_STACK_SIZE(rshader->bc.nstack));
2967	r600_pipe_state_add_reg_bo(rstate,
2968			R_02885C_SQ_PGM_START_VS,
2969			r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2970			shader->bo, RADEON_USAGE_READ);
2971
2972	shader->pa_cl_vs_out_cntl =
2973		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2974		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2975		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2976		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2977}
2978
2979void evergreen_fetch_shader(struct pipe_context *ctx,
2980			    struct r600_vertex_element *ve)
2981{
2982	struct r600_context *rctx = (struct r600_context *)ctx;
2983	struct r600_pipe_state *rstate = &ve->rstate;
2984	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2985	rstate->nregs = 0;
2986	r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
2987				r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2988				ve->fetch_shader, RADEON_USAGE_READ);
2989}
2990
2991void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2992{
2993	struct pipe_depth_stencil_alpha_state dsa = {{0}};
2994
2995	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2996}
2997
2998void evergreen_update_dual_export_state(struct r600_context * rctx)
2999{
3000	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
3001			!rctx->ps_shader->current->ps_depth_export;
3002
3003	unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
3004			V_02880C_EXPORT_DB_FULL;
3005
3006	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3007			S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3008			S_02880C_DB_SOURCE_FORMAT(db_source_format) |
3009			S_02880C_ALPHA_TO_MASK_DISABLE(rctx->cb0_is_integer);
3010
3011	if (db_shader_control != rctx->db_shader_control) {
3012		struct r600_pipe_state rstate;
3013
3014		rctx->db_shader_control = db_shader_control;
3015
3016		rstate.nregs = 0;
3017		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
3018		r600_context_pipe_state_set(rctx, &rstate);
3019	}
3020}
3021