evergreen_state.c revision a01791add08fbcb5386e0e9209ba21ed58fbdc42 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "evergreend.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31#include "evergreen_compute.h"
32
33static uint32_t eg_num_banks(uint32_t nbanks)
34{
35	switch (nbanks) {
36	case 2:
37		return 0;
38	case 4:
39		return 1;
40	case 8:
41	default:
42		return 2;
43	case 16:
44		return 3;
45	}
46}
47
48
49static unsigned eg_tile_split(unsigned tile_split)
50{
51	switch (tile_split) {
52	case 64:	tile_split = 0;	break;
53	case 128:	tile_split = 1;	break;
54	case 256:	tile_split = 2;	break;
55	case 512:	tile_split = 3;	break;
56	default:
57	case 1024:	tile_split = 4;	break;
58	case 2048:	tile_split = 5;	break;
59	case 4096:	tile_split = 6;	break;
60	}
61	return tile_split;
62}
63
64static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65{
66	switch (macro_tile_aspect) {
67	default:
68	case 1:	macro_tile_aspect = 0;	break;
69	case 2:	macro_tile_aspect = 1;	break;
70	case 4:	macro_tile_aspect = 2;	break;
71	case 8:	macro_tile_aspect = 3;	break;
72	}
73	return macro_tile_aspect;
74}
75
76static unsigned eg_bank_wh(unsigned bankwh)
77{
78	switch (bankwh) {
79	default:
80	case 1:	bankwh = 0;	break;
81	case 2:	bankwh = 1;	break;
82	case 4:	bankwh = 2;	break;
83	case 8:	bankwh = 3;	break;
84	}
85	return bankwh;
86}
87
88static uint32_t r600_translate_blend_function(int blend_func)
89{
90	switch (blend_func) {
91	case PIPE_BLEND_ADD:
92		return V_028780_COMB_DST_PLUS_SRC;
93	case PIPE_BLEND_SUBTRACT:
94		return V_028780_COMB_SRC_MINUS_DST;
95	case PIPE_BLEND_REVERSE_SUBTRACT:
96		return V_028780_COMB_DST_MINUS_SRC;
97	case PIPE_BLEND_MIN:
98		return V_028780_COMB_MIN_DST_SRC;
99	case PIPE_BLEND_MAX:
100		return V_028780_COMB_MAX_DST_SRC;
101	default:
102		R600_ERR("Unknown blend function %d\n", blend_func);
103		assert(0);
104		break;
105	}
106	return 0;
107}
108
109static uint32_t r600_translate_blend_factor(int blend_fact)
110{
111	switch (blend_fact) {
112	case PIPE_BLENDFACTOR_ONE:
113		return V_028780_BLEND_ONE;
114	case PIPE_BLENDFACTOR_SRC_COLOR:
115		return V_028780_BLEND_SRC_COLOR;
116	case PIPE_BLENDFACTOR_SRC_ALPHA:
117		return V_028780_BLEND_SRC_ALPHA;
118	case PIPE_BLENDFACTOR_DST_ALPHA:
119		return V_028780_BLEND_DST_ALPHA;
120	case PIPE_BLENDFACTOR_DST_COLOR:
121		return V_028780_BLEND_DST_COLOR;
122	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123		return V_028780_BLEND_SRC_ALPHA_SATURATE;
124	case PIPE_BLENDFACTOR_CONST_COLOR:
125		return V_028780_BLEND_CONST_COLOR;
126	case PIPE_BLENDFACTOR_CONST_ALPHA:
127		return V_028780_BLEND_CONST_ALPHA;
128	case PIPE_BLENDFACTOR_ZERO:
129		return V_028780_BLEND_ZERO;
130	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131		return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133		return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135		return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136	case PIPE_BLENDFACTOR_INV_DST_COLOR:
137		return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139		return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141		return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142	case PIPE_BLENDFACTOR_SRC1_COLOR:
143		return V_028780_BLEND_SRC1_COLOR;
144	case PIPE_BLENDFACTOR_SRC1_ALPHA:
145		return V_028780_BLEND_SRC1_ALPHA;
146	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147		return V_028780_BLEND_INV_SRC1_COLOR;
148	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149		return V_028780_BLEND_INV_SRC1_ALPHA;
150	default:
151		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152		assert(0);
153		break;
154	}
155	return 0;
156}
157
158static unsigned r600_tex_dim(unsigned dim)
159{
160	switch (dim) {
161	default:
162	case PIPE_TEXTURE_1D:
163		return V_030000_SQ_TEX_DIM_1D;
164	case PIPE_TEXTURE_1D_ARRAY:
165		return V_030000_SQ_TEX_DIM_1D_ARRAY;
166	case PIPE_TEXTURE_2D:
167	case PIPE_TEXTURE_RECT:
168		return V_030000_SQ_TEX_DIM_2D;
169	case PIPE_TEXTURE_2D_ARRAY:
170		return V_030000_SQ_TEX_DIM_2D_ARRAY;
171	case PIPE_TEXTURE_3D:
172		return V_030000_SQ_TEX_DIM_3D;
173	case PIPE_TEXTURE_CUBE:
174		return V_030000_SQ_TEX_DIM_CUBEMAP;
175	}
176}
177
178static uint32_t r600_translate_dbformat(enum pipe_format format)
179{
180	switch (format) {
181	case PIPE_FORMAT_Z16_UNORM:
182		return V_028040_Z_16;
183	case PIPE_FORMAT_Z24X8_UNORM:
184	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
185		return V_028040_Z_24;
186	case PIPE_FORMAT_Z32_FLOAT:
187	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
188		return V_028040_Z_32_FLOAT;
189	default:
190		return ~0U;
191	}
192}
193
194static uint32_t r600_translate_colorswap(enum pipe_format format)
195{
196	switch (format) {
197	/* 8-bit buffers. */
198	case PIPE_FORMAT_L4A4_UNORM:
199	case PIPE_FORMAT_A4R4_UNORM:
200		return V_028C70_SWAP_ALT;
201
202	case PIPE_FORMAT_A8_UNORM:
203	case PIPE_FORMAT_A8_SNORM:
204	case PIPE_FORMAT_A8_UINT:
205	case PIPE_FORMAT_A8_SINT:
206	case PIPE_FORMAT_A16_UNORM:
207	case PIPE_FORMAT_A16_SNORM:
208	case PIPE_FORMAT_A16_UINT:
209	case PIPE_FORMAT_A16_SINT:
210	case PIPE_FORMAT_A16_FLOAT:
211	case PIPE_FORMAT_A32_UINT:
212	case PIPE_FORMAT_A32_SINT:
213	case PIPE_FORMAT_A32_FLOAT:
214	case PIPE_FORMAT_R4A4_UNORM:
215		return V_028C70_SWAP_ALT_REV;
216	case PIPE_FORMAT_I8_UNORM:
217	case PIPE_FORMAT_I8_SNORM:
218	case PIPE_FORMAT_I8_UINT:
219	case PIPE_FORMAT_I8_SINT:
220	case PIPE_FORMAT_I16_UNORM:
221	case PIPE_FORMAT_I16_SNORM:
222	case PIPE_FORMAT_I16_UINT:
223	case PIPE_FORMAT_I16_SINT:
224	case PIPE_FORMAT_I16_FLOAT:
225	case PIPE_FORMAT_I32_UINT:
226	case PIPE_FORMAT_I32_SINT:
227	case PIPE_FORMAT_I32_FLOAT:
228	case PIPE_FORMAT_L8_UNORM:
229	case PIPE_FORMAT_L8_SNORM:
230	case PIPE_FORMAT_L8_UINT:
231	case PIPE_FORMAT_L8_SINT:
232	case PIPE_FORMAT_L8_SRGB:
233	case PIPE_FORMAT_L16_UNORM:
234	case PIPE_FORMAT_L16_SNORM:
235	case PIPE_FORMAT_L16_UINT:
236	case PIPE_FORMAT_L16_SINT:
237	case PIPE_FORMAT_L16_FLOAT:
238	case PIPE_FORMAT_L32_UINT:
239	case PIPE_FORMAT_L32_SINT:
240	case PIPE_FORMAT_L32_FLOAT:
241	case PIPE_FORMAT_R8_UNORM:
242	case PIPE_FORMAT_R8_SNORM:
243	case PIPE_FORMAT_R8_UINT:
244	case PIPE_FORMAT_R8_SINT:
245		return V_028C70_SWAP_STD;
246
247	/* 16-bit buffers. */
248	case PIPE_FORMAT_B5G6R5_UNORM:
249		return V_028C70_SWAP_STD_REV;
250
251	case PIPE_FORMAT_B5G5R5A1_UNORM:
252	case PIPE_FORMAT_B5G5R5X1_UNORM:
253		return V_028C70_SWAP_ALT;
254
255	case PIPE_FORMAT_B4G4R4A4_UNORM:
256	case PIPE_FORMAT_B4G4R4X4_UNORM:
257		return V_028C70_SWAP_ALT;
258
259	case PIPE_FORMAT_Z16_UNORM:
260		return V_028C70_SWAP_STD;
261
262	case PIPE_FORMAT_L8A8_UNORM:
263	case PIPE_FORMAT_L8A8_SNORM:
264	case PIPE_FORMAT_L8A8_UINT:
265	case PIPE_FORMAT_L8A8_SINT:
266	case PIPE_FORMAT_L8A8_SRGB:
267	case PIPE_FORMAT_L16A16_UNORM:
268	case PIPE_FORMAT_L16A16_SNORM:
269	case PIPE_FORMAT_L16A16_UINT:
270	case PIPE_FORMAT_L16A16_SINT:
271	case PIPE_FORMAT_L16A16_FLOAT:
272	case PIPE_FORMAT_L32A32_UINT:
273	case PIPE_FORMAT_L32A32_SINT:
274	case PIPE_FORMAT_L32A32_FLOAT:
275		return V_028C70_SWAP_ALT;
276	case PIPE_FORMAT_R8G8_UNORM:
277	case PIPE_FORMAT_R8G8_SNORM:
278	case PIPE_FORMAT_R8G8_UINT:
279	case PIPE_FORMAT_R8G8_SINT:
280		return V_028C70_SWAP_STD;
281
282	case PIPE_FORMAT_R16_UNORM:
283	case PIPE_FORMAT_R16_SNORM:
284	case PIPE_FORMAT_R16_UINT:
285	case PIPE_FORMAT_R16_SINT:
286	case PIPE_FORMAT_R16_FLOAT:
287		return V_028C70_SWAP_STD;
288
289	/* 32-bit buffers. */
290	case PIPE_FORMAT_A8B8G8R8_SRGB:
291		return V_028C70_SWAP_STD_REV;
292	case PIPE_FORMAT_B8G8R8A8_SRGB:
293		return V_028C70_SWAP_ALT;
294
295	case PIPE_FORMAT_B8G8R8A8_UNORM:
296	case PIPE_FORMAT_B8G8R8X8_UNORM:
297		return V_028C70_SWAP_ALT;
298
299	case PIPE_FORMAT_A8R8G8B8_UNORM:
300	case PIPE_FORMAT_X8R8G8B8_UNORM:
301		return V_028C70_SWAP_ALT_REV;
302	case PIPE_FORMAT_R8G8B8A8_SNORM:
303	case PIPE_FORMAT_R8G8B8A8_UNORM:
304	case PIPE_FORMAT_R8G8B8A8_SINT:
305	case PIPE_FORMAT_R8G8B8A8_UINT:
306	case PIPE_FORMAT_R8G8B8X8_UNORM:
307		return V_028C70_SWAP_STD;
308
309	case PIPE_FORMAT_A8B8G8R8_UNORM:
310	case PIPE_FORMAT_X8B8G8R8_UNORM:
311	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
312		return V_028C70_SWAP_STD_REV;
313
314	case PIPE_FORMAT_Z24X8_UNORM:
315	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
316		return V_028C70_SWAP_STD;
317
318	case PIPE_FORMAT_X8Z24_UNORM:
319	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
320		return V_028C70_SWAP_STD;
321
322	case PIPE_FORMAT_R10G10B10A2_UNORM:
323	case PIPE_FORMAT_R10G10B10X2_SNORM:
324	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
325		return V_028C70_SWAP_STD;
326
327	case PIPE_FORMAT_B10G10R10A2_UNORM:
328	case PIPE_FORMAT_B10G10R10A2_UINT:
329		return V_028C70_SWAP_ALT;
330
331	case PIPE_FORMAT_R11G11B10_FLOAT:
332	case PIPE_FORMAT_R32_FLOAT:
333	case PIPE_FORMAT_R32_UINT:
334	case PIPE_FORMAT_R32_SINT:
335	case PIPE_FORMAT_Z32_FLOAT:
336	case PIPE_FORMAT_R16G16_FLOAT:
337	case PIPE_FORMAT_R16G16_UNORM:
338	case PIPE_FORMAT_R16G16_SNORM:
339	case PIPE_FORMAT_R16G16_UINT:
340	case PIPE_FORMAT_R16G16_SINT:
341		return V_028C70_SWAP_STD;
342
343	/* 64-bit buffers. */
344	case PIPE_FORMAT_R32G32_FLOAT:
345	case PIPE_FORMAT_R32G32_UINT:
346	case PIPE_FORMAT_R32G32_SINT:
347	case PIPE_FORMAT_R16G16B16A16_UNORM:
348	case PIPE_FORMAT_R16G16B16A16_SNORM:
349	case PIPE_FORMAT_R16G16B16A16_UINT:
350	case PIPE_FORMAT_R16G16B16A16_SINT:
351	case PIPE_FORMAT_R16G16B16A16_FLOAT:
352	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
353
354	/* 128-bit buffers. */
355	case PIPE_FORMAT_R32G32B32A32_FLOAT:
356	case PIPE_FORMAT_R32G32B32A32_SNORM:
357	case PIPE_FORMAT_R32G32B32A32_UNORM:
358	case PIPE_FORMAT_R32G32B32A32_SINT:
359	case PIPE_FORMAT_R32G32B32A32_UINT:
360		return V_028C70_SWAP_STD;
361	default:
362		R600_ERR("unsupported colorswap format %d\n", format);
363		return ~0U;
364	}
365	return ~0U;
366}
367
368static uint32_t r600_translate_colorformat(enum pipe_format format)
369{
370	switch (format) {
371	/* 8-bit buffers. */
372	case PIPE_FORMAT_A8_UNORM:
373	case PIPE_FORMAT_A8_SNORM:
374	case PIPE_FORMAT_A8_UINT:
375	case PIPE_FORMAT_A8_SINT:
376	case PIPE_FORMAT_I8_UNORM:
377	case PIPE_FORMAT_I8_SNORM:
378	case PIPE_FORMAT_I8_UINT:
379	case PIPE_FORMAT_I8_SINT:
380	case PIPE_FORMAT_L8_UNORM:
381	case PIPE_FORMAT_L8_SNORM:
382	case PIPE_FORMAT_L8_UINT:
383	case PIPE_FORMAT_L8_SINT:
384	case PIPE_FORMAT_L8_SRGB:
385	case PIPE_FORMAT_R8_UNORM:
386	case PIPE_FORMAT_R8_SNORM:
387	case PIPE_FORMAT_R8_UINT:
388	case PIPE_FORMAT_R8_SINT:
389		return V_028C70_COLOR_8;
390
391	/* 16-bit buffers. */
392	case PIPE_FORMAT_B5G6R5_UNORM:
393		return V_028C70_COLOR_5_6_5;
394
395	case PIPE_FORMAT_B5G5R5A1_UNORM:
396	case PIPE_FORMAT_B5G5R5X1_UNORM:
397		return V_028C70_COLOR_1_5_5_5;
398
399	case PIPE_FORMAT_B4G4R4A4_UNORM:
400	case PIPE_FORMAT_B4G4R4X4_UNORM:
401		return V_028C70_COLOR_4_4_4_4;
402
403	case PIPE_FORMAT_Z16_UNORM:
404		return V_028C70_COLOR_16;
405
406	case PIPE_FORMAT_L8A8_UNORM:
407	case PIPE_FORMAT_L8A8_SNORM:
408	case PIPE_FORMAT_L8A8_UINT:
409	case PIPE_FORMAT_L8A8_SINT:
410	case PIPE_FORMAT_L8A8_SRGB:
411	case PIPE_FORMAT_R8G8_UNORM:
412	case PIPE_FORMAT_R8G8_SNORM:
413	case PIPE_FORMAT_R8G8_UINT:
414	case PIPE_FORMAT_R8G8_SINT:
415		return V_028C70_COLOR_8_8;
416
417	case PIPE_FORMAT_R16_UNORM:
418	case PIPE_FORMAT_R16_SNORM:
419	case PIPE_FORMAT_R16_UINT:
420	case PIPE_FORMAT_R16_SINT:
421	case PIPE_FORMAT_A16_UNORM:
422	case PIPE_FORMAT_A16_SNORM:
423	case PIPE_FORMAT_A16_UINT:
424	case PIPE_FORMAT_A16_SINT:
425	case PIPE_FORMAT_L16_UNORM:
426	case PIPE_FORMAT_L16_SNORM:
427	case PIPE_FORMAT_L16_UINT:
428	case PIPE_FORMAT_L16_SINT:
429	case PIPE_FORMAT_I16_UNORM:
430	case PIPE_FORMAT_I16_SNORM:
431	case PIPE_FORMAT_I16_UINT:
432	case PIPE_FORMAT_I16_SINT:
433		return V_028C70_COLOR_16;
434
435	case PIPE_FORMAT_R16_FLOAT:
436	case PIPE_FORMAT_A16_FLOAT:
437	case PIPE_FORMAT_L16_FLOAT:
438	case PIPE_FORMAT_I16_FLOAT:
439		return V_028C70_COLOR_16_FLOAT;
440
441	/* 32-bit buffers. */
442	case PIPE_FORMAT_A8B8G8R8_SRGB:
443	case PIPE_FORMAT_A8B8G8R8_UNORM:
444	case PIPE_FORMAT_A8R8G8B8_UNORM:
445	case PIPE_FORMAT_B8G8R8A8_SRGB:
446	case PIPE_FORMAT_B8G8R8A8_UNORM:
447	case PIPE_FORMAT_B8G8R8X8_UNORM:
448	case PIPE_FORMAT_R8G8B8A8_SNORM:
449	case PIPE_FORMAT_R8G8B8A8_UNORM:
450	case PIPE_FORMAT_R8G8B8X8_UNORM:
451	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
452	case PIPE_FORMAT_X8B8G8R8_UNORM:
453	case PIPE_FORMAT_X8R8G8B8_UNORM:
454	case PIPE_FORMAT_R8G8B8_UNORM:
455	case PIPE_FORMAT_R8G8B8A8_SINT:
456	case PIPE_FORMAT_R8G8B8A8_UINT:
457		return V_028C70_COLOR_8_8_8_8;
458
459	case PIPE_FORMAT_R10G10B10A2_UNORM:
460	case PIPE_FORMAT_R10G10B10X2_SNORM:
461	case PIPE_FORMAT_B10G10R10A2_UNORM:
462	case PIPE_FORMAT_B10G10R10A2_UINT:
463	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
464		return V_028C70_COLOR_2_10_10_10;
465
466	case PIPE_FORMAT_Z24X8_UNORM:
467	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
468		return V_028C70_COLOR_8_24;
469
470	case PIPE_FORMAT_X8Z24_UNORM:
471	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
472		return V_028C70_COLOR_24_8;
473
474	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
475		return V_028C70_COLOR_X24_8_32_FLOAT;
476
477	case PIPE_FORMAT_R32_UINT:
478	case PIPE_FORMAT_R32_SINT:
479	case PIPE_FORMAT_A32_UINT:
480	case PIPE_FORMAT_A32_SINT:
481	case PIPE_FORMAT_L32_UINT:
482	case PIPE_FORMAT_L32_SINT:
483	case PIPE_FORMAT_I32_UINT:
484	case PIPE_FORMAT_I32_SINT:
485		return V_028C70_COLOR_32;
486
487	case PIPE_FORMAT_R32_FLOAT:
488	case PIPE_FORMAT_A32_FLOAT:
489	case PIPE_FORMAT_L32_FLOAT:
490	case PIPE_FORMAT_I32_FLOAT:
491	case PIPE_FORMAT_Z32_FLOAT:
492		return V_028C70_COLOR_32_FLOAT;
493
494	case PIPE_FORMAT_R16G16_FLOAT:
495	case PIPE_FORMAT_L16A16_FLOAT:
496		return V_028C70_COLOR_16_16_FLOAT;
497
498	case PIPE_FORMAT_R16G16_UNORM:
499	case PIPE_FORMAT_R16G16_SNORM:
500	case PIPE_FORMAT_R16G16_UINT:
501	case PIPE_FORMAT_R16G16_SINT:
502	case PIPE_FORMAT_L16A16_UNORM:
503	case PIPE_FORMAT_L16A16_SNORM:
504	case PIPE_FORMAT_L16A16_UINT:
505	case PIPE_FORMAT_L16A16_SINT:
506		return V_028C70_COLOR_16_16;
507
508	case PIPE_FORMAT_R11G11B10_FLOAT:
509		return V_028C70_COLOR_10_11_11_FLOAT;
510
511	/* 64-bit buffers. */
512	case PIPE_FORMAT_R16G16B16A16_UINT:
513	case PIPE_FORMAT_R16G16B16A16_SINT:
514	case PIPE_FORMAT_R16G16B16A16_UNORM:
515	case PIPE_FORMAT_R16G16B16A16_SNORM:
516		return V_028C70_COLOR_16_16_16_16;
517
518	case PIPE_FORMAT_R16G16B16A16_FLOAT:
519		return V_028C70_COLOR_16_16_16_16_FLOAT;
520
521	case PIPE_FORMAT_R32G32_FLOAT:
522	case PIPE_FORMAT_L32A32_FLOAT:
523		return V_028C70_COLOR_32_32_FLOAT;
524
525	case PIPE_FORMAT_R32G32_SINT:
526	case PIPE_FORMAT_R32G32_UINT:
527	case PIPE_FORMAT_L32A32_UINT:
528	case PIPE_FORMAT_L32A32_SINT:
529		return V_028C70_COLOR_32_32;
530
531	/* 128-bit buffers. */
532	case PIPE_FORMAT_R32G32B32A32_SNORM:
533	case PIPE_FORMAT_R32G32B32A32_UNORM:
534	case PIPE_FORMAT_R32G32B32A32_SINT:
535	case PIPE_FORMAT_R32G32B32A32_UINT:
536		return V_028C70_COLOR_32_32_32_32;
537	case PIPE_FORMAT_R32G32B32A32_FLOAT:
538		return V_028C70_COLOR_32_32_32_32_FLOAT;
539
540	/* YUV buffers. */
541	case PIPE_FORMAT_UYVY:
542	case PIPE_FORMAT_YUYV:
543	default:
544		return ~0U; /* Unsupported. */
545	}
546}
547
548static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
549{
550	if (R600_BIG_ENDIAN) {
551		switch(colorformat) {
552
553		/* 8-bit buffers. */
554		case V_028C70_COLOR_8:
555			return ENDIAN_NONE;
556
557		/* 16-bit buffers. */
558		case V_028C70_COLOR_5_6_5:
559		case V_028C70_COLOR_1_5_5_5:
560		case V_028C70_COLOR_4_4_4_4:
561		case V_028C70_COLOR_16:
562		case V_028C70_COLOR_8_8:
563			return ENDIAN_8IN16;
564
565		/* 32-bit buffers. */
566		case V_028C70_COLOR_8_8_8_8:
567		case V_028C70_COLOR_2_10_10_10:
568		case V_028C70_COLOR_8_24:
569		case V_028C70_COLOR_24_8:
570		case V_028C70_COLOR_32_FLOAT:
571		case V_028C70_COLOR_16_16_FLOAT:
572		case V_028C70_COLOR_16_16:
573			return ENDIAN_8IN32;
574
575		/* 64-bit buffers. */
576		case V_028C70_COLOR_16_16_16_16:
577		case V_028C70_COLOR_16_16_16_16_FLOAT:
578			return ENDIAN_8IN16;
579
580		case V_028C70_COLOR_32_32_FLOAT:
581		case V_028C70_COLOR_32_32:
582		case V_028C70_COLOR_X24_8_32_FLOAT:
583			return ENDIAN_8IN32;
584
585		/* 96-bit buffers. */
586		case V_028C70_COLOR_32_32_32_FLOAT:
587		/* 128-bit buffers. */
588		case V_028C70_COLOR_32_32_32_32_FLOAT:
589		case V_028C70_COLOR_32_32_32_32:
590			return ENDIAN_8IN32;
591		default:
592			return ENDIAN_NONE; /* Unsupported. */
593		}
594	} else {
595		return ENDIAN_NONE;
596	}
597}
598
599static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
600{
601	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
602}
603
604static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
605{
606	return r600_translate_colorformat(format) != ~0U &&
607		r600_translate_colorswap(format) != ~0U;
608}
609
610static bool r600_is_zs_format_supported(enum pipe_format format)
611{
612	return r600_translate_dbformat(format) != ~0U;
613}
614
615boolean evergreen_is_format_supported(struct pipe_screen *screen,
616				      enum pipe_format format,
617				      enum pipe_texture_target target,
618				      unsigned sample_count,
619				      unsigned usage)
620{
621	unsigned retval = 0;
622
623	if (target >= PIPE_MAX_TEXTURE_TYPES) {
624		R600_ERR("r600: unsupported texture type %d\n", target);
625		return FALSE;
626	}
627
628	if (!util_format_is_supported(format, usage))
629		return FALSE;
630
631	/* Multisample */
632	if (sample_count > 1)
633		return FALSE;
634
635	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
636	    r600_is_sampler_format_supported(screen, format)) {
637		retval |= PIPE_BIND_SAMPLER_VIEW;
638	}
639
640	if ((usage & (PIPE_BIND_RENDER_TARGET |
641		      PIPE_BIND_DISPLAY_TARGET |
642		      PIPE_BIND_SCANOUT |
643		      PIPE_BIND_SHARED)) &&
644	    r600_is_colorbuffer_format_supported(format)) {
645		retval |= usage &
646			  (PIPE_BIND_RENDER_TARGET |
647			   PIPE_BIND_DISPLAY_TARGET |
648			   PIPE_BIND_SCANOUT |
649			   PIPE_BIND_SHARED);
650	}
651
652	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
653	    r600_is_zs_format_supported(format)) {
654		retval |= PIPE_BIND_DEPTH_STENCIL;
655	}
656
657	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
658	    r600_is_vertex_format_supported(format)) {
659		retval |= PIPE_BIND_VERTEX_BUFFER;
660	}
661
662	if (usage & PIPE_BIND_TRANSFER_READ)
663		retval |= PIPE_BIND_TRANSFER_READ;
664	if (usage & PIPE_BIND_TRANSFER_WRITE)
665		retval |= PIPE_BIND_TRANSFER_WRITE;
666
667	return retval == usage;
668}
669
670static void *evergreen_create_blend_state(struct pipe_context *ctx,
671					const struct pipe_blend_state *state)
672{
673	struct r600_context *rctx = (struct r600_context *)ctx;
674	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
675	struct r600_pipe_state *rstate;
676	uint32_t color_control = 0, target_mask;
677	/* XXX there is more then 8 framebuffer */
678	unsigned blend_cntl[8];
679
680	if (blend == NULL) {
681		return NULL;
682	}
683
684	rstate = &blend->rstate;
685
686	rstate->id = R600_PIPE_STATE_BLEND;
687
688	target_mask = 0;
689	if (state->logicop_enable) {
690		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
691	} else {
692		color_control |= (0xcc << 16);
693	}
694	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
695	if (state->independent_blend_enable) {
696		for (int i = 0; i < 8; i++) {
697			target_mask |= (state->rt[i].colormask << (4 * i));
698		}
699	} else {
700		for (int i = 0; i < 8; i++) {
701			target_mask |= (state->rt[0].colormask << (4 * i));
702		}
703	}
704	blend->cb_target_mask = target_mask;
705
706	if (target_mask)
707		color_control |= S_028808_MODE(V_028808_CB_NORMAL);
708	else
709		color_control |= S_028808_MODE(V_028808_CB_DISABLE);
710
711	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
712				color_control);
713	/* only have dual source on MRT0 */
714	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
715	for (int i = 0; i < 8; i++) {
716		/* state->rt entries > 0 only written if independent blending */
717		const int j = state->independent_blend_enable ? i : 0;
718
719		unsigned eqRGB = state->rt[j].rgb_func;
720		unsigned srcRGB = state->rt[j].rgb_src_factor;
721		unsigned dstRGB = state->rt[j].rgb_dst_factor;
722		unsigned eqA = state->rt[j].alpha_func;
723		unsigned srcA = state->rt[j].alpha_src_factor;
724		unsigned dstA = state->rt[j].alpha_dst_factor;
725
726		blend_cntl[i] = 0;
727		if (!state->rt[j].blend_enable)
728			continue;
729
730		blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
731		blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
732		blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
733		blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
734
735		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
736			blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
737			blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
738			blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
739			blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
740		}
741	}
742	for (int i = 0; i < 8; i++) {
743		r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
744	}
745
746	r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
747				S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
748				S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
749				S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
750				S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
751				S_028B70_ALPHA_TO_MASK_OFFSET3(2));
752
753	blend->alpha_to_one = state->alpha_to_one;
754	return rstate;
755}
756
757static void *evergreen_create_dsa_state(struct pipe_context *ctx,
758				   const struct pipe_depth_stencil_alpha_state *state)
759{
760	struct r600_context *rctx = (struct r600_context *)ctx;
761	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
762	unsigned db_depth_control, alpha_test_control, alpha_ref;
763	struct r600_pipe_state *rstate;
764
765	if (dsa == NULL) {
766		return NULL;
767	}
768
769	dsa->valuemask[0] = state->stencil[0].valuemask;
770	dsa->valuemask[1] = state->stencil[1].valuemask;
771	dsa->writemask[0] = state->stencil[0].writemask;
772	dsa->writemask[1] = state->stencil[1].writemask;
773
774	rstate = &dsa->rstate;
775
776	rstate->id = R600_PIPE_STATE_DSA;
777	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
778		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
779		S_028800_ZFUNC(state->depth.func);
780
781	/* stencil */
782	if (state->stencil[0].enabled) {
783		db_depth_control |= S_028800_STENCIL_ENABLE(1);
784		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
785		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
786		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
787		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
788
789		if (state->stencil[1].enabled) {
790			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
791			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
792			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
793			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
794			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
795		}
796	}
797
798	/* alpha */
799	alpha_test_control = 0;
800	alpha_ref = 0;
801	if (state->alpha.enabled) {
802		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
803		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
804		alpha_ref = fui(state->alpha.ref_value);
805	}
806	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
807	dsa->alpha_ref = alpha_ref;
808
809	/* misc */
810	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
811	return rstate;
812}
813
814static void *evergreen_create_rs_state(struct pipe_context *ctx,
815					const struct pipe_rasterizer_state *state)
816{
817	struct r600_context *rctx = (struct r600_context *)ctx;
818	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
819	struct r600_pipe_state *rstate;
820	unsigned tmp;
821	unsigned prov_vtx = 1, polygon_dual_mode;
822	float psize_min, psize_max;
823
824	if (rs == NULL) {
825		return NULL;
826	}
827
828	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
829				state->fill_back != PIPE_POLYGON_MODE_FILL);
830
831	if (state->flatshade_first)
832		prov_vtx = 0;
833
834	rstate = &rs->rstate;
835	rs->flatshade = state->flatshade;
836	rs->sprite_coord_enable = state->sprite_coord_enable;
837	rs->two_side = state->light_twoside;
838	rs->clip_plane_enable = state->clip_plane_enable;
839	rs->pa_sc_line_stipple = state->line_stipple_enable ?
840				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
841				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
842	rs->pa_cl_clip_cntl =
843		S_028810_PS_UCP_MODE(3) |
844		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
845		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
846		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
847	rs->multisample_enable = state->multisample;
848
849	/* offset */
850	rs->offset_units = state->offset_units;
851	rs->offset_scale = state->offset_scale * 12.0f;
852
853	rstate->id = R600_PIPE_STATE_RASTERIZER;
854	tmp = S_0286D4_FLAT_SHADE_ENA(1);
855	if (state->sprite_coord_enable) {
856		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
857			S_0286D4_PNT_SPRITE_OVRD_X(2) |
858			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
859			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
860			S_0286D4_PNT_SPRITE_OVRD_W(1);
861		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
862			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
863		}
864	}
865	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
866
867	/* point size 12.4 fixed point */
868	tmp = (unsigned)(state->point_size * 8.0);
869	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
870
871	if (state->point_size_per_vertex) {
872		psize_min = util_get_min_point_size(state);
873		psize_max = 8192;
874	} else {
875		/* Force the point size to be as if the vertex output was disabled. */
876		psize_min = state->point_size;
877		psize_max = state->point_size;
878	}
879	/* Divide by two, because 0.5 = 1 pixel. */
880	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
881				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
882				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
883
884	tmp = (unsigned)state->line_width * 8;
885	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
886	r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
887				S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
888				S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
889
890	if (rctx->chip_class == CAYMAN) {
891		r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
892					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
893	} else {
894		r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
895					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
896	}
897	r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
898	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
899				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
900				S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
901				S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
902				S_028814_FACE(!state->front_ccw) |
903				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
904				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
905				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
906				S_028814_POLY_MODE(polygon_dual_mode) |
907				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
908				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
909	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
910	return rstate;
911}
912
913static void *evergreen_create_sampler_state(struct pipe_context *ctx,
914					const struct pipe_sampler_state *state)
915{
916	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
917	union util_color uc;
918	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
919
920	if (ss == NULL) {
921		return NULL;
922	}
923
924	/* directly into sampler avoid r6xx code to emit useless reg */
925	ss->seamless_cube_map = false;
926	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
927	ss->border_color_use = false;
928	/* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
929	ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
930				S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
931				S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
932				S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
933				S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
934				S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
935				S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
936				S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
937				S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
938	/* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
939	ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
940				S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
941	/* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
942	ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
943				(state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
944				S_03C008_TYPE(1);
945	if (uc.ui) {
946		ss->border_color_use = true;
947		/* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
948		ss->border_color[0] = fui(state->border_color.f[0]);
949		/* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
950		ss->border_color[1] = fui(state->border_color.f[1]);
951		/* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
952		ss->border_color[2] = fui(state->border_color.f[2]);
953		/* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
954		ss->border_color[3] = fui(state->border_color.f[3]);
955	}
956	return ss;
957}
958
959static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
960							struct pipe_resource *texture,
961							const struct pipe_sampler_view *state)
962{
963	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
964	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
965	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
966	unsigned format, endian;
967	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
968	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
969	unsigned height, depth, width;
970	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
971
972	if (view == NULL)
973		return NULL;
974
975	/* initialize base object */
976	view->base = *state;
977	view->base.texture = NULL;
978	pipe_reference(NULL, &texture->reference);
979	view->base.texture = texture;
980	view->base.reference.count = 1;
981	view->base.context = ctx;
982
983	swizzle[0] = state->swizzle_r;
984	swizzle[1] = state->swizzle_g;
985	swizzle[2] = state->swizzle_b;
986	swizzle[3] = state->swizzle_a;
987
988	format = r600_translate_texformat(ctx->screen, state->format,
989					  swizzle,
990					  &word4, &yuv_format);
991	assert(format != ~0);
992	if (format == ~0) {
993		FREE(view);
994		return NULL;
995	}
996
997	if (tmp->is_depth && !tmp->is_flushing_texture) {
998		if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
999			FREE(view);
1000			return NULL;
1001		}
1002		tmp = tmp->flushed_depth_texture;
1003	}
1004
1005	endian = r600_colorformat_endian_swap(format);
1006
1007	width = tmp->surface.level[0].npix_x;
1008	height = tmp->surface.level[0].npix_y;
1009	depth = tmp->surface.level[0].npix_z;
1010	pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1011	tile_type = tmp->tile_type;
1012
1013	switch (tmp->surface.level[0].mode) {
1014	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1015		array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1016		break;
1017	case RADEON_SURF_MODE_2D:
1018		array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1019		break;
1020	case RADEON_SURF_MODE_1D:
1021		array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1022		break;
1023	case RADEON_SURF_MODE_LINEAR:
1024	default:
1025		array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1026		break;
1027	}
1028	tile_split = tmp->surface.tile_split;
1029	macro_aspect = tmp->surface.mtilea;
1030	bankw = tmp->surface.bankw;
1031	bankh = tmp->surface.bankh;
1032	tile_split = eg_tile_split(tile_split);
1033	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1034	bankw = eg_bank_wh(bankw);
1035	bankh = eg_bank_wh(bankh);
1036
1037	/* 128 bit formats require tile type = 1 */
1038	if (rscreen->chip_class == CAYMAN) {
1039		if (util_format_get_blocksize(state->format) >= 16)
1040			tile_type = 1;
1041	}
1042	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1043
1044	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1045	        height = 1;
1046		depth = texture->array_size;
1047	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1048		depth = texture->array_size;
1049	}
1050
1051	view->tex_resource = &tmp->resource;
1052	view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1053				       S_030000_PITCH((pitch / 8) - 1) |
1054				       S_030000_TEX_WIDTH(width - 1));
1055	if (rscreen->chip_class == CAYMAN)
1056		view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1057	else
1058		view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1059	view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1060				       S_030004_TEX_DEPTH(depth - 1) |
1061				       S_030004_ARRAY_MODE(array_mode));
1062	view->tex_resource_words[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1063	if (state->u.tex.last_level) {
1064		view->tex_resource_words[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1065	} else {
1066		view->tex_resource_words[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1067	}
1068	view->tex_resource_words[4] = (word4 |
1069				       S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1070				       S_030010_ENDIAN_SWAP(endian) |
1071				       S_030010_BASE_LEVEL(state->u.tex.first_level));
1072	view->tex_resource_words[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1073				       S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1074				       S_030014_LAST_ARRAY(state->u.tex.last_layer));
1075	/* aniso max 16 samples */
1076	view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1077				      (S_030018_TILE_SPLIT(tile_split));
1078	view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1079				      S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1080				      S_03001C_BANK_WIDTH(bankw) |
1081				      S_03001C_BANK_HEIGHT(bankh) |
1082				      S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1083				      S_03001C_NUM_BANKS(nbanks);
1084	return &view->base;
1085}
1086
1087static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1088					   struct pipe_sampler_view **views)
1089{
1090	struct r600_context *rctx = (struct r600_context *)ctx;
1091	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
1092}
1093
1094static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1095					   struct pipe_sampler_view **views)
1096{
1097	struct r600_context *rctx = (struct r600_context *)ctx;
1098	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
1099}
1100
1101static void evergreen_set_clip_state(struct pipe_context *ctx,
1102				const struct pipe_clip_state *state)
1103{
1104	struct r600_context *rctx = (struct r600_context *)ctx;
1105	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1106	struct pipe_constant_buffer cb;
1107
1108	if (rstate == NULL)
1109		return;
1110
1111	rctx->clip = *state;
1112	rstate->id = R600_PIPE_STATE_CLIP;
1113	for (int i = 0; i < 6; i++) {
1114		r600_pipe_state_add_reg(rstate,
1115					R_0285BC_PA_CL_UCP0_X + i * 16,
1116					fui(state->ucp[i][0]));
1117		r600_pipe_state_add_reg(rstate,
1118					R_0285C0_PA_CL_UCP0_Y + i * 16,
1119					fui(state->ucp[i][1]) );
1120		r600_pipe_state_add_reg(rstate,
1121					R_0285C4_PA_CL_UCP0_Z + i * 16,
1122					fui(state->ucp[i][2]));
1123		r600_pipe_state_add_reg(rstate,
1124					R_0285C8_PA_CL_UCP0_W + i * 16,
1125					fui(state->ucp[i][3]));
1126	}
1127
1128	free(rctx->states[R600_PIPE_STATE_CLIP]);
1129	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1130	r600_context_pipe_state_set(rctx, rstate);
1131
1132	cb.buffer = NULL;
1133	cb.user_buffer = state->ucp;
1134	cb.buffer_offset = 0;
1135	cb.buffer_size = 4*4*8;
1136	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1137	pipe_resource_reference(&cb.buffer, NULL);
1138}
1139
1140static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1141					 const struct pipe_poly_stipple *state)
1142{
1143}
1144
1145static void evergreen_get_scissor_rect(struct r600_context *rctx,
1146				       unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1147				       uint32_t *tl, uint32_t *br)
1148{
1149	/* EG hw workaround */
1150	if (br_x == 0)
1151		tl_x = 1;
1152	if (br_y == 0)
1153		tl_y = 1;
1154
1155	/* cayman hw workaround */
1156	if (rctx->chip_class == CAYMAN) {
1157		if (br_x == 1 && br_y == 1)
1158			br_x = 2;
1159	}
1160
1161	*tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1162	*br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1163}
1164
1165static void evergreen_set_scissor_state(struct pipe_context *ctx,
1166					const struct pipe_scissor_state *state)
1167{
1168	struct r600_context *rctx = (struct r600_context *)ctx;
1169	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1170	uint32_t tl, br;
1171
1172	if (rstate == NULL)
1173		return;
1174
1175	evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1176
1177	rstate->id = R600_PIPE_STATE_SCISSOR;
1178	r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1179	r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1180
1181	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1182	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1183	r600_context_pipe_state_set(rctx, rstate);
1184}
1185
1186static void evergreen_set_viewport_state(struct pipe_context *ctx,
1187					const struct pipe_viewport_state *state)
1188{
1189	struct r600_context *rctx = (struct r600_context *)ctx;
1190	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1191
1192	if (rstate == NULL)
1193		return;
1194
1195	rctx->viewport = *state;
1196	rstate->id = R600_PIPE_STATE_VIEWPORT;
1197	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1198	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1199	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1200	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1201	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1202	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1203
1204	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1205	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1206	r600_context_pipe_state_set(rctx, rstate);
1207}
1208
1209void evergreen_init_color_surface(struct r600_context *rctx,
1210				  struct r600_surface *surf)
1211{
1212	struct r600_screen *rscreen = rctx->screen;
1213	struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1214	struct pipe_resource *pipe_tex = surf->base.texture;
1215	unsigned level = surf->base.u.tex.level;
1216	unsigned pitch, slice;
1217	unsigned color_info, color_attrib, color_dim = 0;
1218	unsigned format, swap, ntype, endian;
1219	uint64_t offset;
1220	unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1221	const struct util_format_description *desc;
1222	int i;
1223	bool blend_clamp = 0, blend_bypass = 0;
1224
1225	if (rtex->is_depth && !rtex->is_flushing_texture) {
1226		r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1227		rtex = rtex->flushed_depth_texture;
1228		assert(rtex);
1229	}
1230
1231	offset = rtex->surface.level[level].offset;
1232	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1233		offset += rtex->surface.level[level].slice_size *
1234			  surf->base.u.tex.first_layer;
1235	}
1236	pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1237	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1238	if (slice) {
1239		slice = slice - 1;
1240	}
1241	color_info = 0;
1242	switch (rtex->surface.level[level].mode) {
1243	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1244		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1245		tile_type = 1;
1246		break;
1247	case RADEON_SURF_MODE_1D:
1248		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1249		tile_type = rtex->tile_type;
1250		break;
1251	case RADEON_SURF_MODE_2D:
1252		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1253		tile_type = rtex->tile_type;
1254		break;
1255	case RADEON_SURF_MODE_LINEAR:
1256	default:
1257		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1258		tile_type = 1;
1259		break;
1260	}
1261	tile_split = rtex->surface.tile_split;
1262	macro_aspect = rtex->surface.mtilea;
1263	bankw = rtex->surface.bankw;
1264	bankh = rtex->surface.bankh;
1265	tile_split = eg_tile_split(tile_split);
1266	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1267	bankw = eg_bank_wh(bankw);
1268	bankh = eg_bank_wh(bankh);
1269
1270	/* 128 bit formats require tile type = 1 */
1271	if (rscreen->chip_class == CAYMAN) {
1272		if (util_format_get_blocksize(surf->base.format) >= 16)
1273			tile_type = 1;
1274	}
1275	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1276	desc = util_format_description(surf->base.format);
1277	for (i = 0; i < 4; i++) {
1278		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1279			break;
1280		}
1281	}
1282
1283	color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1284			S_028C74_NUM_BANKS(nbanks) |
1285			S_028C74_BANK_WIDTH(bankw) |
1286			S_028C74_BANK_HEIGHT(bankh) |
1287			S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1288			S_028C74_NON_DISP_TILING_ORDER(tile_type);
1289
1290	ntype = V_028C70_NUMBER_UNORM;
1291	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1292		ntype = V_028C70_NUMBER_SRGB;
1293	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1294		if (desc->channel[i].normalized)
1295			ntype = V_028C70_NUMBER_SNORM;
1296		else if (desc->channel[i].pure_integer)
1297			ntype = V_028C70_NUMBER_SINT;
1298	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1299		if (desc->channel[i].normalized)
1300			ntype = V_028C70_NUMBER_UNORM;
1301		else if (desc->channel[i].pure_integer)
1302			ntype = V_028C70_NUMBER_UINT;
1303	}
1304
1305	format = r600_translate_colorformat(surf->base.format);
1306	assert(format != ~0);
1307
1308	swap = r600_translate_colorswap(surf->base.format);
1309	assert(swap != ~0);
1310
1311	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1312		endian = ENDIAN_NONE;
1313	} else {
1314		endian = r600_colorformat_endian_swap(format);
1315	}
1316
1317	/* blend clamp should be set for all NORM/SRGB types */
1318	if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1319	    ntype == V_028C70_NUMBER_SRGB)
1320		blend_clamp = 1;
1321
1322	/* set blend bypass according to docs if SINT/UINT or
1323	   8/24 COLOR variants */
1324	if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1325	    format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1326	    format == V_028C70_COLOR_X24_8_32_FLOAT) {
1327		blend_clamp = 0;
1328		blend_bypass = 1;
1329	}
1330
1331	surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1332
1333	color_info |= S_028C70_FORMAT(format) |
1334		S_028C70_COMP_SWAP(swap) |
1335		S_028C70_BLEND_CLAMP(blend_clamp) |
1336		S_028C70_BLEND_BYPASS(blend_bypass) |
1337		S_028C70_NUMBER_TYPE(ntype) |
1338		S_028C70_ENDIAN(endian);
1339
1340	if (rtex->is_rat) {
1341		color_info |= S_028C70_RAT(1);
1342		color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1343				| S_028C78_HEIGHT_MAX(pipe_tex->height0);
1344	}
1345
1346	/* EXPORT_NORM is an optimzation that can be enabled for better
1347	 * performance in certain cases.
1348	 * EXPORT_NORM can be enabled if:
1349	 * - 11-bit or smaller UNORM/SNORM/SRGB
1350	 * - 16-bit or smaller FLOAT
1351	 */
1352	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1353	    ((desc->channel[i].size < 12 &&
1354	      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1355	      ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1356	     (desc->channel[i].size < 17 &&
1357	      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1358		color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1359		surf->export_16bpc = true;
1360	}
1361
1362	offset += r600_resource_va(rctx->context.screen, pipe_tex);
1363	offset >>= 8;
1364
1365	/* XXX handle enabling of CB beyond BASE8 which has different offset */
1366	surf->cb_color_base = offset;
1367	surf->cb_color_dim = color_dim;
1368	surf->cb_color_info = color_info;
1369	surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1370	surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1371	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1372		surf->cb_color_view = 0;
1373	} else {
1374		surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1375				      S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1376	}
1377	surf->cb_color_attrib = color_attrib;
1378
1379	surf->color_initialized = true;
1380}
1381
1382static void evergreen_init_depth_surface(struct r600_context *rctx,
1383					 struct r600_surface *surf)
1384{
1385	struct r600_screen *rscreen = rctx->screen;
1386	struct pipe_screen *screen = &rscreen->screen;
1387	struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1388	uint64_t offset;
1389	unsigned level, pitch, slice, format, array_mode;
1390	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1391
1392	level = surf->base.u.tex.level;
1393	format = r600_translate_dbformat(surf->base.format);
1394	assert(format != ~0);
1395
1396	offset = r600_resource_va(screen, surf->base.texture);
1397	offset += rtex->surface.level[level].offset;
1398	pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1399	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1400	if (slice) {
1401		slice = slice - 1;
1402	}
1403	switch (rtex->surface.level[level].mode) {
1404	case RADEON_SURF_MODE_2D:
1405		array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1406		break;
1407	case RADEON_SURF_MODE_1D:
1408	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1409	case RADEON_SURF_MODE_LINEAR:
1410	default:
1411		array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1412		break;
1413	}
1414	tile_split = rtex->surface.tile_split;
1415	macro_aspect = rtex->surface.mtilea;
1416	bankw = rtex->surface.bankw;
1417	bankh = rtex->surface.bankh;
1418	tile_split = eg_tile_split(tile_split);
1419	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1420	bankw = eg_bank_wh(bankw);
1421	bankh = eg_bank_wh(bankh);
1422	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1423	offset >>= 8;
1424
1425	surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1426			      S_028040_FORMAT(format) |
1427			      S_028040_TILE_SPLIT(tile_split)|
1428			      S_028040_NUM_BANKS(nbanks) |
1429			      S_028040_BANK_WIDTH(bankw) |
1430			      S_028040_BANK_HEIGHT(bankh) |
1431			      S_028040_MACRO_TILE_ASPECT(macro_aspect);
1432	surf->db_depth_base = offset;
1433	surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1434			      S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1435	surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1436	surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1437
1438	if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1439		uint64_t stencil_offset = rtex->surface.stencil_offset;
1440		unsigned stile_split = rtex->surface.stencil_tile_split;
1441
1442		stile_split = eg_tile_split(stile_split);
1443		stencil_offset += r600_resource_va(screen, surf->base.texture);
1444		stencil_offset += rtex->surface.level[level].offset / 4;
1445		stencil_offset >>= 8;
1446
1447		surf->db_stencil_base = stencil_offset;
1448		surf->db_stencil_info = 1 | S_028044_TILE_SPLIT(stile_split);
1449	} else {
1450		surf->db_stencil_base = offset;
1451		surf->db_stencil_info = 1;
1452	}
1453
1454	surf->depth_initialized = true;
1455}
1456
1457static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1458					    const struct pipe_framebuffer_state *state)
1459{
1460	struct r600_context *rctx = (struct r600_context *)ctx;
1461	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1462	struct r600_surface *surf;
1463	struct r600_resource *res;
1464	uint32_t tl, br;
1465	int i;
1466
1467	if (rstate == NULL)
1468		return;
1469
1470	r600_flush_framebuffer(rctx, false);
1471
1472	/* unreference old buffer and reference new one */
1473	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1474
1475	util_copy_framebuffer_state(&rctx->framebuffer, state);
1476
1477	/* build states */
1478	rctx->export_16bpc = true;
1479	rctx->nr_cbufs = state->nr_cbufs;
1480	rctx->cb0_is_integer = state->nr_cbufs &&
1481			       util_format_is_pure_integer(state->cbufs[0]->format);
1482
1483	for (i = 0; i < state->nr_cbufs; i++) {
1484		surf = (struct r600_surface*)state->cbufs[i];
1485		res = (struct r600_resource*)surf->base.texture;
1486
1487		if (!surf->color_initialized) {
1488			evergreen_init_color_surface(rctx, surf);
1489		}
1490
1491		if (!surf->export_16bpc) {
1492			rctx->export_16bpc = false;
1493		}
1494
1495		r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C,
1496					   surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1497		r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + i * 0x3C,
1498					surf->cb_color_dim);
1499		r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1500					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1501		r600_pipe_state_add_reg(rstate, R_028C64_CB_COLOR0_PITCH + i * 0x3C,
1502					surf->cb_color_pitch);
1503		r600_pipe_state_add_reg(rstate, R_028C68_CB_COLOR0_SLICE + i * 0x3C,
1504					surf->cb_color_slice);
1505		r600_pipe_state_add_reg(rstate, R_028C6C_CB_COLOR0_VIEW + i * 0x3C,
1506					surf->cb_color_view);
1507		r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C,
1508					   surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
1509	}
1510	/* set CB_COLOR1_INFO for possible dual-src blending */
1511	if (i == 1 && !((struct r600_resource_texture*)res)->is_rat) {
1512		r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1513					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1514		i++;
1515	}
1516	for (; i < 8 ; i++) {
1517		r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1518	}
1519
1520	/* Update alpha-test state dependencies.
1521	 * Alpha-test is done on the first colorbuffer only. */
1522	if (state->nr_cbufs) {
1523		surf = (struct r600_surface*)state->cbufs[0];
1524		if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1525			rctx->alphatest_state.bypass = surf->alphatest_bypass;
1526			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1527		}
1528		if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1529			rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1530			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1531		}
1532	}
1533
1534	if (state->zsbuf) {
1535		surf = (struct r600_surface*)state->zsbuf;
1536		res = (struct r600_resource*)surf->base.texture;
1537
1538		if (!surf->depth_initialized) {
1539			evergreen_init_depth_surface(rctx, surf);
1540		}
1541
1542		r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1543					   res, RADEON_USAGE_READWRITE);
1544		r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1545					   res, RADEON_USAGE_READWRITE);
1546		r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1547
1548		r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1549					   res, RADEON_USAGE_READWRITE);
1550		r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1551					   res, RADEON_USAGE_READWRITE);
1552		r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1553					   res, RADEON_USAGE_READWRITE);
1554
1555		r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1556					   res, RADEON_USAGE_READWRITE);
1557		r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1558		r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
1559	}
1560
1561	evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1562
1563	r600_pipe_state_add_reg(rstate,
1564				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1565	r600_pipe_state_add_reg(rstate,
1566				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1567
1568	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1569	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1570	r600_context_pipe_state_set(rctx, rstate);
1571
1572	if (state->zsbuf) {
1573		evergreen_polygon_offset_update(rctx);
1574	}
1575
1576	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1577		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1578		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1579	}
1580
1581	if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1582		rctx->alphatest_state.bypass = false;
1583		r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1584	}
1585}
1586
1587static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1588{
1589	struct radeon_winsys_cs *cs = rctx->cs;
1590	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1591	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1592	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1593
1594	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1595	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1596	/* Always enable the first colorbuffer in CB_SHADER_MASK. This
1597	 * will assure that the alpha-test will work even if there is
1598	 * no colorbuffer bound. */
1599	r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1600}
1601
1602static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1603{
1604	struct radeon_winsys_cs *cs = rctx->cs;
1605	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1606	unsigned db_render_control = 0;
1607	unsigned db_count_control = 0;
1608	unsigned db_render_override =
1609		S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1610		S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1611		S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1612
1613	if (a->occlusion_query_enabled) {
1614		db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1615		db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1616	}
1617
1618	if (a->flush_depthstencil_through_cb) {
1619		assert(a->copy_depth || a->copy_stencil);
1620
1621		db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1622				     S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1623				     S_028000_COPY_CENTROID(1);
1624	}
1625
1626	r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1627	r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1628	r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1629	r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1630}
1631
1632static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1633					  struct r600_vertexbuf_state *state,
1634					  unsigned resource_offset,
1635					  unsigned pkt_flags)
1636{
1637	struct radeon_winsys_cs *cs = rctx->cs;
1638	uint32_t dirty_mask = state->dirty_mask;
1639
1640	while (dirty_mask) {
1641		struct pipe_vertex_buffer *vb;
1642		struct r600_resource *rbuffer;
1643		uint64_t va;
1644		unsigned buffer_index = u_bit_scan(&dirty_mask);
1645
1646		vb = &state->vb[buffer_index];
1647		rbuffer = (struct r600_resource*)vb->buffer;
1648		assert(rbuffer);
1649
1650		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1651		va += vb->buffer_offset;
1652
1653		/* fetch resources start at index 992 */
1654		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1655		r600_write_value(cs, (resource_offset + buffer_index) * 8);
1656		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1657		r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1658		r600_write_value(cs, /* RESOURCEi_WORD2 */
1659				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1660				 S_030008_STRIDE(vb->stride) |
1661				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1662		r600_write_value(cs, /* RESOURCEi_WORD3 */
1663				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1664				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1665				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1666				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1667		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1668		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1669		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1670		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1671
1672		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1673		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1674	}
1675	state->dirty_mask = 0;
1676}
1677
1678static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1679{
1680	evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1681}
1682
1683static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1684{
1685	evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1686				      RADEON_CP_PACKET3_COMPUTE_MODE);
1687}
1688
1689static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1690					    struct r600_constbuf_state *state,
1691					    unsigned buffer_id_base,
1692					    unsigned reg_alu_constbuf_size,
1693					    unsigned reg_alu_const_cache)
1694{
1695	struct radeon_winsys_cs *cs = rctx->cs;
1696	uint32_t dirty_mask = state->dirty_mask;
1697
1698	while (dirty_mask) {
1699		struct pipe_constant_buffer *cb;
1700		struct r600_resource *rbuffer;
1701		uint64_t va;
1702		unsigned buffer_index = ffs(dirty_mask) - 1;
1703
1704		cb = &state->cb[buffer_index];
1705		rbuffer = (struct r600_resource*)cb->buffer;
1706		assert(rbuffer);
1707
1708		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1709		va += cb->buffer_offset;
1710
1711		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1712				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1713		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1714
1715		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1716		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1717
1718		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1719		r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1720		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1721		r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1722		r600_write_value(cs, /* RESOURCEi_WORD2 */
1723				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1724				 S_030008_STRIDE(16) |
1725				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1726		r600_write_value(cs, /* RESOURCEi_WORD3 */
1727				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1728				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1729				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1730				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1731		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1732		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1733		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1734		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1735
1736		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1737		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1738
1739		dirty_mask &= ~(1 << buffer_index);
1740	}
1741	state->dirty_mask = 0;
1742}
1743
1744static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1745{
1746	evergreen_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 176,
1747					R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1748					R_028980_ALU_CONST_CACHE_VS_0);
1749}
1750
1751static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1752{
1753	evergreen_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1754				       R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1755				       R_028940_ALU_CONST_CACHE_PS_0);
1756}
1757
1758static void evergreen_emit_sampler_views(struct r600_context *rctx,
1759					 struct r600_samplerview_state *state,
1760					 unsigned resource_id_base)
1761{
1762	struct radeon_winsys_cs *cs = rctx->cs;
1763	uint32_t dirty_mask = state->dirty_mask;
1764
1765	while (dirty_mask) {
1766		struct r600_pipe_sampler_view *rview;
1767		unsigned resource_index = u_bit_scan(&dirty_mask);
1768		unsigned reloc;
1769
1770		rview = state->views[resource_index];
1771		assert(rview);
1772
1773		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1774		r600_write_value(cs, (resource_id_base + resource_index) * 8);
1775		r600_write_array(cs, 8, rview->tex_resource_words);
1776
1777		/* XXX The kernel needs two relocations. This is stupid. */
1778		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1779					      RADEON_USAGE_READ);
1780		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1781		r600_write_value(cs, reloc);
1782		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1783		r600_write_value(cs, reloc);
1784	}
1785	state->dirty_mask = 0;
1786}
1787
1788static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1789{
1790	evergreen_emit_sampler_views(rctx, &rctx->vs_samplers.views, 176 + R600_MAX_CONST_BUFFERS);
1791}
1792
1793static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1794{
1795	evergreen_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1796}
1797
1798static void evergreen_emit_sampler(struct r600_context *rctx,
1799				struct r600_textures_info *texinfo,
1800				unsigned resource_id_base,
1801				unsigned border_index_reg)
1802{
1803	struct radeon_winsys_cs *cs = rctx->cs;
1804	unsigned i;
1805
1806	for (i = 0; i < texinfo->n_samplers; i++) {
1807
1808		if (texinfo->samplers[i] == NULL) {
1809			continue;
1810		}
1811		r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1812		r600_write_value(cs, (resource_id_base + i) * 3);
1813		r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1814
1815		if (texinfo->samplers[i]->border_color_use) {
1816			r600_write_config_reg_seq(cs, border_index_reg, 5);
1817			r600_write_value(cs, i);
1818			r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
1819		}
1820	}
1821}
1822
1823static void evergreen_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
1824{
1825	evergreen_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
1826}
1827
1828static void evergreen_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
1829{
1830	evergreen_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
1831}
1832
1833static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1834{
1835	struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1836	uint8_t mask = s->sample_mask;
1837
1838	r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
1839			       mask | (mask << 8) | (mask << 16) | (mask << 24));
1840}
1841
1842static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1843{
1844	struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1845	struct radeon_winsys_cs *cs = rctx->cs;
1846	uint16_t mask = s->sample_mask;
1847
1848	r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
1849	r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
1850	r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
1851}
1852
1853void evergreen_init_state_functions(struct r600_context *rctx)
1854{
1855	r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
1856	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1857	r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 7, 0);
1858	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1859	r600_init_atom(&rctx->vertex_buffer_state.atom, evergreen_fs_emit_vertex_buffers, 0, 0);
1860	r600_init_atom(&rctx->cs_vertex_buffer_state.atom, evergreen_cs_emit_vertex_buffers, 0, 0);
1861	r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
1862	r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
1863	r600_init_atom(&rctx->vs_samplers.views.atom, evergreen_emit_vs_sampler_views, 0, 0);
1864	r600_init_atom(&rctx->ps_samplers.views.atom, evergreen_emit_ps_sampler_views, 0, 0);
1865	r600_init_atom(&rctx->cs_shader_state.atom, evergreen_emit_cs_shader, 0, 0);
1866	r600_init_atom(&rctx->vs_samplers.atom_sampler, evergreen_emit_vs_sampler, 0, 0);
1867	r600_init_atom(&rctx->ps_samplers.atom_sampler, evergreen_emit_ps_sampler, 0, 0);
1868
1869	if (rctx->chip_class == EVERGREEN)
1870		r600_init_atom(&rctx->sample_mask.atom, evergreen_emit_sample_mask, 3, 0);
1871	else
1872		r600_init_atom(&rctx->sample_mask.atom, cayman_emit_sample_mask, 4, 0);
1873	rctx->sample_mask.sample_mask = ~0;
1874	r600_atom_dirty(rctx, &rctx->sample_mask.atom);
1875
1876	rctx->context.create_blend_state = evergreen_create_blend_state;
1877	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1878	rctx->context.create_fs_state = r600_create_shader_state_ps;
1879	rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1880	rctx->context.create_sampler_state = evergreen_create_sampler_state;
1881	rctx->context.create_sampler_view = evergreen_create_sampler_view;
1882	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1883	rctx->context.create_vs_state = r600_create_shader_state_vs;
1884	rctx->context.bind_blend_state = r600_bind_blend_state;
1885	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1886	rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1887	rctx->context.bind_fs_state = r600_bind_ps_shader;
1888	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1889	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1890	rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1891	rctx->context.bind_vs_state = r600_bind_vs_shader;
1892	rctx->context.delete_blend_state = r600_delete_state;
1893	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1894	rctx->context.delete_fs_state = r600_delete_ps_shader;
1895	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1896	rctx->context.delete_sampler_state = r600_delete_sampler;
1897	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1898	rctx->context.delete_vs_state = r600_delete_vs_shader;
1899	rctx->context.set_blend_color = r600_set_blend_color;
1900	rctx->context.set_clip_state = evergreen_set_clip_state;
1901	rctx->context.set_constant_buffer = r600_set_constant_buffer;
1902	rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_views;
1903	rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1904	rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1905	rctx->context.set_sample_mask = r600_set_sample_mask;
1906	rctx->context.set_scissor_state = evergreen_set_scissor_state;
1907	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1908	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1909	rctx->context.set_index_buffer = r600_set_index_buffer;
1910	rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_views;
1911	rctx->context.set_viewport_state = evergreen_set_viewport_state;
1912	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1913	rctx->context.texture_barrier = r600_texture_barrier;
1914	rctx->context.create_stream_output_target = r600_create_so_target;
1915	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1916	rctx->context.set_stream_output_targets = r600_set_so_targets;
1917	evergreen_init_compute_state_functions(rctx);
1918}
1919
1920static void cayman_init_atom_start_cs(struct r600_context *rctx)
1921{
1922	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1923
1924	r600_init_command_buffer(cb, 256, EMIT_EARLY);
1925
1926	/* This must be first. */
1927	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1928	r600_store_value(cb, 0x80000000);
1929	r600_store_value(cb, 0x80000000);
1930
1931	r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1932	r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1933	/* always set the temp clauses */
1934	r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1935
1936	r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1937	r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1938	r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1939
1940	r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1941
1942	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1943
1944	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1945	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1946	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1947	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1948	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1949	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1950	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1951	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1952	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1953	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1954	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1955	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1956	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1957	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1958
1959	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1960	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1961	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1962
1963	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1964	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1965	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1966
1967	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1968
1969	r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1970
1971	r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1972	r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1973	r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1974
1975	r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1976	r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1977	r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1978
1979	r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1980
1981	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1982	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1983	r600_store_value(cb, 0);
1984	r600_store_value(cb, 0);
1985	r600_store_value(cb, 0);
1986	r600_store_value(cb, 0);
1987	r600_store_value(cb, 0);
1988	r600_store_value(cb, 0);
1989	r600_store_value(cb, 0);
1990	r600_store_value(cb, 0);
1991	r600_store_value(cb, 0);
1992	r600_store_value(cb, 0);
1993	r600_store_value(cb, 0);
1994	r600_store_value(cb, 0);
1995	r600_store_value(cb, 0);
1996	r600_store_value(cb, 0);
1997	r600_store_value(cb, 0);
1998	r600_store_value(cb, 0);
1999	r600_store_value(cb, 0);
2000	r600_store_value(cb, 0);
2001	r600_store_value(cb, 0);
2002	r600_store_value(cb, 0);
2003	r600_store_value(cb, 0);
2004	r600_store_value(cb, 0);
2005	r600_store_value(cb, 0);
2006	r600_store_value(cb, 0);
2007	r600_store_value(cb, 0);
2008	r600_store_value(cb, 0);
2009	r600_store_value(cb, 0);
2010	r600_store_value(cb, 0);
2011	r600_store_value(cb, 0);
2012	r600_store_value(cb, 0);
2013	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2014	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2015	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2016
2017	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2018
2019	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2020	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2021	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2022
2023	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2024
2025	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2026	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2027	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2028	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2029
2030	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2031	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2032
2033	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2034	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2035	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2036
2037	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2038	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2039	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2040
2041	r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2042	r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2043	r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2044
2045	r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2046	r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2047	r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2048	r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2049	r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2050
2051	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2052	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2053	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2054
2055	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2056	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2057	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2058
2059	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2060	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2061	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2062
2063	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2064	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2065	if (rctx->screen->has_streamout) {
2066		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2067	}
2068
2069	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2070	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2071}
2072
2073void evergreen_init_atom_start_cs(struct r600_context *rctx)
2074{
2075	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2076	int ps_prio;
2077	int vs_prio;
2078	int gs_prio;
2079	int es_prio;
2080	int hs_prio, cs_prio, ls_prio;
2081	int num_ps_gprs;
2082	int num_vs_gprs;
2083	int num_gs_gprs;
2084	int num_es_gprs;
2085	int num_hs_gprs;
2086	int num_ls_gprs;
2087	int num_temp_gprs;
2088	int num_ps_threads;
2089	int num_vs_threads;
2090	int num_gs_threads;
2091	int num_es_threads;
2092	int num_hs_threads;
2093	int num_ls_threads;
2094	int num_ps_stack_entries;
2095	int num_vs_stack_entries;
2096	int num_gs_stack_entries;
2097	int num_es_stack_entries;
2098	int num_hs_stack_entries;
2099	int num_ls_stack_entries;
2100	enum radeon_family family;
2101	unsigned tmp;
2102
2103	if (rctx->chip_class == CAYMAN) {
2104		cayman_init_atom_start_cs(rctx);
2105		return;
2106	}
2107
2108	r600_init_command_buffer(cb, 256, EMIT_EARLY);
2109
2110	/* This must be first. */
2111	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2112	r600_store_value(cb, 0x80000000);
2113	r600_store_value(cb, 0x80000000);
2114
2115	family = rctx->family;
2116	ps_prio = 0;
2117	vs_prio = 1;
2118	gs_prio = 2;
2119	es_prio = 3;
2120	hs_prio = 0;
2121	ls_prio = 0;
2122	cs_prio = 0;
2123
2124	switch (family) {
2125	case CHIP_CEDAR:
2126	default:
2127		num_ps_gprs = 93;
2128		num_vs_gprs = 46;
2129		num_temp_gprs = 4;
2130		num_gs_gprs = 31;
2131		num_es_gprs = 31;
2132		num_hs_gprs = 23;
2133		num_ls_gprs = 23;
2134		num_ps_threads = 96;
2135		num_vs_threads = 16;
2136		num_gs_threads = 16;
2137		num_es_threads = 16;
2138		num_hs_threads = 16;
2139		num_ls_threads = 16;
2140		num_ps_stack_entries = 42;
2141		num_vs_stack_entries = 42;
2142		num_gs_stack_entries = 42;
2143		num_es_stack_entries = 42;
2144		num_hs_stack_entries = 42;
2145		num_ls_stack_entries = 42;
2146		break;
2147	case CHIP_REDWOOD:
2148		num_ps_gprs = 93;
2149		num_vs_gprs = 46;
2150		num_temp_gprs = 4;
2151		num_gs_gprs = 31;
2152		num_es_gprs = 31;
2153		num_hs_gprs = 23;
2154		num_ls_gprs = 23;
2155		num_ps_threads = 128;
2156		num_vs_threads = 20;
2157		num_gs_threads = 20;
2158		num_es_threads = 20;
2159		num_hs_threads = 20;
2160		num_ls_threads = 20;
2161		num_ps_stack_entries = 42;
2162		num_vs_stack_entries = 42;
2163		num_gs_stack_entries = 42;
2164		num_es_stack_entries = 42;
2165		num_hs_stack_entries = 42;
2166		num_ls_stack_entries = 42;
2167		break;
2168	case CHIP_JUNIPER:
2169		num_ps_gprs = 93;
2170		num_vs_gprs = 46;
2171		num_temp_gprs = 4;
2172		num_gs_gprs = 31;
2173		num_es_gprs = 31;
2174		num_hs_gprs = 23;
2175		num_ls_gprs = 23;
2176		num_ps_threads = 128;
2177		num_vs_threads = 20;
2178		num_gs_threads = 20;
2179		num_es_threads = 20;
2180		num_hs_threads = 20;
2181		num_ls_threads = 20;
2182		num_ps_stack_entries = 85;
2183		num_vs_stack_entries = 85;
2184		num_gs_stack_entries = 85;
2185		num_es_stack_entries = 85;
2186		num_hs_stack_entries = 85;
2187		num_ls_stack_entries = 85;
2188		break;
2189	case CHIP_CYPRESS:
2190	case CHIP_HEMLOCK:
2191		num_ps_gprs = 93;
2192		num_vs_gprs = 46;
2193		num_temp_gprs = 4;
2194		num_gs_gprs = 31;
2195		num_es_gprs = 31;
2196		num_hs_gprs = 23;
2197		num_ls_gprs = 23;
2198		num_ps_threads = 128;
2199		num_vs_threads = 20;
2200		num_gs_threads = 20;
2201		num_es_threads = 20;
2202		num_hs_threads = 20;
2203		num_ls_threads = 20;
2204		num_ps_stack_entries = 85;
2205		num_vs_stack_entries = 85;
2206		num_gs_stack_entries = 85;
2207		num_es_stack_entries = 85;
2208		num_hs_stack_entries = 85;
2209		num_ls_stack_entries = 85;
2210		break;
2211	case CHIP_PALM:
2212		num_ps_gprs = 93;
2213		num_vs_gprs = 46;
2214		num_temp_gprs = 4;
2215		num_gs_gprs = 31;
2216		num_es_gprs = 31;
2217		num_hs_gprs = 23;
2218		num_ls_gprs = 23;
2219		num_ps_threads = 96;
2220		num_vs_threads = 16;
2221		num_gs_threads = 16;
2222		num_es_threads = 16;
2223		num_hs_threads = 16;
2224		num_ls_threads = 16;
2225		num_ps_stack_entries = 42;
2226		num_vs_stack_entries = 42;
2227		num_gs_stack_entries = 42;
2228		num_es_stack_entries = 42;
2229		num_hs_stack_entries = 42;
2230		num_ls_stack_entries = 42;
2231		break;
2232	case CHIP_SUMO:
2233		num_ps_gprs = 93;
2234		num_vs_gprs = 46;
2235		num_temp_gprs = 4;
2236		num_gs_gprs = 31;
2237		num_es_gprs = 31;
2238		num_hs_gprs = 23;
2239		num_ls_gprs = 23;
2240		num_ps_threads = 96;
2241		num_vs_threads = 25;
2242		num_gs_threads = 25;
2243		num_es_threads = 25;
2244		num_hs_threads = 25;
2245		num_ls_threads = 25;
2246		num_ps_stack_entries = 42;
2247		num_vs_stack_entries = 42;
2248		num_gs_stack_entries = 42;
2249		num_es_stack_entries = 42;
2250		num_hs_stack_entries = 42;
2251		num_ls_stack_entries = 42;
2252		break;
2253	case CHIP_SUMO2:
2254		num_ps_gprs = 93;
2255		num_vs_gprs = 46;
2256		num_temp_gprs = 4;
2257		num_gs_gprs = 31;
2258		num_es_gprs = 31;
2259		num_hs_gprs = 23;
2260		num_ls_gprs = 23;
2261		num_ps_threads = 96;
2262		num_vs_threads = 25;
2263		num_gs_threads = 25;
2264		num_es_threads = 25;
2265		num_hs_threads = 25;
2266		num_ls_threads = 25;
2267		num_ps_stack_entries = 85;
2268		num_vs_stack_entries = 85;
2269		num_gs_stack_entries = 85;
2270		num_es_stack_entries = 85;
2271		num_hs_stack_entries = 85;
2272		num_ls_stack_entries = 85;
2273		break;
2274	case CHIP_BARTS:
2275		num_ps_gprs = 93;
2276		num_vs_gprs = 46;
2277		num_temp_gprs = 4;
2278		num_gs_gprs = 31;
2279		num_es_gprs = 31;
2280		num_hs_gprs = 23;
2281		num_ls_gprs = 23;
2282		num_ps_threads = 128;
2283		num_vs_threads = 20;
2284		num_gs_threads = 20;
2285		num_es_threads = 20;
2286		num_hs_threads = 20;
2287		num_ls_threads = 20;
2288		num_ps_stack_entries = 85;
2289		num_vs_stack_entries = 85;
2290		num_gs_stack_entries = 85;
2291		num_es_stack_entries = 85;
2292		num_hs_stack_entries = 85;
2293		num_ls_stack_entries = 85;
2294		break;
2295	case CHIP_TURKS:
2296		num_ps_gprs = 93;
2297		num_vs_gprs = 46;
2298		num_temp_gprs = 4;
2299		num_gs_gprs = 31;
2300		num_es_gprs = 31;
2301		num_hs_gprs = 23;
2302		num_ls_gprs = 23;
2303		num_ps_threads = 128;
2304		num_vs_threads = 20;
2305		num_gs_threads = 20;
2306		num_es_threads = 20;
2307		num_hs_threads = 20;
2308		num_ls_threads = 20;
2309		num_ps_stack_entries = 42;
2310		num_vs_stack_entries = 42;
2311		num_gs_stack_entries = 42;
2312		num_es_stack_entries = 42;
2313		num_hs_stack_entries = 42;
2314		num_ls_stack_entries = 42;
2315		break;
2316	case CHIP_CAICOS:
2317		num_ps_gprs = 93;
2318		num_vs_gprs = 46;
2319		num_temp_gprs = 4;
2320		num_gs_gprs = 31;
2321		num_es_gprs = 31;
2322		num_hs_gprs = 23;
2323		num_ls_gprs = 23;
2324		num_ps_threads = 128;
2325		num_vs_threads = 10;
2326		num_gs_threads = 10;
2327		num_es_threads = 10;
2328		num_hs_threads = 10;
2329		num_ls_threads = 10;
2330		num_ps_stack_entries = 42;
2331		num_vs_stack_entries = 42;
2332		num_gs_stack_entries = 42;
2333		num_es_stack_entries = 42;
2334		num_hs_stack_entries = 42;
2335		num_ls_stack_entries = 42;
2336		break;
2337	}
2338
2339	tmp = 0;
2340	switch (family) {
2341	case CHIP_CEDAR:
2342	case CHIP_PALM:
2343	case CHIP_SUMO:
2344	case CHIP_SUMO2:
2345	case CHIP_CAICOS:
2346		break;
2347	default:
2348		tmp |= S_008C00_VC_ENABLE(1);
2349		break;
2350	}
2351	tmp |= S_008C00_EXPORT_SRC_C(1);
2352	tmp |= S_008C00_CS_PRIO(cs_prio);
2353	tmp |= S_008C00_LS_PRIO(ls_prio);
2354	tmp |= S_008C00_HS_PRIO(hs_prio);
2355	tmp |= S_008C00_PS_PRIO(ps_prio);
2356	tmp |= S_008C00_VS_PRIO(vs_prio);
2357	tmp |= S_008C00_GS_PRIO(gs_prio);
2358	tmp |= S_008C00_ES_PRIO(es_prio);
2359
2360	/* enable dynamic GPR resource management */
2361	if (rctx->screen->info.drm_minor >= 7) {
2362		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2363		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2364		/* always set temp clauses */
2365		r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2366		r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2367		r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2368		r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2369		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2370		r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2371					S_028838_PS_GPRS(0x1e) |
2372					S_028838_VS_GPRS(0x1e) |
2373					S_028838_GS_GPRS(0x1e) |
2374					S_028838_ES_GPRS(0x1e) |
2375					S_028838_HS_GPRS(0x1e) |
2376					S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2377	} else {
2378		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2379		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2380
2381		tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2382		tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2383		tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2384		r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2385
2386		tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2387		tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2388		r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2389
2390		tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2391		tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2392		r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2393	}
2394
2395	tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2396	tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2397	tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2398	tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2399	r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2400	r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2401
2402	tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2403	tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2404	r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2405
2406	tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2407	tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2408	r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2409
2410	tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2411	tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2412	r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2413
2414	tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2415	tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2416	r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2417
2418	r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2419			      S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2420
2421	r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2422	r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2423
2424	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2425
2426	r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2427	r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2428	r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2429	r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2430	r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2431	r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2432	r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2433
2434	r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2435	r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2436	r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2437	r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2438	r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2439
2440	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2441	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2442	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2443	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2444	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2445	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2446	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2447	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2448	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2449	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2450	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2451	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2452	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2453	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2454
2455	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2456	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2457	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2458
2459	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2460	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2461	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2462
2463	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2464
2465	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2466	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2467	r600_store_value(cb, 0);
2468	r600_store_value(cb, 0);
2469	r600_store_value(cb, 0);
2470	r600_store_value(cb, 0);
2471	r600_store_value(cb, 0);
2472	r600_store_value(cb, 0);
2473	r600_store_value(cb, 0);
2474	r600_store_value(cb, 0);
2475	r600_store_value(cb, 0);
2476	r600_store_value(cb, 0);
2477	r600_store_value(cb, 0);
2478	r600_store_value(cb, 0);
2479	r600_store_value(cb, 0);
2480	r600_store_value(cb, 0);
2481	r600_store_value(cb, 0);
2482	r600_store_value(cb, 0);
2483	r600_store_value(cb, 0);
2484	r600_store_value(cb, 0);
2485	r600_store_value(cb, 0);
2486	r600_store_value(cb, 0);
2487	r600_store_value(cb, 0);
2488	r600_store_value(cb, 0);
2489	r600_store_value(cb, 0);
2490	r600_store_value(cb, 0);
2491	r600_store_value(cb, 0);
2492	r600_store_value(cb, 0);
2493	r600_store_value(cb, 0);
2494	r600_store_value(cb, 0);
2495	r600_store_value(cb, 0);
2496	r600_store_value(cb, 0);
2497	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2498	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2499	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2500
2501	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2502
2503	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2504	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2505	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2506
2507	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2508	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2509	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2510
2511	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2512	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2513	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2514
2515	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2516	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2517	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2518
2519	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2520	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2521	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2522	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2523
2524	r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2525	r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2526	r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2527
2528	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2529	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2530	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2531	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2532	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2533	r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2534
2535	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2536	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2537	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2538
2539	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2540	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2541	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2542
2543	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2544	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2545	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2546
2547	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2548	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2549	if (rctx->screen->has_streamout) {
2550		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2551	}
2552
2553	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2554	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2555}
2556
2557void evergreen_polygon_offset_update(struct r600_context *rctx)
2558{
2559	struct r600_pipe_state state;
2560
2561	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2562	state.nregs = 0;
2563	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2564		float offset_units = rctx->rasterizer->offset_units;
2565		unsigned offset_db_fmt_cntl = 0, depth;
2566
2567		switch (rctx->framebuffer.zsbuf->format) {
2568		case PIPE_FORMAT_Z24X8_UNORM:
2569		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2570			depth = -24;
2571			offset_units *= 2.0f;
2572			break;
2573		case PIPE_FORMAT_Z32_FLOAT:
2574		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2575			depth = -23;
2576			offset_units *= 1.0f;
2577			offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2578			break;
2579		case PIPE_FORMAT_Z16_UNORM:
2580			depth = -16;
2581			offset_units *= 4.0f;
2582			break;
2583		default:
2584			return;
2585		}
2586		/* XXX some of those reg can be computed with cso */
2587		offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2588		r600_pipe_state_add_reg(&state,
2589				R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2590				fui(rctx->rasterizer->offset_scale));
2591		r600_pipe_state_add_reg(&state,
2592				R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2593				fui(offset_units));
2594		r600_pipe_state_add_reg(&state,
2595				R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2596				fui(rctx->rasterizer->offset_scale));
2597		r600_pipe_state_add_reg(&state,
2598				R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2599				fui(offset_units));
2600		r600_pipe_state_add_reg(&state,
2601				R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2602				offset_db_fmt_cntl);
2603		r600_context_pipe_state_set(rctx, &state);
2604	}
2605}
2606
2607void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2608{
2609	struct r600_context *rctx = (struct r600_context *)ctx;
2610	struct r600_pipe_state *rstate = &shader->rstate;
2611	struct r600_shader *rshader = &shader->shader;
2612	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2613	int pos_index = -1, face_index = -1;
2614	int ninterp = 0;
2615	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2616	unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2617	unsigned z_export = 0, stencil_export = 0;
2618
2619	rstate->nregs = 0;
2620
2621	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2622	for (i = 0; i < rshader->ninput; i++) {
2623		/* evergreen NUM_INTERP only contains values interpolated into the LDS,
2624		   POSITION goes via GPRs from the SC so isn't counted */
2625		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2626			pos_index = i;
2627		else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2628			face_index = i;
2629		else {
2630			ninterp++;
2631			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2632				have_linear = TRUE;
2633			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2634				have_perspective = TRUE;
2635			if (rshader->input[i].centroid)
2636				have_centroid = TRUE;
2637		}
2638
2639		sid = rshader->input[i].spi_sid;
2640
2641		if (sid) {
2642
2643			tmp = S_028644_SEMANTIC(sid);
2644
2645			if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2646				rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2647				(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2648					rctx->rasterizer && rctx->rasterizer->flatshade)) {
2649				tmp |= S_028644_FLAT_SHADE(1);
2650			}
2651
2652			if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2653					(rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2654				tmp |= S_028644_PT_SPRITE_TEX(1);
2655			}
2656
2657			r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2658					tmp);
2659
2660			idx++;
2661		}
2662	}
2663
2664	for (i = 0; i < rshader->noutput; i++) {
2665		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2666			z_export = 1;
2667		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2668			stencil_export = 1;
2669	}
2670	if (rshader->uses_kill)
2671		db_shader_control |= S_02880C_KILL_ENABLE(1);
2672
2673	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2674	db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2675
2676	exports_ps = 0;
2677	for (i = 0; i < rshader->noutput; i++) {
2678		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2679		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2680			exports_ps |= 1;
2681	}
2682
2683	num_cout = rshader->nr_ps_color_exports;
2684
2685	exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2686	if (!exports_ps) {
2687		/* always at least export 1 component per pixel */
2688		exports_ps = 2;
2689	}
2690	shader->nr_ps_color_outputs = num_cout;
2691	if (ninterp == 0) {
2692		ninterp = 1;
2693		have_perspective = TRUE;
2694	}
2695
2696	if (!have_perspective && !have_linear)
2697		have_perspective = TRUE;
2698
2699	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2700		              S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2701		              S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2702	spi_input_z = 0;
2703	if (pos_index != -1) {
2704		spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
2705			S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2706			S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2707		spi_input_z |= 1;
2708	}
2709
2710	spi_ps_in_control_1 = 0;
2711	if (face_index != -1) {
2712		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2713			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2714	}
2715
2716	spi_baryc_cntl = 0;
2717	if (have_perspective)
2718		spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2719				  S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2720	if (have_linear)
2721		spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2722				  S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2723
2724	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2725				spi_ps_in_control_0);
2726	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2727				spi_ps_in_control_1);
2728	r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2729				0);
2730	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2731	r600_pipe_state_add_reg(rstate,
2732				R_0286E0_SPI_BARYC_CNTL,
2733				spi_baryc_cntl);
2734
2735	r600_pipe_state_add_reg_bo(rstate,
2736				R_028840_SQ_PGM_START_PS,
2737				r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2738				shader->bo, RADEON_USAGE_READ);
2739	r600_pipe_state_add_reg(rstate,
2740				R_028844_SQ_PGM_RESOURCES_PS,
2741				S_028844_NUM_GPRS(rshader->bc.ngpr) |
2742				S_028844_PRIME_CACHE_ON_DRAW(1) |
2743				S_028844_STACK_SIZE(rshader->bc.nstack));
2744	r600_pipe_state_add_reg(rstate,
2745				R_02884C_SQ_PGM_EXPORTS_PS,
2746				exports_ps);
2747
2748	shader->db_shader_control = db_shader_control;
2749	shader->ps_depth_export = z_export | stencil_export;
2750
2751	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2752	if (rctx->rasterizer)
2753		shader->flatshade = rctx->rasterizer->flatshade;
2754}
2755
2756void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2757{
2758	struct r600_context *rctx = (struct r600_context *)ctx;
2759	struct r600_pipe_state *rstate = &shader->rstate;
2760	struct r600_shader *rshader = &shader->shader;
2761	unsigned spi_vs_out_id[10] = {};
2762	unsigned i, tmp, nparams = 0;
2763
2764	/* clear previous register */
2765	rstate->nregs = 0;
2766
2767	for (i = 0; i < rshader->noutput; i++) {
2768		if (rshader->output[i].spi_sid) {
2769			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2770			spi_vs_out_id[nparams / 4] |= tmp;
2771			nparams++;
2772		}
2773	}
2774
2775	for (i = 0; i < 10; i++) {
2776		r600_pipe_state_add_reg(rstate,
2777					R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2778					spi_vs_out_id[i]);
2779	}
2780
2781	/* Certain attributes (position, psize, etc.) don't count as params.
2782	 * VS is required to export at least one param and r600_shader_from_tgsi()
2783	 * takes care of adding a dummy export.
2784	 */
2785	if (nparams < 1)
2786		nparams = 1;
2787
2788	r600_pipe_state_add_reg(rstate,
2789			R_0286C4_SPI_VS_OUT_CONFIG,
2790			S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2791	r600_pipe_state_add_reg(rstate,
2792			R_028860_SQ_PGM_RESOURCES_VS,
2793			S_028860_NUM_GPRS(rshader->bc.ngpr) |
2794			S_028860_STACK_SIZE(rshader->bc.nstack));
2795	r600_pipe_state_add_reg_bo(rstate,
2796			R_02885C_SQ_PGM_START_VS,
2797			r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2798			shader->bo, RADEON_USAGE_READ);
2799
2800	shader->pa_cl_vs_out_cntl =
2801		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2802		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2803		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2804		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2805}
2806
2807void evergreen_fetch_shader(struct pipe_context *ctx,
2808			    struct r600_vertex_element *ve)
2809{
2810	struct r600_context *rctx = (struct r600_context *)ctx;
2811	struct r600_pipe_state *rstate = &ve->rstate;
2812	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2813	rstate->nregs = 0;
2814	r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
2815				r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2816				ve->fetch_shader, RADEON_USAGE_READ);
2817}
2818
2819void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2820{
2821	struct pipe_depth_stencil_alpha_state dsa = {{0}};
2822
2823	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2824}
2825
2826void evergreen_update_dual_export_state(struct r600_context * rctx)
2827{
2828	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2829			!rctx->ps_shader->current->ps_depth_export;
2830
2831	unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
2832			V_02880C_EXPORT_DB_FULL;
2833
2834	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2835			S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
2836			S_02880C_DB_SOURCE_FORMAT(db_source_format) |
2837			S_02880C_ALPHA_TO_MASK_DISABLE(rctx->cb0_is_integer);
2838
2839	if (db_shader_control != rctx->db_shader_control) {
2840		struct r600_pipe_state rstate;
2841
2842		rctx->db_shader_control = db_shader_control;
2843
2844		rstate.nregs = 0;
2845		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2846		r600_context_pipe_state_set(rctx, &rstate);
2847	}
2848}
2849