evergreen_state.c revision a940c74bc3bb129b074601cc7967c331e2b97322 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "evergreend.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31#include "evergreen_compute.h"
32
33static uint32_t eg_num_banks(uint32_t nbanks)
34{
35	switch (nbanks) {
36	case 2:
37		return 0;
38	case 4:
39		return 1;
40	case 8:
41	default:
42		return 2;
43	case 16:
44		return 3;
45	}
46}
47
48
49static unsigned eg_tile_split(unsigned tile_split)
50{
51	switch (tile_split) {
52	case 64:	tile_split = 0;	break;
53	case 128:	tile_split = 1;	break;
54	case 256:	tile_split = 2;	break;
55	case 512:	tile_split = 3;	break;
56	default:
57	case 1024:	tile_split = 4;	break;
58	case 2048:	tile_split = 5;	break;
59	case 4096:	tile_split = 6;	break;
60	}
61	return tile_split;
62}
63
64static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65{
66	switch (macro_tile_aspect) {
67	default:
68	case 1:	macro_tile_aspect = 0;	break;
69	case 2:	macro_tile_aspect = 1;	break;
70	case 4:	macro_tile_aspect = 2;	break;
71	case 8:	macro_tile_aspect = 3;	break;
72	}
73	return macro_tile_aspect;
74}
75
76static unsigned eg_bank_wh(unsigned bankwh)
77{
78	switch (bankwh) {
79	default:
80	case 1:	bankwh = 0;	break;
81	case 2:	bankwh = 1;	break;
82	case 4:	bankwh = 2;	break;
83	case 8:	bankwh = 3;	break;
84	}
85	return bankwh;
86}
87
88static uint32_t r600_translate_blend_function(int blend_func)
89{
90	switch (blend_func) {
91	case PIPE_BLEND_ADD:
92		return V_028780_COMB_DST_PLUS_SRC;
93	case PIPE_BLEND_SUBTRACT:
94		return V_028780_COMB_SRC_MINUS_DST;
95	case PIPE_BLEND_REVERSE_SUBTRACT:
96		return V_028780_COMB_DST_MINUS_SRC;
97	case PIPE_BLEND_MIN:
98		return V_028780_COMB_MIN_DST_SRC;
99	case PIPE_BLEND_MAX:
100		return V_028780_COMB_MAX_DST_SRC;
101	default:
102		R600_ERR("Unknown blend function %d\n", blend_func);
103		assert(0);
104		break;
105	}
106	return 0;
107}
108
109static uint32_t r600_translate_blend_factor(int blend_fact)
110{
111	switch (blend_fact) {
112	case PIPE_BLENDFACTOR_ONE:
113		return V_028780_BLEND_ONE;
114	case PIPE_BLENDFACTOR_SRC_COLOR:
115		return V_028780_BLEND_SRC_COLOR;
116	case PIPE_BLENDFACTOR_SRC_ALPHA:
117		return V_028780_BLEND_SRC_ALPHA;
118	case PIPE_BLENDFACTOR_DST_ALPHA:
119		return V_028780_BLEND_DST_ALPHA;
120	case PIPE_BLENDFACTOR_DST_COLOR:
121		return V_028780_BLEND_DST_COLOR;
122	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123		return V_028780_BLEND_SRC_ALPHA_SATURATE;
124	case PIPE_BLENDFACTOR_CONST_COLOR:
125		return V_028780_BLEND_CONST_COLOR;
126	case PIPE_BLENDFACTOR_CONST_ALPHA:
127		return V_028780_BLEND_CONST_ALPHA;
128	case PIPE_BLENDFACTOR_ZERO:
129		return V_028780_BLEND_ZERO;
130	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131		return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133		return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135		return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136	case PIPE_BLENDFACTOR_INV_DST_COLOR:
137		return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139		return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141		return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142	case PIPE_BLENDFACTOR_SRC1_COLOR:
143		return V_028780_BLEND_SRC1_COLOR;
144	case PIPE_BLENDFACTOR_SRC1_ALPHA:
145		return V_028780_BLEND_SRC1_ALPHA;
146	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147		return V_028780_BLEND_INV_SRC1_COLOR;
148	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149		return V_028780_BLEND_INV_SRC1_ALPHA;
150	default:
151		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152		assert(0);
153		break;
154	}
155	return 0;
156}
157
158static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
159{
160	switch (dim) {
161	default:
162	case PIPE_TEXTURE_1D:
163		return V_030000_SQ_TEX_DIM_1D;
164	case PIPE_TEXTURE_1D_ARRAY:
165		return V_030000_SQ_TEX_DIM_1D_ARRAY;
166	case PIPE_TEXTURE_2D:
167	case PIPE_TEXTURE_RECT:
168		return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_MSAA :
169					V_030000_SQ_TEX_DIM_2D;
170	case PIPE_TEXTURE_2D_ARRAY:
171		return nr_samples > 1 ? V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA :
172					V_030000_SQ_TEX_DIM_2D_ARRAY;
173	case PIPE_TEXTURE_3D:
174		return V_030000_SQ_TEX_DIM_3D;
175	case PIPE_TEXTURE_CUBE:
176		return V_030000_SQ_TEX_DIM_CUBEMAP;
177	}
178}
179
180static uint32_t r600_translate_dbformat(enum pipe_format format)
181{
182	switch (format) {
183	case PIPE_FORMAT_Z16_UNORM:
184		return V_028040_Z_16;
185	case PIPE_FORMAT_Z24X8_UNORM:
186	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
187		return V_028040_Z_24;
188	case PIPE_FORMAT_Z32_FLOAT:
189	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
190		return V_028040_Z_32_FLOAT;
191	default:
192		return ~0U;
193	}
194}
195
196static uint32_t r600_translate_colorswap(enum pipe_format format)
197{
198	switch (format) {
199	/* 8-bit buffers. */
200	case PIPE_FORMAT_L4A4_UNORM:
201	case PIPE_FORMAT_A4R4_UNORM:
202		return V_028C70_SWAP_ALT;
203
204	case PIPE_FORMAT_A8_UNORM:
205	case PIPE_FORMAT_A8_SNORM:
206	case PIPE_FORMAT_A8_UINT:
207	case PIPE_FORMAT_A8_SINT:
208	case PIPE_FORMAT_A16_UNORM:
209	case PIPE_FORMAT_A16_SNORM:
210	case PIPE_FORMAT_A16_UINT:
211	case PIPE_FORMAT_A16_SINT:
212	case PIPE_FORMAT_A16_FLOAT:
213	case PIPE_FORMAT_A32_UINT:
214	case PIPE_FORMAT_A32_SINT:
215	case PIPE_FORMAT_A32_FLOAT:
216	case PIPE_FORMAT_R4A4_UNORM:
217		return V_028C70_SWAP_ALT_REV;
218	case PIPE_FORMAT_I8_UNORM:
219	case PIPE_FORMAT_I8_SNORM:
220	case PIPE_FORMAT_I8_UINT:
221	case PIPE_FORMAT_I8_SINT:
222	case PIPE_FORMAT_I16_UNORM:
223	case PIPE_FORMAT_I16_SNORM:
224	case PIPE_FORMAT_I16_UINT:
225	case PIPE_FORMAT_I16_SINT:
226	case PIPE_FORMAT_I16_FLOAT:
227	case PIPE_FORMAT_I32_UINT:
228	case PIPE_FORMAT_I32_SINT:
229	case PIPE_FORMAT_I32_FLOAT:
230	case PIPE_FORMAT_L8_UNORM:
231	case PIPE_FORMAT_L8_SNORM:
232	case PIPE_FORMAT_L8_UINT:
233	case PIPE_FORMAT_L8_SINT:
234	case PIPE_FORMAT_L8_SRGB:
235	case PIPE_FORMAT_L16_UNORM:
236	case PIPE_FORMAT_L16_SNORM:
237	case PIPE_FORMAT_L16_UINT:
238	case PIPE_FORMAT_L16_SINT:
239	case PIPE_FORMAT_L16_FLOAT:
240	case PIPE_FORMAT_L32_UINT:
241	case PIPE_FORMAT_L32_SINT:
242	case PIPE_FORMAT_L32_FLOAT:
243	case PIPE_FORMAT_R8_UNORM:
244	case PIPE_FORMAT_R8_SNORM:
245	case PIPE_FORMAT_R8_UINT:
246	case PIPE_FORMAT_R8_SINT:
247		return V_028C70_SWAP_STD;
248
249	/* 16-bit buffers. */
250	case PIPE_FORMAT_B5G6R5_UNORM:
251		return V_028C70_SWAP_STD_REV;
252
253	case PIPE_FORMAT_B5G5R5A1_UNORM:
254	case PIPE_FORMAT_B5G5R5X1_UNORM:
255		return V_028C70_SWAP_ALT;
256
257	case PIPE_FORMAT_B4G4R4A4_UNORM:
258	case PIPE_FORMAT_B4G4R4X4_UNORM:
259		return V_028C70_SWAP_ALT;
260
261	case PIPE_FORMAT_Z16_UNORM:
262		return V_028C70_SWAP_STD;
263
264	case PIPE_FORMAT_L8A8_UNORM:
265	case PIPE_FORMAT_L8A8_SNORM:
266	case PIPE_FORMAT_L8A8_UINT:
267	case PIPE_FORMAT_L8A8_SINT:
268	case PIPE_FORMAT_L8A8_SRGB:
269	case PIPE_FORMAT_L16A16_UNORM:
270	case PIPE_FORMAT_L16A16_SNORM:
271	case PIPE_FORMAT_L16A16_UINT:
272	case PIPE_FORMAT_L16A16_SINT:
273	case PIPE_FORMAT_L16A16_FLOAT:
274	case PIPE_FORMAT_L32A32_UINT:
275	case PIPE_FORMAT_L32A32_SINT:
276	case PIPE_FORMAT_L32A32_FLOAT:
277		return V_028C70_SWAP_ALT;
278	case PIPE_FORMAT_R8G8_UNORM:
279	case PIPE_FORMAT_R8G8_SNORM:
280	case PIPE_FORMAT_R8G8_UINT:
281	case PIPE_FORMAT_R8G8_SINT:
282		return V_028C70_SWAP_STD;
283
284	case PIPE_FORMAT_R16_UNORM:
285	case PIPE_FORMAT_R16_SNORM:
286	case PIPE_FORMAT_R16_UINT:
287	case PIPE_FORMAT_R16_SINT:
288	case PIPE_FORMAT_R16_FLOAT:
289		return V_028C70_SWAP_STD;
290
291	/* 32-bit buffers. */
292	case PIPE_FORMAT_A8B8G8R8_SRGB:
293		return V_028C70_SWAP_STD_REV;
294	case PIPE_FORMAT_B8G8R8A8_SRGB:
295		return V_028C70_SWAP_ALT;
296
297	case PIPE_FORMAT_B8G8R8A8_UNORM:
298	case PIPE_FORMAT_B8G8R8X8_UNORM:
299		return V_028C70_SWAP_ALT;
300
301	case PIPE_FORMAT_A8R8G8B8_UNORM:
302	case PIPE_FORMAT_X8R8G8B8_UNORM:
303		return V_028C70_SWAP_ALT_REV;
304	case PIPE_FORMAT_R8G8B8A8_SNORM:
305	case PIPE_FORMAT_R8G8B8A8_UNORM:
306	case PIPE_FORMAT_R8G8B8A8_SINT:
307	case PIPE_FORMAT_R8G8B8A8_UINT:
308	case PIPE_FORMAT_R8G8B8X8_UNORM:
309		return V_028C70_SWAP_STD;
310
311	case PIPE_FORMAT_A8B8G8R8_UNORM:
312	case PIPE_FORMAT_X8B8G8R8_UNORM:
313	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
314		return V_028C70_SWAP_STD_REV;
315
316	case PIPE_FORMAT_Z24X8_UNORM:
317	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318		return V_028C70_SWAP_STD;
319
320	case PIPE_FORMAT_X8Z24_UNORM:
321	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
322		return V_028C70_SWAP_STD;
323
324	case PIPE_FORMAT_R10G10B10A2_UNORM:
325	case PIPE_FORMAT_R10G10B10X2_SNORM:
326	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
327		return V_028C70_SWAP_STD;
328
329	case PIPE_FORMAT_B10G10R10A2_UNORM:
330	case PIPE_FORMAT_B10G10R10A2_UINT:
331		return V_028C70_SWAP_ALT;
332
333	case PIPE_FORMAT_R11G11B10_FLOAT:
334	case PIPE_FORMAT_R32_FLOAT:
335	case PIPE_FORMAT_R32_UINT:
336	case PIPE_FORMAT_R32_SINT:
337	case PIPE_FORMAT_Z32_FLOAT:
338	case PIPE_FORMAT_R16G16_FLOAT:
339	case PIPE_FORMAT_R16G16_UNORM:
340	case PIPE_FORMAT_R16G16_SNORM:
341	case PIPE_FORMAT_R16G16_UINT:
342	case PIPE_FORMAT_R16G16_SINT:
343		return V_028C70_SWAP_STD;
344
345	/* 64-bit buffers. */
346	case PIPE_FORMAT_R32G32_FLOAT:
347	case PIPE_FORMAT_R32G32_UINT:
348	case PIPE_FORMAT_R32G32_SINT:
349	case PIPE_FORMAT_R16G16B16A16_UNORM:
350	case PIPE_FORMAT_R16G16B16A16_SNORM:
351	case PIPE_FORMAT_R16G16B16A16_UINT:
352	case PIPE_FORMAT_R16G16B16A16_SINT:
353	case PIPE_FORMAT_R16G16B16A16_FLOAT:
354	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356	/* 128-bit buffers. */
357	case PIPE_FORMAT_R32G32B32A32_FLOAT:
358	case PIPE_FORMAT_R32G32B32A32_SNORM:
359	case PIPE_FORMAT_R32G32B32A32_UNORM:
360	case PIPE_FORMAT_R32G32B32A32_SINT:
361	case PIPE_FORMAT_R32G32B32A32_UINT:
362		return V_028C70_SWAP_STD;
363	default:
364		R600_ERR("unsupported colorswap format %d\n", format);
365		return ~0U;
366	}
367	return ~0U;
368}
369
370static uint32_t r600_translate_colorformat(enum pipe_format format)
371{
372	switch (format) {
373	/* 8-bit buffers. */
374	case PIPE_FORMAT_A8_UNORM:
375	case PIPE_FORMAT_A8_SNORM:
376	case PIPE_FORMAT_A8_UINT:
377	case PIPE_FORMAT_A8_SINT:
378	case PIPE_FORMAT_I8_UNORM:
379	case PIPE_FORMAT_I8_SNORM:
380	case PIPE_FORMAT_I8_UINT:
381	case PIPE_FORMAT_I8_SINT:
382	case PIPE_FORMAT_L8_UNORM:
383	case PIPE_FORMAT_L8_SNORM:
384	case PIPE_FORMAT_L8_UINT:
385	case PIPE_FORMAT_L8_SINT:
386	case PIPE_FORMAT_L8_SRGB:
387	case PIPE_FORMAT_R8_UNORM:
388	case PIPE_FORMAT_R8_SNORM:
389	case PIPE_FORMAT_R8_UINT:
390	case PIPE_FORMAT_R8_SINT:
391		return V_028C70_COLOR_8;
392
393	/* 16-bit buffers. */
394	case PIPE_FORMAT_B5G6R5_UNORM:
395		return V_028C70_COLOR_5_6_5;
396
397	case PIPE_FORMAT_B5G5R5A1_UNORM:
398	case PIPE_FORMAT_B5G5R5X1_UNORM:
399		return V_028C70_COLOR_1_5_5_5;
400
401	case PIPE_FORMAT_B4G4R4A4_UNORM:
402	case PIPE_FORMAT_B4G4R4X4_UNORM:
403		return V_028C70_COLOR_4_4_4_4;
404
405	case PIPE_FORMAT_Z16_UNORM:
406		return V_028C70_COLOR_16;
407
408	case PIPE_FORMAT_L8A8_UNORM:
409	case PIPE_FORMAT_L8A8_SNORM:
410	case PIPE_FORMAT_L8A8_UINT:
411	case PIPE_FORMAT_L8A8_SINT:
412	case PIPE_FORMAT_L8A8_SRGB:
413	case PIPE_FORMAT_R8G8_UNORM:
414	case PIPE_FORMAT_R8G8_SNORM:
415	case PIPE_FORMAT_R8G8_UINT:
416	case PIPE_FORMAT_R8G8_SINT:
417		return V_028C70_COLOR_8_8;
418
419	case PIPE_FORMAT_R16_UNORM:
420	case PIPE_FORMAT_R16_SNORM:
421	case PIPE_FORMAT_R16_UINT:
422	case PIPE_FORMAT_R16_SINT:
423	case PIPE_FORMAT_A16_UNORM:
424	case PIPE_FORMAT_A16_SNORM:
425	case PIPE_FORMAT_A16_UINT:
426	case PIPE_FORMAT_A16_SINT:
427	case PIPE_FORMAT_L16_UNORM:
428	case PIPE_FORMAT_L16_SNORM:
429	case PIPE_FORMAT_L16_UINT:
430	case PIPE_FORMAT_L16_SINT:
431	case PIPE_FORMAT_I16_UNORM:
432	case PIPE_FORMAT_I16_SNORM:
433	case PIPE_FORMAT_I16_UINT:
434	case PIPE_FORMAT_I16_SINT:
435		return V_028C70_COLOR_16;
436
437	case PIPE_FORMAT_R16_FLOAT:
438	case PIPE_FORMAT_A16_FLOAT:
439	case PIPE_FORMAT_L16_FLOAT:
440	case PIPE_FORMAT_I16_FLOAT:
441		return V_028C70_COLOR_16_FLOAT;
442
443	/* 32-bit buffers. */
444	case PIPE_FORMAT_A8B8G8R8_SRGB:
445	case PIPE_FORMAT_A8B8G8R8_UNORM:
446	case PIPE_FORMAT_A8R8G8B8_UNORM:
447	case PIPE_FORMAT_B8G8R8A8_SRGB:
448	case PIPE_FORMAT_B8G8R8A8_UNORM:
449	case PIPE_FORMAT_B8G8R8X8_UNORM:
450	case PIPE_FORMAT_R8G8B8A8_SNORM:
451	case PIPE_FORMAT_R8G8B8A8_UNORM:
452	case PIPE_FORMAT_R8G8B8X8_UNORM:
453	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454	case PIPE_FORMAT_X8B8G8R8_UNORM:
455	case PIPE_FORMAT_X8R8G8B8_UNORM:
456	case PIPE_FORMAT_R8G8B8_UNORM:
457	case PIPE_FORMAT_R8G8B8A8_SINT:
458	case PIPE_FORMAT_R8G8B8A8_UINT:
459		return V_028C70_COLOR_8_8_8_8;
460
461	case PIPE_FORMAT_R10G10B10A2_UNORM:
462	case PIPE_FORMAT_R10G10B10X2_SNORM:
463	case PIPE_FORMAT_B10G10R10A2_UNORM:
464	case PIPE_FORMAT_B10G10R10A2_UINT:
465	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466		return V_028C70_COLOR_2_10_10_10;
467
468	case PIPE_FORMAT_Z24X8_UNORM:
469	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470		return V_028C70_COLOR_8_24;
471
472	case PIPE_FORMAT_X8Z24_UNORM:
473	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474		return V_028C70_COLOR_24_8;
475
476	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477		return V_028C70_COLOR_X24_8_32_FLOAT;
478
479	case PIPE_FORMAT_R32_UINT:
480	case PIPE_FORMAT_R32_SINT:
481	case PIPE_FORMAT_A32_UINT:
482	case PIPE_FORMAT_A32_SINT:
483	case PIPE_FORMAT_L32_UINT:
484	case PIPE_FORMAT_L32_SINT:
485	case PIPE_FORMAT_I32_UINT:
486	case PIPE_FORMAT_I32_SINT:
487		return V_028C70_COLOR_32;
488
489	case PIPE_FORMAT_R32_FLOAT:
490	case PIPE_FORMAT_A32_FLOAT:
491	case PIPE_FORMAT_L32_FLOAT:
492	case PIPE_FORMAT_I32_FLOAT:
493	case PIPE_FORMAT_Z32_FLOAT:
494		return V_028C70_COLOR_32_FLOAT;
495
496	case PIPE_FORMAT_R16G16_FLOAT:
497	case PIPE_FORMAT_L16A16_FLOAT:
498		return V_028C70_COLOR_16_16_FLOAT;
499
500	case PIPE_FORMAT_R16G16_UNORM:
501	case PIPE_FORMAT_R16G16_SNORM:
502	case PIPE_FORMAT_R16G16_UINT:
503	case PIPE_FORMAT_R16G16_SINT:
504	case PIPE_FORMAT_L16A16_UNORM:
505	case PIPE_FORMAT_L16A16_SNORM:
506	case PIPE_FORMAT_L16A16_UINT:
507	case PIPE_FORMAT_L16A16_SINT:
508		return V_028C70_COLOR_16_16;
509
510	case PIPE_FORMAT_R11G11B10_FLOAT:
511		return V_028C70_COLOR_10_11_11_FLOAT;
512
513	/* 64-bit buffers. */
514	case PIPE_FORMAT_R16G16B16A16_UINT:
515	case PIPE_FORMAT_R16G16B16A16_SINT:
516	case PIPE_FORMAT_R16G16B16A16_UNORM:
517	case PIPE_FORMAT_R16G16B16A16_SNORM:
518		return V_028C70_COLOR_16_16_16_16;
519
520	case PIPE_FORMAT_R16G16B16A16_FLOAT:
521		return V_028C70_COLOR_16_16_16_16_FLOAT;
522
523	case PIPE_FORMAT_R32G32_FLOAT:
524	case PIPE_FORMAT_L32A32_FLOAT:
525		return V_028C70_COLOR_32_32_FLOAT;
526
527	case PIPE_FORMAT_R32G32_SINT:
528	case PIPE_FORMAT_R32G32_UINT:
529	case PIPE_FORMAT_L32A32_UINT:
530	case PIPE_FORMAT_L32A32_SINT:
531		return V_028C70_COLOR_32_32;
532
533	/* 128-bit buffers. */
534	case PIPE_FORMAT_R32G32B32A32_SNORM:
535	case PIPE_FORMAT_R32G32B32A32_UNORM:
536	case PIPE_FORMAT_R32G32B32A32_SINT:
537	case PIPE_FORMAT_R32G32B32A32_UINT:
538		return V_028C70_COLOR_32_32_32_32;
539	case PIPE_FORMAT_R32G32B32A32_FLOAT:
540		return V_028C70_COLOR_32_32_32_32_FLOAT;
541
542	/* YUV buffers. */
543	case PIPE_FORMAT_UYVY:
544	case PIPE_FORMAT_YUYV:
545	default:
546		return ~0U; /* Unsupported. */
547	}
548}
549
550static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
551{
552	if (R600_BIG_ENDIAN) {
553		switch(colorformat) {
554
555		/* 8-bit buffers. */
556		case V_028C70_COLOR_8:
557			return ENDIAN_NONE;
558
559		/* 16-bit buffers. */
560		case V_028C70_COLOR_5_6_5:
561		case V_028C70_COLOR_1_5_5_5:
562		case V_028C70_COLOR_4_4_4_4:
563		case V_028C70_COLOR_16:
564		case V_028C70_COLOR_8_8:
565			return ENDIAN_8IN16;
566
567		/* 32-bit buffers. */
568		case V_028C70_COLOR_8_8_8_8:
569		case V_028C70_COLOR_2_10_10_10:
570		case V_028C70_COLOR_8_24:
571		case V_028C70_COLOR_24_8:
572		case V_028C70_COLOR_32_FLOAT:
573		case V_028C70_COLOR_16_16_FLOAT:
574		case V_028C70_COLOR_16_16:
575			return ENDIAN_8IN32;
576
577		/* 64-bit buffers. */
578		case V_028C70_COLOR_16_16_16_16:
579		case V_028C70_COLOR_16_16_16_16_FLOAT:
580			return ENDIAN_8IN16;
581
582		case V_028C70_COLOR_32_32_FLOAT:
583		case V_028C70_COLOR_32_32:
584		case V_028C70_COLOR_X24_8_32_FLOAT:
585			return ENDIAN_8IN32;
586
587		/* 96-bit buffers. */
588		case V_028C70_COLOR_32_32_32_FLOAT:
589		/* 128-bit buffers. */
590		case V_028C70_COLOR_32_32_32_32_FLOAT:
591		case V_028C70_COLOR_32_32_32_32:
592			return ENDIAN_8IN32;
593		default:
594			return ENDIAN_NONE; /* Unsupported. */
595		}
596	} else {
597		return ENDIAN_NONE;
598	}
599}
600
601static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
602{
603	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
604}
605
606static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
607{
608	return r600_translate_colorformat(format) != ~0U &&
609		r600_translate_colorswap(format) != ~0U;
610}
611
612static bool r600_is_zs_format_supported(enum pipe_format format)
613{
614	return r600_translate_dbformat(format) != ~0U;
615}
616
617boolean evergreen_is_format_supported(struct pipe_screen *screen,
618				      enum pipe_format format,
619				      enum pipe_texture_target target,
620				      unsigned sample_count,
621				      unsigned usage)
622{
623	struct r600_screen *rscreen = (struct r600_screen*)screen;
624	unsigned retval = 0;
625
626	if (target >= PIPE_MAX_TEXTURE_TYPES) {
627		R600_ERR("r600: unsupported texture type %d\n", target);
628		return FALSE;
629	}
630
631	if (!util_format_is_supported(format, usage))
632		return FALSE;
633
634	if (sample_count > 1) {
635		if (rscreen->info.drm_minor < 19)
636			return FALSE;
637
638		switch (sample_count) {
639		case 2:
640		case 4:
641		case 8:
642			break;
643		default:
644			return FALSE;
645		}
646	}
647
648	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
649	    r600_is_sampler_format_supported(screen, format)) {
650		retval |= PIPE_BIND_SAMPLER_VIEW;
651	}
652
653	if ((usage & (PIPE_BIND_RENDER_TARGET |
654		      PIPE_BIND_DISPLAY_TARGET |
655		      PIPE_BIND_SCANOUT |
656		      PIPE_BIND_SHARED)) &&
657	    r600_is_colorbuffer_format_supported(format)) {
658		retval |= usage &
659			  (PIPE_BIND_RENDER_TARGET |
660			   PIPE_BIND_DISPLAY_TARGET |
661			   PIPE_BIND_SCANOUT |
662			   PIPE_BIND_SHARED);
663	}
664
665	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
666	    r600_is_zs_format_supported(format)) {
667		retval |= PIPE_BIND_DEPTH_STENCIL;
668	}
669
670	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
671	    r600_is_vertex_format_supported(format)) {
672		retval |= PIPE_BIND_VERTEX_BUFFER;
673	}
674
675	if (usage & PIPE_BIND_TRANSFER_READ)
676		retval |= PIPE_BIND_TRANSFER_READ;
677	if (usage & PIPE_BIND_TRANSFER_WRITE)
678		retval |= PIPE_BIND_TRANSFER_WRITE;
679
680	return retval == usage;
681}
682
683static void *evergreen_create_blend_state_mode(struct pipe_context *ctx,
684					       const struct pipe_blend_state *state, int mode)
685{
686	struct r600_context *rctx = (struct r600_context *)ctx;
687	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
688	struct r600_pipe_state *rstate;
689	uint32_t color_control = 0, target_mask;
690	/* XXX there is more then 8 framebuffer */
691	unsigned blend_cntl[8];
692
693	if (blend == NULL) {
694		return NULL;
695	}
696
697	rstate = &blend->rstate;
698
699	rstate->id = R600_PIPE_STATE_BLEND;
700
701	target_mask = 0;
702	if (state->logicop_enable) {
703		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
704	} else {
705		color_control |= (0xcc << 16);
706	}
707	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
708	if (state->independent_blend_enable) {
709		for (int i = 0; i < 8; i++) {
710			target_mask |= (state->rt[i].colormask << (4 * i));
711		}
712	} else {
713		for (int i = 0; i < 8; i++) {
714			target_mask |= (state->rt[0].colormask << (4 * i));
715		}
716	}
717	blend->cb_target_mask = target_mask;
718
719	if (target_mask)
720		color_control |= S_028808_MODE(mode);
721	else
722		color_control |= S_028808_MODE(V_028808_CB_DISABLE);
723
724	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
725				color_control);
726	/* only have dual source on MRT0 */
727	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
728	for (int i = 0; i < 8; i++) {
729		/* state->rt entries > 0 only written if independent blending */
730		const int j = state->independent_blend_enable ? i : 0;
731
732		unsigned eqRGB = state->rt[j].rgb_func;
733		unsigned srcRGB = state->rt[j].rgb_src_factor;
734		unsigned dstRGB = state->rt[j].rgb_dst_factor;
735		unsigned eqA = state->rt[j].alpha_func;
736		unsigned srcA = state->rt[j].alpha_src_factor;
737		unsigned dstA = state->rt[j].alpha_dst_factor;
738
739		blend_cntl[i] = 0;
740		if (!state->rt[j].blend_enable)
741			continue;
742
743		blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
744		blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
745		blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
746		blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
747
748		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
749			blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
750			blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
751			blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
752			blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
753		}
754	}
755	for (int i = 0; i < 8; i++) {
756		r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
757	}
758
759	r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK,
760				S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
761				S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
762				S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
763				S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
764				S_028B70_ALPHA_TO_MASK_OFFSET3(2));
765
766	blend->alpha_to_one = state->alpha_to_one;
767	return rstate;
768}
769
770static void *evergreen_create_blend_state(struct pipe_context *ctx,
771					const struct pipe_blend_state *state)
772{
773
774	return evergreen_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
775}
776
777static void *evergreen_create_dsa_state(struct pipe_context *ctx,
778				   const struct pipe_depth_stencil_alpha_state *state)
779{
780	struct r600_context *rctx = (struct r600_context *)ctx;
781	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
782	unsigned db_depth_control, alpha_test_control, alpha_ref;
783	struct r600_pipe_state *rstate;
784
785	if (dsa == NULL) {
786		return NULL;
787	}
788
789	dsa->valuemask[0] = state->stencil[0].valuemask;
790	dsa->valuemask[1] = state->stencil[1].valuemask;
791	dsa->writemask[0] = state->stencil[0].writemask;
792	dsa->writemask[1] = state->stencil[1].writemask;
793
794	rstate = &dsa->rstate;
795
796	rstate->id = R600_PIPE_STATE_DSA;
797	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
798		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
799		S_028800_ZFUNC(state->depth.func);
800
801	/* stencil */
802	if (state->stencil[0].enabled) {
803		db_depth_control |= S_028800_STENCIL_ENABLE(1);
804		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
805		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
806		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
807		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
808
809		if (state->stencil[1].enabled) {
810			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
811			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
812			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
813			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
814			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
815		}
816	}
817
818	/* alpha */
819	alpha_test_control = 0;
820	alpha_ref = 0;
821	if (state->alpha.enabled) {
822		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
823		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
824		alpha_ref = fui(state->alpha.ref_value);
825	}
826	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
827	dsa->alpha_ref = alpha_ref;
828
829	/* misc */
830	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
831	return rstate;
832}
833
834static void *evergreen_create_rs_state(struct pipe_context *ctx,
835					const struct pipe_rasterizer_state *state)
836{
837	struct r600_context *rctx = (struct r600_context *)ctx;
838	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
839	struct r600_pipe_state *rstate;
840	unsigned tmp;
841	unsigned prov_vtx = 1, polygon_dual_mode;
842	float psize_min, psize_max;
843
844	if (rs == NULL) {
845		return NULL;
846	}
847
848	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
849				state->fill_back != PIPE_POLYGON_MODE_FILL);
850
851	if (state->flatshade_first)
852		prov_vtx = 0;
853
854	rstate = &rs->rstate;
855	rs->flatshade = state->flatshade;
856	rs->sprite_coord_enable = state->sprite_coord_enable;
857	rs->two_side = state->light_twoside;
858	rs->clip_plane_enable = state->clip_plane_enable;
859	rs->pa_sc_line_stipple = state->line_stipple_enable ?
860				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
861				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
862	rs->pa_cl_clip_cntl =
863		S_028810_PS_UCP_MODE(3) |
864		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
865		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
866		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
867	rs->multisample_enable = state->multisample;
868
869	/* offset */
870	rs->offset_units = state->offset_units;
871	rs->offset_scale = state->offset_scale * 12.0f;
872
873	rstate->id = R600_PIPE_STATE_RASTERIZER;
874	tmp = S_0286D4_FLAT_SHADE_ENA(1);
875	if (state->sprite_coord_enable) {
876		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
877			S_0286D4_PNT_SPRITE_OVRD_X(2) |
878			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
879			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
880			S_0286D4_PNT_SPRITE_OVRD_W(1);
881		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
882			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
883		}
884	}
885	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
886
887	/* point size 12.4 fixed point */
888	tmp = (unsigned)(state->point_size * 8.0);
889	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
890
891	if (state->point_size_per_vertex) {
892		psize_min = util_get_min_point_size(state);
893		psize_max = 8192;
894	} else {
895		/* Force the point size to be as if the vertex output was disabled. */
896		psize_min = state->point_size;
897		psize_max = state->point_size;
898	}
899	/* Divide by two, because 0.5 = 1 pixel. */
900	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
901				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
902				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
903
904	tmp = (unsigned)state->line_width * 8;
905	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
906	r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
907				S_028A48_MSAA_ENABLE(state->multisample) |
908				S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
909				S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
910
911	if (rctx->chip_class == CAYMAN) {
912		r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
913					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
914					S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
915	} else {
916		r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
917					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
918					S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
919	}
920	r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
921	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
922				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
923				S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
924				S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
925				S_028814_FACE(!state->front_ccw) |
926				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
927				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
928				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
929				S_028814_POLY_MODE(polygon_dual_mode) |
930				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
931				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
932	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
933	return rstate;
934}
935
936static void *evergreen_create_sampler_state(struct pipe_context *ctx,
937					const struct pipe_sampler_state *state)
938{
939	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
940	union util_color uc;
941	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
942
943	if (ss == NULL) {
944		return NULL;
945	}
946
947	/* directly into sampler avoid r6xx code to emit useless reg */
948	ss->seamless_cube_map = false;
949	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
950	ss->border_color_use = false;
951	/* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
952	ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
953				S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
954				S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
955				S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
956				S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
957				S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
958				S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
959				S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
960				S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
961	/* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
962	ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
963				S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8));
964	/* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
965	ss->tex_sampler_words[2] = S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
966				(state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
967				S_03C008_TYPE(1);
968	if (uc.ui) {
969		ss->border_color_use = true;
970		/* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
971		ss->border_color[0] = fui(state->border_color.f[0]);
972		/* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
973		ss->border_color[1] = fui(state->border_color.f[1]);
974		/* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
975		ss->border_color[2] = fui(state->border_color.f[2]);
976		/* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
977		ss->border_color[3] = fui(state->border_color.f[3]);
978	}
979	return ss;
980}
981
982static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
983							struct pipe_resource *texture,
984							const struct pipe_sampler_view *state)
985{
986	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
987	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
988	struct r600_texture *tmp = (struct r600_texture*)texture;
989	unsigned format, endian;
990	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
991	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
992	unsigned height, depth, width;
993	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
994
995	if (view == NULL)
996		return NULL;
997
998	/* initialize base object */
999	view->base = *state;
1000	view->base.texture = NULL;
1001	pipe_reference(NULL, &texture->reference);
1002	view->base.texture = texture;
1003	view->base.reference.count = 1;
1004	view->base.context = ctx;
1005
1006	swizzle[0] = state->swizzle_r;
1007	swizzle[1] = state->swizzle_g;
1008	swizzle[2] = state->swizzle_b;
1009	swizzle[3] = state->swizzle_a;
1010
1011	format = r600_translate_texformat(ctx->screen, state->format,
1012					  swizzle,
1013					  &word4, &yuv_format);
1014	assert(format != ~0);
1015	if (format == ~0) {
1016		FREE(view);
1017		return NULL;
1018	}
1019
1020	if (tmp->is_depth && !tmp->is_flushing_texture) {
1021		if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1022			FREE(view);
1023			return NULL;
1024		}
1025		tmp = tmp->flushed_depth_texture;
1026	}
1027
1028	endian = r600_colorformat_endian_swap(format);
1029
1030	width = tmp->surface.level[0].npix_x;
1031	height = tmp->surface.level[0].npix_y;
1032	depth = tmp->surface.level[0].npix_z;
1033	pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1034	tile_type = tmp->tile_type;
1035
1036	switch (tmp->surface.level[0].mode) {
1037	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1038		array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1039		break;
1040	case RADEON_SURF_MODE_2D:
1041		array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1042		break;
1043	case RADEON_SURF_MODE_1D:
1044		array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1045		break;
1046	case RADEON_SURF_MODE_LINEAR:
1047	default:
1048		array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1049		break;
1050	}
1051	tile_split = tmp->surface.tile_split;
1052	macro_aspect = tmp->surface.mtilea;
1053	bankw = tmp->surface.bankw;
1054	bankh = tmp->surface.bankh;
1055	tile_split = eg_tile_split(tile_split);
1056	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1057	bankw = eg_bank_wh(bankw);
1058	bankh = eg_bank_wh(bankh);
1059
1060	/* 128 bit formats require tile type = 1 */
1061	if (rscreen->chip_class == CAYMAN) {
1062		if (util_format_get_blocksize(state->format) >= 16)
1063			tile_type = 1;
1064	}
1065	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1066
1067	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1068	        height = 1;
1069		depth = texture->array_size;
1070	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1071		depth = texture->array_size;
1072	}
1073
1074	view->tex_resource = &tmp->resource;
1075	view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1076				       S_030000_PITCH((pitch / 8) - 1) |
1077				       S_030000_TEX_WIDTH(width - 1));
1078	if (rscreen->chip_class == CAYMAN)
1079		view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1080	else
1081		view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1082	view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1083				       S_030004_TEX_DEPTH(depth - 1) |
1084				       S_030004_ARRAY_MODE(array_mode));
1085	view->tex_resource_words[2] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1086	if (state->u.tex.last_level && texture->nr_samples <= 1) {
1087		view->tex_resource_words[3] = (tmp->surface.level[1].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1088	} else {
1089		view->tex_resource_words[3] = (tmp->surface.level[0].offset + r600_resource_va(ctx->screen, texture)) >> 8;
1090	}
1091	view->tex_resource_words[4] = (word4 |
1092				       S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1093				       S_030010_ENDIAN_SWAP(endian));
1094	view->tex_resource_words[5] = S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1095				      S_030014_LAST_ARRAY(state->u.tex.last_layer);
1096	if (texture->nr_samples > 1) {
1097		unsigned log_samples = util_logbase2(texture->nr_samples);
1098		if (rscreen->chip_class == CAYMAN) {
1099			view->tex_resource_words[4] |= S_030010_LOG2_NUM_FRAGMENTS(log_samples);
1100		}
1101		/* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1102		view->tex_resource_words[5] |= S_030014_LAST_LEVEL(log_samples);
1103	} else {
1104		view->tex_resource_words[4] |= S_030010_BASE_LEVEL(state->u.tex.first_level);
1105		view->tex_resource_words[5] |= S_030014_LAST_LEVEL(state->u.tex.last_level);
1106	}
1107	/* aniso max 16 samples */
1108	view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1109				      (S_030018_TILE_SPLIT(tile_split));
1110	view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1111				      S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1112				      S_03001C_BANK_WIDTH(bankw) |
1113				      S_03001C_BANK_HEIGHT(bankh) |
1114				      S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1115				      S_03001C_NUM_BANKS(nbanks);
1116	return &view->base;
1117}
1118
1119static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1120					   struct pipe_sampler_view **views)
1121{
1122	r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
1123}
1124
1125static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1126					   struct pipe_sampler_view **views)
1127{
1128	r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
1129}
1130
1131static void evergreen_set_clip_state(struct pipe_context *ctx,
1132				const struct pipe_clip_state *state)
1133{
1134	struct r600_context *rctx = (struct r600_context *)ctx;
1135	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1136	struct pipe_constant_buffer cb;
1137
1138	if (rstate == NULL)
1139		return;
1140
1141	rctx->clip = *state;
1142	rstate->id = R600_PIPE_STATE_CLIP;
1143	for (int i = 0; i < 6; i++) {
1144		r600_pipe_state_add_reg(rstate,
1145					R_0285BC_PA_CL_UCP0_X + i * 16,
1146					fui(state->ucp[i][0]));
1147		r600_pipe_state_add_reg(rstate,
1148					R_0285C0_PA_CL_UCP0_Y + i * 16,
1149					fui(state->ucp[i][1]) );
1150		r600_pipe_state_add_reg(rstate,
1151					R_0285C4_PA_CL_UCP0_Z + i * 16,
1152					fui(state->ucp[i][2]));
1153		r600_pipe_state_add_reg(rstate,
1154					R_0285C8_PA_CL_UCP0_W + i * 16,
1155					fui(state->ucp[i][3]));
1156	}
1157
1158	free(rctx->states[R600_PIPE_STATE_CLIP]);
1159	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1160	r600_context_pipe_state_set(rctx, rstate);
1161
1162	cb.buffer = NULL;
1163	cb.user_buffer = state->ucp;
1164	cb.buffer_offset = 0;
1165	cb.buffer_size = 4*4*8;
1166	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1167	pipe_resource_reference(&cb.buffer, NULL);
1168}
1169
1170static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1171					 const struct pipe_poly_stipple *state)
1172{
1173}
1174
1175static void evergreen_get_scissor_rect(struct r600_context *rctx,
1176				       unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1177				       uint32_t *tl, uint32_t *br)
1178{
1179	/* EG hw workaround */
1180	if (br_x == 0)
1181		tl_x = 1;
1182	if (br_y == 0)
1183		tl_y = 1;
1184
1185	/* cayman hw workaround */
1186	if (rctx->chip_class == CAYMAN) {
1187		if (br_x == 1 && br_y == 1)
1188			br_x = 2;
1189	}
1190
1191	*tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1192	*br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1193}
1194
1195static void evergreen_set_scissor_state(struct pipe_context *ctx,
1196					const struct pipe_scissor_state *state)
1197{
1198	struct r600_context *rctx = (struct r600_context *)ctx;
1199	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1200	uint32_t tl, br;
1201
1202	if (rstate == NULL)
1203		return;
1204
1205	evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1206
1207	rstate->id = R600_PIPE_STATE_SCISSOR;
1208	r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1209	r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1210
1211	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1212	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1213	r600_context_pipe_state_set(rctx, rstate);
1214}
1215
1216static void evergreen_set_viewport_state(struct pipe_context *ctx,
1217					const struct pipe_viewport_state *state)
1218{
1219	struct r600_context *rctx = (struct r600_context *)ctx;
1220	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1221
1222	if (rstate == NULL)
1223		return;
1224
1225	rctx->viewport = *state;
1226	rstate->id = R600_PIPE_STATE_VIEWPORT;
1227	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1228	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1229	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1230	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1231	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1232	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1233
1234	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1235	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1236	r600_context_pipe_state_set(rctx, rstate);
1237}
1238
1239void evergreen_init_color_surface(struct r600_context *rctx,
1240				  struct r600_surface *surf)
1241{
1242	struct r600_screen *rscreen = rctx->screen;
1243	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1244	struct pipe_resource *pipe_tex = surf->base.texture;
1245	unsigned level = surf->base.u.tex.level;
1246	unsigned pitch, slice;
1247	unsigned color_info, color_attrib, color_dim = 0;
1248	unsigned format, swap, ntype, endian;
1249	uint64_t offset, base_offset;
1250	unsigned tile_type, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks;
1251	const struct util_format_description *desc;
1252	int i;
1253	bool blend_clamp = 0, blend_bypass = 0;
1254
1255	if (rtex->is_depth && !rtex->is_flushing_texture) {
1256		r600_init_flushed_depth_texture(&rctx->context, pipe_tex, NULL);
1257		rtex = rtex->flushed_depth_texture;
1258		assert(rtex);
1259	}
1260
1261	offset = rtex->surface.level[level].offset;
1262	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1263		offset += rtex->surface.level[level].slice_size *
1264			  surf->base.u.tex.first_layer;
1265	}
1266	pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1267	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1268	if (slice) {
1269		slice = slice - 1;
1270	}
1271	color_info = 0;
1272	switch (rtex->surface.level[level].mode) {
1273	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1274		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1275		tile_type = 1;
1276		break;
1277	case RADEON_SURF_MODE_1D:
1278		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1279		tile_type = rtex->tile_type;
1280		break;
1281	case RADEON_SURF_MODE_2D:
1282		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1283		tile_type = rtex->tile_type;
1284		break;
1285	case RADEON_SURF_MODE_LINEAR:
1286	default:
1287		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1288		tile_type = 1;
1289		break;
1290	}
1291	tile_split = rtex->surface.tile_split;
1292	macro_aspect = rtex->surface.mtilea;
1293	bankw = rtex->surface.bankw;
1294	bankh = rtex->surface.bankh;
1295	fmask_bankh = rtex->fmask_bank_height;
1296	tile_split = eg_tile_split(tile_split);
1297	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1298	bankw = eg_bank_wh(bankw);
1299	bankh = eg_bank_wh(bankh);
1300	fmask_bankh = eg_bank_wh(fmask_bankh);
1301
1302	/* 128 bit formats require tile type = 1 */
1303	if (rscreen->chip_class == CAYMAN) {
1304		if (util_format_get_blocksize(surf->base.format) >= 16)
1305			tile_type = 1;
1306	}
1307	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1308	desc = util_format_description(surf->base.format);
1309	for (i = 0; i < 4; i++) {
1310		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1311			break;
1312		}
1313	}
1314
1315	color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1316			S_028C74_NUM_BANKS(nbanks) |
1317			S_028C74_BANK_WIDTH(bankw) |
1318			S_028C74_BANK_HEIGHT(bankh) |
1319			S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1320			S_028C74_NON_DISP_TILING_ORDER(tile_type) |
1321		        S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1322
1323	if (rctx->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1324		unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1325		color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1326				S_028C74_NUM_FRAGMENTS(log_samples);
1327	}
1328
1329	ntype = V_028C70_NUMBER_UNORM;
1330	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1331		ntype = V_028C70_NUMBER_SRGB;
1332	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1333		if (desc->channel[i].normalized)
1334			ntype = V_028C70_NUMBER_SNORM;
1335		else if (desc->channel[i].pure_integer)
1336			ntype = V_028C70_NUMBER_SINT;
1337	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1338		if (desc->channel[i].normalized)
1339			ntype = V_028C70_NUMBER_UNORM;
1340		else if (desc->channel[i].pure_integer)
1341			ntype = V_028C70_NUMBER_UINT;
1342	}
1343
1344	format = r600_translate_colorformat(surf->base.format);
1345	assert(format != ~0);
1346
1347	swap = r600_translate_colorswap(surf->base.format);
1348	assert(swap != ~0);
1349
1350	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1351		endian = ENDIAN_NONE;
1352	} else {
1353		endian = r600_colorformat_endian_swap(format);
1354	}
1355
1356	/* blend clamp should be set for all NORM/SRGB types */
1357	if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1358	    ntype == V_028C70_NUMBER_SRGB)
1359		blend_clamp = 1;
1360
1361	/* set blend bypass according to docs if SINT/UINT or
1362	   8/24 COLOR variants */
1363	if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1364	    format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1365	    format == V_028C70_COLOR_X24_8_32_FLOAT) {
1366		blend_clamp = 0;
1367		blend_bypass = 1;
1368	}
1369
1370	surf->alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1371
1372	color_info |= S_028C70_FORMAT(format) |
1373		S_028C70_COMP_SWAP(swap) |
1374		S_028C70_BLEND_CLAMP(blend_clamp) |
1375		S_028C70_BLEND_BYPASS(blend_bypass) |
1376		S_028C70_NUMBER_TYPE(ntype) |
1377		S_028C70_ENDIAN(endian);
1378
1379	if (rtex->is_rat) {
1380		color_info |= S_028C70_RAT(1);
1381		color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1382				| S_028C78_HEIGHT_MAX(pipe_tex->height0);
1383	}
1384
1385	/* EXPORT_NORM is an optimzation that can be enabled for better
1386	 * performance in certain cases.
1387	 * EXPORT_NORM can be enabled if:
1388	 * - 11-bit or smaller UNORM/SNORM/SRGB
1389	 * - 16-bit or smaller FLOAT
1390	 */
1391	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1392	    ((desc->channel[i].size < 12 &&
1393	      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1394	      ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1395	     (desc->channel[i].size < 17 &&
1396	      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1397		color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1398		surf->export_16bpc = true;
1399	}
1400
1401	if (rtex->fmask_size && rtex->cmask_size) {
1402		color_info |= S_028C70_COMPRESSION(1) | S_028C70_FAST_CLEAR(1);
1403	}
1404
1405	base_offset = r600_resource_va(rctx->context.screen, pipe_tex);
1406
1407	/* XXX handle enabling of CB beyond BASE8 which has different offset */
1408	surf->cb_color_base = (base_offset + offset) >> 8;
1409	surf->cb_color_dim = color_dim;
1410	surf->cb_color_info = color_info;
1411	surf->cb_color_pitch = S_028C64_PITCH_TILE_MAX(pitch);
1412	surf->cb_color_slice = S_028C68_SLICE_TILE_MAX(slice);
1413	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1414		surf->cb_color_view = 0;
1415	} else {
1416		surf->cb_color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1417				      S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1418	}
1419	surf->cb_color_attrib = color_attrib;
1420	if (rtex->fmask_size && rtex->cmask_size) {
1421		surf->cb_color_fmask = (base_offset + rtex->fmask_offset) >> 8;
1422		surf->cb_color_cmask = (base_offset + rtex->cmask_offset) >> 8;
1423	} else {
1424		surf->cb_color_fmask = surf->cb_color_base;
1425		surf->cb_color_cmask = surf->cb_color_base;
1426	}
1427	surf->cb_color_fmask_slice = S_028C88_TILE_MAX(slice);
1428	surf->cb_color_cmask_slice = S_028C80_TILE_MAX(rtex->cmask_slice_tile_max);
1429
1430	surf->color_initialized = true;
1431}
1432
1433static void evergreen_init_depth_surface(struct r600_context *rctx,
1434					 struct r600_surface *surf)
1435{
1436	struct r600_screen *rscreen = rctx->screen;
1437	struct pipe_screen *screen = &rscreen->screen;
1438	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1439	uint64_t offset;
1440	unsigned level, pitch, slice, format, array_mode;
1441	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1442
1443	level = surf->base.u.tex.level;
1444	format = r600_translate_dbformat(surf->base.format);
1445	assert(format != ~0);
1446
1447	offset = r600_resource_va(screen, surf->base.texture);
1448	offset += rtex->surface.level[level].offset;
1449	pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1450	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1451	if (slice) {
1452		slice = slice - 1;
1453	}
1454	switch (rtex->surface.level[level].mode) {
1455	case RADEON_SURF_MODE_2D:
1456		array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1457		break;
1458	case RADEON_SURF_MODE_1D:
1459	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1460	case RADEON_SURF_MODE_LINEAR:
1461	default:
1462		array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1463		break;
1464	}
1465	tile_split = rtex->surface.tile_split;
1466	macro_aspect = rtex->surface.mtilea;
1467	bankw = rtex->surface.bankw;
1468	bankh = rtex->surface.bankh;
1469	tile_split = eg_tile_split(tile_split);
1470	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1471	bankw = eg_bank_wh(bankw);
1472	bankh = eg_bank_wh(bankh);
1473	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1474	offset >>= 8;
1475
1476	surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1477			      S_028040_FORMAT(format) |
1478			      S_028040_TILE_SPLIT(tile_split)|
1479			      S_028040_NUM_BANKS(nbanks) |
1480			      S_028040_BANK_WIDTH(bankw) |
1481			      S_028040_BANK_HEIGHT(bankh) |
1482			      S_028040_MACRO_TILE_ASPECT(macro_aspect);
1483	if (rscreen->chip_class == CAYMAN && rtex->resource.b.b.nr_samples > 1) {
1484		surf->db_depth_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1485	}
1486	surf->db_depth_base = offset;
1487	surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1488			      S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1489	surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1490	surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1491
1492	if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1493		uint64_t stencil_offset = rtex->surface.stencil_offset;
1494		unsigned stile_split = rtex->surface.stencil_tile_split;
1495
1496		stile_split = eg_tile_split(stile_split);
1497		stencil_offset += r600_resource_va(screen, surf->base.texture);
1498		stencil_offset += rtex->surface.level[level].offset / 4;
1499		stencil_offset >>= 8;
1500
1501		surf->db_stencil_base = stencil_offset;
1502		surf->db_stencil_info = 1 | S_028044_TILE_SPLIT(stile_split);
1503	} else {
1504		surf->db_stencil_base = offset;
1505		surf->db_stencil_info = 1;
1506	}
1507
1508	surf->depth_initialized = true;
1509}
1510
1511#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
1512	(((s0x) & 0xf) | (((s0y) & 0xf) << 4) |		   \
1513	(((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |	   \
1514	(((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |	   \
1515	 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1516
1517static uint32_t evergreen_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1518{
1519	/* 2xMSAA
1520	 * There are two locations (-4, 4), (4, -4). */
1521	static uint32_t sample_locs_2x[] = {
1522		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1523		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1524		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1525		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1526	};
1527	static unsigned max_dist_2x = 4;
1528	/* 4xMSAA
1529	 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1530	static uint32_t sample_locs_4x[] = {
1531		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1532		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1533		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1534		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1535	};
1536	static unsigned max_dist_4x = 6;
1537	/* 8xMSAA */
1538	static uint32_t sample_locs_8x[] = {
1539		FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1540		FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1541		FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1542		FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1543		FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1544		FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1545		FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1546		FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1547	};
1548	static unsigned max_dist_8x = 8;
1549	struct r600_context *rctx = (struct r600_context *)ctx;
1550	unsigned i;
1551
1552	switch (nsample) {
1553	case 2:
1554		for (i = 0; i < Elements(sample_locs_2x); i++) {
1555			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1556						sample_locs_2x[i]);
1557		}
1558		return max_dist_2x;
1559	case 4:
1560		for (i = 0; i < Elements(sample_locs_4x); i++) {
1561			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1562						sample_locs_4x[i]);
1563		}
1564		return max_dist_4x;
1565	case 8:
1566		for (i = 0; i < Elements(sample_locs_8x); i++) {
1567			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 + i*4,
1568						sample_locs_8x[i]);
1569		}
1570		return max_dist_8x;
1571	default:
1572		R600_ERR("Invalid nr_samples %i\n", nsample);
1573		return 0;
1574	}
1575}
1576
1577static uint32_t cayman_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1578{
1579	/* 2xMSAA
1580	 * There are two locations (-4, 4), (4, -4). */
1581	static uint32_t sample_locs_2x[] = {
1582		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1583		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1584		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1585		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1586	};
1587	static unsigned max_dist_2x = 4;
1588	/* 4xMSAA
1589	 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1590	static uint32_t sample_locs_4x[] = {
1591		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1592		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1593		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1594		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1595	};
1596	static unsigned max_dist_4x = 6;
1597	/* 8xMSAA */
1598	static uint32_t sample_locs_8x[] = {
1599		FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1600		FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1601		FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1602		FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1603		FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1604		FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1605		FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1606		FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1607	};
1608	static unsigned max_dist_8x = 8;
1609	/* 16xMSAA */
1610	static uint32_t sample_locs_16x[] = {
1611		FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1612		FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1613		FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1614		FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1615		FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1616		FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1617		FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1618		FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1619		FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1620		FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1621		FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1622		FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1623		FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1624		FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1625		FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1626		FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1627	};
1628	static unsigned max_dist_16x = 8;
1629	struct r600_context *rctx = (struct r600_context *)ctx;
1630	uint32_t max_dist, num_regs, *sample_locs;
1631
1632	switch (nsample) {
1633	case 2:
1634		sample_locs = sample_locs_2x;
1635		num_regs = Elements(sample_locs_2x);
1636		max_dist = max_dist_2x;
1637		break;
1638	case 4:
1639		sample_locs = sample_locs_4x;
1640		num_regs = Elements(sample_locs_4x);
1641		max_dist = max_dist_4x;
1642		break;
1643	case 8:
1644		sample_locs = sample_locs_8x;
1645		num_regs = Elements(sample_locs_8x);
1646		max_dist = max_dist_8x;
1647		break;
1648	case 16:
1649		sample_locs = sample_locs_16x;
1650		num_regs = Elements(sample_locs_16x);
1651		max_dist = max_dist_16x;
1652		break;
1653	default:
1654		R600_ERR("Invalid nr_samples %i\n", nsample);
1655		return 0;
1656	}
1657
1658	r600_pipe_state_add_reg(rstate, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs[0]);
1659	r600_pipe_state_add_reg(rstate, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs[1]);
1660	r600_pipe_state_add_reg(rstate, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs[2]);
1661	r600_pipe_state_add_reg(rstate, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs[3]);
1662	if (num_regs <= 8) {
1663		r600_pipe_state_add_reg(rstate, CM_R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, sample_locs[4]);
1664		r600_pipe_state_add_reg(rstate, CM_R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, sample_locs[5]);
1665		r600_pipe_state_add_reg(rstate, CM_R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, sample_locs[6]);
1666		r600_pipe_state_add_reg(rstate, CM_R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, sample_locs[7]);
1667	}
1668	if (num_regs <= 16) {
1669		r600_pipe_state_add_reg(rstate, CM_R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, sample_locs[8]);
1670		r600_pipe_state_add_reg(rstate, CM_R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, sample_locs[9]);
1671		r600_pipe_state_add_reg(rstate, CM_R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, sample_locs[10]);
1672		r600_pipe_state_add_reg(rstate, CM_R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, sample_locs[11]);
1673		r600_pipe_state_add_reg(rstate, CM_R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, sample_locs[12]);
1674		r600_pipe_state_add_reg(rstate, CM_R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, sample_locs[13]);
1675		r600_pipe_state_add_reg(rstate, CM_R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, sample_locs[14]);
1676		r600_pipe_state_add_reg(rstate, CM_R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, sample_locs[15]);
1677	}
1678	return max_dist;
1679}
1680
1681static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1682					    const struct pipe_framebuffer_state *state)
1683{
1684	struct r600_context *rctx = (struct r600_context *)ctx;
1685	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1686	struct r600_surface *surf;
1687	struct r600_resource *res;
1688	struct r600_texture *rtex;
1689	uint32_t tl, br, i, nr_samples, log_samples;
1690
1691	if (rstate == NULL)
1692		return;
1693
1694	r600_flush_framebuffer(rctx, false);
1695
1696	/* unreference old buffer and reference new one */
1697	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1698
1699	util_copy_framebuffer_state(&rctx->framebuffer, state);
1700
1701	/* Colorbuffers. */
1702	rctx->export_16bpc = true;
1703	rctx->nr_cbufs = state->nr_cbufs;
1704	rctx->cb0_is_integer = state->nr_cbufs &&
1705			       util_format_is_pure_integer(state->cbufs[0]->format);
1706	rctx->compressed_cb_mask = 0;
1707
1708	for (i = 0; i < state->nr_cbufs; i++) {
1709		surf = (struct r600_surface*)state->cbufs[i];
1710		res = (struct r600_resource*)surf->base.texture;
1711		rtex = (struct r600_texture*)res;
1712
1713		if (!surf->color_initialized) {
1714			evergreen_init_color_surface(rctx, surf);
1715		}
1716
1717		if (!surf->export_16bpc) {
1718			rctx->export_16bpc = false;
1719		}
1720
1721		r600_pipe_state_add_reg_bo(rstate, R_028C60_CB_COLOR0_BASE + i * 0x3C,
1722					   surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1723		r600_pipe_state_add_reg(rstate, R_028C78_CB_COLOR0_DIM + i * 0x3C,
1724					surf->cb_color_dim);
1725		r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C,
1726					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1727		r600_pipe_state_add_reg(rstate, R_028C64_CB_COLOR0_PITCH + i * 0x3C,
1728					surf->cb_color_pitch);
1729		r600_pipe_state_add_reg(rstate, R_028C68_CB_COLOR0_SLICE + i * 0x3C,
1730					surf->cb_color_slice);
1731		r600_pipe_state_add_reg(rstate, R_028C6C_CB_COLOR0_VIEW + i * 0x3C,
1732					surf->cb_color_view);
1733		r600_pipe_state_add_reg_bo(rstate, R_028C74_CB_COLOR0_ATTRIB + i * 0x3C,
1734					   surf->cb_color_attrib, res, RADEON_USAGE_READWRITE);
1735		r600_pipe_state_add_reg_bo(rstate, R_028C7C_CB_COLOR0_CMASK + i * 0x3c,
1736					   surf->cb_color_cmask, res, RADEON_USAGE_READWRITE);
1737		r600_pipe_state_add_reg(rstate, R_028C80_CB_COLOR0_CMASK_SLICE + i * 0x3c,
1738					surf->cb_color_cmask_slice);
1739		r600_pipe_state_add_reg_bo(rstate,  R_028C84_CB_COLOR0_FMASK + i * 0x3c,
1740					   surf->cb_color_fmask, res, RADEON_USAGE_READWRITE);
1741		r600_pipe_state_add_reg(rstate, R_028C88_CB_COLOR0_FMASK_SLICE + i * 0x3c,
1742					surf->cb_color_fmask_slice);
1743
1744		/* Cayman can fetch from a compressed MSAA colorbuffer,
1745		 * so it's pointless to track them. */
1746		if (rctx->chip_class != CAYMAN && rtex->fmask_size && rtex->cmask_size) {
1747			rctx->compressed_cb_mask |= 1 << i;
1748		}
1749	}
1750	/* set CB_COLOR1_INFO for possible dual-src blending */
1751	if (i == 1 && !((struct r600_texture*)res)->is_rat) {
1752		r600_pipe_state_add_reg_bo(rstate, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1753					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1754		i++;
1755	}
1756	for (; i < 8 ; i++) {
1757		r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1758	}
1759
1760	/* Update alpha-test state dependencies.
1761	 * Alpha-test is done on the first colorbuffer only. */
1762	if (state->nr_cbufs) {
1763		surf = (struct r600_surface*)state->cbufs[0];
1764		if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1765			rctx->alphatest_state.bypass = surf->alphatest_bypass;
1766			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1767		}
1768		if (rctx->alphatest_state.cb0_export_16bpc != surf->export_16bpc) {
1769			rctx->alphatest_state.cb0_export_16bpc = surf->export_16bpc;
1770			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1771		}
1772	}
1773
1774	/* ZS buffer. */
1775	if (state->zsbuf) {
1776		surf = (struct r600_surface*)state->zsbuf;
1777		res = (struct r600_resource*)surf->base.texture;
1778
1779		if (!surf->depth_initialized) {
1780			evergreen_init_depth_surface(rctx, surf);
1781		}
1782
1783		r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1784					   res, RADEON_USAGE_READWRITE);
1785		r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1786					   res, RADEON_USAGE_READWRITE);
1787		r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1788
1789		r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1790					   res, RADEON_USAGE_READWRITE);
1791		r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1792					   res, RADEON_USAGE_READWRITE);
1793		r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1794					   res, RADEON_USAGE_READWRITE);
1795
1796		r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1797					   res, RADEON_USAGE_READWRITE);
1798		r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1799		r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
1800	}
1801
1802	/* Framebuffer dimensions. */
1803	evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1804
1805	r600_pipe_state_add_reg(rstate,
1806				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1807	r600_pipe_state_add_reg(rstate,
1808				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1809
1810	/* Multisampling */
1811	if (state->nr_cbufs)
1812		nr_samples = state->cbufs[0]->texture->nr_samples;
1813	else if (state->zsbuf)
1814		nr_samples = state->zsbuf->texture->nr_samples;
1815	else
1816		nr_samples = 0;
1817
1818	if (nr_samples > 1) {
1819		unsigned line_cntl = S_028C00_LAST_PIXEL(1) |
1820				     S_028C00_EXPAND_LINE_WIDTH(1);
1821		log_samples = util_logbase2(nr_samples);
1822
1823		if (rctx->chip_class == CAYMAN) {
1824			unsigned max_dist = cayman_set_ms_pos(ctx, rstate, nr_samples);
1825
1826			r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, line_cntl);
1827			r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG,
1828						S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1829						S_028BE0_MAX_SAMPLE_DIST(max_dist) |
1830						S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
1831			r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
1832						S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1833						S_028804_PS_ITER_SAMPLES(log_samples) |
1834						S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1835						S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
1836						S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1837						S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1838		} else {
1839			unsigned max_dist = evergreen_set_ms_pos(ctx, rstate, nr_samples);
1840
1841			r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, line_cntl);
1842			r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1843						S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1844						S_028C04_MAX_SAMPLE_DIST(max_dist));
1845		}
1846	} else {
1847		log_samples = 0;
1848
1849		if (rctx->chip_class == CAYMAN) {
1850			r600_pipe_state_add_reg(rstate, CM_R_028BDC_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1851			r600_pipe_state_add_reg(rstate, CM_R_028BE0_PA_SC_AA_CONFIG, 0);
1852			r600_pipe_state_add_reg(rstate, CM_R_028804_DB_EQAA,
1853						S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1854						S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
1855
1856		} else {
1857			r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1858			r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1859		}
1860	}
1861
1862	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1863	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1864	r600_context_pipe_state_set(rctx, rstate);
1865
1866	if (state->zsbuf) {
1867		evergreen_polygon_offset_update(rctx);
1868	}
1869
1870	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1871		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1872		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1873	}
1874
1875	if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1876		rctx->alphatest_state.bypass = false;
1877		r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1878	}
1879
1880	if (rctx->chip_class == CAYMAN && rctx->db_misc_state.log_samples != log_samples) {
1881		rctx->db_misc_state.log_samples = log_samples;
1882		r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1883	}
1884}
1885
1886static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1887{
1888	struct radeon_winsys_cs *cs = rctx->cs;
1889	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1890	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1891	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1892
1893	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1894	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1895	/* Always enable the first colorbuffer in CB_SHADER_MASK. This
1896	 * will assure that the alpha-test will work even if there is
1897	 * no colorbuffer bound. */
1898	r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1899}
1900
1901static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1902{
1903	struct radeon_winsys_cs *cs = rctx->cs;
1904	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1905	unsigned db_render_control = 0;
1906	unsigned db_count_control = 0;
1907	unsigned db_render_override =
1908		S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1909		S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1910		S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1911
1912	if (a->occlusion_query_enabled) {
1913		db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1914		if (rctx->chip_class == CAYMAN) {
1915			db_count_control |= S_028004_SAMPLE_RATE(a->log_samples);
1916		}
1917		db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1918	}
1919
1920	if (a->flush_depthstencil_through_cb) {
1921		assert(a->copy_depth || a->copy_stencil);
1922
1923		db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1924				     S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1925				     S_028000_COPY_CENTROID(1) |
1926				     S_028000_COPY_SAMPLE(a->copy_sample);
1927	}
1928
1929	r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1930	r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1931	r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1932	r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1933}
1934
1935static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1936					  struct r600_vertexbuf_state *state,
1937					  unsigned resource_offset,
1938					  unsigned pkt_flags)
1939{
1940	struct radeon_winsys_cs *cs = rctx->cs;
1941	uint32_t dirty_mask = state->dirty_mask;
1942
1943	while (dirty_mask) {
1944		struct pipe_vertex_buffer *vb;
1945		struct r600_resource *rbuffer;
1946		uint64_t va;
1947		unsigned buffer_index = u_bit_scan(&dirty_mask);
1948
1949		vb = &state->vb[buffer_index];
1950		rbuffer = (struct r600_resource*)vb->buffer;
1951		assert(rbuffer);
1952
1953		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1954		va += vb->buffer_offset;
1955
1956		/* fetch resources start at index 992 */
1957		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1958		r600_write_value(cs, (resource_offset + buffer_index) * 8);
1959		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1960		r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1961		r600_write_value(cs, /* RESOURCEi_WORD2 */
1962				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1963				 S_030008_STRIDE(vb->stride) |
1964				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1965		r600_write_value(cs, /* RESOURCEi_WORD3 */
1966				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1967				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1968				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1969				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1970		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1971		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1972		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1973		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1974
1975		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1976		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1977	}
1978	state->dirty_mask = 0;
1979}
1980
1981static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1982{
1983	evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1984}
1985
1986static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1987{
1988	evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1989				      RADEON_CP_PACKET3_COMPUTE_MODE);
1990}
1991
1992static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1993					    struct r600_constbuf_state *state,
1994					    unsigned buffer_id_base,
1995					    unsigned reg_alu_constbuf_size,
1996					    unsigned reg_alu_const_cache)
1997{
1998	struct radeon_winsys_cs *cs = rctx->cs;
1999	uint32_t dirty_mask = state->dirty_mask;
2000
2001	while (dirty_mask) {
2002		struct pipe_constant_buffer *cb;
2003		struct r600_resource *rbuffer;
2004		uint64_t va;
2005		unsigned buffer_index = ffs(dirty_mask) - 1;
2006
2007		cb = &state->cb[buffer_index];
2008		rbuffer = (struct r600_resource*)cb->buffer;
2009		assert(rbuffer);
2010
2011		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
2012		va += cb->buffer_offset;
2013
2014		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
2015				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
2016		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
2017
2018		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2019		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2020
2021		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2022		r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
2023		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
2024		r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
2025		r600_write_value(cs, /* RESOURCEi_WORD2 */
2026				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
2027				 S_030008_STRIDE(16) |
2028				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
2029		r600_write_value(cs, /* RESOURCEi_WORD3 */
2030				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
2031				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
2032				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
2033				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
2034		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
2035		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
2036		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
2037		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
2038
2039		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2040		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
2041
2042		dirty_mask &= ~(1 << buffer_index);
2043	}
2044	state->dirty_mask = 0;
2045}
2046
2047static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2048{
2049	evergreen_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 176,
2050					R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
2051					R_028980_ALU_CONST_CACHE_VS_0);
2052}
2053
2054static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
2055{
2056	evergreen_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
2057				       R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
2058				       R_028940_ALU_CONST_CACHE_PS_0);
2059}
2060
2061static void evergreen_emit_sampler_views(struct r600_context *rctx,
2062					 struct r600_samplerview_state *state,
2063					 unsigned resource_id_base)
2064{
2065	struct radeon_winsys_cs *cs = rctx->cs;
2066	uint32_t dirty_mask = state->dirty_mask;
2067
2068	while (dirty_mask) {
2069		struct r600_pipe_sampler_view *rview;
2070		unsigned resource_index = u_bit_scan(&dirty_mask);
2071		unsigned reloc;
2072
2073		rview = state->views[resource_index];
2074		assert(rview);
2075
2076		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
2077		r600_write_value(cs, (resource_id_base + resource_index) * 8);
2078		r600_write_array(cs, 8, rview->tex_resource_words);
2079
2080		/* XXX The kernel needs two relocations. This is stupid. */
2081		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
2082					      RADEON_USAGE_READ);
2083		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2084		r600_write_value(cs, reloc);
2085		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
2086		r600_write_value(cs, reloc);
2087	}
2088	state->dirty_mask = 0;
2089}
2090
2091static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2092{
2093	evergreen_emit_sampler_views(rctx, &rctx->vs_samplers.views, 176 + R600_MAX_CONST_BUFFERS);
2094}
2095
2096static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
2097{
2098	evergreen_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
2099}
2100
2101static void evergreen_emit_sampler(struct r600_context *rctx,
2102				struct r600_textures_info *texinfo,
2103				unsigned resource_id_base,
2104				unsigned border_index_reg)
2105{
2106	struct radeon_winsys_cs *cs = rctx->cs;
2107	unsigned i;
2108
2109	for (i = 0; i < texinfo->n_samplers; i++) {
2110
2111		if (texinfo->samplers[i] == NULL) {
2112			continue;
2113		}
2114		r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
2115		r600_write_value(cs, (resource_id_base + i) * 3);
2116		r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
2117
2118		if (texinfo->samplers[i]->border_color_use) {
2119			r600_write_config_reg_seq(cs, border_index_reg, 5);
2120			r600_write_value(cs, i);
2121			r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
2122		}
2123	}
2124}
2125
2126static void evergreen_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
2127{
2128	evergreen_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A414_TD_VS_SAMPLER0_BORDER_INDEX);
2129}
2130
2131static void evergreen_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
2132{
2133	evergreen_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_INDEX);
2134}
2135
2136static void evergreen_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2137{
2138	struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2139	uint8_t mask = s->sample_mask;
2140
2141	r600_write_context_reg(rctx->cs, R_028C3C_PA_SC_AA_MASK,
2142			       mask | (mask << 8) | (mask << 16) | (mask << 24));
2143}
2144
2145static void cayman_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2146{
2147	struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2148	struct radeon_winsys_cs *cs = rctx->cs;
2149	uint16_t mask = s->sample_mask;
2150
2151	r600_write_context_reg_seq(cs, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2152	r600_write_value(cs, mask | (mask << 16)); /* X0Y0_X1Y0 */
2153	r600_write_value(cs, mask | (mask << 16)); /* X0Y1_X1Y1 */
2154}
2155
2156void evergreen_init_state_functions(struct r600_context *rctx)
2157{
2158	r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
2159	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2160	r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 7, 0);
2161	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
2162	r600_init_atom(&rctx->vertex_buffer_state.atom, evergreen_fs_emit_vertex_buffers, 0, 0);
2163	r600_init_atom(&rctx->cs_vertex_buffer_state.atom, evergreen_cs_emit_vertex_buffers, 0, 0);
2164	r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
2165	r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
2166	r600_init_atom(&rctx->vs_samplers.views.atom, evergreen_emit_vs_sampler_views, 0, 0);
2167	r600_init_atom(&rctx->ps_samplers.views.atom, evergreen_emit_ps_sampler_views, 0, 0);
2168	r600_init_atom(&rctx->cs_shader_state.atom, evergreen_emit_cs_shader, 0, 0);
2169	r600_init_atom(&rctx->vs_samplers.atom_sampler, evergreen_emit_vs_sampler, 0, 0);
2170	r600_init_atom(&rctx->ps_samplers.atom_sampler, evergreen_emit_ps_sampler, 0, 0);
2171
2172	if (rctx->chip_class == EVERGREEN)
2173		r600_init_atom(&rctx->sample_mask.atom, evergreen_emit_sample_mask, 3, 0);
2174	else
2175		r600_init_atom(&rctx->sample_mask.atom, cayman_emit_sample_mask, 4, 0);
2176	rctx->sample_mask.sample_mask = ~0;
2177	r600_atom_dirty(rctx, &rctx->sample_mask.atom);
2178
2179	rctx->context.create_blend_state = evergreen_create_blend_state;
2180	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
2181	rctx->context.create_fs_state = r600_create_shader_state_ps;
2182	rctx->context.create_rasterizer_state = evergreen_create_rs_state;
2183	rctx->context.create_sampler_state = evergreen_create_sampler_state;
2184	rctx->context.create_sampler_view = evergreen_create_sampler_view;
2185	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
2186	rctx->context.create_vs_state = r600_create_shader_state_vs;
2187	rctx->context.bind_blend_state = r600_bind_blend_state;
2188	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2189	rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
2190	rctx->context.bind_fs_state = r600_bind_ps_shader;
2191	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
2192	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
2193	rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
2194	rctx->context.bind_vs_state = r600_bind_vs_shader;
2195	rctx->context.delete_blend_state = r600_delete_state;
2196	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
2197	rctx->context.delete_fs_state = r600_delete_ps_shader;
2198	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
2199	rctx->context.delete_sampler_state = r600_delete_sampler;
2200	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
2201	rctx->context.delete_vs_state = r600_delete_vs_shader;
2202	rctx->context.set_blend_color = r600_set_blend_color;
2203	rctx->context.set_clip_state = evergreen_set_clip_state;
2204	rctx->context.set_constant_buffer = r600_set_constant_buffer;
2205	rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_views;
2206	rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
2207	rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
2208	rctx->context.set_sample_mask = r600_set_sample_mask;
2209	rctx->context.set_scissor_state = evergreen_set_scissor_state;
2210	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
2211	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
2212	rctx->context.set_index_buffer = r600_set_index_buffer;
2213	rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_views;
2214	rctx->context.set_viewport_state = evergreen_set_viewport_state;
2215	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
2216	rctx->context.texture_barrier = r600_texture_barrier;
2217	rctx->context.create_stream_output_target = r600_create_so_target;
2218	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
2219	rctx->context.set_stream_output_targets = r600_set_so_targets;
2220	evergreen_init_compute_state_functions(rctx);
2221}
2222
2223static void cayman_init_atom_start_cs(struct r600_context *rctx)
2224{
2225	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2226
2227	r600_init_command_buffer(cb, 256, EMIT_EARLY);
2228
2229	/* This must be first. */
2230	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2231	r600_store_value(cb, 0x80000000);
2232	r600_store_value(cb, 0x80000000);
2233
2234	r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2235	r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
2236	/* always set the temp clauses */
2237	r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2238
2239	r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2240	r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2241	r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2242
2243	r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2244
2245	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2246
2247	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2248	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2249	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2250	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2251	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2252	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2253	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2254	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2255	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2256	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2257	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2258	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2259	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2260	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2261
2262	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2263	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2264	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2265
2266	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2267	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2268	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2269
2270	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2271
2272	r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2273
2274	r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2275	r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2276	r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2277
2278	r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2279	r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2280	r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2281
2282	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2283	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2284	r600_store_value(cb, 0);
2285	r600_store_value(cb, 0);
2286	r600_store_value(cb, 0);
2287	r600_store_value(cb, 0);
2288	r600_store_value(cb, 0);
2289	r600_store_value(cb, 0);
2290	r600_store_value(cb, 0);
2291	r600_store_value(cb, 0);
2292	r600_store_value(cb, 0);
2293	r600_store_value(cb, 0);
2294	r600_store_value(cb, 0);
2295	r600_store_value(cb, 0);
2296	r600_store_value(cb, 0);
2297	r600_store_value(cb, 0);
2298	r600_store_value(cb, 0);
2299	r600_store_value(cb, 0);
2300	r600_store_value(cb, 0);
2301	r600_store_value(cb, 0);
2302	r600_store_value(cb, 0);
2303	r600_store_value(cb, 0);
2304	r600_store_value(cb, 0);
2305	r600_store_value(cb, 0);
2306	r600_store_value(cb, 0);
2307	r600_store_value(cb, 0);
2308	r600_store_value(cb, 0);
2309	r600_store_value(cb, 0);
2310	r600_store_value(cb, 0);
2311	r600_store_value(cb, 0);
2312	r600_store_value(cb, 0);
2313	r600_store_value(cb, 0);
2314	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2315	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2316	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2317
2318	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2319
2320	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2321	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2322	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2323
2324	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2325
2326	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2327	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2328	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2329	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2330
2331	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2332	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2333
2334	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2335	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2336	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2337
2338	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2339	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2340	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2341
2342	r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2343	r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2344	r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2345	r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2346	r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2347
2348	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2349	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2350	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2351
2352	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2353	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2354	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2355
2356	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2357	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2358	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2359
2360	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2361	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2362	if (rctx->screen->has_streamout) {
2363		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2364	}
2365
2366	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2367	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2368}
2369
2370void evergreen_init_common_regs(struct r600_command_buffer *cb,
2371	enum chip_class ctx_chip_class,
2372	enum radeon_family ctx_family,
2373	int ctx_drm_minor)
2374{
2375	int ps_prio;
2376	int vs_prio;
2377	int gs_prio;
2378	int es_prio;
2379
2380	int hs_prio;
2381	int cs_prio;
2382	int ls_prio;
2383
2384	int num_ps_gprs;
2385	int num_vs_gprs;
2386	int num_gs_gprs;
2387	int num_es_gprs;
2388	int num_hs_gprs;
2389	int num_ls_gprs;
2390	int num_temp_gprs;
2391
2392	unsigned tmp;
2393
2394	ps_prio = 0;
2395	vs_prio = 1;
2396	gs_prio = 2;
2397	es_prio = 3;
2398	hs_prio = 0;
2399	ls_prio = 0;
2400	cs_prio = 0;
2401
2402	switch (ctx_family) {
2403	case CHIP_CEDAR:
2404	default:
2405		num_ps_gprs = 93;
2406		num_vs_gprs = 46;
2407		num_temp_gprs = 4;
2408		num_gs_gprs = 31;
2409		num_es_gprs = 31;
2410		num_hs_gprs = 23;
2411		num_ls_gprs = 23;
2412		break;
2413	case CHIP_REDWOOD:
2414		num_ps_gprs = 93;
2415		num_vs_gprs = 46;
2416		num_temp_gprs = 4;
2417		num_gs_gprs = 31;
2418		num_es_gprs = 31;
2419		num_hs_gprs = 23;
2420		num_ls_gprs = 23;
2421		break;
2422	case CHIP_JUNIPER:
2423		num_ps_gprs = 93;
2424		num_vs_gprs = 46;
2425		num_temp_gprs = 4;
2426		num_gs_gprs = 31;
2427		num_es_gprs = 31;
2428		num_hs_gprs = 23;
2429		num_ls_gprs = 23;
2430		break;
2431	case CHIP_CYPRESS:
2432	case CHIP_HEMLOCK:
2433		num_ps_gprs = 93;
2434		num_vs_gprs = 46;
2435		num_temp_gprs = 4;
2436		num_gs_gprs = 31;
2437		num_es_gprs = 31;
2438		num_hs_gprs = 23;
2439		num_ls_gprs = 23;
2440		break;
2441	case CHIP_PALM:
2442		num_ps_gprs = 93;
2443		num_vs_gprs = 46;
2444		num_temp_gprs = 4;
2445		num_gs_gprs = 31;
2446		num_es_gprs = 31;
2447		num_hs_gprs = 23;
2448		num_ls_gprs = 23;
2449		break;
2450	case CHIP_SUMO:
2451		num_ps_gprs = 93;
2452		num_vs_gprs = 46;
2453		num_temp_gprs = 4;
2454		num_gs_gprs = 31;
2455		num_es_gprs = 31;
2456		num_hs_gprs = 23;
2457		num_ls_gprs = 23;
2458		break;
2459	case CHIP_SUMO2:
2460		num_ps_gprs = 93;
2461		num_vs_gprs = 46;
2462		num_temp_gprs = 4;
2463		num_gs_gprs = 31;
2464		num_es_gprs = 31;
2465		num_hs_gprs = 23;
2466		num_ls_gprs = 23;
2467		break;
2468	case CHIP_BARTS:
2469		num_ps_gprs = 93;
2470		num_vs_gprs = 46;
2471		num_temp_gprs = 4;
2472		num_gs_gprs = 31;
2473		num_es_gprs = 31;
2474		num_hs_gprs = 23;
2475		num_ls_gprs = 23;
2476		break;
2477	case CHIP_TURKS:
2478		num_ps_gprs = 93;
2479		num_vs_gprs = 46;
2480		num_temp_gprs = 4;
2481		num_gs_gprs = 31;
2482		num_es_gprs = 31;
2483		num_hs_gprs = 23;
2484		num_ls_gprs = 23;
2485		break;
2486	case CHIP_CAICOS:
2487		num_ps_gprs = 93;
2488		num_vs_gprs = 46;
2489		num_temp_gprs = 4;
2490		num_gs_gprs = 31;
2491		num_es_gprs = 31;
2492		num_hs_gprs = 23;
2493		num_ls_gprs = 23;
2494		break;
2495	}
2496
2497	tmp = 0;
2498	switch (ctx_family) {
2499	case CHIP_CEDAR:
2500	case CHIP_PALM:
2501	case CHIP_SUMO:
2502	case CHIP_SUMO2:
2503	case CHIP_CAICOS:
2504		break;
2505	default:
2506		tmp |= S_008C00_VC_ENABLE(1);
2507		break;
2508	}
2509	tmp |= S_008C00_EXPORT_SRC_C(1);
2510	tmp |= S_008C00_CS_PRIO(cs_prio);
2511	tmp |= S_008C00_LS_PRIO(ls_prio);
2512	tmp |= S_008C00_HS_PRIO(hs_prio);
2513	tmp |= S_008C00_PS_PRIO(ps_prio);
2514	tmp |= S_008C00_VS_PRIO(vs_prio);
2515	tmp |= S_008C00_GS_PRIO(gs_prio);
2516	tmp |= S_008C00_ES_PRIO(es_prio);
2517
2518	/* enable dynamic GPR resource management */
2519	if (ctx_drm_minor >= 7) {
2520		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2521		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2522		/* always set temp clauses */
2523		r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2524		r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2525		r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2526		r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2527		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2528		r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2529					S_028838_PS_GPRS(0x1e) |
2530					S_028838_VS_GPRS(0x1e) |
2531					S_028838_GS_GPRS(0x1e) |
2532					S_028838_ES_GPRS(0x1e) |
2533					S_028838_HS_GPRS(0x1e) |
2534					S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2535	} else {
2536		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2537		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2538
2539		tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2540		tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2541		tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2542		r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2543
2544		tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2545		tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2546		r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2547
2548		tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2549		tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2550		r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2551	}
2552
2553	r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2554			      S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2555
2556	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2557
2558	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2559	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2560	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2561
2562	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2563
2564	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2565	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2566	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2567
2568	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2569	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2570	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2571	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2572
2573	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2574	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2575
2576	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2577
2578	return;
2579}
2580
2581void evergreen_init_atom_start_cs(struct r600_context *rctx)
2582{
2583	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2584	int num_ps_threads;
2585	int num_vs_threads;
2586	int num_gs_threads;
2587	int num_es_threads;
2588	int num_hs_threads;
2589	int num_ls_threads;
2590
2591	int num_ps_stack_entries;
2592	int num_vs_stack_entries;
2593	int num_gs_stack_entries;
2594	int num_es_stack_entries;
2595	int num_hs_stack_entries;
2596	int num_ls_stack_entries;
2597	enum radeon_family family;
2598	unsigned tmp;
2599
2600	if (rctx->chip_class == CAYMAN) {
2601		cayman_init_atom_start_cs(rctx);
2602		return;
2603	}
2604
2605	r600_init_command_buffer(cb, 256, EMIT_EARLY);
2606
2607	/* This must be first. */
2608	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2609	r600_store_value(cb, 0x80000000);
2610	r600_store_value(cb, 0x80000000);
2611
2612	evergreen_init_common_regs(cb, rctx->chip_class
2613			, rctx->family, rctx->screen->info.drm_minor);
2614
2615	family = rctx->family;
2616	switch (family) {
2617	case CHIP_CEDAR:
2618	default:
2619		num_ps_threads = 96;
2620		num_vs_threads = 16;
2621		num_gs_threads = 16;
2622		num_es_threads = 16;
2623		num_hs_threads = 16;
2624		num_ls_threads = 16;
2625		num_ps_stack_entries = 42;
2626		num_vs_stack_entries = 42;
2627		num_gs_stack_entries = 42;
2628		num_es_stack_entries = 42;
2629		num_hs_stack_entries = 42;
2630		num_ls_stack_entries = 42;
2631		break;
2632	case CHIP_REDWOOD:
2633		num_ps_threads = 128;
2634		num_vs_threads = 20;
2635		num_gs_threads = 20;
2636		num_es_threads = 20;
2637		num_hs_threads = 20;
2638		num_ls_threads = 20;
2639		num_ps_stack_entries = 42;
2640		num_vs_stack_entries = 42;
2641		num_gs_stack_entries = 42;
2642		num_es_stack_entries = 42;
2643		num_hs_stack_entries = 42;
2644		num_ls_stack_entries = 42;
2645		break;
2646	case CHIP_JUNIPER:
2647		num_ps_threads = 128;
2648		num_vs_threads = 20;
2649		num_gs_threads = 20;
2650		num_es_threads = 20;
2651		num_hs_threads = 20;
2652		num_ls_threads = 20;
2653		num_ps_stack_entries = 85;
2654		num_vs_stack_entries = 85;
2655		num_gs_stack_entries = 85;
2656		num_es_stack_entries = 85;
2657		num_hs_stack_entries = 85;
2658		num_ls_stack_entries = 85;
2659		break;
2660	case CHIP_CYPRESS:
2661	case CHIP_HEMLOCK:
2662		num_ps_threads = 128;
2663		num_vs_threads = 20;
2664		num_gs_threads = 20;
2665		num_es_threads = 20;
2666		num_hs_threads = 20;
2667		num_ls_threads = 20;
2668		num_ps_stack_entries = 85;
2669		num_vs_stack_entries = 85;
2670		num_gs_stack_entries = 85;
2671		num_es_stack_entries = 85;
2672		num_hs_stack_entries = 85;
2673		num_ls_stack_entries = 85;
2674		break;
2675	case CHIP_PALM:
2676		num_ps_threads = 96;
2677		num_vs_threads = 16;
2678		num_gs_threads = 16;
2679		num_es_threads = 16;
2680		num_hs_threads = 16;
2681		num_ls_threads = 16;
2682		num_ps_stack_entries = 42;
2683		num_vs_stack_entries = 42;
2684		num_gs_stack_entries = 42;
2685		num_es_stack_entries = 42;
2686		num_hs_stack_entries = 42;
2687		num_ls_stack_entries = 42;
2688		break;
2689	case CHIP_SUMO:
2690		num_ps_threads = 96;
2691		num_vs_threads = 25;
2692		num_gs_threads = 25;
2693		num_es_threads = 25;
2694		num_hs_threads = 25;
2695		num_ls_threads = 25;
2696		num_ps_stack_entries = 42;
2697		num_vs_stack_entries = 42;
2698		num_gs_stack_entries = 42;
2699		num_es_stack_entries = 42;
2700		num_hs_stack_entries = 42;
2701		num_ls_stack_entries = 42;
2702		break;
2703	case CHIP_SUMO2:
2704		num_ps_threads = 96;
2705		num_vs_threads = 25;
2706		num_gs_threads = 25;
2707		num_es_threads = 25;
2708		num_hs_threads = 25;
2709		num_ls_threads = 25;
2710		num_ps_stack_entries = 85;
2711		num_vs_stack_entries = 85;
2712		num_gs_stack_entries = 85;
2713		num_es_stack_entries = 85;
2714		num_hs_stack_entries = 85;
2715		num_ls_stack_entries = 85;
2716		break;
2717	case CHIP_BARTS:
2718		num_ps_threads = 128;
2719		num_vs_threads = 20;
2720		num_gs_threads = 20;
2721		num_es_threads = 20;
2722		num_hs_threads = 20;
2723		num_ls_threads = 20;
2724		num_ps_stack_entries = 85;
2725		num_vs_stack_entries = 85;
2726		num_gs_stack_entries = 85;
2727		num_es_stack_entries = 85;
2728		num_hs_stack_entries = 85;
2729		num_ls_stack_entries = 85;
2730		break;
2731	case CHIP_TURKS:
2732		num_ps_threads = 128;
2733		num_vs_threads = 20;
2734		num_gs_threads = 20;
2735		num_es_threads = 20;
2736		num_hs_threads = 20;
2737		num_ls_threads = 20;
2738		num_ps_stack_entries = 42;
2739		num_vs_stack_entries = 42;
2740		num_gs_stack_entries = 42;
2741		num_es_stack_entries = 42;
2742		num_hs_stack_entries = 42;
2743		num_ls_stack_entries = 42;
2744		break;
2745	case CHIP_CAICOS:
2746		num_ps_threads = 128;
2747		num_vs_threads = 10;
2748		num_gs_threads = 10;
2749		num_es_threads = 10;
2750		num_hs_threads = 10;
2751		num_ls_threads = 10;
2752		num_ps_stack_entries = 42;
2753		num_vs_stack_entries = 42;
2754		num_gs_stack_entries = 42;
2755		num_es_stack_entries = 42;
2756		num_hs_stack_entries = 42;
2757		num_ls_stack_entries = 42;
2758		break;
2759	}
2760
2761	tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2762	tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2763	tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2764	tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2765
2766	r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2767	r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2768
2769	tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2770	tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2771	r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2772
2773	tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2774	tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2775	r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2776
2777	tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2778	tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2779	r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2780
2781	tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2782	tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2783	r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2784
2785	r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2786	r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2787
2788	r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2789	r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2790	r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2791	r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2792	r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2793	r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2794	r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2795
2796	r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2797	r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2798	r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2799	r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2800	r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2801
2802	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2803	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2804	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2805	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2806	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2807	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2808	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2809	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2810	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2811	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2812	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2813	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2814	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2815	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2816
2817	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2818	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2819	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2820
2821	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2822
2823	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2824	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2825	r600_store_value(cb, 0);
2826	r600_store_value(cb, 0);
2827	r600_store_value(cb, 0);
2828	r600_store_value(cb, 0);
2829	r600_store_value(cb, 0);
2830	r600_store_value(cb, 0);
2831	r600_store_value(cb, 0);
2832	r600_store_value(cb, 0);
2833	r600_store_value(cb, 0);
2834	r600_store_value(cb, 0);
2835	r600_store_value(cb, 0);
2836	r600_store_value(cb, 0);
2837	r600_store_value(cb, 0);
2838	r600_store_value(cb, 0);
2839	r600_store_value(cb, 0);
2840	r600_store_value(cb, 0);
2841	r600_store_value(cb, 0);
2842	r600_store_value(cb, 0);
2843	r600_store_value(cb, 0);
2844	r600_store_value(cb, 0);
2845	r600_store_value(cb, 0);
2846	r600_store_value(cb, 0);
2847	r600_store_value(cb, 0);
2848	r600_store_value(cb, 0);
2849	r600_store_value(cb, 0);
2850	r600_store_value(cb, 0);
2851	r600_store_value(cb, 0);
2852	r600_store_value(cb, 0);
2853	r600_store_value(cb, 0);
2854	r600_store_value(cb, 0);
2855	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2856	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2857	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2858
2859	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2860
2861	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2862	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2863	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2864
2865	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2866	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2867
2868	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2869	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2870	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2871
2872	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2873	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2874	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2875	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2876
2877	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2878	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2879	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2880	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2881	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2882
2883	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2884	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2885	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2886
2887	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2888	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2889	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2890
2891	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2892
2893	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2894	if (rctx->screen->has_streamout) {
2895		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2896	}
2897
2898	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2899	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2900}
2901
2902void evergreen_polygon_offset_update(struct r600_context *rctx)
2903{
2904	struct r600_pipe_state state;
2905
2906	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2907	state.nregs = 0;
2908	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2909		float offset_units = rctx->rasterizer->offset_units;
2910		unsigned offset_db_fmt_cntl = 0, depth;
2911
2912		switch (rctx->framebuffer.zsbuf->format) {
2913		case PIPE_FORMAT_Z24X8_UNORM:
2914		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2915			depth = -24;
2916			offset_units *= 2.0f;
2917			break;
2918		case PIPE_FORMAT_Z32_FLOAT:
2919		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2920			depth = -23;
2921			offset_units *= 1.0f;
2922			offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2923			break;
2924		case PIPE_FORMAT_Z16_UNORM:
2925			depth = -16;
2926			offset_units *= 4.0f;
2927			break;
2928		default:
2929			return;
2930		}
2931		/* XXX some of those reg can be computed with cso */
2932		offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2933		r600_pipe_state_add_reg(&state,
2934				R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2935				fui(rctx->rasterizer->offset_scale));
2936		r600_pipe_state_add_reg(&state,
2937				R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2938				fui(offset_units));
2939		r600_pipe_state_add_reg(&state,
2940				R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2941				fui(rctx->rasterizer->offset_scale));
2942		r600_pipe_state_add_reg(&state,
2943				R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2944				fui(offset_units));
2945		r600_pipe_state_add_reg(&state,
2946				R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2947				offset_db_fmt_cntl);
2948		r600_context_pipe_state_set(rctx, &state);
2949	}
2950}
2951
2952void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2953{
2954	struct r600_context *rctx = (struct r600_context *)ctx;
2955	struct r600_pipe_state *rstate = &shader->rstate;
2956	struct r600_shader *rshader = &shader->shader;
2957	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2958	int pos_index = -1, face_index = -1;
2959	int ninterp = 0;
2960	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2961	unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2962	unsigned z_export = 0, stencil_export = 0;
2963
2964	rstate->nregs = 0;
2965
2966	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2967	for (i = 0; i < rshader->ninput; i++) {
2968		/* evergreen NUM_INTERP only contains values interpolated into the LDS,
2969		   POSITION goes via GPRs from the SC so isn't counted */
2970		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2971			pos_index = i;
2972		else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2973			face_index = i;
2974		else {
2975			ninterp++;
2976			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2977				have_linear = TRUE;
2978			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2979				have_perspective = TRUE;
2980			if (rshader->input[i].centroid)
2981				have_centroid = TRUE;
2982		}
2983
2984		sid = rshader->input[i].spi_sid;
2985
2986		if (sid) {
2987
2988			tmp = S_028644_SEMANTIC(sid);
2989
2990			if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2991				rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2992				(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2993					rctx->rasterizer && rctx->rasterizer->flatshade)) {
2994				tmp |= S_028644_FLAT_SHADE(1);
2995			}
2996
2997			if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2998					(rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2999				tmp |= S_028644_PT_SPRITE_TEX(1);
3000			}
3001
3002			r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
3003					tmp);
3004
3005			idx++;
3006		}
3007	}
3008
3009	for (i = 0; i < rshader->noutput; i++) {
3010		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
3011			z_export = 1;
3012		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3013			stencil_export = 1;
3014	}
3015	if (rshader->uses_kill)
3016		db_shader_control |= S_02880C_KILL_ENABLE(1);
3017
3018	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
3019	db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
3020
3021	exports_ps = 0;
3022	for (i = 0; i < rshader->noutput; i++) {
3023		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
3024		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
3025			exports_ps |= 1;
3026	}
3027
3028	num_cout = rshader->nr_ps_color_exports;
3029
3030	exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
3031	if (!exports_ps) {
3032		/* always at least export 1 component per pixel */
3033		exports_ps = 2;
3034	}
3035	shader->nr_ps_color_outputs = num_cout;
3036	if (ninterp == 0) {
3037		ninterp = 1;
3038		have_perspective = TRUE;
3039	}
3040
3041	if (!have_perspective && !have_linear)
3042		have_perspective = TRUE;
3043
3044	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
3045		              S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
3046		              S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
3047	spi_input_z = 0;
3048	if (pos_index != -1) {
3049		spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
3050			S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
3051			S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
3052		spi_input_z |= 1;
3053	}
3054
3055	spi_ps_in_control_1 = 0;
3056	if (face_index != -1) {
3057		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
3058			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
3059	}
3060
3061	spi_baryc_cntl = 0;
3062	if (have_perspective)
3063		spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
3064				  S_0286E0_PERSP_CENTROID_ENA(have_centroid);
3065	if (have_linear)
3066		spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
3067				  S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
3068
3069	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
3070				spi_ps_in_control_0);
3071	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
3072				spi_ps_in_control_1);
3073	r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
3074				0);
3075	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
3076	r600_pipe_state_add_reg(rstate,
3077				R_0286E0_SPI_BARYC_CNTL,
3078				spi_baryc_cntl);
3079
3080	r600_pipe_state_add_reg_bo(rstate,
3081				R_028840_SQ_PGM_START_PS,
3082				r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3083				shader->bo, RADEON_USAGE_READ);
3084	r600_pipe_state_add_reg(rstate,
3085				R_028844_SQ_PGM_RESOURCES_PS,
3086				S_028844_NUM_GPRS(rshader->bc.ngpr) |
3087				S_028844_PRIME_CACHE_ON_DRAW(1) |
3088				S_028844_STACK_SIZE(rshader->bc.nstack));
3089	r600_pipe_state_add_reg(rstate,
3090				R_02884C_SQ_PGM_EXPORTS_PS,
3091				exports_ps);
3092
3093	shader->db_shader_control = db_shader_control;
3094	shader->ps_depth_export = z_export | stencil_export;
3095
3096	shader->sprite_coord_enable = rctx->sprite_coord_enable;
3097	if (rctx->rasterizer)
3098		shader->flatshade = rctx->rasterizer->flatshade;
3099}
3100
3101void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
3102{
3103	struct r600_context *rctx = (struct r600_context *)ctx;
3104	struct r600_pipe_state *rstate = &shader->rstate;
3105	struct r600_shader *rshader = &shader->shader;
3106	unsigned spi_vs_out_id[10] = {};
3107	unsigned i, tmp, nparams = 0;
3108
3109	/* clear previous register */
3110	rstate->nregs = 0;
3111
3112	for (i = 0; i < rshader->noutput; i++) {
3113		if (rshader->output[i].spi_sid) {
3114			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
3115			spi_vs_out_id[nparams / 4] |= tmp;
3116			nparams++;
3117		}
3118	}
3119
3120	for (i = 0; i < 10; i++) {
3121		r600_pipe_state_add_reg(rstate,
3122					R_02861C_SPI_VS_OUT_ID_0 + i * 4,
3123					spi_vs_out_id[i]);
3124	}
3125
3126	/* Certain attributes (position, psize, etc.) don't count as params.
3127	 * VS is required to export at least one param and r600_shader_from_tgsi()
3128	 * takes care of adding a dummy export.
3129	 */
3130	if (nparams < 1)
3131		nparams = 1;
3132
3133	r600_pipe_state_add_reg(rstate,
3134			R_0286C4_SPI_VS_OUT_CONFIG,
3135			S_0286C4_VS_EXPORT_COUNT(nparams - 1));
3136	r600_pipe_state_add_reg(rstate,
3137			R_028860_SQ_PGM_RESOURCES_VS,
3138			S_028860_NUM_GPRS(rshader->bc.ngpr) |
3139			S_028860_STACK_SIZE(rshader->bc.nstack));
3140	r600_pipe_state_add_reg_bo(rstate,
3141			R_02885C_SQ_PGM_START_VS,
3142			r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
3143			shader->bo, RADEON_USAGE_READ);
3144
3145	shader->pa_cl_vs_out_cntl =
3146		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
3147		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
3148		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
3149		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
3150}
3151
3152void evergreen_fetch_shader(struct pipe_context *ctx,
3153			    struct r600_vertex_element *ve)
3154{
3155	struct r600_context *rctx = (struct r600_context *)ctx;
3156	struct r600_pipe_state *rstate = &ve->rstate;
3157	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
3158	rstate->nregs = 0;
3159	r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
3160				r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
3161				ve->fetch_shader, RADEON_USAGE_READ);
3162}
3163
3164void *evergreen_create_resolve_blend(struct r600_context *rctx)
3165{
3166	struct pipe_blend_state blend;
3167	struct r600_pipe_state *rstate;
3168
3169	memset(&blend, 0, sizeof(blend));
3170	blend.independent_blend_enable = true;
3171	blend.rt[0].colormask = 0xf;
3172	rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3173	return rstate;
3174}
3175
3176void *evergreen_create_decompress_blend(struct r600_context *rctx)
3177{
3178	struct pipe_blend_state blend;
3179	struct r600_pipe_state *rstate;
3180
3181	memset(&blend, 0, sizeof(blend));
3182	blend.independent_blend_enable = true;
3183	blend.rt[0].colormask = 0xf;
3184	rstate = evergreen_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_DECOMPRESS);
3185	return rstate;
3186}
3187
3188void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
3189{
3190	struct pipe_depth_stencil_alpha_state dsa = {{0}};
3191
3192	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
3193}
3194
3195void evergreen_update_dual_export_state(struct r600_context * rctx)
3196{
3197	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
3198			!rctx->ps_shader->current->ps_depth_export;
3199
3200	unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
3201			V_02880C_EXPORT_DB_FULL;
3202
3203	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
3204			S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
3205			S_02880C_DB_SOURCE_FORMAT(db_source_format) |
3206			S_02880C_ALPHA_TO_MASK_DISABLE(rctx->cb0_is_integer);
3207
3208	if (db_shader_control != rctx->db_shader_control) {
3209		struct r600_pipe_state rstate;
3210
3211		rctx->db_shader_control = db_shader_control;
3212
3213		rstate.nregs = 0;
3214		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
3215		r600_context_pipe_state_set(rctx, &rstate);
3216	}
3217}
3218