evergreen_state.c revision cdc681c3ad746fe8adab4ea71358bcc54e024ff9 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "evergreend.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31#include "evergreen_compute.h"
32
33static uint32_t eg_num_banks(uint32_t nbanks)
34{
35	switch (nbanks) {
36	case 2:
37		return 0;
38	case 4:
39		return 1;
40	case 8:
41	default:
42		return 2;
43	case 16:
44		return 3;
45	}
46}
47
48
49static unsigned eg_tile_split(unsigned tile_split)
50{
51	switch (tile_split) {
52	case 64:	tile_split = 0;	break;
53	case 128:	tile_split = 1;	break;
54	case 256:	tile_split = 2;	break;
55	case 512:	tile_split = 3;	break;
56	default:
57	case 1024:	tile_split = 4;	break;
58	case 2048:	tile_split = 5;	break;
59	case 4096:	tile_split = 6;	break;
60	}
61	return tile_split;
62}
63
64static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65{
66	switch (macro_tile_aspect) {
67	default:
68	case 1:	macro_tile_aspect = 0;	break;
69	case 2:	macro_tile_aspect = 1;	break;
70	case 4:	macro_tile_aspect = 2;	break;
71	case 8:	macro_tile_aspect = 3;	break;
72	}
73	return macro_tile_aspect;
74}
75
76static unsigned eg_bank_wh(unsigned bankwh)
77{
78	switch (bankwh) {
79	default:
80	case 1:	bankwh = 0;	break;
81	case 2:	bankwh = 1;	break;
82	case 4:	bankwh = 2;	break;
83	case 8:	bankwh = 3;	break;
84	}
85	return bankwh;
86}
87
88static uint32_t r600_translate_blend_function(int blend_func)
89{
90	switch (blend_func) {
91	case PIPE_BLEND_ADD:
92		return V_028780_COMB_DST_PLUS_SRC;
93	case PIPE_BLEND_SUBTRACT:
94		return V_028780_COMB_SRC_MINUS_DST;
95	case PIPE_BLEND_REVERSE_SUBTRACT:
96		return V_028780_COMB_DST_MINUS_SRC;
97	case PIPE_BLEND_MIN:
98		return V_028780_COMB_MIN_DST_SRC;
99	case PIPE_BLEND_MAX:
100		return V_028780_COMB_MAX_DST_SRC;
101	default:
102		R600_ERR("Unknown blend function %d\n", blend_func);
103		assert(0);
104		break;
105	}
106	return 0;
107}
108
109static uint32_t r600_translate_blend_factor(int blend_fact)
110{
111	switch (blend_fact) {
112	case PIPE_BLENDFACTOR_ONE:
113		return V_028780_BLEND_ONE;
114	case PIPE_BLENDFACTOR_SRC_COLOR:
115		return V_028780_BLEND_SRC_COLOR;
116	case PIPE_BLENDFACTOR_SRC_ALPHA:
117		return V_028780_BLEND_SRC_ALPHA;
118	case PIPE_BLENDFACTOR_DST_ALPHA:
119		return V_028780_BLEND_DST_ALPHA;
120	case PIPE_BLENDFACTOR_DST_COLOR:
121		return V_028780_BLEND_DST_COLOR;
122	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123		return V_028780_BLEND_SRC_ALPHA_SATURATE;
124	case PIPE_BLENDFACTOR_CONST_COLOR:
125		return V_028780_BLEND_CONST_COLOR;
126	case PIPE_BLENDFACTOR_CONST_ALPHA:
127		return V_028780_BLEND_CONST_ALPHA;
128	case PIPE_BLENDFACTOR_ZERO:
129		return V_028780_BLEND_ZERO;
130	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131		return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133		return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135		return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136	case PIPE_BLENDFACTOR_INV_DST_COLOR:
137		return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139		return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141		return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142	case PIPE_BLENDFACTOR_SRC1_COLOR:
143		return V_028780_BLEND_SRC1_COLOR;
144	case PIPE_BLENDFACTOR_SRC1_ALPHA:
145		return V_028780_BLEND_SRC1_ALPHA;
146	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147		return V_028780_BLEND_INV_SRC1_COLOR;
148	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149		return V_028780_BLEND_INV_SRC1_ALPHA;
150	default:
151		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152		assert(0);
153		break;
154	}
155	return 0;
156}
157
158static unsigned r600_tex_dim(unsigned dim)
159{
160	switch (dim) {
161	default:
162	case PIPE_TEXTURE_1D:
163		return V_030000_SQ_TEX_DIM_1D;
164	case PIPE_TEXTURE_1D_ARRAY:
165		return V_030000_SQ_TEX_DIM_1D_ARRAY;
166	case PIPE_TEXTURE_2D:
167	case PIPE_TEXTURE_RECT:
168		return V_030000_SQ_TEX_DIM_2D;
169	case PIPE_TEXTURE_2D_ARRAY:
170		return V_030000_SQ_TEX_DIM_2D_ARRAY;
171	case PIPE_TEXTURE_3D:
172		return V_030000_SQ_TEX_DIM_3D;
173	case PIPE_TEXTURE_CUBE:
174		return V_030000_SQ_TEX_DIM_CUBEMAP;
175	}
176}
177
178static uint32_t r600_translate_dbformat(enum pipe_format format)
179{
180	switch (format) {
181	case PIPE_FORMAT_Z16_UNORM:
182		return V_028040_Z_16;
183	case PIPE_FORMAT_Z24X8_UNORM:
184	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
185		return V_028040_Z_24;
186	case PIPE_FORMAT_Z32_FLOAT:
187	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
188		return V_028040_Z_32_FLOAT;
189	default:
190		return ~0U;
191	}
192}
193
194static uint32_t r600_translate_colorswap(enum pipe_format format)
195{
196	switch (format) {
197	/* 8-bit buffers. */
198	case PIPE_FORMAT_L4A4_UNORM:
199	case PIPE_FORMAT_A4R4_UNORM:
200		return V_028C70_SWAP_ALT;
201
202	case PIPE_FORMAT_A8_UNORM:
203	case PIPE_FORMAT_A8_SNORM:
204	case PIPE_FORMAT_A8_UINT:
205	case PIPE_FORMAT_A8_SINT:
206	case PIPE_FORMAT_A16_UNORM:
207	case PIPE_FORMAT_A16_SNORM:
208	case PIPE_FORMAT_A16_UINT:
209	case PIPE_FORMAT_A16_SINT:
210	case PIPE_FORMAT_A16_FLOAT:
211	case PIPE_FORMAT_A32_UINT:
212	case PIPE_FORMAT_A32_SINT:
213	case PIPE_FORMAT_A32_FLOAT:
214	case PIPE_FORMAT_R4A4_UNORM:
215		return V_028C70_SWAP_ALT_REV;
216	case PIPE_FORMAT_I8_UNORM:
217	case PIPE_FORMAT_I8_SNORM:
218	case PIPE_FORMAT_I8_UINT:
219	case PIPE_FORMAT_I8_SINT:
220	case PIPE_FORMAT_I16_UNORM:
221	case PIPE_FORMAT_I16_SNORM:
222	case PIPE_FORMAT_I16_UINT:
223	case PIPE_FORMAT_I16_SINT:
224	case PIPE_FORMAT_I16_FLOAT:
225	case PIPE_FORMAT_I32_UINT:
226	case PIPE_FORMAT_I32_SINT:
227	case PIPE_FORMAT_I32_FLOAT:
228	case PIPE_FORMAT_L8_UNORM:
229	case PIPE_FORMAT_L8_SNORM:
230	case PIPE_FORMAT_L8_UINT:
231	case PIPE_FORMAT_L8_SINT:
232	case PIPE_FORMAT_L8_SRGB:
233	case PIPE_FORMAT_L16_UNORM:
234	case PIPE_FORMAT_L16_SNORM:
235	case PIPE_FORMAT_L16_UINT:
236	case PIPE_FORMAT_L16_SINT:
237	case PIPE_FORMAT_L16_FLOAT:
238	case PIPE_FORMAT_L32_UINT:
239	case PIPE_FORMAT_L32_SINT:
240	case PIPE_FORMAT_L32_FLOAT:
241	case PIPE_FORMAT_R8_UNORM:
242	case PIPE_FORMAT_R8_SNORM:
243	case PIPE_FORMAT_R8_UINT:
244	case PIPE_FORMAT_R8_SINT:
245		return V_028C70_SWAP_STD;
246
247	/* 16-bit buffers. */
248	case PIPE_FORMAT_B5G6R5_UNORM:
249		return V_028C70_SWAP_STD_REV;
250
251	case PIPE_FORMAT_B5G5R5A1_UNORM:
252	case PIPE_FORMAT_B5G5R5X1_UNORM:
253		return V_028C70_SWAP_ALT;
254
255	case PIPE_FORMAT_B4G4R4A4_UNORM:
256	case PIPE_FORMAT_B4G4R4X4_UNORM:
257		return V_028C70_SWAP_ALT;
258
259	case PIPE_FORMAT_Z16_UNORM:
260		return V_028C70_SWAP_STD;
261
262	case PIPE_FORMAT_L8A8_UNORM:
263	case PIPE_FORMAT_L8A8_SNORM:
264	case PIPE_FORMAT_L8A8_UINT:
265	case PIPE_FORMAT_L8A8_SINT:
266	case PIPE_FORMAT_L8A8_SRGB:
267	case PIPE_FORMAT_L16A16_UNORM:
268	case PIPE_FORMAT_L16A16_SNORM:
269	case PIPE_FORMAT_L16A16_UINT:
270	case PIPE_FORMAT_L16A16_SINT:
271	case PIPE_FORMAT_L16A16_FLOAT:
272	case PIPE_FORMAT_L32A32_UINT:
273	case PIPE_FORMAT_L32A32_SINT:
274	case PIPE_FORMAT_L32A32_FLOAT:
275		return V_028C70_SWAP_ALT;
276	case PIPE_FORMAT_R8G8_UNORM:
277	case PIPE_FORMAT_R8G8_SNORM:
278	case PIPE_FORMAT_R8G8_UINT:
279	case PIPE_FORMAT_R8G8_SINT:
280		return V_028C70_SWAP_STD;
281
282	case PIPE_FORMAT_R16_UNORM:
283	case PIPE_FORMAT_R16_SNORM:
284	case PIPE_FORMAT_R16_UINT:
285	case PIPE_FORMAT_R16_SINT:
286	case PIPE_FORMAT_R16_FLOAT:
287		return V_028C70_SWAP_STD;
288
289	/* 32-bit buffers. */
290	case PIPE_FORMAT_A8B8G8R8_SRGB:
291		return V_028C70_SWAP_STD_REV;
292	case PIPE_FORMAT_B8G8R8A8_SRGB:
293		return V_028C70_SWAP_ALT;
294
295	case PIPE_FORMAT_B8G8R8A8_UNORM:
296	case PIPE_FORMAT_B8G8R8X8_UNORM:
297		return V_028C70_SWAP_ALT;
298
299	case PIPE_FORMAT_A8R8G8B8_UNORM:
300	case PIPE_FORMAT_X8R8G8B8_UNORM:
301		return V_028C70_SWAP_ALT_REV;
302	case PIPE_FORMAT_R8G8B8A8_SNORM:
303	case PIPE_FORMAT_R8G8B8A8_UNORM:
304	case PIPE_FORMAT_R8G8B8A8_SINT:
305	case PIPE_FORMAT_R8G8B8A8_UINT:
306	case PIPE_FORMAT_R8G8B8X8_UNORM:
307		return V_028C70_SWAP_STD;
308
309	case PIPE_FORMAT_A8B8G8R8_UNORM:
310	case PIPE_FORMAT_X8B8G8R8_UNORM:
311	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
312		return V_028C70_SWAP_STD_REV;
313
314	case PIPE_FORMAT_Z24X8_UNORM:
315	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
316		return V_028C70_SWAP_STD;
317
318	case PIPE_FORMAT_X8Z24_UNORM:
319	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
320		return V_028C70_SWAP_STD;
321
322	case PIPE_FORMAT_R10G10B10A2_UNORM:
323	case PIPE_FORMAT_R10G10B10X2_SNORM:
324	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
325		return V_028C70_SWAP_STD;
326
327	case PIPE_FORMAT_B10G10R10A2_UNORM:
328	case PIPE_FORMAT_B10G10R10A2_UINT:
329		return V_028C70_SWAP_ALT;
330
331	case PIPE_FORMAT_R11G11B10_FLOAT:
332	case PIPE_FORMAT_R32_FLOAT:
333	case PIPE_FORMAT_R32_UINT:
334	case PIPE_FORMAT_R32_SINT:
335	case PIPE_FORMAT_Z32_FLOAT:
336	case PIPE_FORMAT_R16G16_FLOAT:
337	case PIPE_FORMAT_R16G16_UNORM:
338	case PIPE_FORMAT_R16G16_SNORM:
339	case PIPE_FORMAT_R16G16_UINT:
340	case PIPE_FORMAT_R16G16_SINT:
341	case PIPE_FORMAT_R16G16B16_FLOAT:
342	case PIPE_FORMAT_R32G32B32_FLOAT:
343		return V_028C70_SWAP_STD;
344
345	/* 64-bit buffers. */
346	case PIPE_FORMAT_R32G32_FLOAT:
347	case PIPE_FORMAT_R32G32_UINT:
348	case PIPE_FORMAT_R32G32_SINT:
349	case PIPE_FORMAT_R16G16B16A16_UNORM:
350	case PIPE_FORMAT_R16G16B16A16_SNORM:
351	case PIPE_FORMAT_R16G16B16A16_UINT:
352	case PIPE_FORMAT_R16G16B16A16_SINT:
353	case PIPE_FORMAT_R16G16B16A16_FLOAT:
354	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356	/* 128-bit buffers. */
357	case PIPE_FORMAT_R32G32B32A32_FLOAT:
358	case PIPE_FORMAT_R32G32B32A32_SNORM:
359	case PIPE_FORMAT_R32G32B32A32_UNORM:
360	case PIPE_FORMAT_R32G32B32A32_SINT:
361	case PIPE_FORMAT_R32G32B32A32_UINT:
362		return V_028C70_SWAP_STD;
363	default:
364		R600_ERR("unsupported colorswap format %d\n", format);
365		return ~0U;
366	}
367	return ~0U;
368}
369
370static uint32_t r600_translate_colorformat(enum pipe_format format)
371{
372	switch (format) {
373	/* 8-bit buffers. */
374	case PIPE_FORMAT_A8_UNORM:
375	case PIPE_FORMAT_A8_SNORM:
376	case PIPE_FORMAT_A8_UINT:
377	case PIPE_FORMAT_A8_SINT:
378	case PIPE_FORMAT_I8_UNORM:
379	case PIPE_FORMAT_I8_SNORM:
380	case PIPE_FORMAT_I8_UINT:
381	case PIPE_FORMAT_I8_SINT:
382	case PIPE_FORMAT_L8_UNORM:
383	case PIPE_FORMAT_L8_SNORM:
384	case PIPE_FORMAT_L8_UINT:
385	case PIPE_FORMAT_L8_SINT:
386	case PIPE_FORMAT_L8_SRGB:
387	case PIPE_FORMAT_R8_UNORM:
388	case PIPE_FORMAT_R8_SNORM:
389	case PIPE_FORMAT_R8_UINT:
390	case PIPE_FORMAT_R8_SINT:
391		return V_028C70_COLOR_8;
392
393	/* 16-bit buffers. */
394	case PIPE_FORMAT_B5G6R5_UNORM:
395		return V_028C70_COLOR_5_6_5;
396
397	case PIPE_FORMAT_B5G5R5A1_UNORM:
398	case PIPE_FORMAT_B5G5R5X1_UNORM:
399		return V_028C70_COLOR_1_5_5_5;
400
401	case PIPE_FORMAT_B4G4R4A4_UNORM:
402	case PIPE_FORMAT_B4G4R4X4_UNORM:
403		return V_028C70_COLOR_4_4_4_4;
404
405	case PIPE_FORMAT_Z16_UNORM:
406		return V_028C70_COLOR_16;
407
408	case PIPE_FORMAT_L8A8_UNORM:
409	case PIPE_FORMAT_L8A8_SNORM:
410	case PIPE_FORMAT_L8A8_UINT:
411	case PIPE_FORMAT_L8A8_SINT:
412	case PIPE_FORMAT_L8A8_SRGB:
413	case PIPE_FORMAT_R8G8_UNORM:
414	case PIPE_FORMAT_R8G8_SNORM:
415	case PIPE_FORMAT_R8G8_UINT:
416	case PIPE_FORMAT_R8G8_SINT:
417		return V_028C70_COLOR_8_8;
418
419	case PIPE_FORMAT_R16_UNORM:
420	case PIPE_FORMAT_R16_SNORM:
421	case PIPE_FORMAT_R16_UINT:
422	case PIPE_FORMAT_R16_SINT:
423	case PIPE_FORMAT_A16_UNORM:
424	case PIPE_FORMAT_A16_SNORM:
425	case PIPE_FORMAT_A16_UINT:
426	case PIPE_FORMAT_A16_SINT:
427	case PIPE_FORMAT_L16_UNORM:
428	case PIPE_FORMAT_L16_SNORM:
429	case PIPE_FORMAT_L16_UINT:
430	case PIPE_FORMAT_L16_SINT:
431	case PIPE_FORMAT_I16_UNORM:
432	case PIPE_FORMAT_I16_SNORM:
433	case PIPE_FORMAT_I16_UINT:
434	case PIPE_FORMAT_I16_SINT:
435		return V_028C70_COLOR_16;
436
437	case PIPE_FORMAT_R16_FLOAT:
438	case PIPE_FORMAT_A16_FLOAT:
439	case PIPE_FORMAT_L16_FLOAT:
440	case PIPE_FORMAT_I16_FLOAT:
441		return V_028C70_COLOR_16_FLOAT;
442
443	/* 32-bit buffers. */
444	case PIPE_FORMAT_A8B8G8R8_SRGB:
445	case PIPE_FORMAT_A8B8G8R8_UNORM:
446	case PIPE_FORMAT_A8R8G8B8_UNORM:
447	case PIPE_FORMAT_B8G8R8A8_SRGB:
448	case PIPE_FORMAT_B8G8R8A8_UNORM:
449	case PIPE_FORMAT_B8G8R8X8_UNORM:
450	case PIPE_FORMAT_R8G8B8A8_SNORM:
451	case PIPE_FORMAT_R8G8B8A8_UNORM:
452	case PIPE_FORMAT_R8G8B8X8_UNORM:
453	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454	case PIPE_FORMAT_X8B8G8R8_UNORM:
455	case PIPE_FORMAT_X8R8G8B8_UNORM:
456	case PIPE_FORMAT_R8G8B8_UNORM:
457	case PIPE_FORMAT_R8G8B8A8_SINT:
458	case PIPE_FORMAT_R8G8B8A8_UINT:
459		return V_028C70_COLOR_8_8_8_8;
460
461	case PIPE_FORMAT_R10G10B10A2_UNORM:
462	case PIPE_FORMAT_R10G10B10X2_SNORM:
463	case PIPE_FORMAT_B10G10R10A2_UNORM:
464	case PIPE_FORMAT_B10G10R10A2_UINT:
465	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466		return V_028C70_COLOR_2_10_10_10;
467
468	case PIPE_FORMAT_Z24X8_UNORM:
469	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470		return V_028C70_COLOR_8_24;
471
472	case PIPE_FORMAT_X8Z24_UNORM:
473	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474		return V_028C70_COLOR_24_8;
475
476	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477		return V_028C70_COLOR_X24_8_32_FLOAT;
478
479	case PIPE_FORMAT_R32_UINT:
480	case PIPE_FORMAT_R32_SINT:
481	case PIPE_FORMAT_A32_UINT:
482	case PIPE_FORMAT_A32_SINT:
483	case PIPE_FORMAT_L32_UINT:
484	case PIPE_FORMAT_L32_SINT:
485	case PIPE_FORMAT_I32_UINT:
486	case PIPE_FORMAT_I32_SINT:
487		return V_028C70_COLOR_32;
488
489	case PIPE_FORMAT_R32_FLOAT:
490	case PIPE_FORMAT_A32_FLOAT:
491	case PIPE_FORMAT_L32_FLOAT:
492	case PIPE_FORMAT_I32_FLOAT:
493	case PIPE_FORMAT_Z32_FLOAT:
494		return V_028C70_COLOR_32_FLOAT;
495
496	case PIPE_FORMAT_R16G16_FLOAT:
497	case PIPE_FORMAT_L16A16_FLOAT:
498		return V_028C70_COLOR_16_16_FLOAT;
499
500	case PIPE_FORMAT_R16G16_UNORM:
501	case PIPE_FORMAT_R16G16_SNORM:
502	case PIPE_FORMAT_R16G16_UINT:
503	case PIPE_FORMAT_R16G16_SINT:
504	case PIPE_FORMAT_L16A16_UNORM:
505	case PIPE_FORMAT_L16A16_SNORM:
506	case PIPE_FORMAT_L16A16_UINT:
507	case PIPE_FORMAT_L16A16_SINT:
508		return V_028C70_COLOR_16_16;
509
510	case PIPE_FORMAT_R11G11B10_FLOAT:
511		return V_028C70_COLOR_10_11_11_FLOAT;
512
513	/* 64-bit buffers. */
514	case PIPE_FORMAT_R16G16B16A16_UINT:
515	case PIPE_FORMAT_R16G16B16A16_SINT:
516	case PIPE_FORMAT_R16G16B16A16_UNORM:
517	case PIPE_FORMAT_R16G16B16A16_SNORM:
518		return V_028C70_COLOR_16_16_16_16;
519
520	case PIPE_FORMAT_R16G16B16_FLOAT:
521	case PIPE_FORMAT_R16G16B16A16_FLOAT:
522		return V_028C70_COLOR_16_16_16_16_FLOAT;
523
524	case PIPE_FORMAT_R32G32_FLOAT:
525	case PIPE_FORMAT_L32A32_FLOAT:
526		return V_028C70_COLOR_32_32_FLOAT;
527
528	case PIPE_FORMAT_R32G32_SINT:
529	case PIPE_FORMAT_R32G32_UINT:
530	case PIPE_FORMAT_L32A32_UINT:
531	case PIPE_FORMAT_L32A32_SINT:
532		return V_028C70_COLOR_32_32;
533
534	/* 96-bit buffers. */
535	case PIPE_FORMAT_R32G32B32_FLOAT:
536		return V_028C70_COLOR_32_32_32_FLOAT;
537
538	/* 128-bit buffers. */
539	case PIPE_FORMAT_R32G32B32A32_SNORM:
540	case PIPE_FORMAT_R32G32B32A32_UNORM:
541	case PIPE_FORMAT_R32G32B32A32_SINT:
542	case PIPE_FORMAT_R32G32B32A32_UINT:
543		return V_028C70_COLOR_32_32_32_32;
544	case PIPE_FORMAT_R32G32B32A32_FLOAT:
545		return V_028C70_COLOR_32_32_32_32_FLOAT;
546
547	/* YUV buffers. */
548	case PIPE_FORMAT_UYVY:
549	case PIPE_FORMAT_YUYV:
550	default:
551		return ~0U; /* Unsupported. */
552	}
553}
554
555static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
556{
557	if (R600_BIG_ENDIAN) {
558		switch(colorformat) {
559
560		/* 8-bit buffers. */
561		case V_028C70_COLOR_8:
562			return ENDIAN_NONE;
563
564		/* 16-bit buffers. */
565		case V_028C70_COLOR_5_6_5:
566		case V_028C70_COLOR_1_5_5_5:
567		case V_028C70_COLOR_4_4_4_4:
568		case V_028C70_COLOR_16:
569		case V_028C70_COLOR_8_8:
570			return ENDIAN_8IN16;
571
572		/* 32-bit buffers. */
573		case V_028C70_COLOR_8_8_8_8:
574		case V_028C70_COLOR_2_10_10_10:
575		case V_028C70_COLOR_8_24:
576		case V_028C70_COLOR_24_8:
577		case V_028C70_COLOR_32_FLOAT:
578		case V_028C70_COLOR_16_16_FLOAT:
579		case V_028C70_COLOR_16_16:
580			return ENDIAN_8IN32;
581
582		/* 64-bit buffers. */
583		case V_028C70_COLOR_16_16_16_16:
584		case V_028C70_COLOR_16_16_16_16_FLOAT:
585			return ENDIAN_8IN16;
586
587		case V_028C70_COLOR_32_32_FLOAT:
588		case V_028C70_COLOR_32_32:
589		case V_028C70_COLOR_X24_8_32_FLOAT:
590			return ENDIAN_8IN32;
591
592		/* 96-bit buffers. */
593		case V_028C70_COLOR_32_32_32_FLOAT:
594		/* 128-bit buffers. */
595		case V_028C70_COLOR_32_32_32_32_FLOAT:
596		case V_028C70_COLOR_32_32_32_32:
597			return ENDIAN_8IN32;
598		default:
599			return ENDIAN_NONE; /* Unsupported. */
600		}
601	} else {
602		return ENDIAN_NONE;
603	}
604}
605
606static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
607{
608	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
609}
610
611static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
612{
613	return r600_translate_colorformat(format) != ~0U &&
614		r600_translate_colorswap(format) != ~0U;
615}
616
617static bool r600_is_zs_format_supported(enum pipe_format format)
618{
619	return r600_translate_dbformat(format) != ~0U;
620}
621
622boolean evergreen_is_format_supported(struct pipe_screen *screen,
623				      enum pipe_format format,
624				      enum pipe_texture_target target,
625				      unsigned sample_count,
626				      unsigned usage)
627{
628	unsigned retval = 0;
629
630	if (target >= PIPE_MAX_TEXTURE_TYPES) {
631		R600_ERR("r600: unsupported texture type %d\n", target);
632		return FALSE;
633	}
634
635	if (!util_format_is_supported(format, usage))
636		return FALSE;
637
638	/* Multisample */
639	if (sample_count > 1)
640		return FALSE;
641
642	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
643	    r600_is_sampler_format_supported(screen, format)) {
644		retval |= PIPE_BIND_SAMPLER_VIEW;
645	}
646
647	if ((usage & (PIPE_BIND_RENDER_TARGET |
648		      PIPE_BIND_DISPLAY_TARGET |
649		      PIPE_BIND_SCANOUT |
650		      PIPE_BIND_SHARED)) &&
651	    r600_is_colorbuffer_format_supported(format)) {
652		retval |= usage &
653			  (PIPE_BIND_RENDER_TARGET |
654			   PIPE_BIND_DISPLAY_TARGET |
655			   PIPE_BIND_SCANOUT |
656			   PIPE_BIND_SHARED);
657	}
658
659	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
660	    r600_is_zs_format_supported(format)) {
661		retval |= PIPE_BIND_DEPTH_STENCIL;
662	}
663
664	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
665	    r600_is_vertex_format_supported(format)) {
666		retval |= PIPE_BIND_VERTEX_BUFFER;
667	}
668
669	if (usage & PIPE_BIND_TRANSFER_READ)
670		retval |= PIPE_BIND_TRANSFER_READ;
671	if (usage & PIPE_BIND_TRANSFER_WRITE)
672		retval |= PIPE_BIND_TRANSFER_WRITE;
673
674	return retval == usage;
675}
676
677static void *evergreen_create_blend_state(struct pipe_context *ctx,
678					const struct pipe_blend_state *state)
679{
680	struct r600_context *rctx = (struct r600_context *)ctx;
681	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
682	struct r600_pipe_state *rstate;
683	uint32_t color_control = 0, target_mask;
684	/* XXX there is more then 8 framebuffer */
685	unsigned blend_cntl[8];
686
687	if (blend == NULL) {
688		return NULL;
689	}
690
691	rstate = &blend->rstate;
692
693	rstate->id = R600_PIPE_STATE_BLEND;
694
695	target_mask = 0;
696	if (state->logicop_enable) {
697		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
698	} else {
699		color_control |= (0xcc << 16);
700	}
701	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
702	if (state->independent_blend_enable) {
703		for (int i = 0; i < 8; i++) {
704			target_mask |= (state->rt[i].colormask << (4 * i));
705		}
706	} else {
707		for (int i = 0; i < 8; i++) {
708			target_mask |= (state->rt[0].colormask << (4 * i));
709		}
710	}
711	blend->cb_target_mask = target_mask;
712
713	if (target_mask)
714		color_control |= S_028808_MODE(V_028808_CB_NORMAL);
715	else
716		color_control |= S_028808_MODE(V_028808_CB_DISABLE);
717
718	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
719				color_control);
720	/* only have dual source on MRT0 */
721	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
722	for (int i = 0; i < 8; i++) {
723		/* state->rt entries > 0 only written if independent blending */
724		const int j = state->independent_blend_enable ? i : 0;
725
726		unsigned eqRGB = state->rt[j].rgb_func;
727		unsigned srcRGB = state->rt[j].rgb_src_factor;
728		unsigned dstRGB = state->rt[j].rgb_dst_factor;
729		unsigned eqA = state->rt[j].alpha_func;
730		unsigned srcA = state->rt[j].alpha_src_factor;
731		unsigned dstA = state->rt[j].alpha_dst_factor;
732
733		blend_cntl[i] = 0;
734		if (!state->rt[j].blend_enable)
735			continue;
736
737		blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
738		blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
739		blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
740		blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
741
742		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
743			blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
744			blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
745			blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
746			blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
747		}
748	}
749	for (int i = 0; i < 8; i++) {
750		r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
751	}
752
753	return rstate;
754}
755
756static void *evergreen_create_dsa_state(struct pipe_context *ctx,
757				   const struct pipe_depth_stencil_alpha_state *state)
758{
759	struct r600_context *rctx = (struct r600_context *)ctx;
760	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
761	unsigned db_depth_control, alpha_test_control, alpha_ref;
762	struct r600_pipe_state *rstate;
763
764	if (dsa == NULL) {
765		return NULL;
766	}
767
768	dsa->valuemask[0] = state->stencil[0].valuemask;
769	dsa->valuemask[1] = state->stencil[1].valuemask;
770	dsa->writemask[0] = state->stencil[0].writemask;
771	dsa->writemask[1] = state->stencil[1].writemask;
772
773	rstate = &dsa->rstate;
774
775	rstate->id = R600_PIPE_STATE_DSA;
776	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
777		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
778		S_028800_ZFUNC(state->depth.func);
779
780	/* stencil */
781	if (state->stencil[0].enabled) {
782		db_depth_control |= S_028800_STENCIL_ENABLE(1);
783		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
784		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
785		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
786		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
787
788		if (state->stencil[1].enabled) {
789			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
790			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
791			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
792			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
793			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
794		}
795	}
796
797	/* alpha */
798	alpha_test_control = 0;
799	alpha_ref = 0;
800	if (state->alpha.enabled) {
801		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
802		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
803		alpha_ref = fui(state->alpha.ref_value);
804	}
805	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
806	dsa->alpha_ref = alpha_ref;
807
808	/* misc */
809	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
810	return rstate;
811}
812
813static void *evergreen_create_rs_state(struct pipe_context *ctx,
814					const struct pipe_rasterizer_state *state)
815{
816	struct r600_context *rctx = (struct r600_context *)ctx;
817	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
818	struct r600_pipe_state *rstate;
819	unsigned tmp;
820	unsigned prov_vtx = 1, polygon_dual_mode;
821	float psize_min, psize_max;
822
823	if (rs == NULL) {
824		return NULL;
825	}
826
827	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
828				state->fill_back != PIPE_POLYGON_MODE_FILL);
829
830	if (state->flatshade_first)
831		prov_vtx = 0;
832
833	rstate = &rs->rstate;
834	rs->flatshade = state->flatshade;
835	rs->sprite_coord_enable = state->sprite_coord_enable;
836	rs->two_side = state->light_twoside;
837	rs->clip_plane_enable = state->clip_plane_enable;
838	rs->pa_sc_line_stipple = state->line_stipple_enable ?
839				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
840				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
841	rs->pa_cl_clip_cntl =
842		S_028810_PS_UCP_MODE(3) |
843		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
844		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
845		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
846
847	/* offset */
848	rs->offset_units = state->offset_units;
849	rs->offset_scale = state->offset_scale * 12.0f;
850
851	rstate->id = R600_PIPE_STATE_RASTERIZER;
852	tmp = S_0286D4_FLAT_SHADE_ENA(1);
853	if (state->sprite_coord_enable) {
854		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
855			S_0286D4_PNT_SPRITE_OVRD_X(2) |
856			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
857			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
858			S_0286D4_PNT_SPRITE_OVRD_W(1);
859		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
860			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
861		}
862	}
863	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
864
865	/* point size 12.4 fixed point */
866	tmp = (unsigned)(state->point_size * 8.0);
867	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
868
869	if (state->point_size_per_vertex) {
870		psize_min = util_get_min_point_size(state);
871		psize_max = 8192;
872	} else {
873		/* Force the point size to be as if the vertex output was disabled. */
874		psize_min = state->point_size;
875		psize_max = state->point_size;
876	}
877	/* Divide by two, because 0.5 = 1 pixel. */
878	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
879				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
880				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
881
882	tmp = (unsigned)state->line_width * 8;
883	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
884	r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
885				S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
886				S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
887
888	if (rctx->chip_class == CAYMAN) {
889		r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
890					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
891	} else {
892		r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
893					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
894	}
895	r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
896	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
897				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
898				S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
899				S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
900				S_028814_FACE(!state->front_ccw) |
901				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
902				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
903				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
904				S_028814_POLY_MODE(polygon_dual_mode) |
905				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
906				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
907	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
908	return rstate;
909}
910
911static void *evergreen_create_sampler_state(struct pipe_context *ctx,
912					const struct pipe_sampler_state *state)
913{
914	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
915	union util_color uc;
916	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
917
918	if (rstate == NULL) {
919		return NULL;
920	}
921
922	rstate->id = R600_PIPE_STATE_SAMPLER;
923	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
924	r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
925			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
926			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
927			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
928			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
929			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
930			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
931			S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
932			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
933			S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
934	r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
935			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
936			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
937			NULL, 0);
938	r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
939					S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
940					(state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
941					S_03C008_TYPE(1),
942					NULL, 0);
943
944	if (uc.ui) {
945		r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
946		r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
947		r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
948		r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
949	}
950	return rstate;
951}
952
953static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
954							struct pipe_resource *texture,
955							const struct pipe_sampler_view *state)
956{
957	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
958	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
959	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
960	unsigned format, endian;
961	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
962	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
963	unsigned height, depth, width;
964	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
965
966	if (view == NULL)
967		return NULL;
968
969	/* initialize base object */
970	view->base = *state;
971	view->base.texture = NULL;
972	pipe_reference(NULL, &texture->reference);
973	view->base.texture = texture;
974	view->base.reference.count = 1;
975	view->base.context = ctx;
976
977	swizzle[0] = state->swizzle_r;
978	swizzle[1] = state->swizzle_g;
979	swizzle[2] = state->swizzle_b;
980	swizzle[3] = state->swizzle_a;
981
982	format = r600_translate_texformat(ctx->screen, state->format,
983					  swizzle,
984					  &word4, &yuv_format);
985	assert(format != ~0);
986	if (format == ~0) {
987		FREE(view);
988		return NULL;
989	}
990
991	if (tmp->is_depth && !tmp->is_flushing_texture) {
992		if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
993			FREE(view);
994			return NULL;
995		}
996		tmp = tmp->flushed_depth_texture;
997	}
998
999	endian = r600_colorformat_endian_swap(format);
1000
1001	width = tmp->surface.level[0].npix_x;
1002	height = tmp->surface.level[0].npix_y;
1003	depth = tmp->surface.level[0].npix_z;
1004	pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1005	tile_type = tmp->tile_type;
1006
1007	switch (tmp->surface.level[0].mode) {
1008	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1009		array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1010		break;
1011	case RADEON_SURF_MODE_2D:
1012		array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1013		break;
1014	case RADEON_SURF_MODE_1D:
1015		array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1016		break;
1017	case RADEON_SURF_MODE_LINEAR:
1018	default:
1019		array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1020		break;
1021	}
1022	tile_split = tmp->surface.tile_split;
1023	macro_aspect = tmp->surface.mtilea;
1024	bankw = tmp->surface.bankw;
1025	bankh = tmp->surface.bankh;
1026	tile_split = eg_tile_split(tile_split);
1027	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1028	bankw = eg_bank_wh(bankw);
1029	bankh = eg_bank_wh(bankh);
1030
1031	/* 128 bit formats require tile type = 1 */
1032	if (rscreen->chip_class == CAYMAN) {
1033		if (util_format_get_blocksize(state->format) >= 16)
1034			tile_type = 1;
1035	}
1036	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1037
1038	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1039	        height = 1;
1040		depth = texture->array_size;
1041	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1042		depth = texture->array_size;
1043	}
1044
1045	view->tex_resource = &tmp->resource;
1046	view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1047				       S_030000_PITCH((pitch / 8) - 1) |
1048				       S_030000_TEX_WIDTH(width - 1));
1049	if (rscreen->chip_class == CAYMAN)
1050		view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1051	else
1052		view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1053	view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1054				       S_030004_TEX_DEPTH(depth - 1) |
1055				       S_030004_ARRAY_MODE(array_mode));
1056	view->tex_resource_words[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1057	if (state->u.tex.last_level) {
1058		view->tex_resource_words[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1059	} else {
1060		view->tex_resource_words[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1061	}
1062	view->tex_resource_words[4] = (word4 |
1063				       S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1064				       S_030010_ENDIAN_SWAP(endian) |
1065				       S_030010_BASE_LEVEL(state->u.tex.first_level));
1066	view->tex_resource_words[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1067				       S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1068				       S_030014_LAST_ARRAY(state->u.tex.last_layer));
1069	/* aniso max 16 samples */
1070	view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1071				      (S_030018_TILE_SPLIT(tile_split));
1072	view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1073				      S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1074				      S_03001C_BANK_WIDTH(bankw) |
1075				      S_03001C_BANK_HEIGHT(bankh) |
1076				      S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1077				      S_03001C_NUM_BANKS(nbanks);
1078	return &view->base;
1079}
1080
1081static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1082					   struct pipe_sampler_view **views)
1083{
1084	struct r600_context *rctx = (struct r600_context *)ctx;
1085	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
1086}
1087
1088static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1089					   struct pipe_sampler_view **views)
1090{
1091	struct r600_context *rctx = (struct r600_context *)ctx;
1092	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
1093}
1094
1095static void evergreen_bind_samplers(struct r600_context *rctx,
1096				    struct r600_textures_info *dst,
1097				    unsigned count, void **states,
1098				    void (*set_sampler)(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id))
1099{
1100	struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
1101
1102	for (int i = 0; i < count; i++) {
1103		if (rstates[i] != dst->samplers[i]) {
1104			set_sampler(rctx, &rstates[i]->rstate, i);
1105		}
1106	}
1107
1108	memcpy(dst->samplers, states, sizeof(void*) * count);
1109	dst->n_samplers = count;
1110}
1111
1112static void evergreen_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1113{
1114	struct r600_context *rctx = (struct r600_context *)ctx;
1115	evergreen_bind_samplers(rctx, &rctx->ps_samplers, count, states,
1116				evergreen_context_pipe_state_set_ps_sampler);
1117}
1118
1119static void evergreen_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1120{
1121	struct r600_context *rctx = (struct r600_context *)ctx;
1122	evergreen_bind_samplers(rctx, &rctx->vs_samplers, count, states,
1123				evergreen_context_pipe_state_set_vs_sampler);
1124}
1125
1126static void evergreen_set_clip_state(struct pipe_context *ctx,
1127				const struct pipe_clip_state *state)
1128{
1129	struct r600_context *rctx = (struct r600_context *)ctx;
1130	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1131	struct pipe_constant_buffer cb;
1132
1133	if (rstate == NULL)
1134		return;
1135
1136	rctx->clip = *state;
1137	rstate->id = R600_PIPE_STATE_CLIP;
1138	for (int i = 0; i < 6; i++) {
1139		r600_pipe_state_add_reg(rstate,
1140					R_0285BC_PA_CL_UCP0_X + i * 16,
1141					fui(state->ucp[i][0]));
1142		r600_pipe_state_add_reg(rstate,
1143					R_0285C0_PA_CL_UCP0_Y + i * 16,
1144					fui(state->ucp[i][1]) );
1145		r600_pipe_state_add_reg(rstate,
1146					R_0285C4_PA_CL_UCP0_Z + i * 16,
1147					fui(state->ucp[i][2]));
1148		r600_pipe_state_add_reg(rstate,
1149					R_0285C8_PA_CL_UCP0_W + i * 16,
1150					fui(state->ucp[i][3]));
1151	}
1152
1153	free(rctx->states[R600_PIPE_STATE_CLIP]);
1154	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1155	r600_context_pipe_state_set(rctx, rstate);
1156
1157	cb.buffer = NULL;
1158	cb.user_buffer = state->ucp;
1159	cb.buffer_offset = 0;
1160	cb.buffer_size = 4*4*8;
1161	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1162	pipe_resource_reference(&cb.buffer, NULL);
1163}
1164
1165static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1166					 const struct pipe_poly_stipple *state)
1167{
1168}
1169
1170static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1171{
1172}
1173
1174static void evergreen_get_scissor_rect(struct r600_context *rctx,
1175				       unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1176				       uint32_t *tl, uint32_t *br)
1177{
1178	/* EG hw workaround */
1179	if (br_x == 0)
1180		tl_x = 1;
1181	if (br_y == 0)
1182		tl_y = 1;
1183
1184	/* cayman hw workaround */
1185	if (rctx->chip_class == CAYMAN) {
1186		if (br_x == 1 && br_y == 1)
1187			br_x = 2;
1188	}
1189
1190	*tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1191	*br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1192}
1193
1194static void evergreen_set_scissor_state(struct pipe_context *ctx,
1195					const struct pipe_scissor_state *state)
1196{
1197	struct r600_context *rctx = (struct r600_context *)ctx;
1198	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1199	uint32_t tl, br;
1200
1201	if (rstate == NULL)
1202		return;
1203
1204	evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1205
1206	rstate->id = R600_PIPE_STATE_SCISSOR;
1207	r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1208	r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1209
1210	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1211	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1212	r600_context_pipe_state_set(rctx, rstate);
1213}
1214
1215static void evergreen_set_viewport_state(struct pipe_context *ctx,
1216					const struct pipe_viewport_state *state)
1217{
1218	struct r600_context *rctx = (struct r600_context *)ctx;
1219	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1220
1221	if (rstate == NULL)
1222		return;
1223
1224	rctx->viewport = *state;
1225	rstate->id = R600_PIPE_STATE_VIEWPORT;
1226	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1227	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1228	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1229	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1230	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1231	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1232
1233	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1234	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1235	r600_context_pipe_state_set(rctx, rstate);
1236}
1237
1238void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1239			 const struct pipe_framebuffer_state *state, int cb)
1240{
1241	struct r600_screen *rscreen = rctx->screen;
1242	struct r600_resource_texture *rtex;
1243	struct pipe_resource * pipe_tex;
1244	struct r600_surface *surf;
1245	unsigned level = state->cbufs[cb]->u.tex.level;
1246	unsigned pitch, slice;
1247	unsigned color_info, color_attrib, color_dim = 0;
1248	unsigned format, swap, ntype, endian;
1249	uint64_t offset;
1250	unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1251	const struct util_format_description *desc;
1252	int i;
1253	bool blend_clamp = 0, blend_bypass = 0, alphatest_bypass;
1254
1255	surf = (struct r600_surface *)state->cbufs[cb];
1256	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1257	pipe_tex = state->cbufs[cb]->texture;
1258
1259	if (rtex->is_depth && !rtex->is_flushing_texture) {
1260		r600_init_flushed_depth_texture(&rctx->context,
1261				state->cbufs[cb]->texture, NULL);
1262		rtex = rtex->flushed_depth_texture;
1263		assert(rtex);
1264	}
1265
1266	offset = rtex->surface.level[level].offset;
1267	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1268		offset += rtex->surface.level[level].slice_size *
1269			  state->cbufs[cb]->u.tex.first_layer;
1270	}
1271	pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1272	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1273	if (slice) {
1274		slice = slice - 1;
1275	}
1276	color_info = 0;
1277	switch (rtex->surface.level[level].mode) {
1278	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1279		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1280		tile_type = 1;
1281		break;
1282	case RADEON_SURF_MODE_1D:
1283		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1284		tile_type = rtex->tile_type;
1285		break;
1286	case RADEON_SURF_MODE_2D:
1287		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1288		tile_type = rtex->tile_type;
1289		break;
1290	case RADEON_SURF_MODE_LINEAR:
1291	default:
1292		color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1293		tile_type = 1;
1294		break;
1295	}
1296	tile_split = rtex->surface.tile_split;
1297	macro_aspect = rtex->surface.mtilea;
1298	bankw = rtex->surface.bankw;
1299	bankh = rtex->surface.bankh;
1300	tile_split = eg_tile_split(tile_split);
1301	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1302	bankw = eg_bank_wh(bankw);
1303	bankh = eg_bank_wh(bankh);
1304
1305	/* 128 bit formats require tile type = 1 */
1306	if (rscreen->chip_class == CAYMAN) {
1307		if (util_format_get_blocksize(surf->base.format) >= 16)
1308			tile_type = 1;
1309	}
1310	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1311	desc = util_format_description(surf->base.format);
1312	for (i = 0; i < 4; i++) {
1313		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1314			break;
1315		}
1316	}
1317
1318	color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1319			S_028C74_NUM_BANKS(nbanks) |
1320			S_028C74_BANK_WIDTH(bankw) |
1321			S_028C74_BANK_HEIGHT(bankh) |
1322			S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1323			S_028C74_NON_DISP_TILING_ORDER(tile_type);
1324
1325	ntype = V_028C70_NUMBER_UNORM;
1326	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1327		ntype = V_028C70_NUMBER_SRGB;
1328	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1329		if (desc->channel[i].normalized)
1330			ntype = V_028C70_NUMBER_SNORM;
1331		else if (desc->channel[i].pure_integer)
1332			ntype = V_028C70_NUMBER_SINT;
1333	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1334		if (desc->channel[i].normalized)
1335			ntype = V_028C70_NUMBER_UNORM;
1336		else if (desc->channel[i].pure_integer)
1337			ntype = V_028C70_NUMBER_UINT;
1338	}
1339
1340	format = r600_translate_colorformat(surf->base.format);
1341	assert(format != ~0);
1342
1343	swap = r600_translate_colorswap(surf->base.format);
1344	assert(swap != ~0);
1345
1346	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1347		endian = ENDIAN_NONE;
1348	} else {
1349		endian = r600_colorformat_endian_swap(format);
1350	}
1351
1352	/* blend clamp should be set for all NORM/SRGB types */
1353	if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1354	    ntype == V_028C70_NUMBER_SRGB)
1355		blend_clamp = 1;
1356
1357	/* set blend bypass according to docs if SINT/UINT or
1358	   8/24 COLOR variants */
1359	if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1360	    format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1361	    format == V_028C70_COLOR_X24_8_32_FLOAT) {
1362		blend_clamp = 0;
1363		blend_bypass = 1;
1364	}
1365
1366	/* Alpha-test is done on the first colorbuffer only. */
1367	if (cb == 0) {
1368		alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1369		if (rctx->alphatest_state.bypass != alphatest_bypass) {
1370			rctx->alphatest_state.bypass = alphatest_bypass;
1371			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1372		}
1373	}
1374
1375	color_info |= S_028C70_FORMAT(format) |
1376		S_028C70_COMP_SWAP(swap) |
1377		S_028C70_BLEND_CLAMP(blend_clamp) |
1378		S_028C70_BLEND_BYPASS(blend_bypass) |
1379		S_028C70_NUMBER_TYPE(ntype) |
1380		S_028C70_ENDIAN(endian);
1381
1382	if (rtex->is_rat) {
1383		color_info |= S_028C70_RAT(1);
1384		color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1385				| S_028C78_HEIGHT_MAX(pipe_tex->height0);
1386	}
1387
1388	/* EXPORT_NORM is an optimzation that can be enabled for better
1389	 * performance in certain cases.
1390	 * EXPORT_NORM can be enabled if:
1391	 * - 11-bit or smaller UNORM/SNORM/SRGB
1392	 * - 16-bit or smaller FLOAT
1393	 */
1394	/* XXX: This should probably be the same for all CBs if we want
1395	 * useful alpha tests. */
1396	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1397	    ((desc->channel[i].size < 12 &&
1398	      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1399	      ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1400	     (desc->channel[i].size < 17 &&
1401	      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1402		color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1403	} else {
1404		rctx->export_16bpc = false;
1405	}
1406
1407	/* Alpha-test is done on the first colorbuffer only. */
1408	if (cb == 0 && rctx->alphatest_state.cb0_export_16bpc != rctx->export_16bpc) {
1409		rctx->alphatest_state.cb0_export_16bpc = rctx->export_16bpc;
1410		r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1411	}
1412
1413	/* for possible dual-src MRT */
1414	if (cb == 0 && rctx->framebuffer.nr_cbufs == 1 && !rtex->is_rat) {
1415		r600_pipe_state_add_reg_bo(rstate,
1416				R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1417				color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1418	}
1419
1420	offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1421	offset >>= 8;
1422
1423	/* XXX handle enabling of CB beyond BASE8 which has different offset */
1424	r600_pipe_state_add_reg_bo(rstate,
1425				R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1426				offset, &rtex->resource, RADEON_USAGE_READWRITE);
1427	r600_pipe_state_add_reg(rstate,
1428				R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1429				color_dim);
1430	r600_pipe_state_add_reg_bo(rstate,
1431				R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1432				color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1433	r600_pipe_state_add_reg(rstate,
1434				R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1435				S_028C64_PITCH_TILE_MAX(pitch));
1436	r600_pipe_state_add_reg(rstate,
1437				R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1438				S_028C68_SLICE_TILE_MAX(slice));
1439	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1440		r600_pipe_state_add_reg(rstate,
1441					R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1442					0x00000000);
1443	} else {
1444		r600_pipe_state_add_reg(rstate,
1445					R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1446					S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1447					S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1448	}
1449	r600_pipe_state_add_reg_bo(rstate,
1450				R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1451				color_attrib,
1452				&rtex->resource, RADEON_USAGE_READWRITE);
1453}
1454
1455static void evergreen_init_depth_surface(struct r600_context *rctx,
1456					 struct r600_surface *surf)
1457{
1458	struct r600_screen *rscreen = rctx->screen;
1459	struct pipe_screen *screen = &rscreen->screen;
1460	struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1461	uint64_t offset;
1462	unsigned level, pitch, slice, format, array_mode;
1463	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
1464
1465	level = surf->base.u.tex.level;
1466	format = r600_translate_dbformat(surf->base.format);
1467	assert(format != ~0);
1468
1469	offset = r600_resource_va(screen, surf->base.texture);
1470	offset += rtex->surface.level[level].offset;
1471	pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1472	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1473	if (slice) {
1474		slice = slice - 1;
1475	}
1476	switch (rtex->surface.level[level].mode) {
1477	case RADEON_SURF_MODE_2D:
1478		array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1479		break;
1480	case RADEON_SURF_MODE_1D:
1481	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1482	case RADEON_SURF_MODE_LINEAR:
1483	default:
1484		array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1485		break;
1486	}
1487	tile_split = rtex->surface.tile_split;
1488	macro_aspect = rtex->surface.mtilea;
1489	bankw = rtex->surface.bankw;
1490	bankh = rtex->surface.bankh;
1491	tile_split = eg_tile_split(tile_split);
1492	macro_aspect = eg_macro_tile_aspect(macro_aspect);
1493	bankw = eg_bank_wh(bankw);
1494	bankh = eg_bank_wh(bankh);
1495	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1496	offset >>= 8;
1497
1498	surf->db_depth_info = S_028040_ARRAY_MODE(array_mode) |
1499			      S_028040_FORMAT(format) |
1500			      S_028040_TILE_SPLIT(tile_split)|
1501			      S_028040_NUM_BANKS(nbanks) |
1502			      S_028040_BANK_WIDTH(bankw) |
1503			      S_028040_BANK_HEIGHT(bankh) |
1504			      S_028040_MACRO_TILE_ASPECT(macro_aspect);
1505	surf->db_depth_base = offset;
1506	surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1507			      S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1508	surf->db_depth_size = S_028058_PITCH_TILE_MAX(pitch);
1509	surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(slice);
1510
1511	if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1512		uint64_t stencil_offset = rtex->surface.stencil_offset;
1513		unsigned stile_split = rtex->surface.stencil_tile_split;
1514
1515		stile_split = eg_tile_split(stile_split);
1516		stencil_offset += r600_resource_va(screen, surf->base.texture);
1517		stencil_offset += rtex->surface.level[level].offset / 4;
1518		stencil_offset >>= 8;
1519
1520		surf->db_stencil_base = stencil_offset;
1521		surf->db_stencil_info = 1 | S_028044_TILE_SPLIT(stile_split);
1522	} else {
1523		surf->db_stencil_base = offset;
1524		surf->db_stencil_info = 1;
1525	}
1526
1527	surf->depth_initialized = true;
1528}
1529
1530static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1531					    const struct pipe_framebuffer_state *state)
1532{
1533	struct r600_context *rctx = (struct r600_context *)ctx;
1534	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1535	struct r600_surface *surf;
1536	struct r600_resource *res;
1537	uint32_t tl, br;
1538	int i;
1539
1540	if (rstate == NULL)
1541		return;
1542
1543	r600_flush_framebuffer(rctx, false);
1544
1545	/* unreference old buffer and reference new one */
1546	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1547
1548	util_copy_framebuffer_state(&rctx->framebuffer, state);
1549
1550	/* build states */
1551	rctx->export_16bpc = true;
1552	rctx->nr_cbufs = state->nr_cbufs;
1553	for (i = 0; i < state->nr_cbufs; i++) {
1554		evergreen_cb(rctx, rstate, state, i);
1555	}
1556	/* CB_COLOR1_INFO is already initialized for possible dual-src blending */
1557	if (i == 1)
1558		i++;
1559	for (; i < 8 ; i++) {
1560		r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1561	}
1562
1563	if (state->zsbuf) {
1564		surf = (struct r600_surface*)state->zsbuf;
1565		res = (struct r600_resource*)surf->base.texture;
1566
1567		if (!surf->depth_initialized) {
1568			evergreen_init_depth_surface(rctx, surf);
1569		}
1570
1571		r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE, surf->db_depth_base,
1572					   res, RADEON_USAGE_READWRITE);
1573		r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE, surf->db_depth_base,
1574					   res, RADEON_USAGE_READWRITE);
1575		r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, surf->db_depth_view);
1576
1577		r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE, surf->db_stencil_base,
1578					   res, RADEON_USAGE_READWRITE);
1579		r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE, surf->db_stencil_base,
1580					   res, RADEON_USAGE_READWRITE);
1581		r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO, surf->db_stencil_info,
1582					   res, RADEON_USAGE_READWRITE);
1583
1584		r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, surf->db_depth_info,
1585					   res, RADEON_USAGE_READWRITE);
1586		r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, surf->db_depth_size);
1587		r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, surf->db_depth_slice);
1588	}
1589
1590	evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1591
1592	r600_pipe_state_add_reg(rstate,
1593				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1594	r600_pipe_state_add_reg(rstate,
1595				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1596
1597	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1598	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1599	r600_context_pipe_state_set(rctx, rstate);
1600
1601	if (state->zsbuf) {
1602		evergreen_polygon_offset_update(rctx);
1603	}
1604
1605	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1606		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1607		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1608	}
1609}
1610
1611static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1612{
1613	struct radeon_winsys_cs *cs = rctx->cs;
1614	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1615	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1616	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1617
1618	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1619	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1620	/* Always enable the first colorbuffer in CB_SHADER_MASK. This
1621	 * will assure that the alpha-test will work even if there is
1622	 * no colorbuffer bound. */
1623	r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1624}
1625
1626static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1627{
1628	struct radeon_winsys_cs *cs = rctx->cs;
1629	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1630	unsigned db_render_control = 0;
1631	unsigned db_count_control = 0;
1632	unsigned db_render_override =
1633		S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1634		S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1635		S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1636
1637	if (a->occlusion_query_enabled) {
1638		db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1639		db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1640	}
1641
1642	if (a->flush_depthstencil_through_cb) {
1643		assert(a->copy_depth || a->copy_stencil);
1644
1645		db_render_control |= S_028000_DEPTH_COPY_ENABLE(a->copy_depth) |
1646				     S_028000_STENCIL_COPY_ENABLE(a->copy_stencil) |
1647				     S_028000_COPY_CENTROID(1);
1648	}
1649
1650	r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1651	r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1652	r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1653	r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1654}
1655
1656static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1657					  struct r600_vertexbuf_state *state,
1658					  unsigned resource_offset,
1659					  unsigned pkt_flags)
1660{
1661	struct radeon_winsys_cs *cs = rctx->cs;
1662	uint32_t dirty_mask = state->dirty_mask;
1663
1664	while (dirty_mask) {
1665		struct pipe_vertex_buffer *vb;
1666		struct r600_resource *rbuffer;
1667		uint64_t va;
1668		unsigned buffer_index = u_bit_scan(&dirty_mask);
1669
1670		vb = &state->vb[buffer_index];
1671		rbuffer = (struct r600_resource*)vb->buffer;
1672		assert(rbuffer);
1673
1674		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1675		va += vb->buffer_offset;
1676
1677		/* fetch resources start at index 992 */
1678		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1679		r600_write_value(cs, (resource_offset + buffer_index) * 8);
1680		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1681		r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1682		r600_write_value(cs, /* RESOURCEi_WORD2 */
1683				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1684				 S_030008_STRIDE(vb->stride) |
1685				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1686		r600_write_value(cs, /* RESOURCEi_WORD3 */
1687				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1688				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1689				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1690				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1691		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1692		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1693		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1694		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1695
1696		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1697		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1698	}
1699	state->dirty_mask = 0;
1700}
1701
1702static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1703{
1704	evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1705}
1706
1707static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1708{
1709	evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1710				      RADEON_CP_PACKET3_COMPUTE_MODE);
1711}
1712
1713static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1714					    struct r600_constbuf_state *state,
1715					    unsigned buffer_id_base,
1716					    unsigned reg_alu_constbuf_size,
1717					    unsigned reg_alu_const_cache)
1718{
1719	struct radeon_winsys_cs *cs = rctx->cs;
1720	uint32_t dirty_mask = state->dirty_mask;
1721
1722	while (dirty_mask) {
1723		struct pipe_constant_buffer *cb;
1724		struct r600_resource *rbuffer;
1725		uint64_t va;
1726		unsigned buffer_index = ffs(dirty_mask) - 1;
1727
1728		cb = &state->cb[buffer_index];
1729		rbuffer = (struct r600_resource*)cb->buffer;
1730		assert(rbuffer);
1731
1732		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1733		va += cb->buffer_offset;
1734
1735		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1736				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1737		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1738
1739		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1740		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1741
1742		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1743		r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1744		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1745		r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1746		r600_write_value(cs, /* RESOURCEi_WORD2 */
1747				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1748				 S_030008_STRIDE(16) |
1749				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1750		r600_write_value(cs, /* RESOURCEi_WORD3 */
1751				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1752				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1753				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1754				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1755		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1756		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1757		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1758		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1759
1760		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1761		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1762
1763		dirty_mask &= ~(1 << buffer_index);
1764	}
1765	state->dirty_mask = 0;
1766}
1767
1768static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1769{
1770	evergreen_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 176,
1771					R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1772					R_028980_ALU_CONST_CACHE_VS_0);
1773}
1774
1775static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1776{
1777	evergreen_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1778				       R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1779				       R_028940_ALU_CONST_CACHE_PS_0);
1780}
1781
1782static void evergreen_emit_sampler_views(struct r600_context *rctx,
1783					 struct r600_samplerview_state *state,
1784					 unsigned resource_id_base)
1785{
1786	struct radeon_winsys_cs *cs = rctx->cs;
1787	uint32_t dirty_mask = state->dirty_mask;
1788
1789	while (dirty_mask) {
1790		struct r600_pipe_sampler_view *rview;
1791		unsigned resource_index = u_bit_scan(&dirty_mask);
1792		unsigned reloc;
1793
1794		rview = state->views[resource_index];
1795		assert(rview);
1796
1797		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1798		r600_write_value(cs, (resource_id_base + resource_index) * 8);
1799		r600_write_array(cs, 8, rview->tex_resource_words);
1800
1801		/* XXX The kernel needs two relocations. This is stupid. */
1802		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1803					      RADEON_USAGE_READ);
1804		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1805		r600_write_value(cs, reloc);
1806		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1807		r600_write_value(cs, reloc);
1808	}
1809	state->dirty_mask = 0;
1810}
1811
1812static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1813{
1814	evergreen_emit_sampler_views(rctx, &rctx->vs_samplers.views, 176 + R600_MAX_CONST_BUFFERS);
1815}
1816
1817static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1818{
1819	evergreen_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1820}
1821
1822void evergreen_init_state_functions(struct r600_context *rctx)
1823{
1824	r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
1825	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1826	r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 7, 0);
1827	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1828	r600_init_atom(&rctx->vertex_buffer_state.atom, evergreen_fs_emit_vertex_buffers, 0, 0);
1829	r600_init_atom(&rctx->cs_vertex_buffer_state.atom, evergreen_cs_emit_vertex_buffers, 0, 0);
1830	r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
1831	r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
1832	r600_init_atom(&rctx->vs_samplers.views.atom, evergreen_emit_vs_sampler_views, 0, 0);
1833	r600_init_atom(&rctx->ps_samplers.views.atom, evergreen_emit_ps_sampler_views, 0, 0);
1834	r600_init_atom(&rctx->cs_shader_state.atom, evergreen_emit_cs_shader, 0, 0);
1835
1836	rctx->context.create_blend_state = evergreen_create_blend_state;
1837	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1838	rctx->context.create_fs_state = r600_create_shader_state_ps;
1839	rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1840	rctx->context.create_sampler_state = evergreen_create_sampler_state;
1841	rctx->context.create_sampler_view = evergreen_create_sampler_view;
1842	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1843	rctx->context.create_vs_state = r600_create_shader_state_vs;
1844	rctx->context.bind_blend_state = r600_bind_blend_state;
1845	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1846	rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_samplers;
1847	rctx->context.bind_fs_state = r600_bind_ps_shader;
1848	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1849	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1850	rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_samplers;
1851	rctx->context.bind_vs_state = r600_bind_vs_shader;
1852	rctx->context.delete_blend_state = r600_delete_state;
1853	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1854	rctx->context.delete_fs_state = r600_delete_ps_shader;
1855	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1856	rctx->context.delete_sampler_state = r600_delete_state;
1857	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1858	rctx->context.delete_vs_state = r600_delete_vs_shader;
1859	rctx->context.set_blend_color = r600_set_blend_color;
1860	rctx->context.set_clip_state = evergreen_set_clip_state;
1861	rctx->context.set_constant_buffer = r600_set_constant_buffer;
1862	rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_views;
1863	rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1864	rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1865	rctx->context.set_sample_mask = evergreen_set_sample_mask;
1866	rctx->context.set_scissor_state = evergreen_set_scissor_state;
1867	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1868	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1869	rctx->context.set_index_buffer = r600_set_index_buffer;
1870	rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_views;
1871	rctx->context.set_viewport_state = evergreen_set_viewport_state;
1872	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1873	rctx->context.texture_barrier = r600_texture_barrier;
1874	rctx->context.create_stream_output_target = r600_create_so_target;
1875	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1876	rctx->context.set_stream_output_targets = r600_set_so_targets;
1877	evergreen_init_compute_state_functions(rctx);
1878}
1879
1880static void cayman_init_atom_start_cs(struct r600_context *rctx)
1881{
1882	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1883
1884	r600_init_command_buffer(cb, 256, EMIT_EARLY);
1885
1886	/* This must be first. */
1887	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1888	r600_store_value(cb, 0x80000000);
1889	r600_store_value(cb, 0x80000000);
1890
1891	r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1892	r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1893	/* always set the temp clauses */
1894	r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1895
1896	r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1897	r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1898	r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1899
1900	r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1901
1902	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1903
1904	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1905	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1906	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1907	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1908	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1909	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1910	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1911	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1912	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1913	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1914	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1915	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1916	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1917	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1918
1919	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
1920	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
1921	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
1922
1923	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
1924	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
1925	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
1926
1927	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
1928
1929	r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
1930
1931	r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
1932	r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
1933	r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
1934
1935	r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
1936	r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
1937	r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
1938
1939	r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
1940
1941	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
1942	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
1943	r600_store_value(cb, 0);
1944	r600_store_value(cb, 0);
1945	r600_store_value(cb, 0);
1946	r600_store_value(cb, 0);
1947	r600_store_value(cb, 0);
1948	r600_store_value(cb, 0);
1949	r600_store_value(cb, 0);
1950	r600_store_value(cb, 0);
1951	r600_store_value(cb, 0);
1952	r600_store_value(cb, 0);
1953	r600_store_value(cb, 0);
1954	r600_store_value(cb, 0);
1955	r600_store_value(cb, 0);
1956	r600_store_value(cb, 0);
1957	r600_store_value(cb, 0);
1958	r600_store_value(cb, 0);
1959	r600_store_value(cb, 0);
1960	r600_store_value(cb, 0);
1961	r600_store_value(cb, 0);
1962	r600_store_value(cb, 0);
1963	r600_store_value(cb, 0);
1964	r600_store_value(cb, 0);
1965	r600_store_value(cb, 0);
1966	r600_store_value(cb, 0);
1967	r600_store_value(cb, 0);
1968	r600_store_value(cb, 0);
1969	r600_store_value(cb, 0);
1970	r600_store_value(cb, 0);
1971	r600_store_value(cb, 0);
1972	r600_store_value(cb, 0);
1973	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
1974	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
1975	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
1976
1977	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
1978
1979	r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
1980	r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
1981	r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
1982
1983	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
1984	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
1985	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
1986
1987	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
1988
1989	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
1990	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
1991	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
1992	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
1993
1994	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
1995	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
1996
1997	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
1998	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
1999	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2000
2001	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2002	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2003	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2004	r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2005
2006	r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2007	r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2008	r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2009
2010	r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2011	r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2012	r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2013	r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2014	r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2015
2016	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2017	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2018	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2019
2020	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2021	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2022	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2023
2024	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2025	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2026	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2027
2028	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2029	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2030	if (rctx->screen->has_streamout) {
2031		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2032	}
2033
2034	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2035	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2036}
2037
2038void evergreen_init_atom_start_cs(struct r600_context *rctx)
2039{
2040	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2041	int ps_prio;
2042	int vs_prio;
2043	int gs_prio;
2044	int es_prio;
2045	int hs_prio, cs_prio, ls_prio;
2046	int num_ps_gprs;
2047	int num_vs_gprs;
2048	int num_gs_gprs;
2049	int num_es_gprs;
2050	int num_hs_gprs;
2051	int num_ls_gprs;
2052	int num_temp_gprs;
2053	int num_ps_threads;
2054	int num_vs_threads;
2055	int num_gs_threads;
2056	int num_es_threads;
2057	int num_hs_threads;
2058	int num_ls_threads;
2059	int num_ps_stack_entries;
2060	int num_vs_stack_entries;
2061	int num_gs_stack_entries;
2062	int num_es_stack_entries;
2063	int num_hs_stack_entries;
2064	int num_ls_stack_entries;
2065	enum radeon_family family;
2066	unsigned tmp;
2067
2068	if (rctx->chip_class == CAYMAN) {
2069		cayman_init_atom_start_cs(rctx);
2070		return;
2071	}
2072
2073	r600_init_command_buffer(cb, 256, EMIT_EARLY);
2074
2075	/* This must be first. */
2076	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2077	r600_store_value(cb, 0x80000000);
2078	r600_store_value(cb, 0x80000000);
2079
2080	family = rctx->family;
2081	ps_prio = 0;
2082	vs_prio = 1;
2083	gs_prio = 2;
2084	es_prio = 3;
2085	hs_prio = 0;
2086	ls_prio = 0;
2087	cs_prio = 0;
2088
2089	switch (family) {
2090	case CHIP_CEDAR:
2091	default:
2092		num_ps_gprs = 93;
2093		num_vs_gprs = 46;
2094		num_temp_gprs = 4;
2095		num_gs_gprs = 31;
2096		num_es_gprs = 31;
2097		num_hs_gprs = 23;
2098		num_ls_gprs = 23;
2099		num_ps_threads = 96;
2100		num_vs_threads = 16;
2101		num_gs_threads = 16;
2102		num_es_threads = 16;
2103		num_hs_threads = 16;
2104		num_ls_threads = 16;
2105		num_ps_stack_entries = 42;
2106		num_vs_stack_entries = 42;
2107		num_gs_stack_entries = 42;
2108		num_es_stack_entries = 42;
2109		num_hs_stack_entries = 42;
2110		num_ls_stack_entries = 42;
2111		break;
2112	case CHIP_REDWOOD:
2113		num_ps_gprs = 93;
2114		num_vs_gprs = 46;
2115		num_temp_gprs = 4;
2116		num_gs_gprs = 31;
2117		num_es_gprs = 31;
2118		num_hs_gprs = 23;
2119		num_ls_gprs = 23;
2120		num_ps_threads = 128;
2121		num_vs_threads = 20;
2122		num_gs_threads = 20;
2123		num_es_threads = 20;
2124		num_hs_threads = 20;
2125		num_ls_threads = 20;
2126		num_ps_stack_entries = 42;
2127		num_vs_stack_entries = 42;
2128		num_gs_stack_entries = 42;
2129		num_es_stack_entries = 42;
2130		num_hs_stack_entries = 42;
2131		num_ls_stack_entries = 42;
2132		break;
2133	case CHIP_JUNIPER:
2134		num_ps_gprs = 93;
2135		num_vs_gprs = 46;
2136		num_temp_gprs = 4;
2137		num_gs_gprs = 31;
2138		num_es_gprs = 31;
2139		num_hs_gprs = 23;
2140		num_ls_gprs = 23;
2141		num_ps_threads = 128;
2142		num_vs_threads = 20;
2143		num_gs_threads = 20;
2144		num_es_threads = 20;
2145		num_hs_threads = 20;
2146		num_ls_threads = 20;
2147		num_ps_stack_entries = 85;
2148		num_vs_stack_entries = 85;
2149		num_gs_stack_entries = 85;
2150		num_es_stack_entries = 85;
2151		num_hs_stack_entries = 85;
2152		num_ls_stack_entries = 85;
2153		break;
2154	case CHIP_CYPRESS:
2155	case CHIP_HEMLOCK:
2156		num_ps_gprs = 93;
2157		num_vs_gprs = 46;
2158		num_temp_gprs = 4;
2159		num_gs_gprs = 31;
2160		num_es_gprs = 31;
2161		num_hs_gprs = 23;
2162		num_ls_gprs = 23;
2163		num_ps_threads = 128;
2164		num_vs_threads = 20;
2165		num_gs_threads = 20;
2166		num_es_threads = 20;
2167		num_hs_threads = 20;
2168		num_ls_threads = 20;
2169		num_ps_stack_entries = 85;
2170		num_vs_stack_entries = 85;
2171		num_gs_stack_entries = 85;
2172		num_es_stack_entries = 85;
2173		num_hs_stack_entries = 85;
2174		num_ls_stack_entries = 85;
2175		break;
2176	case CHIP_PALM:
2177		num_ps_gprs = 93;
2178		num_vs_gprs = 46;
2179		num_temp_gprs = 4;
2180		num_gs_gprs = 31;
2181		num_es_gprs = 31;
2182		num_hs_gprs = 23;
2183		num_ls_gprs = 23;
2184		num_ps_threads = 96;
2185		num_vs_threads = 16;
2186		num_gs_threads = 16;
2187		num_es_threads = 16;
2188		num_hs_threads = 16;
2189		num_ls_threads = 16;
2190		num_ps_stack_entries = 42;
2191		num_vs_stack_entries = 42;
2192		num_gs_stack_entries = 42;
2193		num_es_stack_entries = 42;
2194		num_hs_stack_entries = 42;
2195		num_ls_stack_entries = 42;
2196		break;
2197	case CHIP_SUMO:
2198		num_ps_gprs = 93;
2199		num_vs_gprs = 46;
2200		num_temp_gprs = 4;
2201		num_gs_gprs = 31;
2202		num_es_gprs = 31;
2203		num_hs_gprs = 23;
2204		num_ls_gprs = 23;
2205		num_ps_threads = 96;
2206		num_vs_threads = 25;
2207		num_gs_threads = 25;
2208		num_es_threads = 25;
2209		num_hs_threads = 25;
2210		num_ls_threads = 25;
2211		num_ps_stack_entries = 42;
2212		num_vs_stack_entries = 42;
2213		num_gs_stack_entries = 42;
2214		num_es_stack_entries = 42;
2215		num_hs_stack_entries = 42;
2216		num_ls_stack_entries = 42;
2217		break;
2218	case CHIP_SUMO2:
2219		num_ps_gprs = 93;
2220		num_vs_gprs = 46;
2221		num_temp_gprs = 4;
2222		num_gs_gprs = 31;
2223		num_es_gprs = 31;
2224		num_hs_gprs = 23;
2225		num_ls_gprs = 23;
2226		num_ps_threads = 96;
2227		num_vs_threads = 25;
2228		num_gs_threads = 25;
2229		num_es_threads = 25;
2230		num_hs_threads = 25;
2231		num_ls_threads = 25;
2232		num_ps_stack_entries = 85;
2233		num_vs_stack_entries = 85;
2234		num_gs_stack_entries = 85;
2235		num_es_stack_entries = 85;
2236		num_hs_stack_entries = 85;
2237		num_ls_stack_entries = 85;
2238		break;
2239	case CHIP_BARTS:
2240		num_ps_gprs = 93;
2241		num_vs_gprs = 46;
2242		num_temp_gprs = 4;
2243		num_gs_gprs = 31;
2244		num_es_gprs = 31;
2245		num_hs_gprs = 23;
2246		num_ls_gprs = 23;
2247		num_ps_threads = 128;
2248		num_vs_threads = 20;
2249		num_gs_threads = 20;
2250		num_es_threads = 20;
2251		num_hs_threads = 20;
2252		num_ls_threads = 20;
2253		num_ps_stack_entries = 85;
2254		num_vs_stack_entries = 85;
2255		num_gs_stack_entries = 85;
2256		num_es_stack_entries = 85;
2257		num_hs_stack_entries = 85;
2258		num_ls_stack_entries = 85;
2259		break;
2260	case CHIP_TURKS:
2261		num_ps_gprs = 93;
2262		num_vs_gprs = 46;
2263		num_temp_gprs = 4;
2264		num_gs_gprs = 31;
2265		num_es_gprs = 31;
2266		num_hs_gprs = 23;
2267		num_ls_gprs = 23;
2268		num_ps_threads = 128;
2269		num_vs_threads = 20;
2270		num_gs_threads = 20;
2271		num_es_threads = 20;
2272		num_hs_threads = 20;
2273		num_ls_threads = 20;
2274		num_ps_stack_entries = 42;
2275		num_vs_stack_entries = 42;
2276		num_gs_stack_entries = 42;
2277		num_es_stack_entries = 42;
2278		num_hs_stack_entries = 42;
2279		num_ls_stack_entries = 42;
2280		break;
2281	case CHIP_CAICOS:
2282		num_ps_gprs = 93;
2283		num_vs_gprs = 46;
2284		num_temp_gprs = 4;
2285		num_gs_gprs = 31;
2286		num_es_gprs = 31;
2287		num_hs_gprs = 23;
2288		num_ls_gprs = 23;
2289		num_ps_threads = 128;
2290		num_vs_threads = 10;
2291		num_gs_threads = 10;
2292		num_es_threads = 10;
2293		num_hs_threads = 10;
2294		num_ls_threads = 10;
2295		num_ps_stack_entries = 42;
2296		num_vs_stack_entries = 42;
2297		num_gs_stack_entries = 42;
2298		num_es_stack_entries = 42;
2299		num_hs_stack_entries = 42;
2300		num_ls_stack_entries = 42;
2301		break;
2302	}
2303
2304	tmp = 0;
2305	switch (family) {
2306	case CHIP_CEDAR:
2307	case CHIP_PALM:
2308	case CHIP_SUMO:
2309	case CHIP_SUMO2:
2310	case CHIP_CAICOS:
2311		break;
2312	default:
2313		tmp |= S_008C00_VC_ENABLE(1);
2314		break;
2315	}
2316	tmp |= S_008C00_EXPORT_SRC_C(1);
2317	tmp |= S_008C00_CS_PRIO(cs_prio);
2318	tmp |= S_008C00_LS_PRIO(ls_prio);
2319	tmp |= S_008C00_HS_PRIO(hs_prio);
2320	tmp |= S_008C00_PS_PRIO(ps_prio);
2321	tmp |= S_008C00_VS_PRIO(vs_prio);
2322	tmp |= S_008C00_GS_PRIO(gs_prio);
2323	tmp |= S_008C00_ES_PRIO(es_prio);
2324
2325	/* enable dynamic GPR resource management */
2326	if (rctx->screen->info.drm_minor >= 7) {
2327		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2328		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2329		/* always set temp clauses */
2330		r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2331		r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2332		r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2333		r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2334		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2335		r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2336					S_028838_PS_GPRS(0x1e) |
2337					S_028838_VS_GPRS(0x1e) |
2338					S_028838_GS_GPRS(0x1e) |
2339					S_028838_ES_GPRS(0x1e) |
2340					S_028838_HS_GPRS(0x1e) |
2341					S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2342	} else {
2343		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2344		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2345
2346		tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2347		tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2348		tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2349		r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2350
2351		tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2352		tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2353		r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2354
2355		tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2356		tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2357		r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2358	}
2359
2360	tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2361	tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2362	tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2363	tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2364	r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2365	r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2366
2367	tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2368	tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2369	r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2370
2371	tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2372	tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2373	r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2374
2375	tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2376	tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2377	r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2378
2379	tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2380	tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2381	r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2382
2383	r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2384			      S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2385
2386	r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2387	r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2388
2389	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2390
2391	r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2392	r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2393	r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2394	r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2395	r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2396	r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2397	r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2398
2399	r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2400	r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2401	r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2402	r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2403	r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2404
2405	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2406	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2407	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2408	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2409	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2410	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2411	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2412	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2413	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2414	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2415	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2416	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2417	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2418	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2419
2420	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2421	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2422	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2423
2424	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2425	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2426	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2427
2428	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2429
2430	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2431	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2432	r600_store_value(cb, 0);
2433	r600_store_value(cb, 0);
2434	r600_store_value(cb, 0);
2435	r600_store_value(cb, 0);
2436	r600_store_value(cb, 0);
2437	r600_store_value(cb, 0);
2438	r600_store_value(cb, 0);
2439	r600_store_value(cb, 0);
2440	r600_store_value(cb, 0);
2441	r600_store_value(cb, 0);
2442	r600_store_value(cb, 0);
2443	r600_store_value(cb, 0);
2444	r600_store_value(cb, 0);
2445	r600_store_value(cb, 0);
2446	r600_store_value(cb, 0);
2447	r600_store_value(cb, 0);
2448	r600_store_value(cb, 0);
2449	r600_store_value(cb, 0);
2450	r600_store_value(cb, 0);
2451	r600_store_value(cb, 0);
2452	r600_store_value(cb, 0);
2453	r600_store_value(cb, 0);
2454	r600_store_value(cb, 0);
2455	r600_store_value(cb, 0);
2456	r600_store_value(cb, 0);
2457	r600_store_value(cb, 0);
2458	r600_store_value(cb, 0);
2459	r600_store_value(cb, 0);
2460	r600_store_value(cb, 0);
2461	r600_store_value(cb, 0);
2462	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2463	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2464	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2465
2466	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2467
2468	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2469	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2470	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2471
2472	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2473	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2474	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2475
2476	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2477	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2478	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2479
2480	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2481	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2482	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2483
2484	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2485	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2486	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2487	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2488
2489	r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2490
2491	r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2492	r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2493	r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2494
2495	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2496	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2497	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2498	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2499	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2500	r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2501
2502	r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2503
2504	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2505	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2506	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2507
2508	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2509	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2510	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2511
2512	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2513	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2514	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2515
2516	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2517	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2518	if (rctx->screen->has_streamout) {
2519		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2520	}
2521
2522	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2523	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2524}
2525
2526void evergreen_polygon_offset_update(struct r600_context *rctx)
2527{
2528	struct r600_pipe_state state;
2529
2530	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2531	state.nregs = 0;
2532	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2533		float offset_units = rctx->rasterizer->offset_units;
2534		unsigned offset_db_fmt_cntl = 0, depth;
2535
2536		switch (rctx->framebuffer.zsbuf->format) {
2537		case PIPE_FORMAT_Z24X8_UNORM:
2538		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2539			depth = -24;
2540			offset_units *= 2.0f;
2541			break;
2542		case PIPE_FORMAT_Z32_FLOAT:
2543		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2544			depth = -23;
2545			offset_units *= 1.0f;
2546			offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2547			break;
2548		case PIPE_FORMAT_Z16_UNORM:
2549			depth = -16;
2550			offset_units *= 4.0f;
2551			break;
2552		default:
2553			return;
2554		}
2555		/* XXX some of those reg can be computed with cso */
2556		offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2557		r600_pipe_state_add_reg(&state,
2558				R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2559				fui(rctx->rasterizer->offset_scale));
2560		r600_pipe_state_add_reg(&state,
2561				R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2562				fui(offset_units));
2563		r600_pipe_state_add_reg(&state,
2564				R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2565				fui(rctx->rasterizer->offset_scale));
2566		r600_pipe_state_add_reg(&state,
2567				R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2568				fui(offset_units));
2569		r600_pipe_state_add_reg(&state,
2570				R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2571				offset_db_fmt_cntl);
2572		r600_context_pipe_state_set(rctx, &state);
2573	}
2574}
2575
2576void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2577{
2578	struct r600_context *rctx = (struct r600_context *)ctx;
2579	struct r600_pipe_state *rstate = &shader->rstate;
2580	struct r600_shader *rshader = &shader->shader;
2581	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2582	int pos_index = -1, face_index = -1;
2583	int ninterp = 0;
2584	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2585	unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2586	unsigned z_export = 0, stencil_export = 0;
2587
2588	rstate->nregs = 0;
2589
2590	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2591	for (i = 0; i < rshader->ninput; i++) {
2592		/* evergreen NUM_INTERP only contains values interpolated into the LDS,
2593		   POSITION goes via GPRs from the SC so isn't counted */
2594		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2595			pos_index = i;
2596		else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2597			face_index = i;
2598		else {
2599			ninterp++;
2600			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2601				have_linear = TRUE;
2602			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2603				have_perspective = TRUE;
2604			if (rshader->input[i].centroid)
2605				have_centroid = TRUE;
2606		}
2607
2608		sid = rshader->input[i].spi_sid;
2609
2610		if (sid) {
2611
2612			tmp = S_028644_SEMANTIC(sid);
2613
2614			if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2615				rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2616				(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2617					rctx->rasterizer && rctx->rasterizer->flatshade)) {
2618				tmp |= S_028644_FLAT_SHADE(1);
2619			}
2620
2621			if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2622					(rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2623				tmp |= S_028644_PT_SPRITE_TEX(1);
2624			}
2625
2626			r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2627					tmp);
2628
2629			idx++;
2630		}
2631	}
2632
2633	for (i = 0; i < rshader->noutput; i++) {
2634		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2635			z_export = 1;
2636		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2637			stencil_export = 1;
2638	}
2639	if (rshader->uses_kill)
2640		db_shader_control |= S_02880C_KILL_ENABLE(1);
2641
2642	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2643	db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2644
2645	exports_ps = 0;
2646	for (i = 0; i < rshader->noutput; i++) {
2647		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2648		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2649			exports_ps |= 1;
2650	}
2651
2652	num_cout = rshader->nr_ps_color_exports;
2653
2654	exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2655	if (!exports_ps) {
2656		/* always at least export 1 component per pixel */
2657		exports_ps = 2;
2658	}
2659	shader->nr_ps_color_outputs = num_cout;
2660	if (ninterp == 0) {
2661		ninterp = 1;
2662		have_perspective = TRUE;
2663	}
2664
2665	if (!have_perspective && !have_linear)
2666		have_perspective = TRUE;
2667
2668	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2669		              S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2670		              S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2671	spi_input_z = 0;
2672	if (pos_index != -1) {
2673		spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
2674			S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2675			S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2676		spi_input_z |= 1;
2677	}
2678
2679	spi_ps_in_control_1 = 0;
2680	if (face_index != -1) {
2681		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2682			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2683	}
2684
2685	spi_baryc_cntl = 0;
2686	if (have_perspective)
2687		spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2688				  S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2689	if (have_linear)
2690		spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2691				  S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2692
2693	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2694				spi_ps_in_control_0);
2695	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2696				spi_ps_in_control_1);
2697	r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2698				0);
2699	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2700	r600_pipe_state_add_reg(rstate,
2701				R_0286E0_SPI_BARYC_CNTL,
2702				spi_baryc_cntl);
2703
2704	r600_pipe_state_add_reg_bo(rstate,
2705				R_028840_SQ_PGM_START_PS,
2706				r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2707				shader->bo, RADEON_USAGE_READ);
2708	r600_pipe_state_add_reg(rstate,
2709				R_028844_SQ_PGM_RESOURCES_PS,
2710				S_028844_NUM_GPRS(rshader->bc.ngpr) |
2711				S_028844_PRIME_CACHE_ON_DRAW(1) |
2712				S_028844_STACK_SIZE(rshader->bc.nstack));
2713	r600_pipe_state_add_reg(rstate,
2714				R_02884C_SQ_PGM_EXPORTS_PS,
2715				exports_ps);
2716
2717	shader->db_shader_control = db_shader_control;
2718	shader->ps_depth_export = z_export | stencil_export;
2719
2720	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2721	if (rctx->rasterizer)
2722		shader->flatshade = rctx->rasterizer->flatshade;
2723}
2724
2725void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2726{
2727	struct r600_context *rctx = (struct r600_context *)ctx;
2728	struct r600_pipe_state *rstate = &shader->rstate;
2729	struct r600_shader *rshader = &shader->shader;
2730	unsigned spi_vs_out_id[10] = {};
2731	unsigned i, tmp, nparams = 0;
2732
2733	/* clear previous register */
2734	rstate->nregs = 0;
2735
2736	for (i = 0; i < rshader->noutput; i++) {
2737		if (rshader->output[i].spi_sid) {
2738			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2739			spi_vs_out_id[nparams / 4] |= tmp;
2740			nparams++;
2741		}
2742	}
2743
2744	for (i = 0; i < 10; i++) {
2745		r600_pipe_state_add_reg(rstate,
2746					R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2747					spi_vs_out_id[i]);
2748	}
2749
2750	/* Certain attributes (position, psize, etc.) don't count as params.
2751	 * VS is required to export at least one param and r600_shader_from_tgsi()
2752	 * takes care of adding a dummy export.
2753	 */
2754	if (nparams < 1)
2755		nparams = 1;
2756
2757	r600_pipe_state_add_reg(rstate,
2758			R_0286C4_SPI_VS_OUT_CONFIG,
2759			S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2760	r600_pipe_state_add_reg(rstate,
2761			R_028860_SQ_PGM_RESOURCES_VS,
2762			S_028860_NUM_GPRS(rshader->bc.ngpr) |
2763			S_028860_STACK_SIZE(rshader->bc.nstack));
2764	r600_pipe_state_add_reg_bo(rstate,
2765			R_02885C_SQ_PGM_START_VS,
2766			r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2767			shader->bo, RADEON_USAGE_READ);
2768
2769	shader->pa_cl_vs_out_cntl =
2770		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2771		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2772		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2773		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2774}
2775
2776void evergreen_fetch_shader(struct pipe_context *ctx,
2777			    struct r600_vertex_element *ve)
2778{
2779	struct r600_context *rctx = (struct r600_context *)ctx;
2780	struct r600_pipe_state *rstate = &ve->rstate;
2781	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2782	rstate->nregs = 0;
2783	r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
2784				r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2785				ve->fetch_shader, RADEON_USAGE_READ);
2786}
2787
2788void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2789{
2790	struct pipe_depth_stencil_alpha_state dsa = {{0}};
2791
2792	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2793}
2794
2795void evergreen_update_dual_export_state(struct r600_context * rctx)
2796{
2797	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2798			!rctx->ps_shader->current->ps_depth_export;
2799
2800	unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
2801			V_02880C_EXPORT_DB_FULL;
2802
2803	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2804			S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
2805			S_02880C_DB_SOURCE_FORMAT(db_source_format);
2806
2807	if (db_shader_control != rctx->db_shader_control) {
2808		struct r600_pipe_state rstate;
2809
2810		rctx->db_shader_control = db_shader_control;
2811
2812		rstate.nregs = 0;
2813		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2814		r600_context_pipe_state_set(rctx, &rstate);
2815	}
2816}
2817