evergreen_state.c revision d04ab396a54d29948363c3353efa5aaa888076a3
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24/* TODO: 25 * - fix mask for depth control & cull for query 26 */ 27#include <stdio.h> 28#include <errno.h> 29#include <pipe/p_defines.h> 30#include <pipe/p_state.h> 31#include <pipe/p_context.h> 32#include <tgsi/tgsi_scan.h> 33#include <tgsi/tgsi_parse.h> 34#include <tgsi/tgsi_util.h> 35#include <util/u_blitter.h> 36#include <util/u_double_list.h> 37#include <util/u_transfer.h> 38#include <util/u_surface.h> 39#include <util/u_pack_color.h> 40#include <util/u_memory.h> 41#include <util/u_inlines.h> 42#include <util/u_framebuffer.h> 43#include <pipebuffer/pb_buffer.h> 44#include "r600.h" 45#include "evergreend.h" 46#include "r600_resource.h" 47#include "r600_shader.h" 48#include "r600_pipe.h" 49#include "eg_state_inlines.h" 50 51static void evergreen_set_blend_color(struct pipe_context *ctx, 52 const struct pipe_blend_color *state) 53{ 54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 56 57 if (rstate == NULL) 58 return; 59 60 rstate->id = R600_PIPE_STATE_BLEND_COLOR; 61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL); 62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL); 63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL); 64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL); 65 66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]); 67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate; 68 r600_context_pipe_state_set(&rctx->ctx, rstate); 69} 70 71static void *evergreen_create_blend_state(struct pipe_context *ctx, 72 const struct pipe_blend_state *state) 73{ 74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); 75 struct r600_pipe_state *rstate; 76 u32 color_control, target_mask; 77 /* FIXME there is more then 8 framebuffer */ 78 unsigned blend_cntl[8]; 79 80 if (blend == NULL) { 81 return NULL; 82 } 83 rstate = &blend->rstate; 84 85 rstate->id = R600_PIPE_STATE_BLEND; 86 87 target_mask = 0; 88 color_control = S_028808_MODE(1); 89 if (state->logicop_enable) { 90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 91 } else { 92 color_control |= (0xcc << 16); 93 } 94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 95 if (state->independent_blend_enable) { 96 for (int i = 0; i < 8; i++) { 97 target_mask |= (state->rt[i].colormask << (4 * i)); 98 } 99 } else { 100 for (int i = 0; i < 8; i++) { 101 target_mask |= (state->rt[0].colormask << (4 * i)); 102 } 103 } 104 blend->cb_target_mask = target_mask; 105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL, 106 color_control, 0xFFFFFFFD, NULL); 107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL); 108 109 for (int i = 0; i < 8; i++) { 110 unsigned eqRGB = state->rt[i].rgb_func; 111 unsigned srcRGB = state->rt[i].rgb_src_factor; 112 unsigned dstRGB = state->rt[i].rgb_dst_factor; 113 unsigned eqA = state->rt[i].alpha_func; 114 unsigned srcA = state->rt[i].alpha_src_factor; 115 unsigned dstA = state->rt[i].alpha_dst_factor; 116 117 blend_cntl[i] = 0; 118 if (!state->rt[i].blend_enable) 119 continue; 120 121 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1); 122 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 123 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 124 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 125 126 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 127 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1); 128 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 129 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 130 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 131 } 132 } 133 for (int i = 0; i < 8; i++) { 134 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL); 135 } 136 137 return rstate; 138} 139 140static void *evergreen_create_dsa_state(struct pipe_context *ctx, 141 const struct pipe_depth_stencil_alpha_state *state) 142{ 143 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 144 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control; 145 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control; 146 147 if (rstate == NULL) { 148 return NULL; 149 } 150 151 rstate->id = R600_PIPE_STATE_DSA; 152 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */ 153 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 154 stencil_ref_mask = 0; 155 stencil_ref_mask_bf = 0; 156 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 157 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 158 S_028800_ZFUNC(state->depth.func); 159 160 /* stencil */ 161 if (state->stencil[0].enabled) { 162 db_depth_control |= S_028800_STENCIL_ENABLE(1); 163 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)); 164 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 165 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 166 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 167 168 169 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) | 170 S_028430_STENCILWRITEMASK(state->stencil[0].writemask); 171 if (state->stencil[1].enabled) { 172 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 173 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)); 174 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 175 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 176 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 177 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) | 178 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask); 179 } 180 } 181 182 /* alpha */ 183 alpha_test_control = 0; 184 alpha_ref = 0; 185 if (state->alpha.enabled) { 186 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 187 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 188 alpha_ref = fui(state->alpha.ref_value); 189 } 190 191 /* misc */ 192 db_render_control = 0; 193 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) | 194 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 195 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); 196 /* TODO db_render_override depends on query */ 197 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL); 198 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL); 199 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL); 200 r600_pipe_state_add_reg(rstate, 201 R_028430_DB_STENCILREFMASK, stencil_ref_mask, 202 0xFFFFFFFF & C_028430_STENCILREF, NULL); 203 r600_pipe_state_add_reg(rstate, 204 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf, 205 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL); 206 r600_pipe_state_add_reg(rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL); 207 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 208 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL); 209 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE, 210 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by 211 * evergreen_pipe_shader_ps().*/ 212 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL); 213 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL); 214 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL); 215 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL); 216 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL); 217 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL); 218 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL); 219 220 return rstate; 221} 222 223static void *evergreen_create_rs_state(struct pipe_context *ctx, 224 const struct pipe_rasterizer_state *state) 225{ 226 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); 227 struct r600_pipe_state *rstate; 228 unsigned tmp; 229 unsigned prov_vtx = 1, polygon_dual_mode; 230 unsigned clip_rule; 231 232 if (rs == NULL) { 233 return NULL; 234 } 235 236 rstate = &rs->rstate; 237 rs->flatshade = state->flatshade; 238 rs->sprite_coord_enable = state->sprite_coord_enable; 239 240 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 241 242 /* offset */ 243 rs->offset_units = state->offset_units; 244 rs->offset_scale = state->offset_scale * 12.0f; 245 246 rstate->id = R600_PIPE_STATE_RASTERIZER; 247 if (state->flatshade_first) 248 prov_vtx = 0; 249 tmp = S_0286D4_FLAT_SHADE_ENA(1); 250 if (state->sprite_coord_enable) { 251 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 252 S_0286D4_PNT_SPRITE_OVRD_X(2) | 253 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 254 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 255 S_0286D4_PNT_SPRITE_OVRD_W(1); 256 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 257 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 258 } 259 } 260 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL); 261 262 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 263 state->fill_back != PIPE_POLYGON_MODE_FILL); 264 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL, 265 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 266 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 267 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 268 S_028814_FACE(!state->front_ccw) | 269 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 270 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 271 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 272 S_028814_POLY_MODE(polygon_dual_mode) | 273 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 274 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL); 275 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL, 276 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | 277 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL); 278 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 279 /* point size 12.4 fixed point */ 280 tmp = (unsigned)(state->point_size * 8.0); 281 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL); 282 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL); 283 284 tmp = (unsigned)state->line_width * 8; 285 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL); 286 287 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL); 288 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 289 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 290 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 291 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 292 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL); 293 294 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 295 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules), 296 0xFFFFFFFF, NULL); 297 298 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL); 299 return rstate; 300} 301 302static void *evergreen_create_sampler_state(struct pipe_context *ctx, 303 const struct pipe_sampler_state *state) 304{ 305 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 306 union util_color uc; 307 uint32_t coord_trunc = 0; 308 309 if (rstate == NULL) { 310 return NULL; 311 } 312 313 if ((state->mag_img_filter == PIPE_TEX_FILTER_NEAREST) || 314 (state->min_img_filter == PIPE_TEX_FILTER_NEAREST)) 315 coord_trunc = 1; 316 317 rstate->id = R600_PIPE_STATE_SAMPLER; 318 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 319 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 320 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 321 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 322 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 323 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) | 324 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) | 325 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 326 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 327 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL); 328 /* FIXME LOD it depends on texture base level ... */ 329 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 330 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 331 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)), 332 0xFFFFFFFF, NULL); 333 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 334 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 335 S_03C008_MC_COORD_TRUNCATE(coord_trunc) | 336 S_03C008_TYPE(1), 337 0xFFFFFFFF, NULL); 338 339 if (uc.ui) { 340 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL); 341 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL); 342 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL); 343 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL); 344 } 345 return rstate; 346} 347 348static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx, 349 struct pipe_resource *texture, 350 const struct pipe_sampler_view *state) 351{ 352 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view); 353 struct r600_pipe_state *rstate; 354 const struct util_format_description *desc; 355 struct r600_resource_texture *tmp; 356 struct r600_resource *rbuffer; 357 unsigned format; 358 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 359 unsigned char swizzle[4], array_mode = 0, tile_type = 0; 360 struct r600_bo *bo[2]; 361 362 if (resource == NULL) 363 return NULL; 364 rstate = &resource->state; 365 366 /* initialize base object */ 367 resource->base = *state; 368 resource->base.texture = NULL; 369 pipe_reference(NULL, &texture->reference); 370 resource->base.texture = texture; 371 resource->base.reference.count = 1; 372 resource->base.context = ctx; 373 374 swizzle[0] = state->swizzle_r; 375 swizzle[1] = state->swizzle_g; 376 swizzle[2] = state->swizzle_b; 377 swizzle[3] = state->swizzle_a; 378 format = r600_translate_texformat(ctx->screen, state->format, 379 swizzle, 380 &word4, &yuv_format); 381 if (format == ~0) { 382 format = 0; 383 } 384 desc = util_format_description(state->format); 385 if (desc == NULL) { 386 R600_ERR("unknow format %d\n", state->format); 387 } 388 tmp = (struct r600_resource_texture *)texture; 389 if (tmp->depth && !tmp->is_flushing_texture) { 390 r600_texture_depth_flush(ctx, texture, TRUE); 391 tmp = tmp->flushed_depth_texture; 392 } 393 394 if (tmp->force_int_type) { 395 word4 &= C_030010_NUM_FORMAT_ALL; 396 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT); 397 } 398 399 rbuffer = &tmp->resource; 400 bo[0] = rbuffer->bo; 401 bo[1] = rbuffer->bo; 402 403 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8); 404 array_mode = tmp->array_mode[0]; 405 tile_type = tmp->tile_type; 406 407 /* FIXME properly handle first level != 0 */ 408 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, 409 S_030000_DIM(r600_tex_dim(texture->target)) | 410 S_030000_PITCH((pitch / 8) - 1) | 411 S_030000_NON_DISP_TILING_ORDER(tile_type) | 412 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL); 413 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, 414 S_030004_TEX_HEIGHT(texture->height0 - 1) | 415 S_030004_TEX_DEPTH(texture->depth0 - 1) | 416 S_030004_ARRAY_MODE(array_mode), 417 0xFFFFFFFF, NULL); 418 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, 419 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]); 420 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, 421 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]); 422 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 423 word4 | 424 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_NO_ZERO) | 425 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL); 426 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 427 S_030014_LAST_LEVEL(state->u.tex.last_level) | 428 S_030014_BASE_ARRAY(0) | 429 S_030014_LAST_ARRAY(0), 0xffffffff, NULL); 430 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL); 431 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 432 S_03001C_DATA_FORMAT(format) | 433 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL); 434 435 return &resource->base; 436} 437 438static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count, 439 struct pipe_sampler_view **views) 440{ 441 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 442 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views; 443 444 for (int i = 0; i < count; i++) { 445 if (resource[i]) { 446 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, 447 i + R600_MAX_CONST_BUFFERS); 448 } 449 } 450} 451 452static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count, 453 struct pipe_sampler_view **views) 454{ 455 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 456 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views; 457 int i; 458 459 for (i = 0; i < count; i++) { 460 if (&rctx->ps_samplers.views[i]->base != views[i]) { 461 if (resource[i]) 462 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, 463 i + R600_MAX_CONST_BUFFERS); 464 else 465 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, 466 i + R600_MAX_CONST_BUFFERS); 467 468 pipe_sampler_view_reference( 469 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i], 470 views[i]); 471 } 472 } 473 for (i = count; i < NUM_TEX_UNITS; i++) { 474 if (rctx->ps_samplers.views[i]) { 475 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, 476 i + R600_MAX_CONST_BUFFERS); 477 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL); 478 } 479 } 480 rctx->ps_samplers.n_views = count; 481} 482 483static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) 484{ 485 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 486 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states; 487 488 489 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count); 490 rctx->ps_samplers.n_samplers = count; 491 492 for (int i = 0; i < count; i++) { 493 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i); 494 } 495} 496 497static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states) 498{ 499 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 500 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states; 501 502 for (int i = 0; i < count; i++) { 503 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i); 504 } 505} 506 507static void evergreen_set_clip_state(struct pipe_context *ctx, 508 const struct pipe_clip_state *state) 509{ 510 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 511 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 512 513 if (rstate == NULL) 514 return; 515 516 rctx->clip = *state; 517 rstate->id = R600_PIPE_STATE_CLIP; 518 for (int i = 0; i < state->nr; i++) { 519 r600_pipe_state_add_reg(rstate, 520 R_0285BC_PA_CL_UCP0_X + i * 16, 521 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL); 522 r600_pipe_state_add_reg(rstate, 523 R_0285C0_PA_CL_UCP0_Y + i * 16, 524 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL); 525 r600_pipe_state_add_reg(rstate, 526 R_0285C4_PA_CL_UCP0_Z + i * 16, 527 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL); 528 r600_pipe_state_add_reg(rstate, 529 R_0285C8_PA_CL_UCP0_W + i * 16, 530 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL); 531 } 532 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 533 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) | 534 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) | 535 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL); 536 537 free(rctx->states[R600_PIPE_STATE_CLIP]); 538 rctx->states[R600_PIPE_STATE_CLIP] = rstate; 539 r600_context_pipe_state_set(&rctx->ctx, rstate); 540} 541 542static void evergreen_set_polygon_stipple(struct pipe_context *ctx, 543 const struct pipe_poly_stipple *state) 544{ 545} 546 547static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 548{ 549} 550 551static void evergreen_set_scissor_state(struct pipe_context *ctx, 552 const struct pipe_scissor_state *state) 553{ 554 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 555 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 556 u32 tl, br; 557 558 if (rstate == NULL) 559 return; 560 561 rstate->id = R600_PIPE_STATE_SCISSOR; 562 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny); 563 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 564 r600_pipe_state_add_reg(rstate, 565 R_028210_PA_SC_CLIPRECT_0_TL, tl, 566 0xFFFFFFFF, NULL); 567 r600_pipe_state_add_reg(rstate, 568 R_028214_PA_SC_CLIPRECT_0_BR, br, 569 0xFFFFFFFF, NULL); 570 r600_pipe_state_add_reg(rstate, 571 R_028218_PA_SC_CLIPRECT_1_TL, tl, 572 0xFFFFFFFF, NULL); 573 r600_pipe_state_add_reg(rstate, 574 R_02821C_PA_SC_CLIPRECT_1_BR, br, 575 0xFFFFFFFF, NULL); 576 r600_pipe_state_add_reg(rstate, 577 R_028220_PA_SC_CLIPRECT_2_TL, tl, 578 0xFFFFFFFF, NULL); 579 r600_pipe_state_add_reg(rstate, 580 R_028224_PA_SC_CLIPRECT_2_BR, br, 581 0xFFFFFFFF, NULL); 582 r600_pipe_state_add_reg(rstate, 583 R_028228_PA_SC_CLIPRECT_3_TL, tl, 584 0xFFFFFFFF, NULL); 585 r600_pipe_state_add_reg(rstate, 586 R_02822C_PA_SC_CLIPRECT_3_BR, br, 587 0xFFFFFFFF, NULL); 588 589 free(rctx->states[R600_PIPE_STATE_SCISSOR]); 590 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate; 591 r600_context_pipe_state_set(&rctx->ctx, rstate); 592} 593 594static void evergreen_set_stencil_ref(struct pipe_context *ctx, 595 const struct pipe_stencil_ref *state) 596{ 597 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 598 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 599 u32 tmp; 600 601 if (rstate == NULL) 602 return; 603 604 rctx->stencil_ref = *state; 605 rstate->id = R600_PIPE_STATE_STENCIL_REF; 606 tmp = S_028430_STENCILREF(state->ref_value[0]); 607 r600_pipe_state_add_reg(rstate, 608 R_028430_DB_STENCILREFMASK, tmp, 609 ~C_028430_STENCILREF, NULL); 610 tmp = S_028434_STENCILREF_BF(state->ref_value[1]); 611 r600_pipe_state_add_reg(rstate, 612 R_028434_DB_STENCILREFMASK_BF, tmp, 613 ~C_028434_STENCILREF_BF, NULL); 614 615 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]); 616 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate; 617 r600_context_pipe_state_set(&rctx->ctx, rstate); 618} 619 620static void evergreen_set_viewport_state(struct pipe_context *ctx, 621 const struct pipe_viewport_state *state) 622{ 623 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 624 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 625 626 if (rstate == NULL) 627 return; 628 629 rctx->viewport = *state; 630 rstate->id = R600_PIPE_STATE_VIEWPORT; 631 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL); 632 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL); 633 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL); 634 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL); 635 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL); 636 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL); 637 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL); 638 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL); 639 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL); 640 641 free(rctx->states[R600_PIPE_STATE_VIEWPORT]); 642 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate; 643 r600_context_pipe_state_set(&rctx->ctx, rstate); 644} 645 646static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate, 647 const struct pipe_framebuffer_state *state, int cb) 648{ 649 struct r600_resource_texture *rtex; 650 struct r600_resource *rbuffer; 651 struct r600_surface *surf; 652 unsigned level = state->cbufs[cb]->u.tex.level; 653 unsigned pitch, slice; 654 unsigned color_info; 655 unsigned format, swap, ntype; 656 unsigned offset; 657 unsigned tile_type; 658 const struct util_format_description *desc; 659 struct r600_bo *bo[3]; 660 int i; 661 662 surf = (struct r600_surface *)state->cbufs[cb]; 663 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; 664 665 if (rtex->depth && !rtex->is_flushing_texture) { 666 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE); 667 rtex = rtex->flushed_depth_texture; 668 } 669 670 rbuffer = &rtex->resource; 671 bo[0] = rbuffer->bo; 672 bo[1] = rbuffer->bo; 673 bo[2] = rbuffer->bo; 674 675 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 676 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture, 677 level, state->cbufs[cb]->u.tex.first_layer); 678 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 679 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1; 680 ntype = 0; 681 desc = util_format_description(surf->base.format); 682 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 683 ntype = V_028C70_NUMBER_SRGB; 684 685 format = r600_translate_colorformat(surf->base.format); 686 swap = r600_translate_colorswap(surf->base.format); 687 688 /* disable when gallium grows int textures */ 689 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type) 690 ntype = 4; 691 692 color_info = S_028C70_FORMAT(format) | 693 S_028C70_COMP_SWAP(swap) | 694 S_028C70_ARRAY_MODE(rtex->array_mode[level]) | 695 S_028C70_BLEND_CLAMP(1) | 696 S_028C70_NUMBER_TYPE(ntype); 697 698 for (i = 0; i < 4; i++) { 699 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 700 break; 701 } 702 } 703 704 /* we can only set the export size if any thing is snorm/unorm component is > 11 bits, 705 if we aren't a float, sint or uint */ 706 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 707 desc->channel[i].size < 12 && desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 708 ntype != 4 && ntype != 5) 709 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC); 710 711 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) { 712 tile_type = rtex->tile_type; 713 } else /* workaround for linear buffers */ 714 tile_type = 1; 715 716 /* FIXME handle enabling of CB beyond BASE8 which has different offset */ 717 r600_pipe_state_add_reg(rstate, 718 R_028C60_CB_COLOR0_BASE + cb * 0x3C, 719 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]); 720 r600_pipe_state_add_reg(rstate, 721 R_028C78_CB_COLOR0_DIM + cb * 0x3C, 722 0x0, 0xFFFFFFFF, NULL); 723 r600_pipe_state_add_reg(rstate, 724 R_028C70_CB_COLOR0_INFO + cb * 0x3C, 725 color_info, 0xFFFFFFFF, bo[0]); 726 r600_pipe_state_add_reg(rstate, 727 R_028C64_CB_COLOR0_PITCH + cb * 0x3C, 728 S_028C64_PITCH_TILE_MAX(pitch), 729 0xFFFFFFFF, NULL); 730 r600_pipe_state_add_reg(rstate, 731 R_028C68_CB_COLOR0_SLICE + cb * 0x3C, 732 S_028C68_SLICE_TILE_MAX(slice), 733 0xFFFFFFFF, NULL); 734 r600_pipe_state_add_reg(rstate, 735 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 736 0x00000000, 0xFFFFFFFF, NULL); 737 r600_pipe_state_add_reg(rstate, 738 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, 739 S_028C74_NON_DISP_TILING_ORDER(tile_type), 740 0xFFFFFFFF, bo[0]); 741} 742 743static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate, 744 const struct pipe_framebuffer_state *state) 745{ 746 struct r600_resource_texture *rtex; 747 struct r600_resource *rbuffer; 748 struct r600_surface *surf; 749 unsigned level; 750 unsigned pitch, slice, format, stencil_format; 751 unsigned offset; 752 753 if (state->zsbuf == NULL) 754 return; 755 756 level = state->zsbuf->u.tex.level; 757 758 surf = (struct r600_surface *)state->zsbuf; 759 rtex = (struct r600_resource_texture*)state->zsbuf->texture; 760 761 rbuffer = &rtex->resource; 762 763 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 764 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture, 765 level, state->zsbuf->u.tex.first_layer); 766 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 767 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1; 768 format = r600_translate_dbformat(state->zsbuf->texture->format); 769 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format); 770 771 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE, 772 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); 773 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE, 774 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); 775 776 if (stencil_format) { 777 uint32_t stencil_offset; 778 779 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255; 780 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE, 781 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); 782 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE, 783 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); 784 } 785 786 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL); 787 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, 788 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo); 789 790 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 791 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format), 792 0xFFFFFFFF, rbuffer->bo); 793 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, 794 S_028058_PITCH_TILE_MAX(pitch), 795 0xFFFFFFFF, NULL); 796 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, 797 S_02805C_SLICE_TILE_MAX(slice), 798 0xFFFFFFFF, NULL); 799} 800 801static void evergreen_set_framebuffer_state(struct pipe_context *ctx, 802 const struct pipe_framebuffer_state *state) 803{ 804 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 805 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 806 u32 shader_mask, tl, br, target_mask; 807 808 if (rstate == NULL) 809 return; 810 811 /* unreference old buffer and reference new one */ 812 rstate->id = R600_PIPE_STATE_FRAMEBUFFER; 813 814 util_copy_framebuffer_state(&rctx->framebuffer, state); 815 816 /* build states */ 817 for (int i = 0; i < state->nr_cbufs; i++) { 818 evergreen_cb(rctx, rstate, state, i); 819 } 820 if (state->zsbuf) { 821 evergreen_db(rctx, rstate, state); 822 } 823 824 target_mask = 0x00000000; 825 target_mask = 0xFFFFFFFF; 826 shader_mask = 0; 827 for (int i = 0; i < state->nr_cbufs; i++) { 828 target_mask ^= 0xf << (i * 4); 829 shader_mask |= 0xf << (i * 4); 830 } 831 tl = S_028240_TL_X(0) | S_028240_TL_Y(0); 832 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height); 833 834 r600_pipe_state_add_reg(rstate, 835 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl, 836 0xFFFFFFFF, NULL); 837 r600_pipe_state_add_reg(rstate, 838 R_028244_PA_SC_GENERIC_SCISSOR_BR, br, 839 0xFFFFFFFF, NULL); 840 r600_pipe_state_add_reg(rstate, 841 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, 842 0xFFFFFFFF, NULL); 843 r600_pipe_state_add_reg(rstate, 844 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, 845 0xFFFFFFFF, NULL); 846 r600_pipe_state_add_reg(rstate, 847 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl, 848 0xFFFFFFFF, NULL); 849 r600_pipe_state_add_reg(rstate, 850 R_028034_PA_SC_SCREEN_SCISSOR_BR, br, 851 0xFFFFFFFF, NULL); 852 r600_pipe_state_add_reg(rstate, 853 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl, 854 0xFFFFFFFF, NULL); 855 r600_pipe_state_add_reg(rstate, 856 R_028208_PA_SC_WINDOW_SCISSOR_BR, br, 857 0xFFFFFFFF, NULL); 858 r600_pipe_state_add_reg(rstate, 859 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000, 860 0xFFFFFFFF, NULL); 861 r600_pipe_state_add_reg(rstate, 862 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA, 863 0xFFFFFFFF, NULL); 864 865 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK, 866 0x00000000, target_mask, NULL); 867 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK, 868 shader_mask, 0xFFFFFFFF, NULL); 869 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 870 0x00000000, 0xFFFFFFFF, NULL); 871 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 872 0x00000000, 0xFFFFFFFF, NULL); 873 874 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); 875 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; 876 r600_context_pipe_state_set(&rctx->ctx, rstate); 877 878 if (state->zsbuf) { 879 evergreen_polygon_offset_update(rctx); 880 } 881} 882 883void evergreen_init_state_functions(struct r600_pipe_context *rctx) 884{ 885 rctx->context.create_blend_state = evergreen_create_blend_state; 886 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state; 887 rctx->context.create_fs_state = r600_create_shader_state; 888 rctx->context.create_rasterizer_state = evergreen_create_rs_state; 889 rctx->context.create_sampler_state = evergreen_create_sampler_state; 890 rctx->context.create_sampler_view = evergreen_create_sampler_view; 891 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 892 rctx->context.create_vs_state = r600_create_shader_state; 893 rctx->context.bind_blend_state = r600_bind_blend_state; 894 rctx->context.bind_depth_stencil_alpha_state = r600_bind_state; 895 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler; 896 rctx->context.bind_fs_state = r600_bind_ps_shader; 897 rctx->context.bind_rasterizer_state = r600_bind_rs_state; 898 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 899 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler; 900 rctx->context.bind_vs_state = r600_bind_vs_shader; 901 rctx->context.delete_blend_state = r600_delete_state; 902 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 903 rctx->context.delete_fs_state = r600_delete_ps_shader; 904 rctx->context.delete_rasterizer_state = r600_delete_rs_state; 905 rctx->context.delete_sampler_state = r600_delete_state; 906 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 907 rctx->context.delete_vs_state = r600_delete_vs_shader; 908 rctx->context.set_blend_color = evergreen_set_blend_color; 909 rctx->context.set_clip_state = evergreen_set_clip_state; 910 rctx->context.set_constant_buffer = r600_set_constant_buffer; 911 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view; 912 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state; 913 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple; 914 rctx->context.set_sample_mask = evergreen_set_sample_mask; 915 rctx->context.set_scissor_state = evergreen_set_scissor_state; 916 rctx->context.set_stencil_ref = evergreen_set_stencil_ref; 917 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 918 rctx->context.set_index_buffer = r600_set_index_buffer; 919 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view; 920 rctx->context.set_viewport_state = evergreen_set_viewport_state; 921 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 922 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer; 923 rctx->context.texture_barrier = r600_texture_barrier; 924} 925 926void evergreen_init_config(struct r600_pipe_context *rctx) 927{ 928 struct r600_pipe_state *rstate = &rctx->config; 929 int ps_prio; 930 int vs_prio; 931 int gs_prio; 932 int es_prio; 933 int hs_prio, cs_prio, ls_prio; 934 int num_ps_gprs; 935 int num_vs_gprs; 936 int num_gs_gprs; 937 int num_es_gprs; 938 int num_hs_gprs; 939 int num_ls_gprs; 940 int num_temp_gprs; 941 int num_ps_threads; 942 int num_vs_threads; 943 int num_gs_threads; 944 int num_es_threads; 945 int num_hs_threads; 946 int num_ls_threads; 947 int num_ps_stack_entries; 948 int num_vs_stack_entries; 949 int num_gs_stack_entries; 950 int num_es_stack_entries; 951 int num_hs_stack_entries; 952 int num_ls_stack_entries; 953 enum radeon_family family; 954 unsigned tmp; 955 956 family = r600_get_family(rctx->radeon); 957 ps_prio = 0; 958 vs_prio = 1; 959 gs_prio = 2; 960 es_prio = 3; 961 hs_prio = 0; 962 ls_prio = 0; 963 cs_prio = 0; 964 965 switch (family) { 966 case CHIP_CEDAR: 967 default: 968 num_ps_gprs = 93; 969 num_vs_gprs = 46; 970 num_temp_gprs = 4; 971 num_gs_gprs = 31; 972 num_es_gprs = 31; 973 num_hs_gprs = 23; 974 num_ls_gprs = 23; 975 num_ps_threads = 96; 976 num_vs_threads = 16; 977 num_gs_threads = 16; 978 num_es_threads = 16; 979 num_hs_threads = 16; 980 num_ls_threads = 16; 981 num_ps_stack_entries = 42; 982 num_vs_stack_entries = 42; 983 num_gs_stack_entries = 42; 984 num_es_stack_entries = 42; 985 num_hs_stack_entries = 42; 986 num_ls_stack_entries = 42; 987 break; 988 case CHIP_REDWOOD: 989 num_ps_gprs = 93; 990 num_vs_gprs = 46; 991 num_temp_gprs = 4; 992 num_gs_gprs = 31; 993 num_es_gprs = 31; 994 num_hs_gprs = 23; 995 num_ls_gprs = 23; 996 num_ps_threads = 128; 997 num_vs_threads = 20; 998 num_gs_threads = 20; 999 num_es_threads = 20; 1000 num_hs_threads = 20; 1001 num_ls_threads = 20; 1002 num_ps_stack_entries = 42; 1003 num_vs_stack_entries = 42; 1004 num_gs_stack_entries = 42; 1005 num_es_stack_entries = 42; 1006 num_hs_stack_entries = 42; 1007 num_ls_stack_entries = 42; 1008 break; 1009 case CHIP_JUNIPER: 1010 num_ps_gprs = 93; 1011 num_vs_gprs = 46; 1012 num_temp_gprs = 4; 1013 num_gs_gprs = 31; 1014 num_es_gprs = 31; 1015 num_hs_gprs = 23; 1016 num_ls_gprs = 23; 1017 num_ps_threads = 128; 1018 num_vs_threads = 20; 1019 num_gs_threads = 20; 1020 num_es_threads = 20; 1021 num_hs_threads = 20; 1022 num_ls_threads = 20; 1023 num_ps_stack_entries = 85; 1024 num_vs_stack_entries = 85; 1025 num_gs_stack_entries = 85; 1026 num_es_stack_entries = 85; 1027 num_hs_stack_entries = 85; 1028 num_ls_stack_entries = 85; 1029 break; 1030 case CHIP_CYPRESS: 1031 case CHIP_HEMLOCK: 1032 num_ps_gprs = 93; 1033 num_vs_gprs = 46; 1034 num_temp_gprs = 4; 1035 num_gs_gprs = 31; 1036 num_es_gprs = 31; 1037 num_hs_gprs = 23; 1038 num_ls_gprs = 23; 1039 num_ps_threads = 128; 1040 num_vs_threads = 20; 1041 num_gs_threads = 20; 1042 num_es_threads = 20; 1043 num_hs_threads = 20; 1044 num_ls_threads = 20; 1045 num_ps_stack_entries = 85; 1046 num_vs_stack_entries = 85; 1047 num_gs_stack_entries = 85; 1048 num_es_stack_entries = 85; 1049 num_hs_stack_entries = 85; 1050 num_ls_stack_entries = 85; 1051 break; 1052 case CHIP_PALM: 1053 num_ps_gprs = 93; 1054 num_vs_gprs = 46; 1055 num_temp_gprs = 4; 1056 num_gs_gprs = 31; 1057 num_es_gprs = 31; 1058 num_hs_gprs = 23; 1059 num_ls_gprs = 23; 1060 num_ps_threads = 96; 1061 num_vs_threads = 16; 1062 num_gs_threads = 16; 1063 num_es_threads = 16; 1064 num_hs_threads = 16; 1065 num_ls_threads = 16; 1066 num_ps_stack_entries = 42; 1067 num_vs_stack_entries = 42; 1068 num_gs_stack_entries = 42; 1069 num_es_stack_entries = 42; 1070 num_hs_stack_entries = 42; 1071 num_ls_stack_entries = 42; 1072 break; 1073 case CHIP_BARTS: 1074 num_ps_gprs = 93; 1075 num_vs_gprs = 46; 1076 num_temp_gprs = 4; 1077 num_gs_gprs = 31; 1078 num_es_gprs = 31; 1079 num_hs_gprs = 23; 1080 num_ls_gprs = 23; 1081 num_ps_threads = 128; 1082 num_vs_threads = 20; 1083 num_gs_threads = 20; 1084 num_es_threads = 20; 1085 num_hs_threads = 20; 1086 num_ls_threads = 20; 1087 num_ps_stack_entries = 85; 1088 num_vs_stack_entries = 85; 1089 num_gs_stack_entries = 85; 1090 num_es_stack_entries = 85; 1091 num_hs_stack_entries = 85; 1092 num_ls_stack_entries = 85; 1093 break; 1094 case CHIP_TURKS: 1095 num_ps_gprs = 93; 1096 num_vs_gprs = 46; 1097 num_temp_gprs = 4; 1098 num_gs_gprs = 31; 1099 num_es_gprs = 31; 1100 num_hs_gprs = 23; 1101 num_ls_gprs = 23; 1102 num_ps_threads = 128; 1103 num_vs_threads = 20; 1104 num_gs_threads = 20; 1105 num_es_threads = 20; 1106 num_hs_threads = 20; 1107 num_ls_threads = 20; 1108 num_ps_stack_entries = 42; 1109 num_vs_stack_entries = 42; 1110 num_gs_stack_entries = 42; 1111 num_es_stack_entries = 42; 1112 num_hs_stack_entries = 42; 1113 num_ls_stack_entries = 42; 1114 break; 1115 case CHIP_CAICOS: 1116 num_ps_gprs = 93; 1117 num_vs_gprs = 46; 1118 num_temp_gprs = 4; 1119 num_gs_gprs = 31; 1120 num_es_gprs = 31; 1121 num_hs_gprs = 23; 1122 num_ls_gprs = 23; 1123 num_ps_threads = 128; 1124 num_vs_threads = 10; 1125 num_gs_threads = 10; 1126 num_es_threads = 10; 1127 num_hs_threads = 10; 1128 num_ls_threads = 10; 1129 num_ps_stack_entries = 42; 1130 num_vs_stack_entries = 42; 1131 num_gs_stack_entries = 42; 1132 num_es_stack_entries = 42; 1133 num_hs_stack_entries = 42; 1134 num_ls_stack_entries = 42; 1135 break; 1136 } 1137 1138 tmp = 0x00000000; 1139 switch (family) { 1140 case CHIP_CEDAR: 1141 case CHIP_PALM: 1142 case CHIP_CAICOS: 1143 break; 1144 default: 1145 tmp |= S_008C00_VC_ENABLE(1); 1146 break; 1147 } 1148 tmp |= S_008C00_EXPORT_SRC_C(1); 1149 tmp |= S_008C00_CS_PRIO(cs_prio); 1150 tmp |= S_008C00_LS_PRIO(ls_prio); 1151 tmp |= S_008C00_HS_PRIO(hs_prio); 1152 tmp |= S_008C00_PS_PRIO(ps_prio); 1153 tmp |= S_008C00_VS_PRIO(vs_prio); 1154 tmp |= S_008C00_GS_PRIO(gs_prio); 1155 tmp |= S_008C00_ES_PRIO(es_prio); 1156 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL); 1157 1158 tmp = 0; 1159 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs); 1160 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs); 1161 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs); 1162 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL); 1163 1164 tmp = 0; 1165 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs); 1166 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); 1167 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL); 1168 1169 tmp = 0; 1170 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs); 1171 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs); 1172 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL); 1173 1174 tmp = 0; 1175 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads); 1176 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads); 1177 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads); 1178 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads); 1179 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL); 1180 1181 tmp = 0; 1182 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads); 1183 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads); 1184 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL); 1185 1186 tmp = 0; 1187 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 1188 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 1189 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL); 1190 1191 tmp = 0; 1192 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 1193 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 1194 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL); 1195 1196 tmp = 0; 1197 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries); 1198 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries); 1199 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL); 1200 1201 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL); 1202 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL); 1203 1204// r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL); 1205 1206// r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL); 1207 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL); 1208 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL); 1209 1210 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1211 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1212 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1213 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1214 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1215 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1216 1217 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1218 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL); 1219 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL); 1220 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL); 1221 1222 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL); 1223 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL); 1224 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL); 1225 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL); 1226 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL); 1227 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL); 1228 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL); 1229 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL); 1230 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL); 1231 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL); 1232 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL); 1233 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL); 1234 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL); 1235 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL); 1236 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL); 1237 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL); 1238 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL); 1239 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL); 1240 1241 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL); 1242 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL); 1243 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL); 1244 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL); 1245 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL); 1246 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL); 1247 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL); 1248 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL); 1249 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL); 1250 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL); 1251 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL); 1252 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL); 1253 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL); 1254 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL); 1255 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL); 1256 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL); 1257 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL); 1258 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL); 1259 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL); 1260 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL); 1261 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL); 1262 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL); 1263 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL); 1264 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL); 1265 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL); 1266 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL); 1267 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL); 1268 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL); 1269 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL); 1270 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL); 1271 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL); 1272 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL); 1273 1274 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL); 1275 1276 r600_context_pipe_state_set(&rctx->ctx, rstate); 1277} 1278 1279void evergreen_polygon_offset_update(struct r600_pipe_context *rctx) 1280{ 1281 struct r600_pipe_state state; 1282 1283 state.id = R600_PIPE_STATE_POLYGON_OFFSET; 1284 state.nregs = 0; 1285 if (rctx->rasterizer && rctx->framebuffer.zsbuf) { 1286 float offset_units = rctx->rasterizer->offset_units; 1287 unsigned offset_db_fmt_cntl = 0, depth; 1288 1289 switch (rctx->framebuffer.zsbuf->texture->format) { 1290 case PIPE_FORMAT_Z24X8_UNORM: 1291 case PIPE_FORMAT_Z24_UNORM_S8_USCALED: 1292 depth = -24; 1293 offset_units *= 2.0f; 1294 break; 1295 case PIPE_FORMAT_Z32_FLOAT: 1296 depth = -23; 1297 offset_units *= 1.0f; 1298 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 1299 break; 1300 case PIPE_FORMAT_Z16_UNORM: 1301 depth = -16; 1302 offset_units *= 4.0f; 1303 break; 1304 default: 1305 return; 1306 } 1307 /* FIXME some of those reg can be computed with cso */ 1308 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 1309 r600_pipe_state_add_reg(&state, 1310 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 1311 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL); 1312 r600_pipe_state_add_reg(&state, 1313 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 1314 fui(offset_units), 0xFFFFFFFF, NULL); 1315 r600_pipe_state_add_reg(&state, 1316 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 1317 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL); 1318 r600_pipe_state_add_reg(&state, 1319 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 1320 fui(offset_units), 0xFFFFFFFF, NULL); 1321 r600_pipe_state_add_reg(&state, 1322 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 1323 offset_db_fmt_cntl, 0xFFFFFFFF, NULL); 1324 r600_context_pipe_state_set(&rctx->ctx, &state); 1325 } 1326} 1327 1328void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader) 1329{ 1330 struct r600_pipe_state *rstate = &shader->rstate; 1331 struct r600_shader *rshader = &shader->shader; 1332 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; 1333 int pos_index = -1, face_index = -1; 1334 int ninterp = 0; 1335 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE; 1336 unsigned spi_baryc_cntl; 1337 1338 rstate->nregs = 0; 1339 1340 db_shader_control = 0; 1341 for (i = 0; i < rshader->ninput; i++) { 1342 /* evergreen NUM_INTERP only contains values interpolated into the LDS, 1343 POSITION goes via GPRs from the SC so isn't counted */ 1344 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) 1345 pos_index = i; 1346 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) 1347 face_index = i; 1348 else { 1349 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR || 1350 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) 1351 ninterp++; 1352 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) 1353 have_linear = TRUE; 1354 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) 1355 have_perspective = TRUE; 1356 if (rshader->input[i].centroid) 1357 have_centroid = TRUE; 1358 } 1359 } 1360 for (i = 0; i < rshader->noutput; i++) { 1361 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) 1362 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1); 1363 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 1364 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1); 1365 } 1366 if (rshader->uses_kill) 1367 db_shader_control |= S_02880C_KILL_ENABLE(1); 1368 1369 exports_ps = 0; 1370 num_cout = 0; 1371 for (i = 0; i < rshader->noutput; i++) { 1372 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || 1373 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 1374 exports_ps |= 1; 1375 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) { 1376 num_cout++; 1377 } 1378 } 1379 exports_ps |= S_02884C_EXPORT_COLORS(num_cout); 1380 if (!exports_ps) { 1381 /* always at least export 1 component per pixel */ 1382 exports_ps = 2; 1383 } 1384 1385 if (ninterp == 0) { 1386 ninterp = 1; 1387 have_perspective = TRUE; 1388 } 1389 1390 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) | 1391 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) | 1392 S_0286CC_LINEAR_GRADIENT_ENA(have_linear); 1393 spi_input_z = 0; 1394 if (pos_index != -1) { 1395 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) | 1396 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) | 1397 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr); 1398 spi_input_z |= 1; 1399 } 1400 1401 spi_ps_in_control_1 = 0; 1402 if (face_index != -1) { 1403 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | 1404 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); 1405 } 1406 1407 spi_baryc_cntl = 0; 1408 if (have_perspective) 1409 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) | 1410 S_0286E0_PERSP_CENTROID_ENA(have_centroid); 1411 if (have_linear) 1412 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) | 1413 S_0286E0_LINEAR_CENTROID_ENA(have_centroid); 1414 1415 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, 1416 spi_ps_in_control_0, 0xFFFFFFFF, NULL); 1417 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, 1418 spi_ps_in_control_1, 0xFFFFFFFF, NULL); 1419 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2, 1420 0, 0xFFFFFFFF, NULL); 1421 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL); 1422 r600_pipe_state_add_reg(rstate, 1423 R_0286E0_SPI_BARYC_CNTL, 1424 spi_baryc_cntl, 1425 0xFFFFFFFF, NULL); 1426 1427 r600_pipe_state_add_reg(rstate, 1428 R_028840_SQ_PGM_START_PS, 1429 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo); 1430 r600_pipe_state_add_reg(rstate, 1431 R_028844_SQ_PGM_RESOURCES_PS, 1432 S_028844_NUM_GPRS(rshader->bc.ngpr) | 1433 S_028844_PRIME_CACHE_ON_DRAW(1) | 1434 S_028844_STACK_SIZE(rshader->bc.nstack), 1435 0xFFFFFFFF, NULL); 1436 r600_pipe_state_add_reg(rstate, 1437 R_028848_SQ_PGM_RESOURCES_2_PS, 1438 0x0, 0xFFFFFFFF, NULL); 1439 r600_pipe_state_add_reg(rstate, 1440 R_02884C_SQ_PGM_EXPORTS_PS, 1441 exports_ps, 0xFFFFFFFF, NULL); 1442 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */ 1443 /* only set some bits here, the other bits are set in the dsa state */ 1444 r600_pipe_state_add_reg(rstate, 1445 R_02880C_DB_SHADER_CONTROL, 1446 db_shader_control, 1447 S_02880C_Z_EXPORT_ENABLE(1) | 1448 S_02880C_STENCIL_EXPORT_ENABLE(1) | 1449 S_02880C_KILL_ENABLE(1), 1450 NULL); 1451 r600_pipe_state_add_reg(rstate, 1452 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF, 1453 0xFFFFFFFF, NULL); 1454} 1455 1456void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader) 1457{ 1458 struct r600_pipe_state *rstate = &shader->rstate; 1459 struct r600_shader *rshader = &shader->shader; 1460 unsigned spi_vs_out_id[10]; 1461 unsigned i, tmp; 1462 1463 /* clear previous register */ 1464 rstate->nregs = 0; 1465 1466 /* so far never got proper semantic id from tgsi */ 1467 for (i = 0; i < 10; i++) { 1468 spi_vs_out_id[i] = 0; 1469 } 1470 for (i = 0; i < 32; i++) { 1471 tmp = i << ((i & 3) * 8); 1472 spi_vs_out_id[i / 4] |= tmp; 1473 } 1474 for (i = 0; i < 10; i++) { 1475 r600_pipe_state_add_reg(rstate, 1476 R_02861C_SPI_VS_OUT_ID_0 + i * 4, 1477 spi_vs_out_id[i], 0xFFFFFFFF, NULL); 1478 } 1479 1480 r600_pipe_state_add_reg(rstate, 1481 R_0286C4_SPI_VS_OUT_CONFIG, 1482 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2), 1483 0xFFFFFFFF, NULL); 1484 r600_pipe_state_add_reg(rstate, 1485 R_028860_SQ_PGM_RESOURCES_VS, 1486 S_028860_NUM_GPRS(rshader->bc.ngpr) | 1487 S_028860_STACK_SIZE(rshader->bc.nstack), 1488 0xFFFFFFFF, NULL); 1489 r600_pipe_state_add_reg(rstate, 1490 R_028864_SQ_PGM_RESOURCES_2_VS, 1491 0x0, 0xFFFFFFFF, NULL); 1492 r600_pipe_state_add_reg(rstate, 1493 R_02885C_SQ_PGM_START_VS, 1494 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo); 1495 1496 r600_pipe_state_add_reg(rstate, 1497 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF, 1498 0xFFFFFFFF, NULL); 1499} 1500 1501void evergreen_fetch_shader(struct r600_vertex_element *ve) 1502{ 1503 struct r600_pipe_state *rstate = &ve->rstate; 1504 rstate->id = R600_PIPE_STATE_FETCH_SHADER; 1505 rstate->nregs = 0; 1506 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS, 1507 0x00000000, 0xFFFFFFFF, NULL); 1508 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS, 1509 (r600_bo_offset(ve->fetch_shader)) >> 8, 1510 0xFFFFFFFF, ve->fetch_shader); 1511} 1512 1513void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx) 1514{ 1515 struct pipe_depth_stencil_alpha_state dsa; 1516 struct r600_pipe_state *rstate; 1517 1518 memset(&dsa, 0, sizeof(dsa)); 1519 1520 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 1521 r600_pipe_state_add_reg(rstate, 1522 R_02880C_DB_SHADER_CONTROL, 1523 0x0, 1524 S_02880C_DUAL_EXPORT_ENABLE(1), NULL); 1525 r600_pipe_state_add_reg(rstate, 1526 R_028000_DB_RENDER_CONTROL, 1527 S_028000_DEPTH_COPY_ENABLE(1) | 1528 S_028000_STENCIL_COPY_ENABLE(1) | 1529 S_028000_COPY_CENTROID(1), 1530 S_028000_DEPTH_COPY_ENABLE(1) | 1531 S_028000_STENCIL_COPY_ENABLE(1) | 1532 S_028000_COPY_CENTROID(1), NULL); 1533 return rstate; 1534} 1535 1536void evergreen_pipe_set_buffer_resource(struct r600_pipe_context *rctx, 1537 struct r600_pipe_state *rstate, 1538 struct r600_resource *rbuffer, 1539 unsigned offset, unsigned stride) 1540{ 1541 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, 1542 offset, 0xFFFFFFFF, rbuffer->bo); 1543 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, 1544 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL); 1545 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, 1546 S_030008_STRIDE(stride), 1547 0xFFFFFFFF, NULL); 1548 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, 1549 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) | 1550 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) | 1551 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) | 1552 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W), 1553 0xFFFFFFFF, NULL); 1554 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 1555 0x00000000, 0xFFFFFFFF, NULL); 1556 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 1557 0x00000000, 0xFFFFFFFF, NULL); 1558 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 1559 0x00000000, 0xFFFFFFFF, NULL); 1560 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 1561 0xC0000000, 0xFFFFFFFF, NULL); 1562} 1563