evergreen_state.c revision d3b013049126fb44d65a0a67001b04acbe778613 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "evergreend.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31#include "evergreen_compute.h"
32
33static uint32_t eg_num_banks(uint32_t nbanks)
34{
35	switch (nbanks) {
36	case 2:
37		return 0;
38	case 4:
39		return 1;
40	case 8:
41	default:
42		return 2;
43	case 16:
44		return 3;
45	}
46}
47
48
49static unsigned eg_tile_split(unsigned tile_split)
50{
51	switch (tile_split) {
52	case 64:	tile_split = 0;	break;
53	case 128:	tile_split = 1;	break;
54	case 256:	tile_split = 2;	break;
55	case 512:	tile_split = 3;	break;
56	default:
57	case 1024:	tile_split = 4;	break;
58	case 2048:	tile_split = 5;	break;
59	case 4096:	tile_split = 6;	break;
60	}
61	return tile_split;
62}
63
64static unsigned eg_macro_tile_aspect(unsigned macro_tile_aspect)
65{
66	switch (macro_tile_aspect) {
67	default:
68	case 1:	macro_tile_aspect = 0;	break;
69	case 2:	macro_tile_aspect = 1;	break;
70	case 4:	macro_tile_aspect = 2;	break;
71	case 8:	macro_tile_aspect = 3;	break;
72	}
73	return macro_tile_aspect;
74}
75
76static unsigned eg_bank_wh(unsigned bankwh)
77{
78	switch (bankwh) {
79	default:
80	case 1:	bankwh = 0;	break;
81	case 2:	bankwh = 1;	break;
82	case 4:	bankwh = 2;	break;
83	case 8:	bankwh = 3;	break;
84	}
85	return bankwh;
86}
87
88static uint32_t r600_translate_blend_function(int blend_func)
89{
90	switch (blend_func) {
91	case PIPE_BLEND_ADD:
92		return V_028780_COMB_DST_PLUS_SRC;
93	case PIPE_BLEND_SUBTRACT:
94		return V_028780_COMB_SRC_MINUS_DST;
95	case PIPE_BLEND_REVERSE_SUBTRACT:
96		return V_028780_COMB_DST_MINUS_SRC;
97	case PIPE_BLEND_MIN:
98		return V_028780_COMB_MIN_DST_SRC;
99	case PIPE_BLEND_MAX:
100		return V_028780_COMB_MAX_DST_SRC;
101	default:
102		R600_ERR("Unknown blend function %d\n", blend_func);
103		assert(0);
104		break;
105	}
106	return 0;
107}
108
109static uint32_t r600_translate_blend_factor(int blend_fact)
110{
111	switch (blend_fact) {
112	case PIPE_BLENDFACTOR_ONE:
113		return V_028780_BLEND_ONE;
114	case PIPE_BLENDFACTOR_SRC_COLOR:
115		return V_028780_BLEND_SRC_COLOR;
116	case PIPE_BLENDFACTOR_SRC_ALPHA:
117		return V_028780_BLEND_SRC_ALPHA;
118	case PIPE_BLENDFACTOR_DST_ALPHA:
119		return V_028780_BLEND_DST_ALPHA;
120	case PIPE_BLENDFACTOR_DST_COLOR:
121		return V_028780_BLEND_DST_COLOR;
122	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
123		return V_028780_BLEND_SRC_ALPHA_SATURATE;
124	case PIPE_BLENDFACTOR_CONST_COLOR:
125		return V_028780_BLEND_CONST_COLOR;
126	case PIPE_BLENDFACTOR_CONST_ALPHA:
127		return V_028780_BLEND_CONST_ALPHA;
128	case PIPE_BLENDFACTOR_ZERO:
129		return V_028780_BLEND_ZERO;
130	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
131		return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
132	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
133		return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
134	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
135		return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
136	case PIPE_BLENDFACTOR_INV_DST_COLOR:
137		return V_028780_BLEND_ONE_MINUS_DST_COLOR;
138	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
139		return V_028780_BLEND_ONE_MINUS_CONST_COLOR;
140	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
141		return V_028780_BLEND_ONE_MINUS_CONST_ALPHA;
142	case PIPE_BLENDFACTOR_SRC1_COLOR:
143		return V_028780_BLEND_SRC1_COLOR;
144	case PIPE_BLENDFACTOR_SRC1_ALPHA:
145		return V_028780_BLEND_SRC1_ALPHA;
146	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
147		return V_028780_BLEND_INV_SRC1_COLOR;
148	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
149		return V_028780_BLEND_INV_SRC1_ALPHA;
150	default:
151		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
152		assert(0);
153		break;
154	}
155	return 0;
156}
157
158static unsigned r600_tex_dim(unsigned dim)
159{
160	switch (dim) {
161	default:
162	case PIPE_TEXTURE_1D:
163		return V_030000_SQ_TEX_DIM_1D;
164	case PIPE_TEXTURE_1D_ARRAY:
165		return V_030000_SQ_TEX_DIM_1D_ARRAY;
166	case PIPE_TEXTURE_2D:
167	case PIPE_TEXTURE_RECT:
168		return V_030000_SQ_TEX_DIM_2D;
169	case PIPE_TEXTURE_2D_ARRAY:
170		return V_030000_SQ_TEX_DIM_2D_ARRAY;
171	case PIPE_TEXTURE_3D:
172		return V_030000_SQ_TEX_DIM_3D;
173	case PIPE_TEXTURE_CUBE:
174		return V_030000_SQ_TEX_DIM_CUBEMAP;
175	}
176}
177
178static uint32_t r600_translate_dbformat(enum pipe_format format)
179{
180	switch (format) {
181	case PIPE_FORMAT_Z16_UNORM:
182		return V_028040_Z_16;
183	case PIPE_FORMAT_Z24X8_UNORM:
184	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
185		return V_028040_Z_24;
186	case PIPE_FORMAT_Z32_FLOAT:
187	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
188		return V_028040_Z_32_FLOAT;
189	default:
190		return ~0U;
191	}
192}
193
194static uint32_t r600_translate_colorswap(enum pipe_format format)
195{
196	switch (format) {
197	/* 8-bit buffers. */
198	case PIPE_FORMAT_L4A4_UNORM:
199	case PIPE_FORMAT_A4R4_UNORM:
200		return V_028C70_SWAP_ALT;
201
202	case PIPE_FORMAT_A8_UNORM:
203	case PIPE_FORMAT_A8_SNORM:
204	case PIPE_FORMAT_A8_UINT:
205	case PIPE_FORMAT_A8_SINT:
206	case PIPE_FORMAT_A16_UNORM:
207	case PIPE_FORMAT_A16_SNORM:
208	case PIPE_FORMAT_A16_UINT:
209	case PIPE_FORMAT_A16_SINT:
210	case PIPE_FORMAT_A16_FLOAT:
211	case PIPE_FORMAT_A32_UINT:
212	case PIPE_FORMAT_A32_SINT:
213	case PIPE_FORMAT_A32_FLOAT:
214	case PIPE_FORMAT_R4A4_UNORM:
215		return V_028C70_SWAP_ALT_REV;
216	case PIPE_FORMAT_I8_UNORM:
217	case PIPE_FORMAT_I8_SNORM:
218	case PIPE_FORMAT_I8_UINT:
219	case PIPE_FORMAT_I8_SINT:
220	case PIPE_FORMAT_I16_UNORM:
221	case PIPE_FORMAT_I16_SNORM:
222	case PIPE_FORMAT_I16_UINT:
223	case PIPE_FORMAT_I16_SINT:
224	case PIPE_FORMAT_I16_FLOAT:
225	case PIPE_FORMAT_I32_UINT:
226	case PIPE_FORMAT_I32_SINT:
227	case PIPE_FORMAT_I32_FLOAT:
228	case PIPE_FORMAT_L8_UNORM:
229	case PIPE_FORMAT_L8_SNORM:
230	case PIPE_FORMAT_L8_UINT:
231	case PIPE_FORMAT_L8_SINT:
232	case PIPE_FORMAT_L8_SRGB:
233	case PIPE_FORMAT_L16_UNORM:
234	case PIPE_FORMAT_L16_SNORM:
235	case PIPE_FORMAT_L16_UINT:
236	case PIPE_FORMAT_L16_SINT:
237	case PIPE_FORMAT_L16_FLOAT:
238	case PIPE_FORMAT_L32_UINT:
239	case PIPE_FORMAT_L32_SINT:
240	case PIPE_FORMAT_L32_FLOAT:
241	case PIPE_FORMAT_R8_UNORM:
242	case PIPE_FORMAT_R8_SNORM:
243	case PIPE_FORMAT_R8_UINT:
244	case PIPE_FORMAT_R8_SINT:
245		return V_028C70_SWAP_STD;
246
247	/* 16-bit buffers. */
248	case PIPE_FORMAT_B5G6R5_UNORM:
249		return V_028C70_SWAP_STD_REV;
250
251	case PIPE_FORMAT_B5G5R5A1_UNORM:
252	case PIPE_FORMAT_B5G5R5X1_UNORM:
253		return V_028C70_SWAP_ALT;
254
255	case PIPE_FORMAT_B4G4R4A4_UNORM:
256	case PIPE_FORMAT_B4G4R4X4_UNORM:
257		return V_028C70_SWAP_ALT;
258
259	case PIPE_FORMAT_Z16_UNORM:
260		return V_028C70_SWAP_STD;
261
262	case PIPE_FORMAT_L8A8_UNORM:
263	case PIPE_FORMAT_L8A8_SNORM:
264	case PIPE_FORMAT_L8A8_UINT:
265	case PIPE_FORMAT_L8A8_SINT:
266	case PIPE_FORMAT_L8A8_SRGB:
267	case PIPE_FORMAT_L16A16_UNORM:
268	case PIPE_FORMAT_L16A16_SNORM:
269	case PIPE_FORMAT_L16A16_UINT:
270	case PIPE_FORMAT_L16A16_SINT:
271	case PIPE_FORMAT_L16A16_FLOAT:
272	case PIPE_FORMAT_L32A32_UINT:
273	case PIPE_FORMAT_L32A32_SINT:
274	case PIPE_FORMAT_L32A32_FLOAT:
275		return V_028C70_SWAP_ALT;
276	case PIPE_FORMAT_R8G8_UNORM:
277	case PIPE_FORMAT_R8G8_SNORM:
278	case PIPE_FORMAT_R8G8_UINT:
279	case PIPE_FORMAT_R8G8_SINT:
280		return V_028C70_SWAP_STD;
281
282	case PIPE_FORMAT_R16_UNORM:
283	case PIPE_FORMAT_R16_SNORM:
284	case PIPE_FORMAT_R16_UINT:
285	case PIPE_FORMAT_R16_SINT:
286	case PIPE_FORMAT_R16_FLOAT:
287		return V_028C70_SWAP_STD;
288
289	/* 32-bit buffers. */
290	case PIPE_FORMAT_A8B8G8R8_SRGB:
291		return V_028C70_SWAP_STD_REV;
292	case PIPE_FORMAT_B8G8R8A8_SRGB:
293		return V_028C70_SWAP_ALT;
294
295	case PIPE_FORMAT_B8G8R8A8_UNORM:
296	case PIPE_FORMAT_B8G8R8X8_UNORM:
297		return V_028C70_SWAP_ALT;
298
299	case PIPE_FORMAT_A8R8G8B8_UNORM:
300	case PIPE_FORMAT_X8R8G8B8_UNORM:
301		return V_028C70_SWAP_ALT_REV;
302	case PIPE_FORMAT_R8G8B8A8_SNORM:
303	case PIPE_FORMAT_R8G8B8A8_UNORM:
304	case PIPE_FORMAT_R8G8B8A8_SINT:
305	case PIPE_FORMAT_R8G8B8A8_UINT:
306	case PIPE_FORMAT_R8G8B8X8_UNORM:
307		return V_028C70_SWAP_STD;
308
309	case PIPE_FORMAT_A8B8G8R8_UNORM:
310	case PIPE_FORMAT_X8B8G8R8_UNORM:
311	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
312		return V_028C70_SWAP_STD_REV;
313
314	case PIPE_FORMAT_Z24X8_UNORM:
315	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
316		return V_028C70_SWAP_STD;
317
318	case PIPE_FORMAT_X8Z24_UNORM:
319	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
320		return V_028C70_SWAP_STD;
321
322	case PIPE_FORMAT_R10G10B10A2_UNORM:
323	case PIPE_FORMAT_R10G10B10X2_SNORM:
324	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
325		return V_028C70_SWAP_STD;
326
327	case PIPE_FORMAT_B10G10R10A2_UNORM:
328	case PIPE_FORMAT_B10G10R10A2_UINT:
329		return V_028C70_SWAP_ALT;
330
331	case PIPE_FORMAT_R11G11B10_FLOAT:
332	case PIPE_FORMAT_R32_FLOAT:
333	case PIPE_FORMAT_R32_UINT:
334	case PIPE_FORMAT_R32_SINT:
335	case PIPE_FORMAT_Z32_FLOAT:
336	case PIPE_FORMAT_R16G16_FLOAT:
337	case PIPE_FORMAT_R16G16_UNORM:
338	case PIPE_FORMAT_R16G16_SNORM:
339	case PIPE_FORMAT_R16G16_UINT:
340	case PIPE_FORMAT_R16G16_SINT:
341	case PIPE_FORMAT_R16G16B16_FLOAT:
342	case PIPE_FORMAT_R32G32B32_FLOAT:
343		return V_028C70_SWAP_STD;
344
345	/* 64-bit buffers. */
346	case PIPE_FORMAT_R32G32_FLOAT:
347	case PIPE_FORMAT_R32G32_UINT:
348	case PIPE_FORMAT_R32G32_SINT:
349	case PIPE_FORMAT_R16G16B16A16_UNORM:
350	case PIPE_FORMAT_R16G16B16A16_SNORM:
351	case PIPE_FORMAT_R16G16B16A16_UINT:
352	case PIPE_FORMAT_R16G16B16A16_SINT:
353	case PIPE_FORMAT_R16G16B16A16_FLOAT:
354	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
355
356	/* 128-bit buffers. */
357	case PIPE_FORMAT_R32G32B32A32_FLOAT:
358	case PIPE_FORMAT_R32G32B32A32_SNORM:
359	case PIPE_FORMAT_R32G32B32A32_UNORM:
360	case PIPE_FORMAT_R32G32B32A32_SINT:
361	case PIPE_FORMAT_R32G32B32A32_UINT:
362		return V_028C70_SWAP_STD;
363	default:
364		R600_ERR("unsupported colorswap format %d\n", format);
365		return ~0U;
366	}
367	return ~0U;
368}
369
370static uint32_t r600_translate_colorformat(enum pipe_format format)
371{
372	switch (format) {
373	/* 8-bit buffers. */
374	case PIPE_FORMAT_A8_UNORM:
375	case PIPE_FORMAT_A8_SNORM:
376	case PIPE_FORMAT_A8_UINT:
377	case PIPE_FORMAT_A8_SINT:
378	case PIPE_FORMAT_I8_UNORM:
379	case PIPE_FORMAT_I8_SNORM:
380	case PIPE_FORMAT_I8_UINT:
381	case PIPE_FORMAT_I8_SINT:
382	case PIPE_FORMAT_L8_UNORM:
383	case PIPE_FORMAT_L8_SNORM:
384	case PIPE_FORMAT_L8_UINT:
385	case PIPE_FORMAT_L8_SINT:
386	case PIPE_FORMAT_L8_SRGB:
387	case PIPE_FORMAT_R8_UNORM:
388	case PIPE_FORMAT_R8_SNORM:
389	case PIPE_FORMAT_R8_UINT:
390	case PIPE_FORMAT_R8_SINT:
391		return V_028C70_COLOR_8;
392
393	/* 16-bit buffers. */
394	case PIPE_FORMAT_B5G6R5_UNORM:
395		return V_028C70_COLOR_5_6_5;
396
397	case PIPE_FORMAT_B5G5R5A1_UNORM:
398	case PIPE_FORMAT_B5G5R5X1_UNORM:
399		return V_028C70_COLOR_1_5_5_5;
400
401	case PIPE_FORMAT_B4G4R4A4_UNORM:
402	case PIPE_FORMAT_B4G4R4X4_UNORM:
403		return V_028C70_COLOR_4_4_4_4;
404
405	case PIPE_FORMAT_Z16_UNORM:
406		return V_028C70_COLOR_16;
407
408	case PIPE_FORMAT_L8A8_UNORM:
409	case PIPE_FORMAT_L8A8_SNORM:
410	case PIPE_FORMAT_L8A8_UINT:
411	case PIPE_FORMAT_L8A8_SINT:
412	case PIPE_FORMAT_L8A8_SRGB:
413	case PIPE_FORMAT_R8G8_UNORM:
414	case PIPE_FORMAT_R8G8_SNORM:
415	case PIPE_FORMAT_R8G8_UINT:
416	case PIPE_FORMAT_R8G8_SINT:
417		return V_028C70_COLOR_8_8;
418
419	case PIPE_FORMAT_R16_UNORM:
420	case PIPE_FORMAT_R16_SNORM:
421	case PIPE_FORMAT_R16_UINT:
422	case PIPE_FORMAT_R16_SINT:
423	case PIPE_FORMAT_A16_UNORM:
424	case PIPE_FORMAT_A16_SNORM:
425	case PIPE_FORMAT_A16_UINT:
426	case PIPE_FORMAT_A16_SINT:
427	case PIPE_FORMAT_L16_UNORM:
428	case PIPE_FORMAT_L16_SNORM:
429	case PIPE_FORMAT_L16_UINT:
430	case PIPE_FORMAT_L16_SINT:
431	case PIPE_FORMAT_I16_UNORM:
432	case PIPE_FORMAT_I16_SNORM:
433	case PIPE_FORMAT_I16_UINT:
434	case PIPE_FORMAT_I16_SINT:
435		return V_028C70_COLOR_16;
436
437	case PIPE_FORMAT_R16_FLOAT:
438	case PIPE_FORMAT_A16_FLOAT:
439	case PIPE_FORMAT_L16_FLOAT:
440	case PIPE_FORMAT_I16_FLOAT:
441		return V_028C70_COLOR_16_FLOAT;
442
443	/* 32-bit buffers. */
444	case PIPE_FORMAT_A8B8G8R8_SRGB:
445	case PIPE_FORMAT_A8B8G8R8_UNORM:
446	case PIPE_FORMAT_A8R8G8B8_UNORM:
447	case PIPE_FORMAT_B8G8R8A8_SRGB:
448	case PIPE_FORMAT_B8G8R8A8_UNORM:
449	case PIPE_FORMAT_B8G8R8X8_UNORM:
450	case PIPE_FORMAT_R8G8B8A8_SNORM:
451	case PIPE_FORMAT_R8G8B8A8_UNORM:
452	case PIPE_FORMAT_R8G8B8X8_UNORM:
453	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
454	case PIPE_FORMAT_X8B8G8R8_UNORM:
455	case PIPE_FORMAT_X8R8G8B8_UNORM:
456	case PIPE_FORMAT_R8G8B8_UNORM:
457	case PIPE_FORMAT_R8G8B8A8_SINT:
458	case PIPE_FORMAT_R8G8B8A8_UINT:
459		return V_028C70_COLOR_8_8_8_8;
460
461	case PIPE_FORMAT_R10G10B10A2_UNORM:
462	case PIPE_FORMAT_R10G10B10X2_SNORM:
463	case PIPE_FORMAT_B10G10R10A2_UNORM:
464	case PIPE_FORMAT_B10G10R10A2_UINT:
465	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
466		return V_028C70_COLOR_2_10_10_10;
467
468	case PIPE_FORMAT_Z24X8_UNORM:
469	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
470		return V_028C70_COLOR_8_24;
471
472	case PIPE_FORMAT_X8Z24_UNORM:
473	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
474		return V_028C70_COLOR_24_8;
475
476	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
477		return V_028C70_COLOR_X24_8_32_FLOAT;
478
479	case PIPE_FORMAT_R32_UINT:
480	case PIPE_FORMAT_R32_SINT:
481	case PIPE_FORMAT_A32_UINT:
482	case PIPE_FORMAT_A32_SINT:
483	case PIPE_FORMAT_L32_UINT:
484	case PIPE_FORMAT_L32_SINT:
485	case PIPE_FORMAT_I32_UINT:
486	case PIPE_FORMAT_I32_SINT:
487		return V_028C70_COLOR_32;
488
489	case PIPE_FORMAT_R32_FLOAT:
490	case PIPE_FORMAT_A32_FLOAT:
491	case PIPE_FORMAT_L32_FLOAT:
492	case PIPE_FORMAT_I32_FLOAT:
493	case PIPE_FORMAT_Z32_FLOAT:
494		return V_028C70_COLOR_32_FLOAT;
495
496	case PIPE_FORMAT_R16G16_FLOAT:
497	case PIPE_FORMAT_L16A16_FLOAT:
498		return V_028C70_COLOR_16_16_FLOAT;
499
500	case PIPE_FORMAT_R16G16_UNORM:
501	case PIPE_FORMAT_R16G16_SNORM:
502	case PIPE_FORMAT_R16G16_UINT:
503	case PIPE_FORMAT_R16G16_SINT:
504	case PIPE_FORMAT_L16A16_UNORM:
505	case PIPE_FORMAT_L16A16_SNORM:
506	case PIPE_FORMAT_L16A16_UINT:
507	case PIPE_FORMAT_L16A16_SINT:
508		return V_028C70_COLOR_16_16;
509
510	case PIPE_FORMAT_R11G11B10_FLOAT:
511		return V_028C70_COLOR_10_11_11_FLOAT;
512
513	/* 64-bit buffers. */
514	case PIPE_FORMAT_R16G16B16A16_UINT:
515	case PIPE_FORMAT_R16G16B16A16_SINT:
516	case PIPE_FORMAT_R16G16B16A16_UNORM:
517	case PIPE_FORMAT_R16G16B16A16_SNORM:
518		return V_028C70_COLOR_16_16_16_16;
519
520	case PIPE_FORMAT_R16G16B16_FLOAT:
521	case PIPE_FORMAT_R16G16B16A16_FLOAT:
522		return V_028C70_COLOR_16_16_16_16_FLOAT;
523
524	case PIPE_FORMAT_R32G32_FLOAT:
525	case PIPE_FORMAT_L32A32_FLOAT:
526		return V_028C70_COLOR_32_32_FLOAT;
527
528	case PIPE_FORMAT_R32G32_SINT:
529	case PIPE_FORMAT_R32G32_UINT:
530	case PIPE_FORMAT_L32A32_UINT:
531	case PIPE_FORMAT_L32A32_SINT:
532		return V_028C70_COLOR_32_32;
533
534	/* 96-bit buffers. */
535	case PIPE_FORMAT_R32G32B32_FLOAT:
536		return V_028C70_COLOR_32_32_32_FLOAT;
537
538	/* 128-bit buffers. */
539	case PIPE_FORMAT_R32G32B32A32_SNORM:
540	case PIPE_FORMAT_R32G32B32A32_UNORM:
541	case PIPE_FORMAT_R32G32B32A32_SINT:
542	case PIPE_FORMAT_R32G32B32A32_UINT:
543		return V_028C70_COLOR_32_32_32_32;
544	case PIPE_FORMAT_R32G32B32A32_FLOAT:
545		return V_028C70_COLOR_32_32_32_32_FLOAT;
546
547	/* YUV buffers. */
548	case PIPE_FORMAT_UYVY:
549	case PIPE_FORMAT_YUYV:
550	default:
551		return ~0U; /* Unsupported. */
552	}
553}
554
555static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
556{
557	if (R600_BIG_ENDIAN) {
558		switch(colorformat) {
559
560		/* 8-bit buffers. */
561		case V_028C70_COLOR_8:
562			return ENDIAN_NONE;
563
564		/* 16-bit buffers. */
565		case V_028C70_COLOR_5_6_5:
566		case V_028C70_COLOR_1_5_5_5:
567		case V_028C70_COLOR_4_4_4_4:
568		case V_028C70_COLOR_16:
569		case V_028C70_COLOR_8_8:
570			return ENDIAN_8IN16;
571
572		/* 32-bit buffers. */
573		case V_028C70_COLOR_8_8_8_8:
574		case V_028C70_COLOR_2_10_10_10:
575		case V_028C70_COLOR_8_24:
576		case V_028C70_COLOR_24_8:
577		case V_028C70_COLOR_32_FLOAT:
578		case V_028C70_COLOR_16_16_FLOAT:
579		case V_028C70_COLOR_16_16:
580			return ENDIAN_8IN32;
581
582		/* 64-bit buffers. */
583		case V_028C70_COLOR_16_16_16_16:
584		case V_028C70_COLOR_16_16_16_16_FLOAT:
585			return ENDIAN_8IN16;
586
587		case V_028C70_COLOR_32_32_FLOAT:
588		case V_028C70_COLOR_32_32:
589		case V_028C70_COLOR_X24_8_32_FLOAT:
590			return ENDIAN_8IN32;
591
592		/* 96-bit buffers. */
593		case V_028C70_COLOR_32_32_32_FLOAT:
594		/* 128-bit buffers. */
595		case V_028C70_COLOR_32_32_32_32_FLOAT:
596		case V_028C70_COLOR_32_32_32_32:
597			return ENDIAN_8IN32;
598		default:
599			return ENDIAN_NONE; /* Unsupported. */
600		}
601	} else {
602		return ENDIAN_NONE;
603	}
604}
605
606static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
607{
608	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
609}
610
611static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
612{
613	return r600_translate_colorformat(format) != ~0U &&
614		r600_translate_colorswap(format) != ~0U;
615}
616
617static bool r600_is_zs_format_supported(enum pipe_format format)
618{
619	return r600_translate_dbformat(format) != ~0U;
620}
621
622boolean evergreen_is_format_supported(struct pipe_screen *screen,
623				      enum pipe_format format,
624				      enum pipe_texture_target target,
625				      unsigned sample_count,
626				      unsigned usage)
627{
628	unsigned retval = 0;
629
630	if (target >= PIPE_MAX_TEXTURE_TYPES) {
631		R600_ERR("r600: unsupported texture type %d\n", target);
632		return FALSE;
633	}
634
635	if (!util_format_is_supported(format, usage))
636		return FALSE;
637
638	/* Multisample */
639	if (sample_count > 1)
640		return FALSE;
641
642	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
643	    r600_is_sampler_format_supported(screen, format)) {
644		retval |= PIPE_BIND_SAMPLER_VIEW;
645	}
646
647	if ((usage & (PIPE_BIND_RENDER_TARGET |
648		      PIPE_BIND_DISPLAY_TARGET |
649		      PIPE_BIND_SCANOUT |
650		      PIPE_BIND_SHARED)) &&
651	    r600_is_colorbuffer_format_supported(format)) {
652		retval |= usage &
653			  (PIPE_BIND_RENDER_TARGET |
654			   PIPE_BIND_DISPLAY_TARGET |
655			   PIPE_BIND_SCANOUT |
656			   PIPE_BIND_SHARED);
657	}
658
659	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
660	    r600_is_zs_format_supported(format)) {
661		retval |= PIPE_BIND_DEPTH_STENCIL;
662	}
663
664	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
665	    r600_is_vertex_format_supported(format)) {
666		retval |= PIPE_BIND_VERTEX_BUFFER;
667	}
668
669	if (usage & PIPE_BIND_TRANSFER_READ)
670		retval |= PIPE_BIND_TRANSFER_READ;
671	if (usage & PIPE_BIND_TRANSFER_WRITE)
672		retval |= PIPE_BIND_TRANSFER_WRITE;
673
674	return retval == usage;
675}
676
677static void *evergreen_create_blend_state(struct pipe_context *ctx,
678					const struct pipe_blend_state *state)
679{
680	struct r600_context *rctx = (struct r600_context *)ctx;
681	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
682	struct r600_pipe_state *rstate;
683	uint32_t color_control = 0, target_mask;
684	/* XXX there is more then 8 framebuffer */
685	unsigned blend_cntl[8];
686
687	if (blend == NULL) {
688		return NULL;
689	}
690
691	rstate = &blend->rstate;
692
693	rstate->id = R600_PIPE_STATE_BLEND;
694
695	target_mask = 0;
696	if (state->logicop_enable) {
697		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
698	} else {
699		color_control |= (0xcc << 16);
700	}
701	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
702	if (state->independent_blend_enable) {
703		for (int i = 0; i < 8; i++) {
704			target_mask |= (state->rt[i].colormask << (4 * i));
705		}
706	} else {
707		for (int i = 0; i < 8; i++) {
708			target_mask |= (state->rt[0].colormask << (4 * i));
709		}
710	}
711	blend->cb_target_mask = target_mask;
712
713	if (target_mask)
714		color_control |= S_028808_MODE(V_028808_CB_NORMAL);
715	else
716		color_control |= S_028808_MODE(V_028808_CB_DISABLE);
717
718	r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
719				color_control);
720	/* only have dual source on MRT0 */
721	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
722	for (int i = 0; i < 8; i++) {
723		/* state->rt entries > 0 only written if independent blending */
724		const int j = state->independent_blend_enable ? i : 0;
725
726		unsigned eqRGB = state->rt[j].rgb_func;
727		unsigned srcRGB = state->rt[j].rgb_src_factor;
728		unsigned dstRGB = state->rt[j].rgb_dst_factor;
729		unsigned eqA = state->rt[j].alpha_func;
730		unsigned srcA = state->rt[j].alpha_src_factor;
731		unsigned dstA = state->rt[j].alpha_dst_factor;
732
733		blend_cntl[i] = 0;
734		if (!state->rt[j].blend_enable)
735			continue;
736
737		blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1);
738		blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
739		blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
740		blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
741
742		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
743			blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1);
744			blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
745			blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
746			blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
747		}
748	}
749	for (int i = 0; i < 8; i++) {
750		r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i]);
751	}
752
753	return rstate;
754}
755
756static void *evergreen_create_dsa_state(struct pipe_context *ctx,
757				   const struct pipe_depth_stencil_alpha_state *state)
758{
759	struct r600_context *rctx = (struct r600_context *)ctx;
760	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
761	unsigned db_depth_control, alpha_test_control, alpha_ref;
762	struct r600_pipe_state *rstate;
763
764	if (dsa == NULL) {
765		return NULL;
766	}
767
768	dsa->valuemask[0] = state->stencil[0].valuemask;
769	dsa->valuemask[1] = state->stencil[1].valuemask;
770	dsa->writemask[0] = state->stencil[0].writemask;
771	dsa->writemask[1] = state->stencil[1].writemask;
772
773	rstate = &dsa->rstate;
774
775	rstate->id = R600_PIPE_STATE_DSA;
776	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
777		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
778		S_028800_ZFUNC(state->depth.func);
779
780	/* stencil */
781	if (state->stencil[0].enabled) {
782		db_depth_control |= S_028800_STENCIL_ENABLE(1);
783		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
784		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
785		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
786		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
787
788		if (state->stencil[1].enabled) {
789			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
790			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
791			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
792			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
793			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
794		}
795	}
796
797	/* alpha */
798	alpha_test_control = 0;
799	alpha_ref = 0;
800	if (state->alpha.enabled) {
801		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
802		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
803		alpha_ref = fui(state->alpha.ref_value);
804	}
805	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
806	dsa->alpha_ref = alpha_ref;
807
808	/* misc */
809	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
810	return rstate;
811}
812
813static void *evergreen_create_rs_state(struct pipe_context *ctx,
814					const struct pipe_rasterizer_state *state)
815{
816	struct r600_context *rctx = (struct r600_context *)ctx;
817	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
818	struct r600_pipe_state *rstate;
819	unsigned tmp;
820	unsigned prov_vtx = 1, polygon_dual_mode;
821	float psize_min, psize_max;
822
823	if (rs == NULL) {
824		return NULL;
825	}
826
827	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
828				state->fill_back != PIPE_POLYGON_MODE_FILL);
829
830	if (state->flatshade_first)
831		prov_vtx = 0;
832
833	rstate = &rs->rstate;
834	rs->flatshade = state->flatshade;
835	rs->sprite_coord_enable = state->sprite_coord_enable;
836	rs->two_side = state->light_twoside;
837	rs->clip_plane_enable = state->clip_plane_enable;
838	rs->pa_sc_line_stipple = state->line_stipple_enable ?
839				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
840				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
841	rs->pa_cl_clip_cntl =
842		S_028810_PS_UCP_MODE(3) |
843		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
844		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
845		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
846
847	/* offset */
848	rs->offset_units = state->offset_units;
849	rs->offset_scale = state->offset_scale * 12.0f;
850
851	rstate->id = R600_PIPE_STATE_RASTERIZER;
852	tmp = S_0286D4_FLAT_SHADE_ENA(1);
853	if (state->sprite_coord_enable) {
854		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
855			S_0286D4_PNT_SPRITE_OVRD_X(2) |
856			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
857			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
858			S_0286D4_PNT_SPRITE_OVRD_W(1);
859		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
860			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
861		}
862	}
863	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
864
865	/* point size 12.4 fixed point */
866	tmp = (unsigned)(state->point_size * 8.0);
867	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
868
869	if (state->point_size_per_vertex) {
870		psize_min = util_get_min_point_size(state);
871		psize_max = 8192;
872	} else {
873		/* Force the point size to be as if the vertex output was disabled. */
874		psize_min = state->point_size;
875		psize_max = state->point_size;
876	}
877	/* Divide by two, because 0.5 = 1 pixel. */
878	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
879				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
880				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
881
882	tmp = (unsigned)state->line_width * 8;
883	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
884	r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0,
885				S_028A48_VPORT_SCISSOR_ENABLE(state->scissor) |
886				S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
887
888	if (rctx->chip_class == CAYMAN) {
889		r600_pipe_state_add_reg(rstate, CM_R_028BE4_PA_SU_VTX_CNTL,
890					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
891	} else {
892		r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
893					S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
894	}
895	r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
896	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
897				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
898				S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
899				S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
900				S_028814_FACE(!state->front_ccw) |
901				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
902				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
903				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
904				S_028814_POLY_MODE(polygon_dual_mode) |
905				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
906				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
907	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
908	return rstate;
909}
910
911static void *evergreen_create_sampler_state(struct pipe_context *ctx,
912					const struct pipe_sampler_state *state)
913{
914	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
915	union util_color uc;
916	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
917
918	if (rstate == NULL) {
919		return NULL;
920	}
921
922	rstate->id = R600_PIPE_STATE_SAMPLER;
923	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
924	r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
925			S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
926			S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
927			S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
928			S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
929			S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
930			S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
931			S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
932			S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
933			S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
934	r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
935			S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
936			S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)),
937			NULL, 0);
938	r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0,
939					S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
940					(state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) |
941					S_03C008_TYPE(1),
942					NULL, 0);
943
944	if (uc.ui) {
945		r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
946		r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
947		r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
948		r600_pipe_state_add_reg_noblock(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
949	}
950	return rstate;
951}
952
953static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx,
954							struct pipe_resource *texture,
955							const struct pipe_sampler_view *state)
956{
957	struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
958	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
959	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
960	unsigned format, endian;
961	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
962	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
963	unsigned height, depth, width;
964	unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
965
966	if (view == NULL)
967		return NULL;
968
969	/* initialize base object */
970	view->base = *state;
971	view->base.texture = NULL;
972	pipe_reference(NULL, &texture->reference);
973	view->base.texture = texture;
974	view->base.reference.count = 1;
975	view->base.context = ctx;
976
977	swizzle[0] = state->swizzle_r;
978	swizzle[1] = state->swizzle_g;
979	swizzle[2] = state->swizzle_b;
980	swizzle[3] = state->swizzle_a;
981
982	format = r600_translate_texformat(ctx->screen, state->format,
983					  swizzle,
984					  &word4, &yuv_format);
985	assert(format != ~0);
986	if (format == ~0) {
987		FREE(view);
988		return NULL;
989	}
990
991	if (tmp->is_depth && !tmp->is_flushing_texture) {
992		if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
993			FREE(view);
994			return NULL;
995		}
996		tmp = tmp->flushed_depth_texture;
997	}
998
999	endian = r600_colorformat_endian_swap(format);
1000
1001	if (!rscreen->use_surface_alloc) {
1002		height = texture->height0;
1003		depth = texture->depth0;
1004		width = texture->width0;
1005		pitch = align(tmp->pitch_in_blocks[0] *
1006				util_format_get_blockwidth(state->format), 8);
1007		array_mode = tmp->array_mode[0];
1008		tile_type = tmp->tile_type;
1009		tile_split = 0;
1010		macro_aspect = 0;
1011		bankw = 0;
1012		bankh = 0;
1013	} else {
1014		width = tmp->surface.level[0].npix_x;
1015		height = tmp->surface.level[0].npix_y;
1016		depth = tmp->surface.level[0].npix_z;
1017		pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
1018		tile_type = tmp->tile_type;
1019
1020		switch (tmp->surface.level[0].mode) {
1021		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1022			array_mode = V_028C70_ARRAY_LINEAR_ALIGNED;
1023			break;
1024		case RADEON_SURF_MODE_2D:
1025			array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1026			break;
1027		case RADEON_SURF_MODE_1D:
1028			array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1029			break;
1030		case RADEON_SURF_MODE_LINEAR:
1031		default:
1032			array_mode = V_028C70_ARRAY_LINEAR_GENERAL;
1033			break;
1034		}
1035		tile_split = tmp->surface.tile_split;
1036		macro_aspect = tmp->surface.mtilea;
1037		bankw = tmp->surface.bankw;
1038		bankh = tmp->surface.bankh;
1039		tile_split = eg_tile_split(tile_split);
1040		macro_aspect = eg_macro_tile_aspect(macro_aspect);
1041		bankw = eg_bank_wh(bankw);
1042		bankh = eg_bank_wh(bankh);
1043	}
1044	/* 128 bit formats require tile type = 1 */
1045	if (rscreen->chip_class == CAYMAN) {
1046		if (util_format_get_blocksize(state->format) >= 16)
1047			tile_type = 1;
1048	}
1049	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1050
1051	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1052	        height = 1;
1053		depth = texture->array_size;
1054	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1055		depth = texture->array_size;
1056	}
1057
1058	view->tex_resource = &tmp->resource;
1059	view->tex_resource_words[0] = (S_030000_DIM(r600_tex_dim(texture->target)) |
1060				       S_030000_PITCH((pitch / 8) - 1) |
1061				       S_030000_TEX_WIDTH(width - 1));
1062	if (rscreen->chip_class == CAYMAN)
1063		view->tex_resource_words[0] |= CM_S_030000_NON_DISP_TILING_ORDER(tile_type);
1064	else
1065		view->tex_resource_words[0] |= S_030000_NON_DISP_TILING_ORDER(tile_type);
1066	view->tex_resource_words[1] = (S_030004_TEX_HEIGHT(height - 1) |
1067				       S_030004_TEX_DEPTH(depth - 1) |
1068				       S_030004_ARRAY_MODE(array_mode));
1069	view->tex_resource_words[2] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1070	if (state->u.tex.last_level) {
1071		view->tex_resource_words[3] = (tmp->offset[1] + r600_resource_va(ctx->screen, texture)) >> 8;
1072	} else {
1073		view->tex_resource_words[3] = (tmp->offset[0] + r600_resource_va(ctx->screen, texture)) >> 8;
1074	}
1075	view->tex_resource_words[4] = (word4 |
1076				       S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1077				       S_030010_ENDIAN_SWAP(endian) |
1078				       S_030010_BASE_LEVEL(state->u.tex.first_level));
1079	view->tex_resource_words[5] = (S_030014_LAST_LEVEL(state->u.tex.last_level) |
1080				       S_030014_BASE_ARRAY(state->u.tex.first_layer) |
1081				       S_030014_LAST_ARRAY(state->u.tex.last_layer));
1082	/* aniso max 16 samples */
1083	view->tex_resource_words[6] = (S_030018_MAX_ANISO(4)) |
1084				      (S_030018_TILE_SPLIT(tile_split));
1085	view->tex_resource_words[7] = S_03001C_DATA_FORMAT(format) |
1086				      S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE) |
1087				      S_03001C_BANK_WIDTH(bankw) |
1088				      S_03001C_BANK_HEIGHT(bankh) |
1089				      S_03001C_MACRO_TILE_ASPECT(macro_aspect) |
1090				      S_03001C_NUM_BANKS(nbanks);
1091	return &view->base;
1092}
1093
1094static void evergreen_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1095					   struct pipe_sampler_view **views)
1096{
1097	struct r600_context *rctx = (struct r600_context *)ctx;
1098	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
1099}
1100
1101static void evergreen_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1102					   struct pipe_sampler_view **views)
1103{
1104	struct r600_context *rctx = (struct r600_context *)ctx;
1105	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
1106}
1107
1108static void evergreen_bind_samplers(struct r600_context *rctx,
1109				    struct r600_textures_info *dst,
1110				    unsigned count, void **states,
1111				    void (*set_sampler)(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id))
1112{
1113	struct r600_pipe_sampler_state **rstates = (struct r600_pipe_sampler_state**)states;
1114
1115	for (int i = 0; i < count; i++) {
1116		if (rstates[i] != dst->samplers[i]) {
1117			set_sampler(rctx, &rstates[i]->rstate, i);
1118		}
1119	}
1120
1121	memcpy(dst->samplers, states, sizeof(void*) * count);
1122	dst->n_samplers = count;
1123}
1124
1125static void evergreen_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1126{
1127	struct r600_context *rctx = (struct r600_context *)ctx;
1128	evergreen_bind_samplers(rctx, &rctx->ps_samplers, count, states,
1129				evergreen_context_pipe_state_set_ps_sampler);
1130}
1131
1132static void evergreen_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1133{
1134	struct r600_context *rctx = (struct r600_context *)ctx;
1135	evergreen_bind_samplers(rctx, &rctx->vs_samplers, count, states,
1136				evergreen_context_pipe_state_set_vs_sampler);
1137}
1138
1139static void evergreen_set_clip_state(struct pipe_context *ctx,
1140				const struct pipe_clip_state *state)
1141{
1142	struct r600_context *rctx = (struct r600_context *)ctx;
1143	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1144	struct pipe_constant_buffer cb;
1145
1146	if (rstate == NULL)
1147		return;
1148
1149	rctx->clip = *state;
1150	rstate->id = R600_PIPE_STATE_CLIP;
1151	for (int i = 0; i < 6; i++) {
1152		r600_pipe_state_add_reg(rstate,
1153					R_0285BC_PA_CL_UCP0_X + i * 16,
1154					fui(state->ucp[i][0]));
1155		r600_pipe_state_add_reg(rstate,
1156					R_0285C0_PA_CL_UCP0_Y + i * 16,
1157					fui(state->ucp[i][1]) );
1158		r600_pipe_state_add_reg(rstate,
1159					R_0285C4_PA_CL_UCP0_Z + i * 16,
1160					fui(state->ucp[i][2]));
1161		r600_pipe_state_add_reg(rstate,
1162					R_0285C8_PA_CL_UCP0_W + i * 16,
1163					fui(state->ucp[i][3]));
1164	}
1165
1166	free(rctx->states[R600_PIPE_STATE_CLIP]);
1167	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1168	r600_context_pipe_state_set(rctx, rstate);
1169
1170	cb.buffer = NULL;
1171	cb.user_buffer = state->ucp;
1172	cb.buffer_offset = 0;
1173	cb.buffer_size = 4*4*8;
1174	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1175	pipe_resource_reference(&cb.buffer, NULL);
1176}
1177
1178static void evergreen_set_polygon_stipple(struct pipe_context *ctx,
1179					 const struct pipe_poly_stipple *state)
1180{
1181}
1182
1183static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1184{
1185}
1186
1187static void evergreen_get_scissor_rect(struct r600_context *rctx,
1188				       unsigned tl_x, unsigned tl_y, unsigned br_x, unsigned br_y,
1189				       uint32_t *tl, uint32_t *br)
1190{
1191	/* EG hw workaround */
1192	if (br_x == 0)
1193		tl_x = 1;
1194	if (br_y == 0)
1195		tl_y = 1;
1196
1197	/* cayman hw workaround */
1198	if (rctx->chip_class == CAYMAN) {
1199		if (br_x == 1 && br_y == 1)
1200			br_x = 2;
1201	}
1202
1203	*tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1204	*br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1205}
1206
1207static void evergreen_set_scissor_state(struct pipe_context *ctx,
1208					const struct pipe_scissor_state *state)
1209{
1210	struct r600_context *rctx = (struct r600_context *)ctx;
1211	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1212	uint32_t tl, br;
1213
1214	if (rstate == NULL)
1215		return;
1216
1217	evergreen_get_scissor_rect(rctx, state->minx, state->miny, state->maxx, state->maxy, &tl, &br);
1218
1219	rstate->id = R600_PIPE_STATE_SCISSOR;
1220	r600_pipe_state_add_reg(rstate, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1221	r600_pipe_state_add_reg(rstate, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1222
1223	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1224	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1225	r600_context_pipe_state_set(rctx, rstate);
1226}
1227
1228static void evergreen_set_viewport_state(struct pipe_context *ctx,
1229					const struct pipe_viewport_state *state)
1230{
1231	struct r600_context *rctx = (struct r600_context *)ctx;
1232	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1233
1234	if (rstate == NULL)
1235		return;
1236
1237	rctx->viewport = *state;
1238	rstate->id = R600_PIPE_STATE_VIEWPORT;
1239	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1240	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1241	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1242	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1243	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1244	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1245
1246	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1247	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1248	r600_context_pipe_state_set(rctx, rstate);
1249}
1250
1251void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1252			 const struct pipe_framebuffer_state *state, int cb)
1253{
1254	struct r600_screen *rscreen = rctx->screen;
1255	struct r600_resource_texture *rtex;
1256	struct pipe_resource * pipe_tex;
1257	struct r600_surface *surf;
1258	unsigned level = state->cbufs[cb]->u.tex.level;
1259	unsigned pitch, slice;
1260	unsigned color_info, color_attrib, color_dim = 0;
1261	unsigned format, swap, ntype, endian;
1262	uint64_t offset;
1263	unsigned tile_type, macro_aspect, tile_split, bankh, bankw, nbanks;
1264	const struct util_format_description *desc;
1265	int i;
1266	bool blend_clamp = 0, blend_bypass = 0, alphatest_bypass;
1267
1268	surf = (struct r600_surface *)state->cbufs[cb];
1269	rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1270	pipe_tex = state->cbufs[cb]->texture;
1271
1272	if (rtex->is_depth && !rtex->is_flushing_texture) {
1273		r600_init_flushed_depth_texture(&rctx->context,
1274				state->cbufs[cb]->texture, NULL);
1275		rtex = rtex->flushed_depth_texture;
1276		assert(rtex);
1277	}
1278
1279	/* XXX quite sure for dx10+ hw don't need any offset hacks */
1280	if (!rscreen->use_surface_alloc) {
1281		offset = r600_texture_get_offset(rtex,
1282				level, state->cbufs[cb]->u.tex.first_layer);
1283		pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1284		slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1285		if (slice) {
1286			slice = slice - 1;
1287		}
1288		color_info = S_028C70_ARRAY_MODE(rtex->array_mode[level]);
1289		tile_split = 0;
1290		macro_aspect = 0;
1291		bankw = 0;
1292		bankh = 0;
1293		if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) {
1294			tile_type = rtex->tile_type;
1295		} else {
1296			/* workaround for linear buffers */
1297			tile_type = 1;
1298		}
1299	} else {
1300		offset = rtex->surface.level[level].offset;
1301		if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1302			offset += rtex->surface.level[level].slice_size *
1303				  state->cbufs[cb]->u.tex.first_layer;
1304		}
1305		pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1306		slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1307		if (slice) {
1308			slice = slice - 1;
1309		}
1310		color_info = 0;
1311		switch (rtex->surface.level[level].mode) {
1312		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1313			color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
1314			tile_type = 1;
1315			break;
1316		case RADEON_SURF_MODE_1D:
1317			color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_1D_TILED_THIN1);
1318			tile_type = rtex->tile_type;
1319			break;
1320		case RADEON_SURF_MODE_2D:
1321			color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_2D_TILED_THIN1);
1322			tile_type = rtex->tile_type;
1323			break;
1324		case RADEON_SURF_MODE_LINEAR:
1325		default:
1326			color_info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_GENERAL);
1327			tile_type = 1;
1328			break;
1329		}
1330		tile_split = rtex->surface.tile_split;
1331		macro_aspect = rtex->surface.mtilea;
1332		bankw = rtex->surface.bankw;
1333		bankh = rtex->surface.bankh;
1334		tile_split = eg_tile_split(tile_split);
1335		macro_aspect = eg_macro_tile_aspect(macro_aspect);
1336		bankw = eg_bank_wh(bankw);
1337		bankh = eg_bank_wh(bankh);
1338	}
1339	/* 128 bit formats require tile type = 1 */
1340	if (rscreen->chip_class == CAYMAN) {
1341		if (util_format_get_blocksize(surf->base.format) >= 16)
1342			tile_type = 1;
1343	}
1344	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1345	desc = util_format_description(surf->base.format);
1346	for (i = 0; i < 4; i++) {
1347		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1348			break;
1349		}
1350	}
1351
1352	color_attrib = S_028C74_TILE_SPLIT(tile_split)|
1353			S_028C74_NUM_BANKS(nbanks) |
1354			S_028C74_BANK_WIDTH(bankw) |
1355			S_028C74_BANK_HEIGHT(bankh) |
1356			S_028C74_MACRO_TILE_ASPECT(macro_aspect) |
1357			S_028C74_NON_DISP_TILING_ORDER(tile_type);
1358
1359	ntype = V_028C70_NUMBER_UNORM;
1360	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1361		ntype = V_028C70_NUMBER_SRGB;
1362	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1363		if (desc->channel[i].normalized)
1364			ntype = V_028C70_NUMBER_SNORM;
1365		else if (desc->channel[i].pure_integer)
1366			ntype = V_028C70_NUMBER_SINT;
1367	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1368		if (desc->channel[i].normalized)
1369			ntype = V_028C70_NUMBER_UNORM;
1370		else if (desc->channel[i].pure_integer)
1371			ntype = V_028C70_NUMBER_UINT;
1372	}
1373
1374	format = r600_translate_colorformat(surf->base.format);
1375	assert(format != ~0);
1376
1377	swap = r600_translate_colorswap(surf->base.format);
1378	assert(swap != ~0);
1379
1380	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1381		endian = ENDIAN_NONE;
1382	} else {
1383		endian = r600_colorformat_endian_swap(format);
1384	}
1385
1386	/* blend clamp should be set for all NORM/SRGB types */
1387	if (ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM ||
1388	    ntype == V_028C70_NUMBER_SRGB)
1389		blend_clamp = 1;
1390
1391	/* set blend bypass according to docs if SINT/UINT or
1392	   8/24 COLOR variants */
1393	if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1394	    format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1395	    format == V_028C70_COLOR_X24_8_32_FLOAT) {
1396		blend_clamp = 0;
1397		blend_bypass = 1;
1398	}
1399
1400	/* Alpha-test is done on the first colorbuffer only. */
1401	if (cb == 0) {
1402		alphatest_bypass = ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT;
1403		if (rctx->alphatest_state.bypass != alphatest_bypass) {
1404			rctx->alphatest_state.bypass = alphatest_bypass;
1405			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1406		}
1407	}
1408
1409	color_info |= S_028C70_FORMAT(format) |
1410		S_028C70_COMP_SWAP(swap) |
1411		S_028C70_BLEND_CLAMP(blend_clamp) |
1412		S_028C70_BLEND_BYPASS(blend_bypass) |
1413		S_028C70_NUMBER_TYPE(ntype) |
1414		S_028C70_ENDIAN(endian);
1415
1416	if (rtex->is_rat) {
1417		color_info |= S_028C70_RAT(1);
1418		color_dim = S_028C78_WIDTH_MAX(pipe_tex->width0)
1419				| S_028C78_HEIGHT_MAX(pipe_tex->height0);
1420	}
1421
1422	/* EXPORT_NORM is an optimzation that can be enabled for better
1423	 * performance in certain cases.
1424	 * EXPORT_NORM can be enabled if:
1425	 * - 11-bit or smaller UNORM/SNORM/SRGB
1426	 * - 16-bit or smaller FLOAT
1427	 */
1428	/* XXX: This should probably be the same for all CBs if we want
1429	 * useful alpha tests. */
1430	if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1431	    ((desc->channel[i].size < 12 &&
1432	      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1433	      ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) ||
1434	     (desc->channel[i].size < 17 &&
1435	      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1436		color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC);
1437	} else {
1438		rctx->export_16bpc = false;
1439	}
1440
1441	/* Alpha-test is done on the first colorbuffer only. */
1442	if (cb == 0 && rctx->alphatest_state.cb0_export_16bpc != rctx->export_16bpc) {
1443		rctx->alphatest_state.cb0_export_16bpc = rctx->export_16bpc;
1444		r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1445	}
1446
1447	/* for possible dual-src MRT */
1448	if (cb == 0 && rctx->framebuffer.nr_cbufs == 1 && !rtex->is_rat) {
1449		r600_pipe_state_add_reg_bo(rstate,
1450				R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
1451				color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1452	}
1453
1454	offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1455	offset >>= 8;
1456
1457	/* XXX handle enabling of CB beyond BASE8 which has different offset */
1458	r600_pipe_state_add_reg_bo(rstate,
1459				R_028C60_CB_COLOR0_BASE + cb * 0x3C,
1460				offset, &rtex->resource, RADEON_USAGE_READWRITE);
1461	r600_pipe_state_add_reg(rstate,
1462				R_028C78_CB_COLOR0_DIM + cb * 0x3C,
1463				color_dim);
1464	r600_pipe_state_add_reg_bo(rstate,
1465				R_028C70_CB_COLOR0_INFO + cb * 0x3C,
1466				color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1467	r600_pipe_state_add_reg(rstate,
1468				R_028C64_CB_COLOR0_PITCH + cb * 0x3C,
1469				S_028C64_PITCH_TILE_MAX(pitch));
1470	r600_pipe_state_add_reg(rstate,
1471				R_028C68_CB_COLOR0_SLICE + cb * 0x3C,
1472				S_028C68_SLICE_TILE_MAX(slice));
1473	if (!rscreen->use_surface_alloc) {
1474		r600_pipe_state_add_reg(rstate,
1475					R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1476					0x00000000);
1477	} else {
1478		if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1479			r600_pipe_state_add_reg(rstate,
1480						R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1481						0x00000000);
1482		} else {
1483			r600_pipe_state_add_reg(rstate,
1484						R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1485						S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1486						S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1487		}
1488	}
1489	r600_pipe_state_add_reg_bo(rstate,
1490				R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1491				color_attrib,
1492				&rtex->resource, RADEON_USAGE_READWRITE);
1493}
1494
1495static void evergreen_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1496			 const struct pipe_framebuffer_state *state)
1497{
1498	struct r600_screen *rscreen = rctx->screen;
1499	struct r600_resource_texture *rtex;
1500	struct r600_surface *surf;
1501	uint64_t offset;
1502	unsigned level, first_layer, pitch, slice, format, array_mode;
1503	unsigned macro_aspect, tile_split, bankh, bankw, z_info, nbanks;
1504
1505	if (state->zsbuf == NULL)
1506		return;
1507
1508	surf = (struct r600_surface *)state->zsbuf;
1509	level = surf->base.u.tex.level;
1510	rtex = (struct r600_resource_texture*)surf->base.texture;
1511	first_layer = surf->base.u.tex.first_layer;
1512	format = r600_translate_dbformat(surf->base.format);
1513	assert(format != ~0);
1514
1515	offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1516	/* XXX remove this once tiling is properly supported */
1517	if (!rscreen->use_surface_alloc) {
1518		/* XXX remove this once tiling is properly supported */
1519		array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1520				V_028C70_ARRAY_1D_TILED_THIN1;
1521
1522		offset += r600_texture_get_offset(rtex, level, first_layer);
1523		pitch = (rtex->pitch_in_blocks[level] / 8) - 1;
1524		slice = ((rtex->pitch_in_blocks[level] * surf->aligned_height) / 64);
1525		if (slice) {
1526			slice = slice - 1;
1527		}
1528		tile_split = 0;
1529		macro_aspect = 0;
1530		bankw = 0;
1531		bankh = 0;
1532	} else {
1533		offset += rtex->surface.level[level].offset;
1534		pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1535		slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1536		if (slice) {
1537			slice = slice - 1;
1538		}
1539		switch (rtex->surface.level[level].mode) {
1540		case RADEON_SURF_MODE_2D:
1541			array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
1542			break;
1543		case RADEON_SURF_MODE_1D:
1544		case RADEON_SURF_MODE_LINEAR_ALIGNED:
1545		case RADEON_SURF_MODE_LINEAR:
1546		default:
1547			array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
1548			break;
1549		}
1550		tile_split = rtex->surface.tile_split;
1551		macro_aspect = rtex->surface.mtilea;
1552		bankw = rtex->surface.bankw;
1553		bankh = rtex->surface.bankh;
1554		tile_split = eg_tile_split(tile_split);
1555		macro_aspect = eg_macro_tile_aspect(macro_aspect);
1556		bankw = eg_bank_wh(bankw);
1557		bankh = eg_bank_wh(bankh);
1558	}
1559	nbanks = eg_num_banks(rscreen->tiling_info.num_banks);
1560	offset >>= 8;
1561
1562	z_info = S_028040_ARRAY_MODE(array_mode) |
1563		 S_028040_FORMAT(format) |
1564		 S_028040_TILE_SPLIT(tile_split)|
1565		 S_028040_NUM_BANKS(nbanks) |
1566		 S_028040_BANK_WIDTH(bankw) |
1567		 S_028040_BANK_HEIGHT(bankh) |
1568		 S_028040_MACRO_TILE_ASPECT(macro_aspect);
1569
1570	r600_pipe_state_add_reg_bo(rstate, R_028048_DB_Z_READ_BASE,
1571				offset, &rtex->resource, RADEON_USAGE_READWRITE);
1572	r600_pipe_state_add_reg_bo(rstate, R_028050_DB_Z_WRITE_BASE,
1573				offset, &rtex->resource, RADEON_USAGE_READWRITE);
1574	if (!rscreen->use_surface_alloc) {
1575		r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1576					0x00000000);
1577	} else {
1578		r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW,
1579					S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1580					S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1581	}
1582
1583	if (rtex->stencil) {
1584		uint64_t stencil_offset =
1585			r600_texture_get_offset(rtex->stencil, level, first_layer);
1586		unsigned stile_split;
1587
1588		stile_split = eg_tile_split(rtex->stencil->surface.tile_split);
1589		stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1590		stencil_offset >>= 8;
1591
1592		r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1593					stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1594		r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1595					stencil_offset, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1596		r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1597					1 | S_028044_TILE_SPLIT(stile_split),
1598					&rtex->stencil->resource, RADEON_USAGE_READWRITE);
1599	} else {
1600		if (rscreen->use_surface_alloc && rtex->surface.flags & RADEON_SURF_SBUFFER) {
1601			uint64_t stencil_offset = rtex->surface.stencil_offset;
1602			unsigned stile_split = rtex->surface.stencil_tile_split;
1603
1604			stile_split = eg_tile_split(stile_split);
1605			stencil_offset += r600_resource_va(rctx->context.screen, surf->base.texture);
1606			stencil_offset += rtex->surface.level[level].offset / 4;
1607			stencil_offset >>= 8;
1608
1609			r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1610						stencil_offset, &rtex->resource,
1611						RADEON_USAGE_READWRITE);
1612			r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1613						stencil_offset, &rtex->resource,
1614						RADEON_USAGE_READWRITE);
1615			r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1616						1 | S_028044_TILE_SPLIT(stile_split),
1617						&rtex->resource,
1618						RADEON_USAGE_READWRITE);
1619		} else {
1620			r600_pipe_state_add_reg_bo(rstate, R_02804C_DB_STENCIL_READ_BASE,
1621						offset, &rtex->resource,
1622						RADEON_USAGE_READWRITE);
1623			r600_pipe_state_add_reg_bo(rstate, R_028054_DB_STENCIL_WRITE_BASE,
1624						offset, &rtex->resource,
1625						RADEON_USAGE_READWRITE);
1626			r600_pipe_state_add_reg_bo(rstate, R_028044_DB_STENCIL_INFO,
1627						1, NULL, RADEON_USAGE_READWRITE);
1628		}
1629	}
1630
1631	r600_pipe_state_add_reg_bo(rstate, R_028040_DB_Z_INFO, z_info,
1632				&rtex->resource, RADEON_USAGE_READWRITE);
1633	r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE,
1634				S_028058_PITCH_TILE_MAX(pitch));
1635	r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE,
1636				S_02805C_SLICE_TILE_MAX(slice));
1637}
1638
1639static void evergreen_set_framebuffer_state(struct pipe_context *ctx,
1640					const struct pipe_framebuffer_state *state)
1641{
1642	struct r600_context *rctx = (struct r600_context *)ctx;
1643	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1644	uint32_t tl, br;
1645	int i;
1646
1647	if (rstate == NULL)
1648		return;
1649
1650	r600_flush_framebuffer(rctx, false);
1651
1652	/* unreference old buffer and reference new one */
1653	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1654
1655	util_copy_framebuffer_state(&rctx->framebuffer, state);
1656
1657	/* build states */
1658	rctx->export_16bpc = true;
1659	rctx->nr_cbufs = state->nr_cbufs;
1660	for (i = 0; i < state->nr_cbufs; i++) {
1661		evergreen_cb(rctx, rstate, state, i);
1662	}
1663	/* CB_COLOR1_INFO is already initialized for possible dual-src blending */
1664	if (i == 1)
1665		i++;
1666	for (; i < 8 ; i++) {
1667		r600_pipe_state_add_reg(rstate, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
1668	}
1669
1670	if (state->zsbuf) {
1671		evergreen_db(rctx, rstate, state);
1672	}
1673
1674	evergreen_get_scissor_rect(rctx, 0, 0, state->width, state->height, &tl, &br);
1675
1676	r600_pipe_state_add_reg(rstate,
1677				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1678	r600_pipe_state_add_reg(rstate,
1679				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1680
1681	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1682	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1683	r600_context_pipe_state_set(rctx, rstate);
1684
1685	if (state->zsbuf) {
1686		evergreen_polygon_offset_update(rctx);
1687	}
1688
1689	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1690		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1691		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1692	}
1693}
1694
1695static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1696{
1697	struct radeon_winsys_cs *cs = rctx->cs;
1698	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1699	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1700	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1701
1702	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1703	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1704	/* Always enable the first colorbuffer in CB_SHADER_MASK. This
1705	 * will assure that the alpha-test will work even if there is
1706	 * no colorbuffer bound. */
1707	r600_write_value(cs, 0xf | (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1708}
1709
1710static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1711{
1712	struct radeon_winsys_cs *cs = rctx->cs;
1713	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1714	unsigned db_render_control = 0;
1715	unsigned db_count_control = 0;
1716	unsigned db_render_override =
1717		S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
1718		S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1719		S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1720
1721	if (a->occlusion_query_enabled) {
1722		db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1723		db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1724	}
1725	if (a->flush_depthstencil_through_cb) {
1726		db_render_control |= S_028000_DEPTH_COPY_ENABLE(1) |
1727				     S_028000_STENCIL_COPY_ENABLE(1) |
1728				     S_028000_COPY_CENTROID(1);
1729	}
1730
1731	r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1732	r600_write_value(cs, db_render_control); /* R_028000_DB_RENDER_CONTROL */
1733	r600_write_value(cs, db_count_control); /* R_028004_DB_COUNT_CONTROL */
1734	r600_write_context_reg(cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1735}
1736
1737static void evergreen_emit_vertex_buffers(struct r600_context *rctx,
1738					  struct r600_vertexbuf_state *state,
1739					  unsigned resource_offset,
1740					  unsigned pkt_flags)
1741{
1742	struct radeon_winsys_cs *cs = rctx->cs;
1743	uint32_t dirty_mask = state->dirty_mask;
1744
1745	while (dirty_mask) {
1746		struct pipe_vertex_buffer *vb;
1747		struct r600_resource *rbuffer;
1748		uint64_t va;
1749		unsigned buffer_index = u_bit_scan(&dirty_mask);
1750
1751		vb = &state->vb[buffer_index];
1752		rbuffer = (struct r600_resource*)vb->buffer;
1753		assert(rbuffer);
1754
1755		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1756		va += vb->buffer_offset;
1757
1758		/* fetch resources start at index 992 */
1759		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
1760		r600_write_value(cs, (resource_offset + buffer_index) * 8);
1761		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1762		r600_write_value(cs, rbuffer->buf->size - vb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1763		r600_write_value(cs, /* RESOURCEi_WORD2 */
1764				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1765				 S_030008_STRIDE(vb->stride) |
1766				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1767		r600_write_value(cs, /* RESOURCEi_WORD3 */
1768				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1769				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1770				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1771				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1772		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1773		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1774		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1775		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1776
1777		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0) | pkt_flags);
1778		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1779	}
1780	state->dirty_mask = 0;
1781}
1782
1783static void evergreen_fs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1784{
1785	evergreen_emit_vertex_buffers(rctx, &rctx->vertex_buffer_state, 992, 0);
1786}
1787
1788static void evergreen_cs_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom * atom)
1789{
1790	evergreen_emit_vertex_buffers(rctx, &rctx->cs_vertex_buffer_state, 816,
1791				      RADEON_CP_PACKET3_COMPUTE_MODE);
1792}
1793
1794static void evergreen_emit_constant_buffers(struct r600_context *rctx,
1795					    struct r600_constbuf_state *state,
1796					    unsigned buffer_id_base,
1797					    unsigned reg_alu_constbuf_size,
1798					    unsigned reg_alu_const_cache)
1799{
1800	struct radeon_winsys_cs *cs = rctx->cs;
1801	uint32_t dirty_mask = state->dirty_mask;
1802
1803	while (dirty_mask) {
1804		struct pipe_constant_buffer *cb;
1805		struct r600_resource *rbuffer;
1806		uint64_t va;
1807		unsigned buffer_index = ffs(dirty_mask) - 1;
1808
1809		cb = &state->cb[buffer_index];
1810		rbuffer = (struct r600_resource*)cb->buffer;
1811		assert(rbuffer);
1812
1813		va = r600_resource_va(&rctx->screen->screen, &rbuffer->b.b);
1814		va += cb->buffer_offset;
1815
1816		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1817				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1818		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, va >> 8);
1819
1820		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1821		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1822
1823		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1824		r600_write_value(cs, (buffer_id_base + buffer_index) * 8);
1825		r600_write_value(cs, va); /* RESOURCEi_WORD0 */
1826		r600_write_value(cs, rbuffer->buf->size - cb->buffer_offset - 1); /* RESOURCEi_WORD1 */
1827		r600_write_value(cs, /* RESOURCEi_WORD2 */
1828				 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) |
1829				 S_030008_STRIDE(16) |
1830				 S_030008_BASE_ADDRESS_HI(va >> 32UL));
1831		r600_write_value(cs, /* RESOURCEi_WORD3 */
1832				 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
1833				 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
1834				 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
1835				 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W));
1836		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1837		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1838		r600_write_value(cs, 0); /* RESOURCEi_WORD6 */
1839		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD7 */
1840
1841		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1842		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1843
1844		dirty_mask &= ~(1 << buffer_index);
1845	}
1846	state->dirty_mask = 0;
1847}
1848
1849static void evergreen_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1850{
1851	evergreen_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 176,
1852					R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1853					R_028980_ALU_CONST_CACHE_VS_0);
1854}
1855
1856static void evergreen_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1857{
1858	evergreen_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1859				       R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1860				       R_028940_ALU_CONST_CACHE_PS_0);
1861}
1862
1863static void evergreen_emit_sampler_views(struct r600_context *rctx,
1864					 struct r600_samplerview_state *state,
1865					 unsigned resource_id_base)
1866{
1867	struct radeon_winsys_cs *cs = rctx->cs;
1868	uint32_t dirty_mask = state->dirty_mask;
1869
1870	while (dirty_mask) {
1871		struct r600_pipe_sampler_view *rview;
1872		unsigned resource_index = u_bit_scan(&dirty_mask);
1873		unsigned reloc;
1874
1875		rview = state->views[resource_index];
1876		assert(rview);
1877
1878		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 8, 0));
1879		r600_write_value(cs, (resource_id_base + resource_index) * 8);
1880		r600_write_array(cs, 8, rview->tex_resource_words);
1881
1882		/* XXX The kernel needs two relocations. This is stupid. */
1883		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1884					      RADEON_USAGE_READ);
1885		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1886		r600_write_value(cs, reloc);
1887		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1888		r600_write_value(cs, reloc);
1889	}
1890	state->dirty_mask = 0;
1891}
1892
1893static void evergreen_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1894{
1895	evergreen_emit_sampler_views(rctx, &rctx->vs_samplers.views, 176 + R600_MAX_CONST_BUFFERS);
1896}
1897
1898static void evergreen_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1899{
1900	evergreen_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1901}
1902
1903void evergreen_init_state_functions(struct r600_context *rctx)
1904{
1905	r600_init_atom(&rctx->cb_misc_state.atom, evergreen_emit_cb_misc_state, 0, 0);
1906	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1907	r600_init_atom(&rctx->db_misc_state.atom, evergreen_emit_db_misc_state, 7, 0);
1908	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1909	r600_init_atom(&rctx->vertex_buffer_state.atom, evergreen_fs_emit_vertex_buffers, 0, 0);
1910	r600_init_atom(&rctx->cs_vertex_buffer_state.atom, evergreen_cs_emit_vertex_buffers, 0, 0);
1911	r600_init_atom(&rctx->vs_constbuf_state.atom, evergreen_emit_vs_constant_buffers, 0, 0);
1912	r600_init_atom(&rctx->ps_constbuf_state.atom, evergreen_emit_ps_constant_buffers, 0, 0);
1913	r600_init_atom(&rctx->vs_samplers.views.atom, evergreen_emit_vs_sampler_views, 0, 0);
1914	r600_init_atom(&rctx->ps_samplers.views.atom, evergreen_emit_ps_sampler_views, 0, 0);
1915	r600_init_atom(&rctx->cs_shader_state.atom, evergreen_emit_cs_shader, 0, 0);
1916
1917	rctx->context.create_blend_state = evergreen_create_blend_state;
1918	rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state;
1919	rctx->context.create_fs_state = r600_create_shader_state_ps;
1920	rctx->context.create_rasterizer_state = evergreen_create_rs_state;
1921	rctx->context.create_sampler_state = evergreen_create_sampler_state;
1922	rctx->context.create_sampler_view = evergreen_create_sampler_view;
1923	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1924	rctx->context.create_vs_state = r600_create_shader_state_vs;
1925	rctx->context.bind_blend_state = r600_bind_blend_state;
1926	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1927	rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_samplers;
1928	rctx->context.bind_fs_state = r600_bind_ps_shader;
1929	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1930	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1931	rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_samplers;
1932	rctx->context.bind_vs_state = r600_bind_vs_shader;
1933	rctx->context.delete_blend_state = r600_delete_state;
1934	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1935	rctx->context.delete_fs_state = r600_delete_ps_shader;
1936	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1937	rctx->context.delete_sampler_state = r600_delete_state;
1938	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1939	rctx->context.delete_vs_state = r600_delete_vs_shader;
1940	rctx->context.set_blend_color = r600_set_blend_color;
1941	rctx->context.set_clip_state = evergreen_set_clip_state;
1942	rctx->context.set_constant_buffer = r600_set_constant_buffer;
1943	rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_views;
1944	rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state;
1945	rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple;
1946	rctx->context.set_sample_mask = evergreen_set_sample_mask;
1947	rctx->context.set_scissor_state = evergreen_set_scissor_state;
1948	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1949	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1950	rctx->context.set_index_buffer = r600_set_index_buffer;
1951	rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_views;
1952	rctx->context.set_viewport_state = evergreen_set_viewport_state;
1953	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1954	rctx->context.texture_barrier = r600_texture_barrier;
1955	rctx->context.create_stream_output_target = r600_create_so_target;
1956	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1957	rctx->context.set_stream_output_targets = r600_set_so_targets;
1958	evergreen_init_compute_state_functions(rctx);
1959}
1960
1961static void cayman_init_atom_start_cs(struct r600_context *rctx)
1962{
1963	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1964
1965	r600_init_command_buffer(cb, 256, EMIT_EARLY);
1966
1967	/* This must be first. */
1968	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1969	r600_store_value(cb, 0x80000000);
1970	r600_store_value(cb, 0x80000000);
1971
1972	r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
1973	r600_store_value(cb, S_008C00_EXPORT_SRC_C(1)); /* R_008C00_SQ_CONFIG */
1974	/* always set the temp clauses */
1975	r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(4)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
1976
1977	r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
1978	r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
1979	r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
1980
1981	r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
1982
1983	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
1984
1985	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
1986	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
1987	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
1988	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
1989	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
1990	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
1991	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
1992	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
1993	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
1994	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
1995	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
1996	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
1997	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
1998	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
1999
2000	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2001	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2002	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2003
2004	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2005	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2006	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2007
2008	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2009
2010	r600_store_context_reg(cb, CM_R_028AA8_IA_MULTI_VGT_PARAM, S_028AA8_SWITCH_ON_EOP(1) | S_028AA8_PARTIAL_VS_WAVE_ON(1) | S_028AA8_PRIMGROUP_SIZE(63));
2011
2012	r600_store_context_reg_seq(cb, CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0, 2);
2013	r600_store_value(cb, 0x76543210); /* CM_R_028BD4_PA_SC_CENTROID_PRIORITY_0 */
2014	r600_store_value(cb, 0xfedcba98); /* CM_R_028BD8_PA_SC_CENTROID_PRIORITY_1 */
2015
2016	r600_store_context_reg_seq(cb, CM_R_0288E8_SQ_LDS_ALLOC, 2);
2017	r600_store_value(cb, 0); /* CM_R_0288E8_SQ_LDS_ALLOC */
2018	r600_store_value(cb, 0); /* R_0288EC_SQ_LDS_ALLOC_PS */
2019
2020	r600_store_context_reg(cb, CM_R_028804_DB_EQAA, 0x110000);
2021
2022	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2023	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2024	r600_store_value(cb, 0);
2025	r600_store_value(cb, 0);
2026	r600_store_value(cb, 0);
2027	r600_store_value(cb, 0);
2028	r600_store_value(cb, 0);
2029	r600_store_value(cb, 0);
2030	r600_store_value(cb, 0);
2031	r600_store_value(cb, 0);
2032	r600_store_value(cb, 0);
2033	r600_store_value(cb, 0);
2034	r600_store_value(cb, 0);
2035	r600_store_value(cb, 0);
2036	r600_store_value(cb, 0);
2037	r600_store_value(cb, 0);
2038	r600_store_value(cb, 0);
2039	r600_store_value(cb, 0);
2040	r600_store_value(cb, 0);
2041	r600_store_value(cb, 0);
2042	r600_store_value(cb, 0);
2043	r600_store_value(cb, 0);
2044	r600_store_value(cb, 0);
2045	r600_store_value(cb, 0);
2046	r600_store_value(cb, 0);
2047	r600_store_value(cb, 0);
2048	r600_store_value(cb, 0);
2049	r600_store_value(cb, 0);
2050	r600_store_value(cb, 0);
2051	r600_store_value(cb, 0);
2052	r600_store_value(cb, 0);
2053	r600_store_value(cb, 0);
2054	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2055	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2056	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2057
2058	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2059
2060	r600_store_context_reg_seq(cb, CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2061	r600_store_value(cb, ~0); /* CM_R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0 */
2062	r600_store_value(cb, ~0); /* CM_R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1 */
2063
2064	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2065	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2066	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2067
2068	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2069
2070	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2071	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2072	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2073	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2074
2075	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2076	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2077
2078	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2079	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2080	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2081
2082	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2083	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2084	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2085	r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2086
2087	r600_store_context_reg_seq(cb, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
2088	r600_store_value(cb, 0x00000400); /* CM_R_028BDC_PA_SC_LINE_CNTL */
2089	r600_store_value(cb, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
2090
2091	r600_store_context_reg_seq(cb, CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
2092	r600_store_value(cb, 0x3F800000); /* CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
2093	r600_store_value(cb, 0x3F800000); /* CM_R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
2094	r600_store_value(cb, 0x3F800000); /* CM_R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
2095	r600_store_value(cb, 0x3F800000); /* CM_R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
2096
2097	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2098	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2099	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2100
2101	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2102	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2103	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2104
2105	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2106	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2107	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2108
2109	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2110	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2111	if (rctx->screen->has_streamout) {
2112		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2113	}
2114
2115	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2116	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2117}
2118
2119void evergreen_init_atom_start_cs(struct r600_context *rctx)
2120{
2121	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2122	int ps_prio;
2123	int vs_prio;
2124	int gs_prio;
2125	int es_prio;
2126	int hs_prio, cs_prio, ls_prio;
2127	int num_ps_gprs;
2128	int num_vs_gprs;
2129	int num_gs_gprs;
2130	int num_es_gprs;
2131	int num_hs_gprs;
2132	int num_ls_gprs;
2133	int num_temp_gprs;
2134	int num_ps_threads;
2135	int num_vs_threads;
2136	int num_gs_threads;
2137	int num_es_threads;
2138	int num_hs_threads;
2139	int num_ls_threads;
2140	int num_ps_stack_entries;
2141	int num_vs_stack_entries;
2142	int num_gs_stack_entries;
2143	int num_es_stack_entries;
2144	int num_hs_stack_entries;
2145	int num_ls_stack_entries;
2146	enum radeon_family family;
2147	unsigned tmp;
2148
2149	if (rctx->chip_class == CAYMAN) {
2150		cayman_init_atom_start_cs(rctx);
2151		return;
2152	}
2153
2154	r600_init_command_buffer(cb, 256, EMIT_EARLY);
2155
2156	/* This must be first. */
2157	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2158	r600_store_value(cb, 0x80000000);
2159	r600_store_value(cb, 0x80000000);
2160
2161	family = rctx->family;
2162	ps_prio = 0;
2163	vs_prio = 1;
2164	gs_prio = 2;
2165	es_prio = 3;
2166	hs_prio = 0;
2167	ls_prio = 0;
2168	cs_prio = 0;
2169
2170	switch (family) {
2171	case CHIP_CEDAR:
2172	default:
2173		num_ps_gprs = 93;
2174		num_vs_gprs = 46;
2175		num_temp_gprs = 4;
2176		num_gs_gprs = 31;
2177		num_es_gprs = 31;
2178		num_hs_gprs = 23;
2179		num_ls_gprs = 23;
2180		num_ps_threads = 96;
2181		num_vs_threads = 16;
2182		num_gs_threads = 16;
2183		num_es_threads = 16;
2184		num_hs_threads = 16;
2185		num_ls_threads = 16;
2186		num_ps_stack_entries = 42;
2187		num_vs_stack_entries = 42;
2188		num_gs_stack_entries = 42;
2189		num_es_stack_entries = 42;
2190		num_hs_stack_entries = 42;
2191		num_ls_stack_entries = 42;
2192		break;
2193	case CHIP_REDWOOD:
2194		num_ps_gprs = 93;
2195		num_vs_gprs = 46;
2196		num_temp_gprs = 4;
2197		num_gs_gprs = 31;
2198		num_es_gprs = 31;
2199		num_hs_gprs = 23;
2200		num_ls_gprs = 23;
2201		num_ps_threads = 128;
2202		num_vs_threads = 20;
2203		num_gs_threads = 20;
2204		num_es_threads = 20;
2205		num_hs_threads = 20;
2206		num_ls_threads = 20;
2207		num_ps_stack_entries = 42;
2208		num_vs_stack_entries = 42;
2209		num_gs_stack_entries = 42;
2210		num_es_stack_entries = 42;
2211		num_hs_stack_entries = 42;
2212		num_ls_stack_entries = 42;
2213		break;
2214	case CHIP_JUNIPER:
2215		num_ps_gprs = 93;
2216		num_vs_gprs = 46;
2217		num_temp_gprs = 4;
2218		num_gs_gprs = 31;
2219		num_es_gprs = 31;
2220		num_hs_gprs = 23;
2221		num_ls_gprs = 23;
2222		num_ps_threads = 128;
2223		num_vs_threads = 20;
2224		num_gs_threads = 20;
2225		num_es_threads = 20;
2226		num_hs_threads = 20;
2227		num_ls_threads = 20;
2228		num_ps_stack_entries = 85;
2229		num_vs_stack_entries = 85;
2230		num_gs_stack_entries = 85;
2231		num_es_stack_entries = 85;
2232		num_hs_stack_entries = 85;
2233		num_ls_stack_entries = 85;
2234		break;
2235	case CHIP_CYPRESS:
2236	case CHIP_HEMLOCK:
2237		num_ps_gprs = 93;
2238		num_vs_gprs = 46;
2239		num_temp_gprs = 4;
2240		num_gs_gprs = 31;
2241		num_es_gprs = 31;
2242		num_hs_gprs = 23;
2243		num_ls_gprs = 23;
2244		num_ps_threads = 128;
2245		num_vs_threads = 20;
2246		num_gs_threads = 20;
2247		num_es_threads = 20;
2248		num_hs_threads = 20;
2249		num_ls_threads = 20;
2250		num_ps_stack_entries = 85;
2251		num_vs_stack_entries = 85;
2252		num_gs_stack_entries = 85;
2253		num_es_stack_entries = 85;
2254		num_hs_stack_entries = 85;
2255		num_ls_stack_entries = 85;
2256		break;
2257	case CHIP_PALM:
2258		num_ps_gprs = 93;
2259		num_vs_gprs = 46;
2260		num_temp_gprs = 4;
2261		num_gs_gprs = 31;
2262		num_es_gprs = 31;
2263		num_hs_gprs = 23;
2264		num_ls_gprs = 23;
2265		num_ps_threads = 96;
2266		num_vs_threads = 16;
2267		num_gs_threads = 16;
2268		num_es_threads = 16;
2269		num_hs_threads = 16;
2270		num_ls_threads = 16;
2271		num_ps_stack_entries = 42;
2272		num_vs_stack_entries = 42;
2273		num_gs_stack_entries = 42;
2274		num_es_stack_entries = 42;
2275		num_hs_stack_entries = 42;
2276		num_ls_stack_entries = 42;
2277		break;
2278	case CHIP_SUMO:
2279		num_ps_gprs = 93;
2280		num_vs_gprs = 46;
2281		num_temp_gprs = 4;
2282		num_gs_gprs = 31;
2283		num_es_gprs = 31;
2284		num_hs_gprs = 23;
2285		num_ls_gprs = 23;
2286		num_ps_threads = 96;
2287		num_vs_threads = 25;
2288		num_gs_threads = 25;
2289		num_es_threads = 25;
2290		num_hs_threads = 25;
2291		num_ls_threads = 25;
2292		num_ps_stack_entries = 42;
2293		num_vs_stack_entries = 42;
2294		num_gs_stack_entries = 42;
2295		num_es_stack_entries = 42;
2296		num_hs_stack_entries = 42;
2297		num_ls_stack_entries = 42;
2298		break;
2299	case CHIP_SUMO2:
2300		num_ps_gprs = 93;
2301		num_vs_gprs = 46;
2302		num_temp_gprs = 4;
2303		num_gs_gprs = 31;
2304		num_es_gprs = 31;
2305		num_hs_gprs = 23;
2306		num_ls_gprs = 23;
2307		num_ps_threads = 96;
2308		num_vs_threads = 25;
2309		num_gs_threads = 25;
2310		num_es_threads = 25;
2311		num_hs_threads = 25;
2312		num_ls_threads = 25;
2313		num_ps_stack_entries = 85;
2314		num_vs_stack_entries = 85;
2315		num_gs_stack_entries = 85;
2316		num_es_stack_entries = 85;
2317		num_hs_stack_entries = 85;
2318		num_ls_stack_entries = 85;
2319		break;
2320	case CHIP_BARTS:
2321		num_ps_gprs = 93;
2322		num_vs_gprs = 46;
2323		num_temp_gprs = 4;
2324		num_gs_gprs = 31;
2325		num_es_gprs = 31;
2326		num_hs_gprs = 23;
2327		num_ls_gprs = 23;
2328		num_ps_threads = 128;
2329		num_vs_threads = 20;
2330		num_gs_threads = 20;
2331		num_es_threads = 20;
2332		num_hs_threads = 20;
2333		num_ls_threads = 20;
2334		num_ps_stack_entries = 85;
2335		num_vs_stack_entries = 85;
2336		num_gs_stack_entries = 85;
2337		num_es_stack_entries = 85;
2338		num_hs_stack_entries = 85;
2339		num_ls_stack_entries = 85;
2340		break;
2341	case CHIP_TURKS:
2342		num_ps_gprs = 93;
2343		num_vs_gprs = 46;
2344		num_temp_gprs = 4;
2345		num_gs_gprs = 31;
2346		num_es_gprs = 31;
2347		num_hs_gprs = 23;
2348		num_ls_gprs = 23;
2349		num_ps_threads = 128;
2350		num_vs_threads = 20;
2351		num_gs_threads = 20;
2352		num_es_threads = 20;
2353		num_hs_threads = 20;
2354		num_ls_threads = 20;
2355		num_ps_stack_entries = 42;
2356		num_vs_stack_entries = 42;
2357		num_gs_stack_entries = 42;
2358		num_es_stack_entries = 42;
2359		num_hs_stack_entries = 42;
2360		num_ls_stack_entries = 42;
2361		break;
2362	case CHIP_CAICOS:
2363		num_ps_gprs = 93;
2364		num_vs_gprs = 46;
2365		num_temp_gprs = 4;
2366		num_gs_gprs = 31;
2367		num_es_gprs = 31;
2368		num_hs_gprs = 23;
2369		num_ls_gprs = 23;
2370		num_ps_threads = 128;
2371		num_vs_threads = 10;
2372		num_gs_threads = 10;
2373		num_es_threads = 10;
2374		num_hs_threads = 10;
2375		num_ls_threads = 10;
2376		num_ps_stack_entries = 42;
2377		num_vs_stack_entries = 42;
2378		num_gs_stack_entries = 42;
2379		num_es_stack_entries = 42;
2380		num_hs_stack_entries = 42;
2381		num_ls_stack_entries = 42;
2382		break;
2383	}
2384
2385	tmp = 0;
2386	switch (family) {
2387	case CHIP_CEDAR:
2388	case CHIP_PALM:
2389	case CHIP_SUMO:
2390	case CHIP_SUMO2:
2391	case CHIP_CAICOS:
2392		break;
2393	default:
2394		tmp |= S_008C00_VC_ENABLE(1);
2395		break;
2396	}
2397	tmp |= S_008C00_EXPORT_SRC_C(1);
2398	tmp |= S_008C00_CS_PRIO(cs_prio);
2399	tmp |= S_008C00_LS_PRIO(ls_prio);
2400	tmp |= S_008C00_HS_PRIO(hs_prio);
2401	tmp |= S_008C00_PS_PRIO(ps_prio);
2402	tmp |= S_008C00_VS_PRIO(vs_prio);
2403	tmp |= S_008C00_GS_PRIO(gs_prio);
2404	tmp |= S_008C00_ES_PRIO(es_prio);
2405
2406	/* enable dynamic GPR resource management */
2407	if (rctx->screen->info.drm_minor >= 7) {
2408		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 2);
2409		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2410		/* always set temp clauses */
2411		r600_store_value(cb, S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2412		r600_store_config_reg_seq(cb, R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1, 2);
2413		r600_store_value(cb, 0); /* R_008C10_SQ_GLOBAL_GPR_RESOURCE_MGMT_1 */
2414		r600_store_value(cb, 0); /* R_008C14_SQ_GLOBAL_GPR_RESOURCE_MGMT_2 */
2415		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8));
2416		r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1,
2417					S_028838_PS_GPRS(0x1e) |
2418					S_028838_VS_GPRS(0x1e) |
2419					S_028838_GS_GPRS(0x1e) |
2420					S_028838_ES_GPRS(0x1e) |
2421					S_028838_HS_GPRS(0x1e) |
2422					S_028838_LS_GPRS(0x1e)); /* workaround for hw issues with dyn gpr - must set all limits to 240 instead of 0, 0x1e == 240 / 8*/
2423	} else {
2424		r600_store_config_reg_seq(cb, R_008C00_SQ_CONFIG, 4);
2425		r600_store_value(cb, tmp); /* R_008C00_SQ_CONFIG */
2426
2427		tmp = S_008C04_NUM_PS_GPRS(num_ps_gprs);
2428		tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2429		tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2430		r600_store_value(cb, tmp); /* R_008C04_SQ_GPR_RESOURCE_MGMT_1 */
2431
2432		tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2433		tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2434		r600_store_value(cb, tmp); /* R_008C08_SQ_GPR_RESOURCE_MGMT_2 */
2435
2436		tmp = S_008C0C_NUM_HS_GPRS(num_hs_gprs);
2437		tmp |= S_008C0C_NUM_HS_GPRS(num_ls_gprs);
2438		r600_store_value(cb, tmp); /* R_008C0C_SQ_GPR_RESOURCE_MGMT_3 */
2439	}
2440
2441	tmp = S_008C18_NUM_PS_THREADS(num_ps_threads);
2442	tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads);
2443	tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads);
2444	tmp |= S_008C18_NUM_ES_THREADS(num_es_threads);
2445	r600_store_config_reg_seq(cb, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, 5);
2446	r600_store_value(cb, tmp); /* R_008C18_SQ_THREAD_RESOURCE_MGMT_1 */
2447
2448	tmp = S_008C1C_NUM_HS_THREADS(num_hs_threads);
2449	tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads);
2450	r600_store_value(cb, tmp); /* R_008C1C_SQ_THREAD_RESOURCE_MGMT_2 */
2451
2452	tmp = S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2453	tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2454	r600_store_value(cb, tmp); /* R_008C20_SQ_STACK_RESOURCE_MGMT_1 */
2455
2456	tmp = S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2457	tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2458	r600_store_value(cb, tmp); /* R_008C24_SQ_STACK_RESOURCE_MGMT_2 */
2459
2460	tmp = S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries);
2461	tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries);
2462	r600_store_value(cb, tmp); /* R_008C28_SQ_STACK_RESOURCE_MGMT_3 */
2463
2464	r600_store_config_reg(cb, R_008E2C_SQ_LDS_RESOURCE_MGMT,
2465			      S_008E2C_NUM_PS_LDS(0x1000) | S_008E2C_NUM_LS_LDS(0x1000));
2466
2467	r600_store_config_reg(cb, R_009100_SPI_CONFIG_CNTL, 0);
2468	r600_store_config_reg(cb, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4));
2469
2470	r600_store_context_reg(cb, R_028A4C_PA_SC_MODE_CNTL_1, 0);
2471
2472	r600_store_context_reg_seq(cb, R_028900_SQ_ESGS_RING_ITEMSIZE, 6);
2473	r600_store_value(cb, 0); /* R_028900_SQ_ESGS_RING_ITEMSIZE */
2474	r600_store_value(cb, 0); /* R_028904_SQ_GSVS_RING_ITEMSIZE */
2475	r600_store_value(cb, 0); /* R_028908_SQ_ESTMP_RING_ITEMSIZE */
2476	r600_store_value(cb, 0); /* R_02890C_SQ_GSTMP_RING_ITEMSIZE */
2477	r600_store_value(cb, 0); /* R_028910_SQ_VSTMP_RING_ITEMSIZE */
2478	r600_store_value(cb, 0); /* R_028914_SQ_PSTMP_RING_ITEMSIZE */
2479
2480	r600_store_context_reg_seq(cb, R_02891C_SQ_GS_VERT_ITEMSIZE, 4);
2481	r600_store_value(cb, 0); /* R_02891C_SQ_GS_VERT_ITEMSIZE */
2482	r600_store_value(cb, 0); /* R_028920_SQ_GS_VERT_ITEMSIZE_1 */
2483	r600_store_value(cb, 0); /* R_028924_SQ_GS_VERT_ITEMSIZE_2 */
2484	r600_store_value(cb, 0); /* R_028928_SQ_GS_VERT_ITEMSIZE_3 */
2485
2486	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2487	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2488	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2489	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2490	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2491	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2492	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2493	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2494	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2495	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2496	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2497	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2498	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2499	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE */
2500
2501	r600_store_context_reg_seq(cb, R_028B94_VGT_STRMOUT_CONFIG, 2);
2502	r600_store_value(cb, 0); /* R_028B94_VGT_STRMOUT_CONFIG */
2503	r600_store_value(cb, 0); /* R_028B98_VGT_STRMOUT_BUFFER_CONFIG */
2504
2505	r600_store_context_reg_seq(cb, R_028AB4_VGT_REUSE_OFF, 2);
2506	r600_store_value(cb, 0); /* R_028AB4_VGT_REUSE_OFF */
2507	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2508
2509	r600_store_config_reg(cb, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2510
2511	r600_store_context_reg_seq(cb, R_028380_SQ_VTX_SEMANTIC_0, 34);
2512	r600_store_value(cb, 0); /* R_028380_SQ_VTX_SEMANTIC_0 */
2513	r600_store_value(cb, 0);
2514	r600_store_value(cb, 0);
2515	r600_store_value(cb, 0);
2516	r600_store_value(cb, 0);
2517	r600_store_value(cb, 0);
2518	r600_store_value(cb, 0);
2519	r600_store_value(cb, 0);
2520	r600_store_value(cb, 0);
2521	r600_store_value(cb, 0);
2522	r600_store_value(cb, 0);
2523	r600_store_value(cb, 0);
2524	r600_store_value(cb, 0);
2525	r600_store_value(cb, 0);
2526	r600_store_value(cb, 0);
2527	r600_store_value(cb, 0);
2528	r600_store_value(cb, 0);
2529	r600_store_value(cb, 0);
2530	r600_store_value(cb, 0);
2531	r600_store_value(cb, 0);
2532	r600_store_value(cb, 0);
2533	r600_store_value(cb, 0);
2534	r600_store_value(cb, 0);
2535	r600_store_value(cb, 0);
2536	r600_store_value(cb, 0);
2537	r600_store_value(cb, 0);
2538	r600_store_value(cb, 0);
2539	r600_store_value(cb, 0);
2540	r600_store_value(cb, 0);
2541	r600_store_value(cb, 0);
2542	r600_store_value(cb, 0);
2543	r600_store_value(cb, 0); /* R_0283FC_SQ_VTX_SEMANTIC_31 */
2544	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2545	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2546
2547	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2548
2549	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2550	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2551	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2552
2553	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2554	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2555	r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2556
2557	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2558	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2559	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2560
2561	r600_store_context_reg(cb, R_0286DC_SPI_FOG_CNTL, 0);
2562	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
2563	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2564
2565	r600_store_context_reg_seq(cb, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 3);
2566	r600_store_value(cb, 0); /* R_028AC0_DB_SRESULTS_COMPARE_STATE0 */
2567	r600_store_value(cb, 0); /* R_028AC4_DB_SRESULTS_COMPARE_STATE1 */
2568	r600_store_value(cb, 0); /* R_028AC8_DB_PRELOAD_CONTROL */
2569
2570	r600_store_context_reg(cb, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
2571
2572	r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2573	r600_store_value(cb, 0x00000400); /* R_028C00_PA_SC_LINE_CNTL */
2574	r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2575
2576	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 5);
2577	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2578	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2579	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2580	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2581	r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_0 */
2582
2583	r600_store_context_reg(cb, R_028C3C_PA_SC_AA_MASK, ~0);
2584
2585	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2586	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2587	r600_store_value(cb, S_028244_BR_X(16384) | S_028244_BR_Y(16384)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2588
2589	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2590	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2591	r600_store_value(cb, S_028034_BR_X(16384) | S_028034_BR_Y(16384)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2592
2593	r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2594	r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN));
2595	r600_store_context_reg(cb, R_0288A8_SQ_PGM_RESOURCES_FS, 0);
2596
2597	r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2598	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2599	if (rctx->screen->has_streamout) {
2600		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2601	}
2602
2603	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
2604	eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF);
2605}
2606
2607void evergreen_polygon_offset_update(struct r600_context *rctx)
2608{
2609	struct r600_pipe_state state;
2610
2611	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
2612	state.nregs = 0;
2613	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
2614		float offset_units = rctx->rasterizer->offset_units;
2615		unsigned offset_db_fmt_cntl = 0, depth;
2616
2617		switch (rctx->framebuffer.zsbuf->format) {
2618		case PIPE_FORMAT_Z24X8_UNORM:
2619		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2620			depth = -24;
2621			offset_units *= 2.0f;
2622			break;
2623		case PIPE_FORMAT_Z32_FLOAT:
2624		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2625			depth = -23;
2626			offset_units *= 1.0f;
2627			offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2628			break;
2629		case PIPE_FORMAT_Z16_UNORM:
2630			depth = -16;
2631			offset_units *= 4.0f;
2632			break;
2633		default:
2634			return;
2635		}
2636		/* XXX some of those reg can be computed with cso */
2637		offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
2638		r600_pipe_state_add_reg(&state,
2639				R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
2640				fui(rctx->rasterizer->offset_scale));
2641		r600_pipe_state_add_reg(&state,
2642				R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
2643				fui(offset_units));
2644		r600_pipe_state_add_reg(&state,
2645				R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
2646				fui(rctx->rasterizer->offset_scale));
2647		r600_pipe_state_add_reg(&state,
2648				R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
2649				fui(offset_units));
2650		r600_pipe_state_add_reg(&state,
2651				R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2652				offset_db_fmt_cntl);
2653		r600_context_pipe_state_set(rctx, &state);
2654	}
2655}
2656
2657void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2658{
2659	struct r600_context *rctx = (struct r600_context *)ctx;
2660	struct r600_pipe_state *rstate = &shader->rstate;
2661	struct r600_shader *rshader = &shader->shader;
2662	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2663	int pos_index = -1, face_index = -1;
2664	int ninterp = 0;
2665	boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
2666	unsigned spi_baryc_cntl, sid, tmp, idx = 0;
2667	unsigned z_export = 0, stencil_export = 0;
2668
2669	rstate->nregs = 0;
2670
2671	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2672	for (i = 0; i < rshader->ninput; i++) {
2673		/* evergreen NUM_INTERP only contains values interpolated into the LDS,
2674		   POSITION goes via GPRs from the SC so isn't counted */
2675		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2676			pos_index = i;
2677		else if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2678			face_index = i;
2679		else {
2680			ninterp++;
2681			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
2682				have_linear = TRUE;
2683			if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE)
2684				have_perspective = TRUE;
2685			if (rshader->input[i].centroid)
2686				have_centroid = TRUE;
2687		}
2688
2689		sid = rshader->input[i].spi_sid;
2690
2691		if (sid) {
2692
2693			tmp = S_028644_SEMANTIC(sid);
2694
2695			if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2696				rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2697				(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2698					rctx->rasterizer && rctx->rasterizer->flatshade)) {
2699				tmp |= S_028644_FLAT_SHADE(1);
2700			}
2701
2702			if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2703					(rctx->sprite_coord_enable & (1 << rshader->input[i].sid))) {
2704				tmp |= S_028644_PT_SPRITE_TEX(1);
2705			}
2706
2707			r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + idx * 4,
2708					tmp);
2709
2710			idx++;
2711		}
2712	}
2713
2714	for (i = 0; i < rshader->noutput; i++) {
2715		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2716			z_export = 1;
2717		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2718			stencil_export = 1;
2719	}
2720	if (rshader->uses_kill)
2721		db_shader_control |= S_02880C_KILL_ENABLE(1);
2722
2723	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2724	db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(stencil_export);
2725
2726	exports_ps = 0;
2727	for (i = 0; i < rshader->noutput; i++) {
2728		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2729		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2730			exports_ps |= 1;
2731	}
2732
2733	num_cout = rshader->nr_ps_color_exports;
2734
2735	exports_ps |= S_02884C_EXPORT_COLORS(num_cout);
2736	if (!exports_ps) {
2737		/* always at least export 1 component per pixel */
2738		exports_ps = 2;
2739	}
2740	shader->nr_ps_color_outputs = num_cout;
2741	if (ninterp == 0) {
2742		ninterp = 1;
2743		have_perspective = TRUE;
2744	}
2745
2746	if (!have_perspective && !have_linear)
2747		have_perspective = TRUE;
2748
2749	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) |
2750		              S_0286CC_PERSP_GRADIENT_ENA(have_perspective) |
2751		              S_0286CC_LINEAR_GRADIENT_ENA(have_linear);
2752	spi_input_z = 0;
2753	if (pos_index != -1) {
2754		spi_ps_in_control_0 |=  S_0286CC_POSITION_ENA(1) |
2755			S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2756			S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr);
2757		spi_input_z |= 1;
2758	}
2759
2760	spi_ps_in_control_1 = 0;
2761	if (face_index != -1) {
2762		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2763			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2764	}
2765
2766	spi_baryc_cntl = 0;
2767	if (have_perspective)
2768		spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) |
2769				  S_0286E0_PERSP_CENTROID_ENA(have_centroid);
2770	if (have_linear)
2771		spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
2772				  S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
2773
2774	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
2775				spi_ps_in_control_0);
2776	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
2777				spi_ps_in_control_1);
2778	r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2,
2779				0);
2780	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2781	r600_pipe_state_add_reg(rstate,
2782				R_0286E0_SPI_BARYC_CNTL,
2783				spi_baryc_cntl);
2784
2785	r600_pipe_state_add_reg_bo(rstate,
2786				R_028840_SQ_PGM_START_PS,
2787				r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2788				shader->bo, RADEON_USAGE_READ);
2789	r600_pipe_state_add_reg(rstate,
2790				R_028844_SQ_PGM_RESOURCES_PS,
2791				S_028844_NUM_GPRS(rshader->bc.ngpr) |
2792				S_028844_PRIME_CACHE_ON_DRAW(1) |
2793				S_028844_STACK_SIZE(rshader->bc.nstack));
2794	r600_pipe_state_add_reg(rstate,
2795				R_02884C_SQ_PGM_EXPORTS_PS,
2796				exports_ps);
2797
2798	shader->db_shader_control = db_shader_control;
2799	shader->ps_depth_export = z_export | stencil_export;
2800
2801	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2802	if (rctx->rasterizer)
2803		shader->flatshade = rctx->rasterizer->flatshade;
2804}
2805
2806void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2807{
2808	struct r600_context *rctx = (struct r600_context *)ctx;
2809	struct r600_pipe_state *rstate = &shader->rstate;
2810	struct r600_shader *rshader = &shader->shader;
2811	unsigned spi_vs_out_id[10] = {};
2812	unsigned i, tmp, nparams = 0;
2813
2814	/* clear previous register */
2815	rstate->nregs = 0;
2816
2817	for (i = 0; i < rshader->noutput; i++) {
2818		if (rshader->output[i].spi_sid) {
2819			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2820			spi_vs_out_id[nparams / 4] |= tmp;
2821			nparams++;
2822		}
2823	}
2824
2825	for (i = 0; i < 10; i++) {
2826		r600_pipe_state_add_reg(rstate,
2827					R_02861C_SPI_VS_OUT_ID_0 + i * 4,
2828					spi_vs_out_id[i]);
2829	}
2830
2831	/* Certain attributes (position, psize, etc.) don't count as params.
2832	 * VS is required to export at least one param and r600_shader_from_tgsi()
2833	 * takes care of adding a dummy export.
2834	 */
2835	if (nparams < 1)
2836		nparams = 1;
2837
2838	r600_pipe_state_add_reg(rstate,
2839			R_0286C4_SPI_VS_OUT_CONFIG,
2840			S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2841	r600_pipe_state_add_reg(rstate,
2842			R_028860_SQ_PGM_RESOURCES_VS,
2843			S_028860_NUM_GPRS(rshader->bc.ngpr) |
2844			S_028860_STACK_SIZE(rshader->bc.nstack));
2845	r600_pipe_state_add_reg_bo(rstate,
2846			R_02885C_SQ_PGM_START_VS,
2847			r600_resource_va(ctx->screen, (void *)shader->bo) >> 8,
2848			shader->bo, RADEON_USAGE_READ);
2849
2850	shader->pa_cl_vs_out_cntl =
2851		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2852		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2853		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2854		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2855}
2856
2857void evergreen_fetch_shader(struct pipe_context *ctx,
2858			    struct r600_vertex_element *ve)
2859{
2860	struct r600_context *rctx = (struct r600_context *)ctx;
2861	struct r600_pipe_state *rstate = &ve->rstate;
2862	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2863	rstate->nregs = 0;
2864	r600_pipe_state_add_reg_bo(rstate, R_0288A4_SQ_PGM_START_FS,
2865				r600_resource_va(ctx->screen, (void *)ve->fetch_shader) >> 8,
2866				ve->fetch_shader, RADEON_USAGE_READ);
2867}
2868
2869void *evergreen_create_db_flush_dsa(struct r600_context *rctx)
2870{
2871	struct pipe_depth_stencil_alpha_state dsa = {{0}};
2872
2873	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2874}
2875
2876void evergreen_update_dual_export_state(struct r600_context * rctx)
2877{
2878	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2879			!rctx->ps_shader->current->ps_depth_export;
2880
2881	unsigned db_source_format = dual_export ? V_02880C_EXPORT_DB_TWO :
2882			V_02880C_EXPORT_DB_FULL;
2883
2884	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2885			S_02880C_DUAL_EXPORT_ENABLE(dual_export) |
2886			S_02880C_DB_SOURCE_FORMAT(db_source_format);
2887
2888	if (db_shader_control != rctx->db_shader_control) {
2889		struct r600_pipe_state rstate;
2890
2891		rctx->db_shader_control = db_shader_control;
2892
2893		rstate.nregs = 0;
2894		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2895		r600_context_pipe_state_set(rctx, &rstate);
2896	}
2897}
2898