evergreen_state.c revision d931b0d8b360fc0222d295eca38aaee3e4e5d0be
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24/* TODO: 25 * - fix mask for depth control & cull for query 26 */ 27#include <stdio.h> 28#include <errno.h> 29#include <pipe/p_defines.h> 30#include <pipe/p_state.h> 31#include <pipe/p_context.h> 32#include <tgsi/tgsi_scan.h> 33#include <tgsi/tgsi_parse.h> 34#include <tgsi/tgsi_util.h> 35#include <util/u_blitter.h> 36#include <util/u_double_list.h> 37#include <util/u_transfer.h> 38#include <util/u_surface.h> 39#include <util/u_pack_color.h> 40#include <util/u_memory.h> 41#include <util/u_inlines.h> 42#include <util/u_framebuffer.h> 43#include <pipebuffer/pb_buffer.h> 44#include "r600.h" 45#include "evergreend.h" 46#include "r600_resource.h" 47#include "r600_shader.h" 48#include "r600_pipe.h" 49#include "eg_state_inlines.h" 50 51static void evergreen_set_blend_color(struct pipe_context *ctx, 52 const struct pipe_blend_color *state) 53{ 54 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 55 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 56 57 if (rstate == NULL) 58 return; 59 60 rstate->id = R600_PIPE_STATE_BLEND_COLOR; 61 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL); 62 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL); 63 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL); 64 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL); 65 66 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]); 67 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate; 68 r600_context_pipe_state_set(&rctx->ctx, rstate); 69} 70 71static void *evergreen_create_blend_state(struct pipe_context *ctx, 72 const struct pipe_blend_state *state) 73{ 74 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); 75 struct r600_pipe_state *rstate; 76 u32 color_control, target_mask; 77 /* FIXME there is more then 8 framebuffer */ 78 unsigned blend_cntl[8]; 79 80 if (blend == NULL) { 81 return NULL; 82 } 83 rstate = &blend->rstate; 84 85 rstate->id = R600_PIPE_STATE_BLEND; 86 87 target_mask = 0; 88 color_control = S_028808_MODE(1); 89 if (state->logicop_enable) { 90 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 91 } else { 92 color_control |= (0xcc << 16); 93 } 94 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 95 if (state->independent_blend_enable) { 96 for (int i = 0; i < 8; i++) { 97 target_mask |= (state->rt[i].colormask << (4 * i)); 98 } 99 } else { 100 for (int i = 0; i < 8; i++) { 101 target_mask |= (state->rt[0].colormask << (4 * i)); 102 } 103 } 104 blend->cb_target_mask = target_mask; 105 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL, 106 color_control, 0xFFFFFFFD, NULL); 107 r600_pipe_state_add_reg(rstate, R_028C3C_PA_SC_AA_MASK, 0xFFFFFFFF, 0xFFFFFFFF, NULL); 108 109 for (int i = 0; i < 8; i++) { 110 /* state->rt entries > 0 only written if independent blending */ 111 const int j = state->independent_blend_enable ? i : 0; 112 113 unsigned eqRGB = state->rt[j].rgb_func; 114 unsigned srcRGB = state->rt[j].rgb_src_factor; 115 unsigned dstRGB = state->rt[j].rgb_dst_factor; 116 unsigned eqA = state->rt[j].alpha_func; 117 unsigned srcA = state->rt[j].alpha_src_factor; 118 unsigned dstA = state->rt[j].alpha_dst_factor; 119 120 blend_cntl[i] = 0; 121 if (!state->rt[j].blend_enable) 122 continue; 123 124 blend_cntl[i] |= S_028780_BLEND_CONTROL_ENABLE(1); 125 blend_cntl[i] |= S_028780_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 126 blend_cntl[i] |= S_028780_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 127 blend_cntl[i] |= S_028780_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 128 129 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 130 blend_cntl[i] |= S_028780_SEPARATE_ALPHA_BLEND(1); 131 blend_cntl[i] |= S_028780_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 132 blend_cntl[i] |= S_028780_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 133 blend_cntl[i] |= S_028780_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 134 } 135 } 136 for (int i = 0; i < 8; i++) { 137 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl[i], 0xFFFFFFFF, NULL); 138 } 139 140 return rstate; 141} 142 143static void *evergreen_create_dsa_state(struct pipe_context *ctx, 144 const struct pipe_depth_stencil_alpha_state *state) 145{ 146 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa); 147 unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control; 148 unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control; 149 struct r600_pipe_state *rstate; 150 151 if (dsa == NULL) { 152 return NULL; 153 } 154 155 rstate = &dsa->rstate; 156 157 rstate->id = R600_PIPE_STATE_DSA; 158 /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */ 159 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 160 stencil_ref_mask = 0; 161 stencil_ref_mask_bf = 0; 162 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 163 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 164 S_028800_ZFUNC(state->depth.func); 165 166 /* stencil */ 167 if (state->stencil[0].enabled) { 168 db_depth_control |= S_028800_STENCIL_ENABLE(1); 169 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func)); 170 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 171 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 172 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 173 174 175 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) | 176 S_028430_STENCILWRITEMASK(state->stencil[0].writemask); 177 if (state->stencil[1].enabled) { 178 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 179 db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func)); 180 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 181 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 182 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 183 stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) | 184 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask); 185 } 186 } 187 188 /* alpha */ 189 alpha_test_control = 0; 190 alpha_ref = 0; 191 if (state->alpha.enabled) { 192 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 193 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 194 alpha_ref = fui(state->alpha.ref_value); 195 } 196 dsa->alpha_ref = alpha_ref; 197 198 /* misc */ 199 db_render_control = 0; 200 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) | 201 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) | 202 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE); 203 /* TODO db_render_override depends on query */ 204 r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL); 205 r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL); 206 r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL); 207 r600_pipe_state_add_reg(rstate, 208 R_028430_DB_STENCILREFMASK, stencil_ref_mask, 209 0xFFFFFFFF & C_028430_STENCILREF, NULL); 210 r600_pipe_state_add_reg(rstate, 211 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf, 212 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL); 213 r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 214 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL); 215 /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE, 216 * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by 217 * evergreen_pipe_shader_ps().*/ 218 r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL); 219 r600_pipe_state_add_reg(rstate, R_028000_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL); 220 r600_pipe_state_add_reg(rstate, R_02800C_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL); 221 r600_pipe_state_add_reg(rstate, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0, 0xFFFFFFFF, NULL); 222 r600_pipe_state_add_reg(rstate, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0, 0xFFFFFFFF, NULL); 223 r600_pipe_state_add_reg(rstate, R_028AC8_DB_PRELOAD_CONTROL, 0x0, 0xFFFFFFFF, NULL); 224 r600_pipe_state_add_reg(rstate, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL); 225 226 return rstate; 227} 228 229static void *evergreen_create_rs_state(struct pipe_context *ctx, 230 const struct pipe_rasterizer_state *state) 231{ 232 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); 233 struct r600_pipe_state *rstate; 234 unsigned tmp; 235 unsigned prov_vtx = 1, polygon_dual_mode; 236 unsigned clip_rule; 237 238 if (rs == NULL) { 239 return NULL; 240 } 241 242 rstate = &rs->rstate; 243 rs->flatshade = state->flatshade; 244 rs->sprite_coord_enable = state->sprite_coord_enable; 245 246 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 247 248 /* offset */ 249 rs->offset_units = state->offset_units; 250 rs->offset_scale = state->offset_scale * 12.0f; 251 252 rstate->id = R600_PIPE_STATE_RASTERIZER; 253 if (state->flatshade_first) 254 prov_vtx = 0; 255 tmp = S_0286D4_FLAT_SHADE_ENA(1); 256 if (state->sprite_coord_enable) { 257 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 258 S_0286D4_PNT_SPRITE_OVRD_X(2) | 259 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 260 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 261 S_0286D4_PNT_SPRITE_OVRD_W(1); 262 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 263 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 264 } 265 } 266 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL); 267 268 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 269 state->fill_back != PIPE_POLYGON_MODE_FILL); 270 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL, 271 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 272 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) | 273 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) | 274 S_028814_FACE(!state->front_ccw) | 275 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 276 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 277 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 278 S_028814_POLY_MODE(polygon_dual_mode) | 279 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 280 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL); 281 r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL, 282 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) | 283 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL); 284 r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL); 285 /* point size 12.4 fixed point */ 286 tmp = (unsigned)(state->point_size * 8.0); 287 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL); 288 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL); 289 290 tmp = (unsigned)state->line_width * 8; 291 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL); 292 293 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL); 294 r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 295 r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 296 r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 297 r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL); 298 r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 0x0, 0xFFFFFFFF, NULL); 299 300 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 301 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules), 302 0xFFFFFFFF, NULL); 303 304 r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL); 305 return rstate; 306} 307 308static void *evergreen_create_sampler_state(struct pipe_context *ctx, 309 const struct pipe_sampler_state *state) 310{ 311 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 312 union util_color uc; 313 314 if (rstate == NULL) { 315 return NULL; 316 } 317 318 rstate->id = R600_PIPE_STATE_SAMPLER; 319 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 320 r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 321 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 322 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 323 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 324 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter)) | 325 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter)) | 326 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 327 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 328 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL); 329 r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 330 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) | 331 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)), 332 0xFFFFFFFF, NULL); 333 r600_pipe_state_add_reg(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, 334 S_03C008_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) | 335 (state->seamless_cube_map ? 0 : S_03C008_DISABLE_CUBE_WRAP(1)) | 336 S_03C008_TYPE(1), 337 0xFFFFFFFF, NULL); 338 339 if (uc.ui) { 340 r600_pipe_state_add_reg(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL); 341 r600_pipe_state_add_reg(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL); 342 r600_pipe_state_add_reg(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL); 343 r600_pipe_state_add_reg(rstate, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL); 344 } 345 return rstate; 346} 347 348static struct pipe_sampler_view *evergreen_create_sampler_view(struct pipe_context *ctx, 349 struct pipe_resource *texture, 350 const struct pipe_sampler_view *state) 351{ 352 struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view); 353 struct r600_pipe_state *rstate; 354 const struct util_format_description *desc; 355 struct r600_resource_texture *tmp; 356 struct r600_resource *rbuffer; 357 unsigned format, endian; 358 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 359 unsigned char swizzle[4], array_mode = 0, tile_type = 0; 360 struct r600_bo *bo[2]; 361 362 if (resource == NULL) 363 return NULL; 364 rstate = &resource->state; 365 366 /* initialize base object */ 367 resource->base = *state; 368 resource->base.texture = NULL; 369 pipe_reference(NULL, &texture->reference); 370 resource->base.texture = texture; 371 resource->base.reference.count = 1; 372 resource->base.context = ctx; 373 374 swizzle[0] = state->swizzle_r; 375 swizzle[1] = state->swizzle_g; 376 swizzle[2] = state->swizzle_b; 377 swizzle[3] = state->swizzle_a; 378 format = r600_translate_texformat(ctx->screen, state->format, 379 swizzle, 380 &word4, &yuv_format); 381 if (format == ~0) { 382 format = 0; 383 } 384 desc = util_format_description(state->format); 385 if (desc == NULL) { 386 R600_ERR("unknow format %d\n", state->format); 387 } 388 tmp = (struct r600_resource_texture *)texture; 389 if (tmp->depth && !tmp->is_flushing_texture) { 390 r600_texture_depth_flush(ctx, texture, TRUE); 391 tmp = tmp->flushed_depth_texture; 392 } 393 394 endian = r600_colorformat_endian_swap(format); 395 396 if (tmp->force_int_type) { 397 word4 &= C_030010_NUM_FORMAT_ALL; 398 word4 |= S_030010_NUM_FORMAT_ALL(V_030010_SQ_NUM_FORMAT_INT); 399 } 400 401 rbuffer = &tmp->resource; 402 bo[0] = rbuffer->bo; 403 bo[1] = rbuffer->bo; 404 405 pitch = align(tmp->pitch_in_blocks[0] * util_format_get_blockwidth(state->format), 8); 406 array_mode = tmp->array_mode[0]; 407 tile_type = tmp->tile_type; 408 409 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, 410 S_030000_DIM(r600_tex_dim(texture->target)) | 411 S_030000_PITCH((pitch / 8) - 1) | 412 S_030000_NON_DISP_TILING_ORDER(tile_type) | 413 S_030000_TEX_WIDTH(texture->width0 - 1), 0xFFFFFFFF, NULL); 414 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, 415 S_030004_TEX_HEIGHT(texture->height0 - 1) | 416 S_030004_TEX_DEPTH(texture->depth0 - 1) | 417 S_030004_ARRAY_MODE(array_mode), 418 0xFFFFFFFF, NULL); 419 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, 420 (tmp->offset[0] + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]); 421 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, 422 (tmp->offset[1] + r600_bo_offset(bo[1])) >> 8, 0xFFFFFFFF, bo[1]); 423 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 424 word4 | 425 S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_NO_ZERO) | 426 S_030010_ENDIAN_SWAP(endian) | 427 S_030010_BASE_LEVEL(state->u.tex.first_level), 0xFFFFFFFF, NULL); 428 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 429 S_030014_LAST_LEVEL(state->u.tex.last_level) | 430 S_030014_BASE_ARRAY(0) | 431 S_030014_LAST_ARRAY(0), 0xffffffff, NULL); 432 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0, 0xFFFFFFFF, NULL); 433 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 434 S_03001C_DATA_FORMAT(format) | 435 S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0xFFFFFFFF, NULL); 436 437 return &resource->base; 438} 439 440static void evergreen_set_vs_sampler_view(struct pipe_context *ctx, unsigned count, 441 struct pipe_sampler_view **views) 442{ 443 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 444 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views; 445 446 for (int i = 0; i < count; i++) { 447 if (resource[i]) { 448 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state, 449 i + R600_MAX_CONST_BUFFERS); 450 } 451 } 452} 453 454static void evergreen_set_ps_sampler_view(struct pipe_context *ctx, unsigned count, 455 struct pipe_sampler_view **views) 456{ 457 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 458 struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views; 459 int i; 460 461 for (i = 0; i < count; i++) { 462 if (&rctx->ps_samplers.views[i]->base != views[i]) { 463 if (resource[i]) 464 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state, 465 i + R600_MAX_CONST_BUFFERS); 466 else 467 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, 468 i + R600_MAX_CONST_BUFFERS); 469 470 pipe_sampler_view_reference( 471 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i], 472 views[i]); 473 } 474 } 475 for (i = count; i < NUM_TEX_UNITS; i++) { 476 if (rctx->ps_samplers.views[i]) { 477 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, NULL, 478 i + R600_MAX_CONST_BUFFERS); 479 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL); 480 } 481 } 482 rctx->ps_samplers.n_views = count; 483} 484 485static void evergreen_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states) 486{ 487 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 488 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states; 489 490 491 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count); 492 rctx->ps_samplers.n_samplers = count; 493 494 for (int i = 0; i < count; i++) { 495 evergreen_context_pipe_state_set_ps_sampler(&rctx->ctx, rstates[i], i); 496 } 497} 498 499static void evergreen_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states) 500{ 501 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 502 struct r600_pipe_state **rstates = (struct r600_pipe_state **)states; 503 504 for (int i = 0; i < count; i++) { 505 evergreen_context_pipe_state_set_vs_sampler(&rctx->ctx, rstates[i], i); 506 } 507} 508 509static void evergreen_set_clip_state(struct pipe_context *ctx, 510 const struct pipe_clip_state *state) 511{ 512 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 513 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 514 515 if (rstate == NULL) 516 return; 517 518 rctx->clip = *state; 519 rstate->id = R600_PIPE_STATE_CLIP; 520 for (int i = 0; i < state->nr; i++) { 521 r600_pipe_state_add_reg(rstate, 522 R_0285BC_PA_CL_UCP0_X + i * 16, 523 fui(state->ucp[i][0]), 0xFFFFFFFF, NULL); 524 r600_pipe_state_add_reg(rstate, 525 R_0285C0_PA_CL_UCP0_Y + i * 16, 526 fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL); 527 r600_pipe_state_add_reg(rstate, 528 R_0285C4_PA_CL_UCP0_Z + i * 16, 529 fui(state->ucp[i][2]), 0xFFFFFFFF, NULL); 530 r600_pipe_state_add_reg(rstate, 531 R_0285C8_PA_CL_UCP0_W + i * 16, 532 fui(state->ucp[i][3]), 0xFFFFFFFF, NULL); 533 } 534 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 535 S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) | 536 S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) | 537 S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL); 538 539 free(rctx->states[R600_PIPE_STATE_CLIP]); 540 rctx->states[R600_PIPE_STATE_CLIP] = rstate; 541 r600_context_pipe_state_set(&rctx->ctx, rstate); 542} 543 544static void evergreen_set_polygon_stipple(struct pipe_context *ctx, 545 const struct pipe_poly_stipple *state) 546{ 547} 548 549static void evergreen_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 550{ 551} 552 553static void evergreen_set_scissor_state(struct pipe_context *ctx, 554 const struct pipe_scissor_state *state) 555{ 556 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 557 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 558 u32 tl, br; 559 560 if (rstate == NULL) 561 return; 562 563 rstate->id = R600_PIPE_STATE_SCISSOR; 564 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny); 565 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 566 r600_pipe_state_add_reg(rstate, 567 R_028210_PA_SC_CLIPRECT_0_TL, tl, 568 0xFFFFFFFF, NULL); 569 r600_pipe_state_add_reg(rstate, 570 R_028214_PA_SC_CLIPRECT_0_BR, br, 571 0xFFFFFFFF, NULL); 572 r600_pipe_state_add_reg(rstate, 573 R_028218_PA_SC_CLIPRECT_1_TL, tl, 574 0xFFFFFFFF, NULL); 575 r600_pipe_state_add_reg(rstate, 576 R_02821C_PA_SC_CLIPRECT_1_BR, br, 577 0xFFFFFFFF, NULL); 578 r600_pipe_state_add_reg(rstate, 579 R_028220_PA_SC_CLIPRECT_2_TL, tl, 580 0xFFFFFFFF, NULL); 581 r600_pipe_state_add_reg(rstate, 582 R_028224_PA_SC_CLIPRECT_2_BR, br, 583 0xFFFFFFFF, NULL); 584 r600_pipe_state_add_reg(rstate, 585 R_028228_PA_SC_CLIPRECT_3_TL, tl, 586 0xFFFFFFFF, NULL); 587 r600_pipe_state_add_reg(rstate, 588 R_02822C_PA_SC_CLIPRECT_3_BR, br, 589 0xFFFFFFFF, NULL); 590 591 free(rctx->states[R600_PIPE_STATE_SCISSOR]); 592 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate; 593 r600_context_pipe_state_set(&rctx->ctx, rstate); 594} 595 596static void evergreen_set_stencil_ref(struct pipe_context *ctx, 597 const struct pipe_stencil_ref *state) 598{ 599 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 600 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 601 u32 tmp; 602 603 if (rstate == NULL) 604 return; 605 606 rctx->stencil_ref = *state; 607 rstate->id = R600_PIPE_STATE_STENCIL_REF; 608 tmp = S_028430_STENCILREF(state->ref_value[0]); 609 r600_pipe_state_add_reg(rstate, 610 R_028430_DB_STENCILREFMASK, tmp, 611 ~C_028430_STENCILREF, NULL); 612 tmp = S_028434_STENCILREF_BF(state->ref_value[1]); 613 r600_pipe_state_add_reg(rstate, 614 R_028434_DB_STENCILREFMASK_BF, tmp, 615 ~C_028434_STENCILREF_BF, NULL); 616 617 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]); 618 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate; 619 r600_context_pipe_state_set(&rctx->ctx, rstate); 620} 621 622static void evergreen_set_viewport_state(struct pipe_context *ctx, 623 const struct pipe_viewport_state *state) 624{ 625 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 626 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 627 628 if (rstate == NULL) 629 return; 630 631 rctx->viewport = *state; 632 rstate->id = R600_PIPE_STATE_VIEWPORT; 633 r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL); 634 r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL); 635 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL); 636 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL); 637 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL); 638 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL); 639 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL); 640 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL); 641 r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL); 642 643 free(rctx->states[R600_PIPE_STATE_VIEWPORT]); 644 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate; 645 r600_context_pipe_state_set(&rctx->ctx, rstate); 646} 647 648static void evergreen_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate, 649 const struct pipe_framebuffer_state *state, int cb) 650{ 651 struct r600_resource_texture *rtex; 652 struct r600_resource *rbuffer; 653 struct r600_surface *surf; 654 unsigned level = state->cbufs[cb]->u.tex.level; 655 unsigned pitch, slice; 656 unsigned color_info; 657 unsigned format, swap, ntype, endian; 658 unsigned offset; 659 unsigned tile_type; 660 const struct util_format_description *desc; 661 struct r600_bo *bo[3]; 662 int i; 663 664 surf = (struct r600_surface *)state->cbufs[cb]; 665 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture; 666 667 if (rtex->depth && !rtex->is_flushing_texture) { 668 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE); 669 rtex = rtex->flushed_depth_texture; 670 } 671 672 rbuffer = &rtex->resource; 673 bo[0] = rbuffer->bo; 674 bo[1] = rbuffer->bo; 675 bo[2] = rbuffer->bo; 676 677 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 678 offset = r600_texture_get_offset((struct r600_resource_texture *)state->cbufs[cb]->texture, 679 level, state->cbufs[cb]->u.tex.first_layer); 680 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 681 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1; 682 desc = util_format_description(surf->base.format); 683 for (i = 0; i < 4; i++) { 684 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 685 break; 686 } 687 } 688 ntype = V_028C70_NUMBER_UNORM; 689 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 690 ntype = V_028C70_NUMBER_SRGB; 691 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) 692 ntype = V_028C70_NUMBER_SNORM; 693 694 format = r600_translate_colorformat(surf->base.format); 695 swap = r600_translate_colorswap(surf->base.format); 696 if (rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) { 697 endian = ENDIAN_NONE; 698 } else { 699 endian = r600_colorformat_endian_swap(format); 700 } 701 702 /* disable when gallium grows int textures */ 703 if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type) 704 ntype = V_028C70_NUMBER_UINT; 705 706 color_info = S_028C70_FORMAT(format) | 707 S_028C70_COMP_SWAP(swap) | 708 S_028C70_ARRAY_MODE(rtex->array_mode[level]) | 709 S_028C70_BLEND_CLAMP(1) | 710 S_028C70_NUMBER_TYPE(ntype) | 711 S_028C70_ENDIAN(endian); 712 713 714 /* EXPORT_NORM is an optimzation that can be enabled for better 715 * performance in certain cases. 716 * EXPORT_NORM can be enabled if: 717 * - 11-bit or smaller UNORM/SNORM/SRGB 718 * - 16-bit or smaller FLOAT 719 */ 720 /* FIXME: This should probably be the same for all CBs if we want 721 * useful alpha tests. */ 722 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 723 ((desc->channel[i].size < 12 && 724 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 725 ntype != V_028C70_NUMBER_UINT && ntype != V_028C70_NUMBER_SINT) || 726 (desc->channel[i].size < 17 && 727 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) { 728 color_info |= S_028C70_SOURCE_FORMAT(V_028C70_EXPORT_4C_16BPC); 729 rctx->export_16bpc = true; 730 } else { 731 rctx->export_16bpc = false; 732 } 733 rctx->alpha_ref_dirty = true; 734 735 if (rtex->array_mode[level] > V_028C70_ARRAY_LINEAR_ALIGNED) { 736 tile_type = rtex->tile_type; 737 } else /* workaround for linear buffers */ 738 tile_type = 1; 739 740 /* FIXME handle enabling of CB beyond BASE8 which has different offset */ 741 r600_pipe_state_add_reg(rstate, 742 R_028C60_CB_COLOR0_BASE + cb * 0x3C, 743 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]); 744 r600_pipe_state_add_reg(rstate, 745 R_028C78_CB_COLOR0_DIM + cb * 0x3C, 746 0x0, 0xFFFFFFFF, NULL); 747 r600_pipe_state_add_reg(rstate, 748 R_028C70_CB_COLOR0_INFO + cb * 0x3C, 749 color_info, 0xFFFFFFFF, bo[0]); 750 r600_pipe_state_add_reg(rstate, 751 R_028C64_CB_COLOR0_PITCH + cb * 0x3C, 752 S_028C64_PITCH_TILE_MAX(pitch), 753 0xFFFFFFFF, NULL); 754 r600_pipe_state_add_reg(rstate, 755 R_028C68_CB_COLOR0_SLICE + cb * 0x3C, 756 S_028C68_SLICE_TILE_MAX(slice), 757 0xFFFFFFFF, NULL); 758 r600_pipe_state_add_reg(rstate, 759 R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 760 0x00000000, 0xFFFFFFFF, NULL); 761 r600_pipe_state_add_reg(rstate, 762 R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, 763 S_028C74_NON_DISP_TILING_ORDER(tile_type), 764 0xFFFFFFFF, bo[0]); 765} 766 767static void evergreen_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate, 768 const struct pipe_framebuffer_state *state) 769{ 770 struct r600_resource_texture *rtex; 771 struct r600_resource *rbuffer; 772 struct r600_surface *surf; 773 unsigned level; 774 unsigned pitch, slice, format, stencil_format; 775 unsigned offset; 776 777 if (state->zsbuf == NULL) 778 return; 779 780 level = state->zsbuf->u.tex.level; 781 782 surf = (struct r600_surface *)state->zsbuf; 783 rtex = (struct r600_resource_texture*)state->zsbuf->texture; 784 785 rbuffer = &rtex->resource; 786 787 /* XXX quite sure for dx10+ hw don't need any offset hacks */ 788 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture, 789 level, state->zsbuf->u.tex.first_layer); 790 pitch = rtex->pitch_in_blocks[level] / 8 - 1; 791 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1; 792 format = r600_translate_dbformat(state->zsbuf->texture->format); 793 stencil_format = r600_translate_stencilformat(state->zsbuf->texture->format); 794 795 r600_pipe_state_add_reg(rstate, R_028048_DB_Z_READ_BASE, 796 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); 797 r600_pipe_state_add_reg(rstate, R_028050_DB_Z_WRITE_BASE, 798 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); 799 800 if (stencil_format) { 801 uint32_t stencil_offset; 802 803 stencil_offset = ((surf->aligned_height * rtex->pitch_in_bytes[level]) + 255) & ~255; 804 r600_pipe_state_add_reg(rstate, R_02804C_DB_STENCIL_READ_BASE, 805 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); 806 r600_pipe_state_add_reg(rstate, R_028054_DB_STENCIL_WRITE_BASE, 807 (offset + stencil_offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo); 808 } 809 810 r600_pipe_state_add_reg(rstate, R_028008_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL); 811 r600_pipe_state_add_reg(rstate, R_028044_DB_STENCIL_INFO, 812 S_028044_FORMAT(stencil_format), 0xFFFFFFFF, rbuffer->bo); 813 814 r600_pipe_state_add_reg(rstate, R_028040_DB_Z_INFO, 815 S_028040_ARRAY_MODE(rtex->array_mode[level]) | S_028040_FORMAT(format), 816 0xFFFFFFFF, rbuffer->bo); 817 r600_pipe_state_add_reg(rstate, R_028058_DB_DEPTH_SIZE, 818 S_028058_PITCH_TILE_MAX(pitch), 819 0xFFFFFFFF, NULL); 820 r600_pipe_state_add_reg(rstate, R_02805C_DB_DEPTH_SLICE, 821 S_02805C_SLICE_TILE_MAX(slice), 822 0xFFFFFFFF, NULL); 823} 824 825static void evergreen_set_framebuffer_state(struct pipe_context *ctx, 826 const struct pipe_framebuffer_state *state) 827{ 828 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 829 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 830 u32 shader_mask, tl, br, target_mask; 831 832 if (rstate == NULL) 833 return; 834 835 evergreen_context_flush_dest_caches(&rctx->ctx); 836 rctx->ctx.num_dest_buffers = state->nr_cbufs; 837 838 /* unreference old buffer and reference new one */ 839 rstate->id = R600_PIPE_STATE_FRAMEBUFFER; 840 841 util_copy_framebuffer_state(&rctx->framebuffer, state); 842 843 /* build states */ 844 for (int i = 0; i < state->nr_cbufs; i++) { 845 evergreen_cb(rctx, rstate, state, i); 846 } 847 if (state->zsbuf) { 848 evergreen_db(rctx, rstate, state); 849 rctx->ctx.num_dest_buffers++; 850 } 851 852 target_mask = 0x00000000; 853 target_mask = 0xFFFFFFFF; 854 shader_mask = 0; 855 for (int i = 0; i < state->nr_cbufs; i++) { 856 target_mask ^= 0xf << (i * 4); 857 shader_mask |= 0xf << (i * 4); 858 } 859 tl = S_028240_TL_X(0) | S_028240_TL_Y(0); 860 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height); 861 862 r600_pipe_state_add_reg(rstate, 863 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl, 864 0xFFFFFFFF, NULL); 865 r600_pipe_state_add_reg(rstate, 866 R_028244_PA_SC_GENERIC_SCISSOR_BR, br, 867 0xFFFFFFFF, NULL); 868 r600_pipe_state_add_reg(rstate, 869 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl, 870 0xFFFFFFFF, NULL); 871 r600_pipe_state_add_reg(rstate, 872 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br, 873 0xFFFFFFFF, NULL); 874 r600_pipe_state_add_reg(rstate, 875 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl, 876 0xFFFFFFFF, NULL); 877 r600_pipe_state_add_reg(rstate, 878 R_028034_PA_SC_SCREEN_SCISSOR_BR, br, 879 0xFFFFFFFF, NULL); 880 r600_pipe_state_add_reg(rstate, 881 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl, 882 0xFFFFFFFF, NULL); 883 r600_pipe_state_add_reg(rstate, 884 R_028208_PA_SC_WINDOW_SCISSOR_BR, br, 885 0xFFFFFFFF, NULL); 886 r600_pipe_state_add_reg(rstate, 887 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000, 888 0xFFFFFFFF, NULL); 889 r600_pipe_state_add_reg(rstate, 890 R_028230_PA_SC_EDGERULE, 0xAAAAAAAA, 891 0xFFFFFFFF, NULL); 892 893 r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK, 894 0x00000000, target_mask, NULL); 895 r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK, 896 shader_mask, 0xFFFFFFFF, NULL); 897 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 898 0x00000000, 0xFFFFFFFF, NULL); 899 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 900 0x00000000, 0xFFFFFFFF, NULL); 901 902 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); 903 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; 904 r600_context_pipe_state_set(&rctx->ctx, rstate); 905 906 if (state->zsbuf) { 907 evergreen_polygon_offset_update(rctx); 908 } 909} 910 911static void evergreen_texture_barrier(struct pipe_context *ctx) 912{ 913 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx; 914 915 r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) | 916 S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) | 917 S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) | 918 S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) | 919 S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1) | 920 S_0085F0_CB8_DEST_BASE_ENA(1) | S_0085F0_CB9_DEST_BASE_ENA(1) | 921 S_0085F0_CB10_DEST_BASE_ENA(1) | S_0085F0_CB11_DEST_BASE_ENA(1)); 922} 923 924void evergreen_init_state_functions(struct r600_pipe_context *rctx) 925{ 926 rctx->context.create_blend_state = evergreen_create_blend_state; 927 rctx->context.create_depth_stencil_alpha_state = evergreen_create_dsa_state; 928 rctx->context.create_fs_state = r600_create_shader_state; 929 rctx->context.create_rasterizer_state = evergreen_create_rs_state; 930 rctx->context.create_sampler_state = evergreen_create_sampler_state; 931 rctx->context.create_sampler_view = evergreen_create_sampler_view; 932 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 933 rctx->context.create_vs_state = r600_create_shader_state; 934 rctx->context.bind_blend_state = r600_bind_blend_state; 935 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; 936 rctx->context.bind_fragment_sampler_states = evergreen_bind_ps_sampler; 937 rctx->context.bind_fs_state = r600_bind_ps_shader; 938 rctx->context.bind_rasterizer_state = r600_bind_rs_state; 939 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 940 rctx->context.bind_vertex_sampler_states = evergreen_bind_vs_sampler; 941 rctx->context.bind_vs_state = r600_bind_vs_shader; 942 rctx->context.delete_blend_state = r600_delete_state; 943 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 944 rctx->context.delete_fs_state = r600_delete_ps_shader; 945 rctx->context.delete_rasterizer_state = r600_delete_rs_state; 946 rctx->context.delete_sampler_state = r600_delete_state; 947 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 948 rctx->context.delete_vs_state = r600_delete_vs_shader; 949 rctx->context.set_blend_color = evergreen_set_blend_color; 950 rctx->context.set_clip_state = evergreen_set_clip_state; 951 rctx->context.set_constant_buffer = r600_set_constant_buffer; 952 rctx->context.set_fragment_sampler_views = evergreen_set_ps_sampler_view; 953 rctx->context.set_framebuffer_state = evergreen_set_framebuffer_state; 954 rctx->context.set_polygon_stipple = evergreen_set_polygon_stipple; 955 rctx->context.set_sample_mask = evergreen_set_sample_mask; 956 rctx->context.set_scissor_state = evergreen_set_scissor_state; 957 rctx->context.set_stencil_ref = evergreen_set_stencil_ref; 958 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 959 rctx->context.set_index_buffer = r600_set_index_buffer; 960 rctx->context.set_vertex_sampler_views = evergreen_set_vs_sampler_view; 961 rctx->context.set_viewport_state = evergreen_set_viewport_state; 962 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 963 rctx->context.redefine_user_buffer = u_default_redefine_user_buffer; 964 rctx->context.texture_barrier = evergreen_texture_barrier; 965} 966 967void evergreen_init_config(struct r600_pipe_context *rctx) 968{ 969 struct r600_pipe_state *rstate = &rctx->config; 970 int ps_prio; 971 int vs_prio; 972 int gs_prio; 973 int es_prio; 974 int hs_prio, cs_prio, ls_prio; 975 int num_ps_gprs; 976 int num_vs_gprs; 977 int num_gs_gprs; 978 int num_es_gprs; 979 int num_hs_gprs; 980 int num_ls_gprs; 981 int num_temp_gprs; 982 int num_ps_threads; 983 int num_vs_threads; 984 int num_gs_threads; 985 int num_es_threads; 986 int num_hs_threads; 987 int num_ls_threads; 988 int num_ps_stack_entries; 989 int num_vs_stack_entries; 990 int num_gs_stack_entries; 991 int num_es_stack_entries; 992 int num_hs_stack_entries; 993 int num_ls_stack_entries; 994 enum radeon_family family; 995 unsigned tmp; 996 997 family = r600_get_family(rctx->radeon); 998 ps_prio = 0; 999 vs_prio = 1; 1000 gs_prio = 2; 1001 es_prio = 3; 1002 hs_prio = 0; 1003 ls_prio = 0; 1004 cs_prio = 0; 1005 1006 switch (family) { 1007 case CHIP_CEDAR: 1008 default: 1009 num_ps_gprs = 93; 1010 num_vs_gprs = 46; 1011 num_temp_gprs = 4; 1012 num_gs_gprs = 31; 1013 num_es_gprs = 31; 1014 num_hs_gprs = 23; 1015 num_ls_gprs = 23; 1016 num_ps_threads = 96; 1017 num_vs_threads = 16; 1018 num_gs_threads = 16; 1019 num_es_threads = 16; 1020 num_hs_threads = 16; 1021 num_ls_threads = 16; 1022 num_ps_stack_entries = 42; 1023 num_vs_stack_entries = 42; 1024 num_gs_stack_entries = 42; 1025 num_es_stack_entries = 42; 1026 num_hs_stack_entries = 42; 1027 num_ls_stack_entries = 42; 1028 break; 1029 case CHIP_REDWOOD: 1030 num_ps_gprs = 93; 1031 num_vs_gprs = 46; 1032 num_temp_gprs = 4; 1033 num_gs_gprs = 31; 1034 num_es_gprs = 31; 1035 num_hs_gprs = 23; 1036 num_ls_gprs = 23; 1037 num_ps_threads = 128; 1038 num_vs_threads = 20; 1039 num_gs_threads = 20; 1040 num_es_threads = 20; 1041 num_hs_threads = 20; 1042 num_ls_threads = 20; 1043 num_ps_stack_entries = 42; 1044 num_vs_stack_entries = 42; 1045 num_gs_stack_entries = 42; 1046 num_es_stack_entries = 42; 1047 num_hs_stack_entries = 42; 1048 num_ls_stack_entries = 42; 1049 break; 1050 case CHIP_JUNIPER: 1051 num_ps_gprs = 93; 1052 num_vs_gprs = 46; 1053 num_temp_gprs = 4; 1054 num_gs_gprs = 31; 1055 num_es_gprs = 31; 1056 num_hs_gprs = 23; 1057 num_ls_gprs = 23; 1058 num_ps_threads = 128; 1059 num_vs_threads = 20; 1060 num_gs_threads = 20; 1061 num_es_threads = 20; 1062 num_hs_threads = 20; 1063 num_ls_threads = 20; 1064 num_ps_stack_entries = 85; 1065 num_vs_stack_entries = 85; 1066 num_gs_stack_entries = 85; 1067 num_es_stack_entries = 85; 1068 num_hs_stack_entries = 85; 1069 num_ls_stack_entries = 85; 1070 break; 1071 case CHIP_CYPRESS: 1072 case CHIP_HEMLOCK: 1073 num_ps_gprs = 93; 1074 num_vs_gprs = 46; 1075 num_temp_gprs = 4; 1076 num_gs_gprs = 31; 1077 num_es_gprs = 31; 1078 num_hs_gprs = 23; 1079 num_ls_gprs = 23; 1080 num_ps_threads = 128; 1081 num_vs_threads = 20; 1082 num_gs_threads = 20; 1083 num_es_threads = 20; 1084 num_hs_threads = 20; 1085 num_ls_threads = 20; 1086 num_ps_stack_entries = 85; 1087 num_vs_stack_entries = 85; 1088 num_gs_stack_entries = 85; 1089 num_es_stack_entries = 85; 1090 num_hs_stack_entries = 85; 1091 num_ls_stack_entries = 85; 1092 break; 1093 case CHIP_PALM: 1094 num_ps_gprs = 93; 1095 num_vs_gprs = 46; 1096 num_temp_gprs = 4; 1097 num_gs_gprs = 31; 1098 num_es_gprs = 31; 1099 num_hs_gprs = 23; 1100 num_ls_gprs = 23; 1101 num_ps_threads = 96; 1102 num_vs_threads = 16; 1103 num_gs_threads = 16; 1104 num_es_threads = 16; 1105 num_hs_threads = 16; 1106 num_ls_threads = 16; 1107 num_ps_stack_entries = 42; 1108 num_vs_stack_entries = 42; 1109 num_gs_stack_entries = 42; 1110 num_es_stack_entries = 42; 1111 num_hs_stack_entries = 42; 1112 num_ls_stack_entries = 42; 1113 break; 1114 case CHIP_BARTS: 1115 num_ps_gprs = 93; 1116 num_vs_gprs = 46; 1117 num_temp_gprs = 4; 1118 num_gs_gprs = 31; 1119 num_es_gprs = 31; 1120 num_hs_gprs = 23; 1121 num_ls_gprs = 23; 1122 num_ps_threads = 128; 1123 num_vs_threads = 20; 1124 num_gs_threads = 20; 1125 num_es_threads = 20; 1126 num_hs_threads = 20; 1127 num_ls_threads = 20; 1128 num_ps_stack_entries = 85; 1129 num_vs_stack_entries = 85; 1130 num_gs_stack_entries = 85; 1131 num_es_stack_entries = 85; 1132 num_hs_stack_entries = 85; 1133 num_ls_stack_entries = 85; 1134 break; 1135 case CHIP_TURKS: 1136 num_ps_gprs = 93; 1137 num_vs_gprs = 46; 1138 num_temp_gprs = 4; 1139 num_gs_gprs = 31; 1140 num_es_gprs = 31; 1141 num_hs_gprs = 23; 1142 num_ls_gprs = 23; 1143 num_ps_threads = 128; 1144 num_vs_threads = 20; 1145 num_gs_threads = 20; 1146 num_es_threads = 20; 1147 num_hs_threads = 20; 1148 num_ls_threads = 20; 1149 num_ps_stack_entries = 42; 1150 num_vs_stack_entries = 42; 1151 num_gs_stack_entries = 42; 1152 num_es_stack_entries = 42; 1153 num_hs_stack_entries = 42; 1154 num_ls_stack_entries = 42; 1155 break; 1156 case CHIP_CAICOS: 1157 num_ps_gprs = 93; 1158 num_vs_gprs = 46; 1159 num_temp_gprs = 4; 1160 num_gs_gprs = 31; 1161 num_es_gprs = 31; 1162 num_hs_gprs = 23; 1163 num_ls_gprs = 23; 1164 num_ps_threads = 128; 1165 num_vs_threads = 10; 1166 num_gs_threads = 10; 1167 num_es_threads = 10; 1168 num_hs_threads = 10; 1169 num_ls_threads = 10; 1170 num_ps_stack_entries = 42; 1171 num_vs_stack_entries = 42; 1172 num_gs_stack_entries = 42; 1173 num_es_stack_entries = 42; 1174 num_hs_stack_entries = 42; 1175 num_ls_stack_entries = 42; 1176 break; 1177 } 1178 1179 tmp = 0x00000000; 1180 switch (family) { 1181 case CHIP_CEDAR: 1182 case CHIP_PALM: 1183 case CHIP_CAICOS: 1184 break; 1185 default: 1186 tmp |= S_008C00_VC_ENABLE(1); 1187 break; 1188 } 1189 tmp |= S_008C00_EXPORT_SRC_C(1); 1190 tmp |= S_008C00_CS_PRIO(cs_prio); 1191 tmp |= S_008C00_LS_PRIO(ls_prio); 1192 tmp |= S_008C00_HS_PRIO(hs_prio); 1193 tmp |= S_008C00_PS_PRIO(ps_prio); 1194 tmp |= S_008C00_VS_PRIO(vs_prio); 1195 tmp |= S_008C00_GS_PRIO(gs_prio); 1196 tmp |= S_008C00_ES_PRIO(es_prio); 1197 r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL); 1198 1199 tmp = 0; 1200 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs); 1201 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs); 1202 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs); 1203 r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL); 1204 1205 tmp = 0; 1206 tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs); 1207 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); 1208 r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL); 1209 1210 tmp = 0; 1211 tmp |= S_008C0C_NUM_HS_GPRS(num_hs_gprs); 1212 tmp |= S_008C0C_NUM_LS_GPRS(num_ls_gprs); 1213 r600_pipe_state_add_reg(rstate, R_008C0C_SQ_GPR_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL); 1214 1215 tmp = 0; 1216 tmp |= S_008C18_NUM_PS_THREADS(num_ps_threads); 1217 tmp |= S_008C18_NUM_VS_THREADS(num_vs_threads); 1218 tmp |= S_008C18_NUM_GS_THREADS(num_gs_threads); 1219 tmp |= S_008C18_NUM_ES_THREADS(num_es_threads); 1220 r600_pipe_state_add_reg(rstate, R_008C18_SQ_THREAD_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL); 1221 1222 tmp = 0; 1223 tmp |= S_008C1C_NUM_HS_THREADS(num_hs_threads); 1224 tmp |= S_008C1C_NUM_LS_THREADS(num_ls_threads); 1225 r600_pipe_state_add_reg(rstate, R_008C1C_SQ_THREAD_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL); 1226 1227 tmp = 0; 1228 tmp |= S_008C20_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 1229 tmp |= S_008C20_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 1230 r600_pipe_state_add_reg(rstate, R_008C20_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL); 1231 1232 tmp = 0; 1233 tmp |= S_008C24_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 1234 tmp |= S_008C24_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 1235 r600_pipe_state_add_reg(rstate, R_008C24_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL); 1236 1237 tmp = 0; 1238 tmp |= S_008C28_NUM_HS_STACK_ENTRIES(num_hs_stack_entries); 1239 tmp |= S_008C28_NUM_LS_STACK_ENTRIES(num_ls_stack_entries); 1240 r600_pipe_state_add_reg(rstate, R_008C28_SQ_STACK_RESOURCE_MGMT_3, tmp, 0xFFFFFFFF, NULL); 1241 1242 r600_pipe_state_add_reg(rstate, R_009100_SPI_CONFIG_CNTL, 0x0, 0xFFFFFFFF, NULL); 1243 r600_pipe_state_add_reg(rstate, R_00913C_SPI_CONFIG_CNTL_1, S_00913C_VTX_DONE_DELAY(4), 0xFFFFFFFF, NULL); 1244 1245#if 0 1246 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x0, 0xFFFFFFFF, NULL); 1247 1248 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x0, 0xFFFFFFFF, NULL); 1249#endif 1250 r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MODE_CNTL_0, 0x0, 0xFFFFFFFF, NULL); 1251 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL_1, 0x0, 0xFFFFFFFF, NULL); 1252 1253 r600_pipe_state_add_reg(rstate, R_028900_SQ_ESGS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1254 r600_pipe_state_add_reg(rstate, R_028904_SQ_GSVS_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1255 r600_pipe_state_add_reg(rstate, R_028908_SQ_ESTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1256 r600_pipe_state_add_reg(rstate, R_02890C_SQ_GSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1257 r600_pipe_state_add_reg(rstate, R_028910_SQ_VSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1258 r600_pipe_state_add_reg(rstate, R_028914_SQ_PSTMP_RING_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1259 1260 r600_pipe_state_add_reg(rstate, R_02891C_SQ_GS_VERT_ITEMSIZE, 0x0, 0xFFFFFFFF, NULL); 1261 r600_pipe_state_add_reg(rstate, R_028920_SQ_GS_VERT_ITEMSIZE_1, 0x0, 0xFFFFFFFF, NULL); 1262 r600_pipe_state_add_reg(rstate, R_028924_SQ_GS_VERT_ITEMSIZE_2, 0x0, 0xFFFFFFFF, NULL); 1263 r600_pipe_state_add_reg(rstate, R_028928_SQ_GS_VERT_ITEMSIZE_3, 0x0, 0xFFFFFFFF, NULL); 1264 1265 r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0, 0xFFFFFFFF, NULL); 1266 r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x0, 0xFFFFFFFF, NULL); 1267 r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL); 1268 r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0, 0xFFFFFFFF, NULL); 1269 r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0, 0xFFFFFFFF, NULL); 1270 r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0, 0xFFFFFFFF, NULL); 1271 r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x0, 0xFFFFFFFF, NULL); 1272 r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x0, 0xFFFFFFFF, NULL); 1273 r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0, 0xFFFFFFFF, NULL); 1274 r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0, 0xFFFFFFFF, NULL); 1275 r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL); 1276 r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0, 0xFFFFFFFF, NULL); 1277 r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x0, 0xFFFFFFFF, NULL); 1278 r600_pipe_state_add_reg(rstate, R_028B94_VGT_STRMOUT_CONFIG, 0x0, 0xFFFFFFFF, NULL); 1279 r600_pipe_state_add_reg(rstate, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0, 0xFFFFFFFF, NULL); 1280 r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000000, 0xFFFFFFFF, NULL); 1281 r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x0, 0xFFFFFFFF, NULL); 1282 r600_pipe_state_add_reg(rstate, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1, 0xFFFFFFFF, NULL); 1283 1284 r600_pipe_state_add_reg(rstate, R_028380_SQ_VTX_SEMANTIC_0, 0x0, 0xFFFFFFFF, NULL); 1285 r600_pipe_state_add_reg(rstate, R_028384_SQ_VTX_SEMANTIC_1, 0x0, 0xFFFFFFFF, NULL); 1286 r600_pipe_state_add_reg(rstate, R_028388_SQ_VTX_SEMANTIC_2, 0x0, 0xFFFFFFFF, NULL); 1287 r600_pipe_state_add_reg(rstate, R_02838C_SQ_VTX_SEMANTIC_3, 0x0, 0xFFFFFFFF, NULL); 1288 r600_pipe_state_add_reg(rstate, R_028390_SQ_VTX_SEMANTIC_4, 0x0, 0xFFFFFFFF, NULL); 1289 r600_pipe_state_add_reg(rstate, R_028394_SQ_VTX_SEMANTIC_5, 0x0, 0xFFFFFFFF, NULL); 1290 r600_pipe_state_add_reg(rstate, R_028398_SQ_VTX_SEMANTIC_6, 0x0, 0xFFFFFFFF, NULL); 1291 r600_pipe_state_add_reg(rstate, R_02839C_SQ_VTX_SEMANTIC_7, 0x0, 0xFFFFFFFF, NULL); 1292 r600_pipe_state_add_reg(rstate, R_0283A0_SQ_VTX_SEMANTIC_8, 0x0, 0xFFFFFFFF, NULL); 1293 r600_pipe_state_add_reg(rstate, R_0283A4_SQ_VTX_SEMANTIC_9, 0x0, 0xFFFFFFFF, NULL); 1294 r600_pipe_state_add_reg(rstate, R_0283A8_SQ_VTX_SEMANTIC_10, 0x0, 0xFFFFFFFF, NULL); 1295 r600_pipe_state_add_reg(rstate, R_0283AC_SQ_VTX_SEMANTIC_11, 0x0, 0xFFFFFFFF, NULL); 1296 r600_pipe_state_add_reg(rstate, R_0283B0_SQ_VTX_SEMANTIC_12, 0x0, 0xFFFFFFFF, NULL); 1297 r600_pipe_state_add_reg(rstate, R_0283B4_SQ_VTX_SEMANTIC_13, 0x0, 0xFFFFFFFF, NULL); 1298 r600_pipe_state_add_reg(rstate, R_0283B8_SQ_VTX_SEMANTIC_14, 0x0, 0xFFFFFFFF, NULL); 1299 r600_pipe_state_add_reg(rstate, R_0283BC_SQ_VTX_SEMANTIC_15, 0x0, 0xFFFFFFFF, NULL); 1300 r600_pipe_state_add_reg(rstate, R_0283C0_SQ_VTX_SEMANTIC_16, 0x0, 0xFFFFFFFF, NULL); 1301 r600_pipe_state_add_reg(rstate, R_0283C4_SQ_VTX_SEMANTIC_17, 0x0, 0xFFFFFFFF, NULL); 1302 r600_pipe_state_add_reg(rstate, R_0283C8_SQ_VTX_SEMANTIC_18, 0x0, 0xFFFFFFFF, NULL); 1303 r600_pipe_state_add_reg(rstate, R_0283CC_SQ_VTX_SEMANTIC_19, 0x0, 0xFFFFFFFF, NULL); 1304 r600_pipe_state_add_reg(rstate, R_0283D0_SQ_VTX_SEMANTIC_20, 0x0, 0xFFFFFFFF, NULL); 1305 r600_pipe_state_add_reg(rstate, R_0283D4_SQ_VTX_SEMANTIC_21, 0x0, 0xFFFFFFFF, NULL); 1306 r600_pipe_state_add_reg(rstate, R_0283D8_SQ_VTX_SEMANTIC_22, 0x0, 0xFFFFFFFF, NULL); 1307 r600_pipe_state_add_reg(rstate, R_0283DC_SQ_VTX_SEMANTIC_23, 0x0, 0xFFFFFFFF, NULL); 1308 r600_pipe_state_add_reg(rstate, R_0283E0_SQ_VTX_SEMANTIC_24, 0x0, 0xFFFFFFFF, NULL); 1309 r600_pipe_state_add_reg(rstate, R_0283E4_SQ_VTX_SEMANTIC_25, 0x0, 0xFFFFFFFF, NULL); 1310 r600_pipe_state_add_reg(rstate, R_0283E8_SQ_VTX_SEMANTIC_26, 0x0, 0xFFFFFFFF, NULL); 1311 r600_pipe_state_add_reg(rstate, R_0283EC_SQ_VTX_SEMANTIC_27, 0x0, 0xFFFFFFFF, NULL); 1312 r600_pipe_state_add_reg(rstate, R_0283F0_SQ_VTX_SEMANTIC_28, 0x0, 0xFFFFFFFF, NULL); 1313 r600_pipe_state_add_reg(rstate, R_0283F4_SQ_VTX_SEMANTIC_29, 0x0, 0xFFFFFFFF, NULL); 1314 r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0, 0xFFFFFFFF, NULL); 1315 r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0, 0xFFFFFFFF, NULL); 1316 1317 r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0, 0xFFFFFFFF, NULL); 1318 1319 r600_context_pipe_state_set(&rctx->ctx, rstate); 1320} 1321 1322void evergreen_polygon_offset_update(struct r600_pipe_context *rctx) 1323{ 1324 struct r600_pipe_state state; 1325 1326 state.id = R600_PIPE_STATE_POLYGON_OFFSET; 1327 state.nregs = 0; 1328 if (rctx->rasterizer && rctx->framebuffer.zsbuf) { 1329 float offset_units = rctx->rasterizer->offset_units; 1330 unsigned offset_db_fmt_cntl = 0, depth; 1331 1332 switch (rctx->framebuffer.zsbuf->texture->format) { 1333 case PIPE_FORMAT_Z24X8_UNORM: 1334 case PIPE_FORMAT_Z24_UNORM_S8_USCALED: 1335 depth = -24; 1336 offset_units *= 2.0f; 1337 break; 1338 case PIPE_FORMAT_Z32_FLOAT: 1339 depth = -23; 1340 offset_units *= 1.0f; 1341 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 1342 break; 1343 case PIPE_FORMAT_Z16_UNORM: 1344 depth = -16; 1345 offset_units *= 4.0f; 1346 break; 1347 default: 1348 return; 1349 } 1350 /* FIXME some of those reg can be computed with cso */ 1351 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 1352 r600_pipe_state_add_reg(&state, 1353 R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 1354 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL); 1355 r600_pipe_state_add_reg(&state, 1356 R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, 1357 fui(offset_units), 0xFFFFFFFF, NULL); 1358 r600_pipe_state_add_reg(&state, 1359 R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE, 1360 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL); 1361 r600_pipe_state_add_reg(&state, 1362 R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, 1363 fui(offset_units), 0xFFFFFFFF, NULL); 1364 r600_pipe_state_add_reg(&state, 1365 R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 1366 offset_db_fmt_cntl, 0xFFFFFFFF, NULL); 1367 r600_context_pipe_state_set(&rctx->ctx, &state); 1368 } 1369} 1370 1371void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader) 1372{ 1373 struct r600_pipe_state *rstate = &shader->rstate; 1374 struct r600_shader *rshader = &shader->shader; 1375 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; 1376 int pos_index = -1, face_index = -1; 1377 int ninterp = 0; 1378 boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE; 1379 unsigned spi_baryc_cntl; 1380 1381 rstate->nregs = 0; 1382 1383 db_shader_control = 0; 1384 for (i = 0; i < rshader->ninput; i++) { 1385 /* evergreen NUM_INTERP only contains values interpolated into the LDS, 1386 POSITION goes via GPRs from the SC so isn't counted */ 1387 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) 1388 pos_index = i; 1389 else if (rshader->input[i].name == TGSI_SEMANTIC_FACE) 1390 face_index = i; 1391 else { 1392 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR || 1393 rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) 1394 ninterp++; 1395 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) 1396 have_linear = TRUE; 1397 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_PERSPECTIVE) 1398 have_perspective = TRUE; 1399 if (rshader->input[i].centroid) 1400 have_centroid = TRUE; 1401 } 1402 } 1403 for (i = 0; i < rshader->noutput; i++) { 1404 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) 1405 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1); 1406 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 1407 db_shader_control |= S_02880C_STENCIL_EXPORT_ENABLE(1); 1408 } 1409 if (rshader->uses_kill) 1410 db_shader_control |= S_02880C_KILL_ENABLE(1); 1411 1412 exports_ps = 0; 1413 num_cout = 0; 1414 for (i = 0; i < rshader->noutput; i++) { 1415 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || 1416 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 1417 exports_ps |= 1; 1418 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) { 1419 num_cout++; 1420 } 1421 } 1422 exports_ps |= S_02884C_EXPORT_COLORS(num_cout); 1423 if (!exports_ps) { 1424 /* always at least export 1 component per pixel */ 1425 exports_ps = 2; 1426 } 1427 1428 if (ninterp == 0) { 1429 ninterp = 1; 1430 have_perspective = TRUE; 1431 } 1432 1433 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(ninterp) | 1434 S_0286CC_PERSP_GRADIENT_ENA(have_perspective) | 1435 S_0286CC_LINEAR_GRADIENT_ENA(have_linear); 1436 spi_input_z = 0; 1437 if (pos_index != -1) { 1438 spi_ps_in_control_0 |= S_0286CC_POSITION_ENA(1) | 1439 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) | 1440 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr); 1441 spi_input_z |= 1; 1442 } 1443 1444 spi_ps_in_control_1 = 0; 1445 if (face_index != -1) { 1446 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | 1447 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); 1448 } 1449 1450 spi_baryc_cntl = 0; 1451 if (have_perspective) 1452 spi_baryc_cntl |= S_0286E0_PERSP_CENTER_ENA(1) | 1453 S_0286E0_PERSP_CENTROID_ENA(have_centroid); 1454 if (have_linear) 1455 spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) | 1456 S_0286E0_LINEAR_CENTROID_ENA(have_centroid); 1457 1458 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, 1459 spi_ps_in_control_0, 0xFFFFFFFF, NULL); 1460 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, 1461 spi_ps_in_control_1, 0xFFFFFFFF, NULL); 1462 r600_pipe_state_add_reg(rstate, R_0286E4_SPI_PS_IN_CONTROL_2, 1463 0, 0xFFFFFFFF, NULL); 1464 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL); 1465 r600_pipe_state_add_reg(rstate, 1466 R_0286E0_SPI_BARYC_CNTL, 1467 spi_baryc_cntl, 1468 0xFFFFFFFF, NULL); 1469 1470 r600_pipe_state_add_reg(rstate, 1471 R_028840_SQ_PGM_START_PS, 1472 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo); 1473 r600_pipe_state_add_reg(rstate, 1474 R_028844_SQ_PGM_RESOURCES_PS, 1475 S_028844_NUM_GPRS(rshader->bc.ngpr) | 1476 S_028844_PRIME_CACHE_ON_DRAW(1) | 1477 S_028844_STACK_SIZE(rshader->bc.nstack), 1478 0xFFFFFFFF, NULL); 1479 r600_pipe_state_add_reg(rstate, 1480 R_028848_SQ_PGM_RESOURCES_2_PS, 1481 0x0, 0xFFFFFFFF, NULL); 1482 r600_pipe_state_add_reg(rstate, 1483 R_02884C_SQ_PGM_EXPORTS_PS, 1484 exports_ps, 0xFFFFFFFF, NULL); 1485 /* FIXME: Evergreen doesn't seem to support MULTIWRITE_ENABLE. */ 1486 /* only set some bits here, the other bits are set in the dsa state */ 1487 r600_pipe_state_add_reg(rstate, 1488 R_02880C_DB_SHADER_CONTROL, 1489 db_shader_control, 1490 S_02880C_Z_EXPORT_ENABLE(1) | 1491 S_02880C_STENCIL_EXPORT_ENABLE(1) | 1492 S_02880C_KILL_ENABLE(1), 1493 NULL); 1494 r600_pipe_state_add_reg(rstate, 1495 R_03A200_SQ_LOOP_CONST_0, 0x01000FFF, 1496 0xFFFFFFFF, NULL); 1497} 1498 1499void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader) 1500{ 1501 struct r600_pipe_state *rstate = &shader->rstate; 1502 struct r600_shader *rshader = &shader->shader; 1503 unsigned spi_vs_out_id[10]; 1504 unsigned i, tmp; 1505 1506 /* clear previous register */ 1507 rstate->nregs = 0; 1508 1509 /* so far never got proper semantic id from tgsi */ 1510 for (i = 0; i < 10; i++) { 1511 spi_vs_out_id[i] = 0; 1512 } 1513 for (i = 0; i < 32; i++) { 1514 tmp = i << ((i & 3) * 8); 1515 spi_vs_out_id[i / 4] |= tmp; 1516 } 1517 for (i = 0; i < 10; i++) { 1518 r600_pipe_state_add_reg(rstate, 1519 R_02861C_SPI_VS_OUT_ID_0 + i * 4, 1520 spi_vs_out_id[i], 0xFFFFFFFF, NULL); 1521 } 1522 1523 r600_pipe_state_add_reg(rstate, 1524 R_0286C4_SPI_VS_OUT_CONFIG, 1525 S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2), 1526 0xFFFFFFFF, NULL); 1527 r600_pipe_state_add_reg(rstate, 1528 R_028860_SQ_PGM_RESOURCES_VS, 1529 S_028860_NUM_GPRS(rshader->bc.ngpr) | 1530 S_028860_STACK_SIZE(rshader->bc.nstack), 1531 0xFFFFFFFF, NULL); 1532 r600_pipe_state_add_reg(rstate, 1533 R_028864_SQ_PGM_RESOURCES_2_VS, 1534 0x0, 0xFFFFFFFF, NULL); 1535 r600_pipe_state_add_reg(rstate, 1536 R_02885C_SQ_PGM_START_VS, 1537 (r600_bo_offset(shader->bo)) >> 8, 0xFFFFFFFF, shader->bo); 1538 1539 r600_pipe_state_add_reg(rstate, 1540 R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF, 1541 0xFFFFFFFF, NULL); 1542} 1543 1544void evergreen_fetch_shader(struct r600_vertex_element *ve) 1545{ 1546 struct r600_pipe_state *rstate = &ve->rstate; 1547 rstate->id = R600_PIPE_STATE_FETCH_SHADER; 1548 rstate->nregs = 0; 1549 r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS, 1550 0x00000000, 0xFFFFFFFF, NULL); 1551 r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS, 1552 (r600_bo_offset(ve->fetch_shader)) >> 8, 1553 0xFFFFFFFF, ve->fetch_shader); 1554} 1555 1556void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx) 1557{ 1558 struct pipe_depth_stencil_alpha_state dsa; 1559 struct r600_pipe_state *rstate; 1560 1561 memset(&dsa, 0, sizeof(dsa)); 1562 1563 rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 1564 r600_pipe_state_add_reg(rstate, 1565 R_02880C_DB_SHADER_CONTROL, 1566 0x0, 1567 S_02880C_DUAL_EXPORT_ENABLE(1), NULL); 1568 r600_pipe_state_add_reg(rstate, 1569 R_028000_DB_RENDER_CONTROL, 1570 S_028000_DEPTH_COPY_ENABLE(1) | 1571 S_028000_STENCIL_COPY_ENABLE(1) | 1572 S_028000_COPY_CENTROID(1), 1573 S_028000_DEPTH_COPY_ENABLE(1) | 1574 S_028000_STENCIL_COPY_ENABLE(1) | 1575 S_028000_COPY_CENTROID(1), NULL); 1576 return rstate; 1577} 1578 1579void evergreen_pipe_set_buffer_resource(struct r600_pipe_context *rctx, 1580 struct r600_pipe_state *rstate, 1581 struct r600_resource *rbuffer, 1582 unsigned offset, unsigned stride) 1583{ 1584 r600_pipe_state_add_reg(rstate, R_030000_RESOURCE0_WORD0, 1585 offset, 0xFFFFFFFF, rbuffer->bo); 1586 r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1, 1587 rbuffer->bo_size - offset - 1, 0xFFFFFFFF, NULL); 1588 r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2, 1589 S_030008_ENDIAN_SWAP(r600_endian_swap(32)) | 1590 S_030008_STRIDE(stride), 0xFFFFFFFF, NULL); 1591 r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3, 1592 S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) | 1593 S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) | 1594 S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) | 1595 S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W), 1596 0xFFFFFFFF, NULL); 1597 r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4, 1598 0x00000000, 0xFFFFFFFF, NULL); 1599 r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 1600 0x00000000, 0xFFFFFFFF, NULL); 1601 r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 1602 0x00000000, 0xFFFFFFFF, NULL); 1603 r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 1604 0xC0000000, 0xFFFFFFFF, NULL); 1605} 1606