r600_hw_context.c revision 1e1a7011ee8f7e954b9f77985665495e53efae22
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#include "r600_hw_context_priv.h" 27#include "r600_pipe.h" 28#include "r600d.h" 29#include "util/u_memory.h" 30#include <errno.h> 31 32#define GROUP_FORCE_NEW_BLOCK 0 33 34/* Get backends mask */ 35void r600_get_backend_mask(struct r600_context *ctx) 36{ 37 struct r600_resource *buffer; 38 u32 *results; 39 unsigned num_backends = ctx->screen->info.r600_num_backends; 40 unsigned i, mask = 0; 41 42 /* if backend_map query is supported by the kernel */ 43 if (ctx->screen->info.r600_backend_map_valid) { 44 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes; 45 unsigned backend_map = ctx->screen->info.r600_backend_map; 46 unsigned item_width, item_mask; 47 48 if (ctx->screen->chip_class >= EVERGREEN) { 49 item_width = 4; 50 item_mask = 0x7; 51 } else { 52 item_width = 2; 53 item_mask = 0x3; 54 } 55 56 while(num_tile_pipes--) { 57 i = backend_map & item_mask; 58 mask |= (1<<i); 59 backend_map >>= item_width; 60 } 61 if (mask != 0) { 62 ctx->backend_mask = mask; 63 return; 64 } 65 } 66 67 /* otherwise backup path for older kernels */ 68 69 /* create buffer for event data */ 70 buffer = (struct r600_resource*) 71 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, 72 PIPE_USAGE_STAGING, ctx->max_db*16); 73 if (!buffer) 74 goto err; 75 76 /* initialize buffer with zeroes */ 77 results = ctx->screen->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); 78 if (results) { 79 memset(results, 0, ctx->max_db * 4 * 4); 80 ctx->screen->ws->buffer_unmap(buffer->buf); 81 82 /* emit EVENT_WRITE for ZPASS_DONE */ 83 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 84 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); 85 ctx->pm4[ctx->pm4_cdwords++] = 0; 86 ctx->pm4[ctx->pm4_cdwords++] = 0; 87 88 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 89 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE); 90 91 /* analyze results */ 92 results = ctx->screen->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_READ); 93 if (results) { 94 for(i = 0; i < ctx->max_db; i++) { 95 /* at least highest bit will be set if backend is used */ 96 if (results[i*4 + 1]) 97 mask |= (1<<i); 98 } 99 ctx->screen->ws->buffer_unmap(buffer->buf); 100 } 101 } 102 103 pipe_resource_reference((struct pipe_resource**)&buffer, NULL); 104 105 if (mask != 0) { 106 ctx->backend_mask = mask; 107 return; 108 } 109 110err: 111 /* fallback to old method - set num_backends lower bits to 1 */ 112 ctx->backend_mask = (~((u32)0))>>(32-num_backends); 113 return; 114} 115 116static inline void r600_context_ps_partial_flush(struct r600_context *ctx) 117{ 118 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING)) 119 return; 120 121 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 122 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); 123 124 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING; 125} 126 127void r600_init_cs(struct r600_context *ctx) 128{ 129 /* R6xx requires this packet at the start of each command buffer */ 130 if (ctx->screen->family < CHIP_RV770) { 131 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0); 132 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000; 133 } 134 /* All asics require this one */ 135 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0); 136 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000; 137 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000; 138 139 ctx->init_dwords = ctx->pm4_cdwords; 140} 141 142static void r600_init_block(struct r600_context *ctx, 143 struct r600_block *block, 144 const struct r600_reg *reg, int index, int nreg, 145 unsigned opcode, unsigned offset_base) 146{ 147 int i = index; 148 int j, n = nreg; 149 150 /* initialize block */ 151 if (opcode == PKT3_SET_RESOURCE) { 152 block->flags = BLOCK_FLAG_RESOURCE; 153 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */ 154 } else { 155 block->flags = 0; 156 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */ 157 } 158 block->start_offset = reg[i].offset; 159 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0); 160 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2; 161 block->reg = &block->pm4[block->pm4_ndwords]; 162 block->pm4_ndwords += n; 163 block->nreg = n; 164 block->nreg_dirty = n; 165 LIST_INITHEAD(&block->list); 166 LIST_INITHEAD(&block->enable_list); 167 168 for (j = 0; j < n; j++) { 169 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) { 170 block->flags |= REG_FLAG_DIRTY_ALWAYS; 171 } 172 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) { 173 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 174 block->status |= R600_BLOCK_STATUS_ENABLED; 175 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 176 LIST_ADDTAIL(&block->list,&ctx->dirty); 177 } 178 } 179 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) { 180 block->flags |= REG_FLAG_FLUSH_CHANGE; 181 } 182 183 if (reg[i+j].flags & REG_FLAG_NEED_BO) { 184 block->nbo++; 185 assert(block->nbo < R600_BLOCK_MAX_BO); 186 block->pm4_bo_index[j] = block->nbo; 187 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0); 188 block->pm4[block->pm4_ndwords++] = 0x00000000; 189 if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) { 190 block->reloc[block->nbo].flush_flags = 0; 191 block->reloc[block->nbo].flush_mask = 0; 192 } else { 193 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags; 194 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask; 195 } 196 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1; 197 } 198 if ((ctx->screen->family > CHIP_R600) && 199 (ctx->screen->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) { 200 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0); 201 block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags; 202 } 203 } 204 for (j = 0; j < n; j++) { 205 if (reg[i+j].flush_flags) { 206 block->pm4_flush_ndwords += 7; 207 } 208 } 209 /* check that we stay in limit */ 210 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG); 211} 212 213int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg, 214 unsigned opcode, unsigned offset_base) 215{ 216 struct r600_block *block; 217 struct r600_range *range; 218 int offset; 219 220 for (unsigned i = 0, n = 0; i < nreg; i += n) { 221 /* ignore new block balise */ 222 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) { 223 n = 1; 224 continue; 225 } 226 227 /* ignore regs not on R600 on R600 */ 228 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->screen->family == CHIP_R600) { 229 n = 1; 230 continue; 231 } 232 233 /* register that need relocation are in their own group */ 234 /* find number of consecutive registers */ 235 n = 0; 236 offset = reg[i].offset; 237 while (reg[i + n].offset == offset) { 238 n++; 239 offset += 4; 240 if ((n + i) >= nreg) 241 break; 242 if (n >= (R600_BLOCK_MAX_REG - 2)) 243 break; 244 } 245 246 /* allocate new block */ 247 block = calloc(1, sizeof(struct r600_block)); 248 if (block == NULL) { 249 return -ENOMEM; 250 } 251 ctx->nblocks++; 252 for (int j = 0; j < n; j++) { 253 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)]; 254 /* create block table if it doesn't exist */ 255 if (!range->blocks) 256 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *)); 257 if (!range->blocks) 258 return -1; 259 260 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block; 261 } 262 263 r600_init_block(ctx, block, reg, i, n, opcode, offset_base); 264 265 } 266 return 0; 267} 268 269/* R600/R700 configuration */ 270static const struct r600_reg r600_config_reg_list[] = { 271 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, 272 {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 273 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 274 {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 275 {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 276 {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 277 {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 278 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 279 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 280 {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 281 {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 282 {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 283}; 284 285static const struct r600_reg r600_ctl_const_list[] = { 286 {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, 287 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, 288}; 289 290static const struct r600_reg r600_context_reg_list[] = { 291 {R_028350_SX_MISC, 0, 0, 0}, 292 {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, 293 {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, 294 {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, 295 {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, 296 {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, 297 {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, 298 {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, 299 {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0}, 300 {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0}, 301 {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, 302 {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, 303 {R_028A14_VGT_HOS_CNTL, 0, 0, 0}, 304 {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, 305 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, 306 {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, 307 {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, 308 {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, 309 {R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, 310 {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, 311 {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, 312 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, 313 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, 314 {R_028A40_VGT_GS_MODE, 0, 0, 0}, 315 {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0}, 316 {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0}, 317 {R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, 318 {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, 319 {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0}, 320 {R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, 321 {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, 322 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 323 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0}, 324 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 325 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 326 {R_028060_CB_COLOR0_SIZE, 0, 0, 0}, 327 {R_028080_CB_COLOR0_VIEW, 0, 0, 0}, 328 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 329 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0}, 330 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 331 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0}, 332 {R_028100_CB_COLOR0_MASK, 0, 0, 0}, 333 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 334 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0}, 335 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 336 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 337 {R_028064_CB_COLOR1_SIZE, 0, 0, 0}, 338 {R_028084_CB_COLOR1_VIEW, 0, 0, 0}, 339 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 340 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0}, 341 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 342 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0}, 343 {R_028104_CB_COLOR1_MASK, 0, 0, 0}, 344 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 345 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0}, 346 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 347 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 348 {R_028068_CB_COLOR2_SIZE, 0, 0, 0}, 349 {R_028088_CB_COLOR2_VIEW, 0, 0, 0}, 350 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 351 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0}, 352 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 353 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0}, 354 {R_028108_CB_COLOR2_MASK, 0, 0, 0}, 355 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 356 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0}, 357 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 358 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 359 {R_02806C_CB_COLOR3_SIZE, 0, 0, 0}, 360 {R_02808C_CB_COLOR3_VIEW, 0, 0, 0}, 361 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 362 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0}, 363 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 364 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0}, 365 {R_02810C_CB_COLOR3_MASK, 0, 0, 0}, 366 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 367 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0}, 368 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 369 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 370 {R_028070_CB_COLOR4_SIZE, 0, 0, 0}, 371 {R_028090_CB_COLOR4_VIEW, 0, 0, 0}, 372 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 373 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0}, 374 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 375 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0}, 376 {R_028110_CB_COLOR4_MASK, 0, 0, 0}, 377 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 378 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0}, 379 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 380 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 381 {R_028074_CB_COLOR5_SIZE, 0, 0, 0}, 382 {R_028094_CB_COLOR5_VIEW, 0, 0, 0}, 383 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 384 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0}, 385 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 386 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0}, 387 {R_028114_CB_COLOR5_MASK, 0, 0, 0}, 388 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0}, 389 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 390 {R_028078_CB_COLOR6_SIZE, 0, 0, 0}, 391 {R_028098_CB_COLOR6_VIEW, 0, 0, 0}, 392 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 393 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0}, 394 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 395 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0}, 396 {R_028118_CB_COLOR6_MASK, 0, 0, 0}, 397 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 398 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0}, 399 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 400 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 401 {R_02807C_CB_COLOR7_SIZE, 0, 0, 0}, 402 {R_02809C_CB_COLOR7_VIEW, 0, 0, 0}, 403 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0}, 404 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0}, 405 {R_02811C_CB_COLOR7_MASK, 0, 0, 0}, 406 {R_028120_CB_CLEAR_RED, 0, 0, 0}, 407 {R_028124_CB_CLEAR_GREEN, 0, 0, 0}, 408 {R_028128_CB_CLEAR_BLUE, 0, 0, 0}, 409 {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0}, 410 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, 411 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, 412 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 413 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 414 {R_02823C_CB_SHADER_MASK, 0, 0, 0}, 415 {R_028238_CB_TARGET_MASK, 0, 0, 0}, 416 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, 417 {R_028414_CB_BLEND_RED, 0, 0, 0}, 418 {R_028418_CB_BLEND_GREEN, 0, 0, 0}, 419 {R_02841C_CB_BLEND_BLUE, 0, 0, 0}, 420 {R_028420_CB_BLEND_ALPHA, 0, 0, 0}, 421 {R_028424_CB_FOG_RED, 0, 0, 0}, 422 {R_028428_CB_FOG_GREEN, 0, 0, 0}, 423 {R_02842C_CB_FOG_BLUE, 0, 0, 0}, 424 {R_028430_DB_STENCILREFMASK, 0, 0, 0}, 425 {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, 426 {R_028438_SX_ALPHA_REF, 0, 0, 0}, 427 {R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, 428 {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0}, 429 {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0}, 430 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 431 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 432 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 433 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 434 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 435 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 436 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 437 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 438 {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0}, 439 {R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, 440 {R_028804_CB_BLEND_CONTROL, 0, 0, 0}, 441 {R_028808_CB_COLOR_CONTROL, 0, 0, 0}, 442 {R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, 443 {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, 444 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, 445 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0}, 446 {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0}, 447 {R_028C34_CB_CLRCMP_SRC, 0, 0, 0}, 448 {R_028C38_CB_CLRCMP_DST, 0, 0, 0}, 449 {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0}, 450 {R_028C48_PA_SC_AA_MASK, 0, 0, 0}, 451 {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, 452 {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0}, 453 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0}, 454 {R_028000_DB_DEPTH_SIZE, 0, 0, 0}, 455 {R_028004_DB_DEPTH_VIEW, 0, 0, 0}, 456 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 457 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0}, 458 {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0}, 459 {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0}, 460 {R_028D24_DB_HTILE_SURFACE, 0, 0, 0}, 461 {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0}, 462 {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0}, 463 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, 464 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, 465 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, 466 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, 467 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, 468 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, 469 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, 470 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, 471 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, 472 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, 473 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, 474 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, 475 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, 476 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, 477 {R_028230_PA_SC_EDGERULE, 0, 0, 0}, 478 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, 479 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, 480 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, 481 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, 482 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, 483 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, 484 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, 485 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, 486 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, 487 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, 488 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, 489 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, 490 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, 491 {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, 492 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, 493 {R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, 494 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, 495 {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, 496 {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, 497 {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, 498 {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, 499 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0}, 500 {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0}, 501 {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, 502 {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, 503 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, 504 {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, 505 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, 506 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, 507 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, 508 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, 509 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, 510 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, 511 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, 512 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, 513 {R_028E20_PA_CL_UCP0_X, 0, 0, 0}, 514 {R_028E24_PA_CL_UCP0_Y, 0, 0, 0}, 515 {R_028E28_PA_CL_UCP0_Z, 0, 0, 0}, 516 {R_028E2C_PA_CL_UCP0_W, 0, 0, 0}, 517 {R_028E30_PA_CL_UCP1_X, 0, 0, 0}, 518 {R_028E34_PA_CL_UCP1_Y, 0, 0, 0}, 519 {R_028E38_PA_CL_UCP1_Z, 0, 0, 0}, 520 {R_028E3C_PA_CL_UCP1_W, 0, 0, 0}, 521 {R_028E40_PA_CL_UCP2_X, 0, 0, 0}, 522 {R_028E44_PA_CL_UCP2_Y, 0, 0, 0}, 523 {R_028E48_PA_CL_UCP2_Z, 0, 0, 0}, 524 {R_028E4C_PA_CL_UCP2_W, 0, 0, 0}, 525 {R_028E50_PA_CL_UCP3_X, 0, 0, 0}, 526 {R_028E54_PA_CL_UCP3_Y, 0, 0, 0}, 527 {R_028E58_PA_CL_UCP3_Z, 0, 0, 0}, 528 {R_028E5C_PA_CL_UCP3_W, 0, 0, 0}, 529 {R_028E60_PA_CL_UCP4_X, 0, 0, 0}, 530 {R_028E64_PA_CL_UCP4_Y, 0, 0, 0}, 531 {R_028E68_PA_CL_UCP4_Z, 0, 0, 0}, 532 {R_028E6C_PA_CL_UCP4_W, 0, 0, 0}, 533 {R_028E70_PA_CL_UCP5_X, 0, 0, 0}, 534 {R_028E74_PA_CL_UCP5_Y, 0, 0, 0}, 535 {R_028E78_PA_CL_UCP5_Z, 0, 0, 0}, 536 {R_028E7C_PA_CL_UCP5_W, 0, 0, 0}, 537 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, 538 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, 539 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, 540 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, 541 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, 542 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, 543 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, 544 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, 545 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, 546 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, 547 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, 548 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, 549 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, 550 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, 551 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, 552 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, 553 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, 554 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, 555 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, 556 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, 557 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, 558 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, 559 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, 560 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, 561 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, 562 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, 563 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, 564 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, 565 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, 566 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, 567 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, 568 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, 569 {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0}, 570 {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0}, 571 {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0}, 572 {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0}, 573 {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0}, 574 {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0}, 575 {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0}, 576 {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0}, 577 {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0}, 578 {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0}, 579 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, 580 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 581 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 582 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 583 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0}, 584 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 585 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 586 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 587 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0}, 588 {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0}, 589 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0}, 590 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, 591 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, 592 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, 593 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, 594 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, 595 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, 596 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, 597 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, 598 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, 599 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, 600 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, 601 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, 602 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, 603 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, 604 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, 605 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, 606 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, 607 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, 608 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, 609 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, 610 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, 611 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, 612 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, 613 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, 614 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, 615 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, 616 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, 617 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, 618 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, 619 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, 620 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, 621 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, 622 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, 623 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, 624 {R_0286D8_SPI_INPUT_Z, 0, 0, 0}, 625 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 626 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 627 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 628 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0}, 629 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0}, 630 {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0}, 631 {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, 632 {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, 633 {R_028408_VGT_INDX_OFFSET, 0, 0, 0}, 634 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, 635 {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0}, 636 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, 637 {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0}, 638 {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0}, 639}; 640 641/* SHADER RESOURCE R600/R700 */ 642int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base) 643{ 644 int i; 645 struct r600_block *block; 646 range->blocks = calloc(nblocks, sizeof(struct r600_block *)); 647 if (range->blocks == NULL) 648 return -ENOMEM; 649 650 reg[0].offset += offset; 651 for (i = 0; i < nblocks; i++) { 652 block = calloc(1, sizeof(struct r600_block)); 653 if (block == NULL) { 654 return -ENOMEM; 655 } 656 ctx->nblocks++; 657 range->blocks[i] = block; 658 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base); 659 660 reg[0].offset += stride; 661 } 662 return 0; 663} 664 665 666static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride) 667{ 668 struct r600_reg r600_shader_resource[] = { 669 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, 670 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, 671 {R_038008_RESOURCE0_WORD2, 0, 0, 0}, 672 {R_03800C_RESOURCE0_WORD3, 0, 0, 0}, 673 {R_038010_RESOURCE0_WORD4, 0, 0, 0}, 674 {R_038014_RESOURCE0_WORD5, 0, 0, 0}, 675 {R_038018_RESOURCE0_WORD6, 0, 0, 0}, 676 }; 677 unsigned nreg = Elements(r600_shader_resource); 678 679 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET); 680} 681 682/* SHADER SAMPLER R600/R700 */ 683static int r600_state_sampler_init(struct r600_context *ctx, u32 offset) 684{ 685 struct r600_reg r600_shader_sampler[] = { 686 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, 687 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, 688 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, 689 }; 690 unsigned nreg = Elements(r600_shader_sampler); 691 692 for (int i = 0; i < nreg; i++) { 693 r600_shader_sampler[i].offset += offset; 694 } 695 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET); 696} 697 698/* SHADER SAMPLER BORDER R600/R700 */ 699static int r600_state_sampler_border_init(struct r600_context *ctx, u32 offset) 700{ 701 struct r600_reg r600_shader_sampler_border[] = { 702 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, 703 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, 704 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, 705 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, 706 }; 707 unsigned nreg = Elements(r600_shader_sampler_border); 708 709 for (int i = 0; i < nreg; i++) { 710 r600_shader_sampler_border[i].offset += offset; 711 } 712 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); 713} 714 715static int r600_loop_const_init(struct r600_context *ctx, u32 offset) 716{ 717 unsigned nreg = 32; 718 struct r600_reg r600_loop_consts[32]; 719 int i; 720 721 for (i = 0; i < nreg; i++) { 722 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4); 723 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS; 724 r600_loop_consts[i].flush_flags = 0; 725 r600_loop_consts[i].flush_mask = 0; 726 } 727 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET); 728} 729 730static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks) 731{ 732 struct r600_block *block; 733 int i; 734 for (i = 0; i < nblocks; i++) { 735 block = range->blocks[i]; 736 if (block) { 737 for (int k = 1; k <= block->nbo; k++) 738 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL); 739 free(block); 740 } 741 } 742 free(range->blocks); 743 744} 745 746/* initialize */ 747void r600_context_fini(struct r600_context *ctx) 748{ 749 struct r600_block *block; 750 struct r600_range *range; 751 752 for (int i = 0; i < NUM_RANGES; i++) { 753 if (!ctx->range[i].blocks) 754 continue; 755 for (int j = 0; j < (1 << HASH_SHIFT); j++) { 756 block = ctx->range[i].blocks[j]; 757 if (block) { 758 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) { 759 range = &ctx->range[CTX_RANGE_ID(offset)]; 760 range->blocks[CTX_BLOCK_ID(offset)] = NULL; 761 } 762 for (int k = 1; k <= block->nbo; k++) { 763 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL); 764 } 765 free(block); 766 } 767 } 768 free(ctx->range[i].blocks); 769 } 770 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources); 771 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources); 772 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources); 773 free(ctx->range); 774 free(ctx->blocks); 775 free(ctx->bo); 776 ctx->screen->ws->cs_destroy(ctx->cs); 777 778 memset(ctx, 0, sizeof(struct r600_context)); 779} 780 781static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index) 782{ 783 int c = *index; 784 for (int j = 0; j < num_blocks; j++) { 785 if (!range->blocks[j]) 786 continue; 787 788 ctx->blocks[c++] = range->blocks[j]; 789 } 790 *index = c; 791} 792 793int r600_setup_block_table(struct r600_context *ctx) 794{ 795 /* setup block table */ 796 int c = 0; 797 ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); 798 if (!ctx->blocks) 799 return -ENOMEM; 800 for (int i = 0; i < NUM_RANGES; i++) { 801 if (!ctx->range[i].blocks) 802 continue; 803 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) { 804 if (!ctx->range[i].blocks[j]) 805 continue; 806 807 add = 1; 808 for (int k = 0; k < c; k++) { 809 if (ctx->blocks[k] == ctx->range[i].blocks[j]) { 810 add = 0; 811 break; 812 } 813 } 814 if (add) { 815 assert(c < ctx->nblocks); 816 ctx->blocks[c++] = ctx->range[i].blocks[j]; 817 j += (ctx->range[i].blocks[j]->nreg) - 1; 818 } 819 } 820 } 821 822 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c); 823 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c); 824 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c); 825 return 0; 826} 827 828int r600_context_init(struct r600_context *ctx, struct r600_screen *screen) 829{ 830 int r; 831 832 memset(ctx, 0, sizeof(struct r600_context)); 833 ctx->screen = screen; 834 835 LIST_INITHEAD(&ctx->active_query_list); 836 837 /* init dirty list */ 838 LIST_INITHEAD(&ctx->dirty); 839 LIST_INITHEAD(&ctx->resource_dirty); 840 LIST_INITHEAD(&ctx->enable_list); 841 842 ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range)); 843 if (!ctx->range) { 844 r = -ENOMEM; 845 goto out_err; 846 } 847 848 /* add blocks */ 849 r = r600_context_add_block(ctx, r600_config_reg_list, 850 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); 851 if (r) 852 goto out_err; 853 r = r600_context_add_block(ctx, r600_context_reg_list, 854 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET); 855 if (r) 856 goto out_err; 857 r = r600_context_add_block(ctx, r600_ctl_const_list, 858 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET); 859 if (r) 860 goto out_err; 861 862 /* PS SAMPLER BORDER */ 863 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) { 864 r = r600_state_sampler_border_init(ctx, offset); 865 if (r) 866 goto out_err; 867 } 868 869 /* VS SAMPLER BORDER */ 870 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) { 871 r = r600_state_sampler_border_init(ctx, offset); 872 if (r) 873 goto out_err; 874 } 875 /* PS SAMPLER */ 876 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) { 877 r = r600_state_sampler_init(ctx, offset); 878 if (r) 879 goto out_err; 880 } 881 /* VS SAMPLER */ 882 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) { 883 r = r600_state_sampler_init(ctx, offset); 884 if (r) 885 goto out_err; 886 } 887 888 ctx->num_ps_resources = 160; 889 ctx->num_vs_resources = 160; 890 ctx->num_fs_resources = 16; 891 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c); 892 if (r) 893 goto out_err; 894 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c); 895 if (r) 896 goto out_err; 897 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c); 898 if (r) 899 goto out_err; 900 901 /* PS loop const */ 902 r600_loop_const_init(ctx, 0); 903 /* VS loop const */ 904 r600_loop_const_init(ctx, 32); 905 906 r = r600_setup_block_table(ctx); 907 if (r) 908 goto out_err; 909 910 ctx->cs = screen->ws->cs_create(screen->ws); 911 912 /* allocate cs variables */ 913 ctx->bo = calloc(RADEON_MAX_CMDBUF_DWORDS, sizeof(void *)); 914 if (ctx->bo == NULL) { 915 r = -ENOMEM; 916 goto out_err; 917 } 918 ctx->pm4_ndwords = RADEON_MAX_CMDBUF_DWORDS; 919 ctx->pm4 = ctx->cs->buf; 920 921 r600_init_cs(ctx); 922 /* save 16dwords space for fence mecanism */ 923 ctx->pm4_ndwords -= 16; 924 ctx->max_db = 4; 925 926 r600_get_backend_mask(ctx); 927 return 0; 928out_err: 929 r600_context_fini(ctx); 930 return r; 931} 932 933/* Flushes all surfaces */ 934void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags) 935{ 936 unsigned ndwords = 5; 937 938 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) { 939 /* need to flush */ 940 r600_context_flush(ctx, RADEON_FLUSH_ASYNC); 941 } 942 943 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing); 944 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */ 945 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */ 946 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */ 947 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */ 948} 949 950void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, 951 unsigned flush_mask, struct r600_resource *bo) 952{ 953 /* if bo has already been flushed */ 954 if (!(~bo->cs_buf->last_flush & flush_flags)) { 955 bo->cs_buf->last_flush &= flush_mask; 956 return; 957 } 958 959 if ((ctx->screen->family < CHIP_RV770) && 960 (G_0085F0_CB_ACTION_ENA(flush_flags) || 961 G_0085F0_DB_ACTION_ENA(flush_flags))) { 962 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) { 963 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */ 964 if ((bo->cs_buf->binding & BO_BOUND_TEXTURE) && 965 (flush_flags & S_0085F0_CB_ACTION_ENA(1))) { 966 if ((ctx->screen->family == CHIP_RV670) || 967 (ctx->screen->family == CHIP_RS780) || 968 (ctx->screen->family == CHIP_RS880)) { 969 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing); 970 ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */ 971 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */ 972 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */ 973 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */ 974 } 975 } 976 977 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, ctx->predicate_drawing); 978 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0); 979 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; 980 } 981 } else { 982 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, ctx->predicate_drawing); 983 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; 984 ctx->pm4[ctx->pm4_cdwords++] = (bo->buf->size + 255) >> 8; 985 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000; 986 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; 987 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing); 988 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, bo, RADEON_USAGE_WRITE); 989 } 990 bo->cs_buf->last_flush = (bo->cs_buf->last_flush | flush_flags) & flush_mask; 991} 992 993void r600_context_reg(struct r600_context *ctx, 994 unsigned offset, unsigned value, 995 unsigned mask) 996{ 997 struct r600_range *range; 998 struct r600_block *block; 999 unsigned id; 1000 unsigned new_val; 1001 int dirty; 1002 1003 range = &ctx->range[CTX_RANGE_ID(offset)]; 1004 block = range->blocks[CTX_BLOCK_ID(offset)]; 1005 id = (offset - block->start_offset) >> 2; 1006 1007 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 1008 1009 new_val = block->reg[id]; 1010 new_val &= ~mask; 1011 new_val |= value; 1012 if (new_val != block->reg[id]) { 1013 dirty |= R600_BLOCK_STATUS_DIRTY; 1014 block->reg[id] = new_val; 1015 } 1016 if (dirty) 1017 r600_context_dirty_block(ctx, block, dirty, id); 1018} 1019 1020void r600_context_dirty_block(struct r600_context *ctx, 1021 struct r600_block *block, 1022 int dirty, int index) 1023{ 1024 if ((index + 1) > block->nreg_dirty) 1025 block->nreg_dirty = index + 1; 1026 1027 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) { 1028 block->status |= R600_BLOCK_STATUS_DIRTY; 1029 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; 1030 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 1031 block->status |= R600_BLOCK_STATUS_ENABLED; 1032 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 1033 } 1034 LIST_ADDTAIL(&block->list,&ctx->dirty); 1035 1036 if (block->flags & REG_FLAG_FLUSH_CHANGE) { 1037 r600_context_ps_partial_flush(ctx); 1038 } 1039 } 1040} 1041 1042void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state) 1043{ 1044 struct r600_block *block; 1045 unsigned new_val; 1046 int dirty; 1047 for (int i = 0; i < state->nregs; i++) { 1048 unsigned id, reloc_id; 1049 struct r600_pipe_reg *reg = &state->regs[i]; 1050 1051 block = reg->block; 1052 id = reg->id; 1053 1054 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 1055 1056 new_val = block->reg[id]; 1057 new_val &= ~reg->mask; 1058 new_val |= reg->value; 1059 if (new_val != block->reg[id]) { 1060 block->reg[id] = new_val; 1061 dirty |= R600_BLOCK_STATUS_DIRTY; 1062 } 1063 if (block->flags & REG_FLAG_DIRTY_ALWAYS) 1064 dirty |= R600_BLOCK_STATUS_DIRTY; 1065 if (block->pm4_bo_index[id]) { 1066 /* find relocation */ 1067 reloc_id = block->pm4_bo_index[id]; 1068 pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, ®->bo->b.b.b); 1069 block->reloc[reloc_id].bo_usage = reg->bo_usage; 1070 /* always force dirty for relocs for now */ 1071 dirty |= R600_BLOCK_STATUS_DIRTY; 1072 } 1073 1074 if (dirty) 1075 r600_context_dirty_block(ctx, block, dirty, id); 1076 } 1077} 1078 1079static void r600_context_dirty_resource_block(struct r600_context *ctx, 1080 struct r600_block *block, 1081 int dirty, int index) 1082{ 1083 block->nreg_dirty = index + 1; 1084 1085 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) { 1086 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1087 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; 1088 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 1089 block->status |= R600_BLOCK_STATUS_ENABLED; 1090 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 1091 } 1092 LIST_ADDTAIL(&block->list,&ctx->resource_dirty); 1093 } 1094} 1095 1096void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block) 1097{ 1098 int dirty; 1099 int num_regs = ctx->screen->chip_class >= EVERGREEN ? 8 : 7; 1100 boolean is_vertex; 1101 1102 if (state == NULL) { 1103 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY); 1104 if (block->reloc[1].bo) 1105 block->reloc[1].bo->cs_buf->binding &= ~BO_BOUND_TEXTURE; 1106 1107 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, NULL); 1108 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL); 1109 LIST_DELINIT(&block->list); 1110 LIST_DELINIT(&block->enable_list); 1111 return; 1112 } 1113 1114 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000); 1115 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY; 1116 1117 if (memcmp(block->reg, state->val, num_regs*4)) { 1118 memcpy(block->reg, state->val, num_regs * 4); 1119 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1120 } 1121 1122 /* if no BOs on block, force dirty */ 1123 if (!block->reloc[1].bo || !block->reloc[2].bo) 1124 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1125 1126 if (!dirty) { 1127 if (is_vertex) { 1128 if (block->reloc[1].bo->buf != state->bo[0]->buf) 1129 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1130 } else { 1131 if ((block->reloc[1].bo->buf != state->bo[0]->buf) || 1132 (block->reloc[2].bo->buf != state->bo[1]->buf)) 1133 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1134 } 1135 } 1136 1137 if (dirty) { 1138 if (is_vertex) { 1139 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so 1140 * we have single case btw VERTEX & TEXTURE resource 1141 */ 1142 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b); 1143 block->reloc[1].bo_usage = state->bo_usage[0]; 1144 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL); 1145 } else { 1146 /* TEXTURE RESOURCE */ 1147 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b); 1148 block->reloc[1].bo_usage = state->bo_usage[0]; 1149 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b.b); 1150 block->reloc[2].bo_usage = state->bo_usage[1]; 1151 state->bo[0]->cs_buf->binding |= BO_BOUND_TEXTURE; 1152 } 1153 1154 if (is_vertex) 1155 block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX; 1156 else 1157 block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX; 1158 1159 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1); 1160 } 1161} 1162 1163void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 1164{ 1165 struct r600_block *block = ctx->ps_resources.blocks[rid]; 1166 1167 r600_context_pipe_state_set_resource(ctx, state, block); 1168} 1169 1170void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 1171{ 1172 struct r600_block *block = ctx->vs_resources.blocks[rid]; 1173 1174 r600_context_pipe_state_set_resource(ctx, state, block); 1175} 1176 1177void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 1178{ 1179 struct r600_block *block = ctx->fs_resources.blocks[rid]; 1180 1181 r600_context_pipe_state_set_resource(ctx, state, block); 1182} 1183 1184static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) 1185{ 1186 struct r600_range *range; 1187 struct r600_block *block; 1188 int i; 1189 int dirty; 1190 1191 range = &ctx->range[CTX_RANGE_ID(offset)]; 1192 block = range->blocks[CTX_BLOCK_ID(offset)]; 1193 if (state == NULL) { 1194 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); 1195 LIST_DELINIT(&block->list); 1196 LIST_DELINIT(&block->enable_list); 1197 return; 1198 } 1199 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 1200 for (i = 0; i < 3; i++) { 1201 if (block->reg[i] != state->regs[i].value) { 1202 block->reg[i] = state->regs[i].value; 1203 dirty |= R600_BLOCK_STATUS_DIRTY; 1204 } 1205 } 1206 1207 if (dirty) 1208 r600_context_dirty_block(ctx, block, dirty, 2); 1209} 1210 1211 1212static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) 1213{ 1214 struct r600_range *range; 1215 struct r600_block *block; 1216 int i; 1217 int dirty; 1218 1219 range = &ctx->range[CTX_RANGE_ID(offset)]; 1220 block = range->blocks[CTX_BLOCK_ID(offset)]; 1221 if (state == NULL) { 1222 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); 1223 LIST_DELINIT(&block->list); 1224 LIST_DELINIT(&block->enable_list); 1225 return; 1226 } 1227 if (state->nregs <= 3) { 1228 return; 1229 } 1230 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 1231 for (i = 0; i < 4; i++) { 1232 if (block->reg[i] != state->regs[i + 3].value) { 1233 block->reg[i] = state->regs[i + 3].value; 1234 dirty |= R600_BLOCK_STATUS_DIRTY; 1235 } 1236 } 1237 1238 /* We have to flush the shaders before we change the border color 1239 * registers, or previous draw commands that haven't completed yet 1240 * will end up using the new border color. */ 1241 if (dirty & R600_BLOCK_STATUS_DIRTY) 1242 r600_context_ps_partial_flush(ctx); 1243 if (dirty) 1244 r600_context_dirty_block(ctx, block, dirty, 3); 1245} 1246 1247void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) 1248{ 1249 unsigned offset; 1250 1251 offset = 0x0003C000 + id * 0xc; 1252 r600_context_pipe_state_set_sampler(ctx, state, offset); 1253 offset = 0x0000A400 + id * 0x10; 1254 r600_context_pipe_state_set_sampler_border(ctx, state, offset); 1255} 1256 1257void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) 1258{ 1259 unsigned offset; 1260 1261 offset = 0x0003C0D8 + id * 0xc; 1262 r600_context_pipe_state_set_sampler(ctx, state, offset); 1263 offset = 0x0000A600 + id * 0x10; 1264 r600_context_pipe_state_set_sampler_border(ctx, state, offset); 1265} 1266 1267struct r600_resource *r600_context_reg_bo(struct r600_context *ctx, unsigned offset) 1268{ 1269 struct r600_range *range; 1270 struct r600_block *block; 1271 unsigned id; 1272 1273 range = &ctx->range[CTX_RANGE_ID(offset)]; 1274 block = range->blocks[CTX_BLOCK_ID(offset)]; 1275 offset -= block->start_offset; 1276 id = block->pm4_bo_index[offset >> 2]; 1277 if (block->reloc[id].bo) { 1278 return block->reloc[id].bo; 1279 } 1280 return NULL; 1281} 1282 1283void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block) 1284{ 1285 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS); 1286 int cp_dwords = block->pm4_ndwords, start_dword = 0; 1287 int new_dwords = 0; 1288 int nbo = block->nbo; 1289 1290 if (block->nreg_dirty == 0 && optional) { 1291 goto out; 1292 } 1293 1294 if (nbo) { 1295 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH; 1296 1297 for (int j = 0; j < block->nreg; j++) { 1298 if (block->pm4_bo_index[j]) { 1299 /* find relocation */ 1300 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]]; 1301 block->pm4[reloc->bo_pm4_index] = 1302 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage); 1303 r600_context_bo_flush(ctx, 1304 reloc->flush_flags, 1305 reloc->flush_mask, 1306 reloc->bo); 1307 nbo--; 1308 if (nbo == 0) 1309 break; 1310 } 1311 } 1312 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; 1313 } 1314 1315 optional &= (block->nreg_dirty != block->nreg); 1316 if (optional) { 1317 new_dwords = block->nreg_dirty; 1318 start_dword = ctx->pm4_cdwords; 1319 cp_dwords = new_dwords + 2; 1320 } 1321 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4); 1322 ctx->pm4_cdwords += cp_dwords; 1323 1324 if (optional) { 1325 uint32_t newword; 1326 1327 newword = ctx->pm4[start_dword]; 1328 newword &= PKT_COUNT_C; 1329 newword |= PKT_COUNT_S(new_dwords); 1330 ctx->pm4[start_dword] = newword; 1331 } 1332out: 1333 block->status ^= R600_BLOCK_STATUS_DIRTY; 1334 block->nreg_dirty = 0; 1335 LIST_DELINIT(&block->list); 1336} 1337 1338void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block) 1339{ 1340 int cp_dwords = block->pm4_ndwords; 1341 int nbo = block->nbo; 1342 1343 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH; 1344 1345 if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) { 1346 nbo = 1; 1347 cp_dwords -= 2; /* don't copy the second NOP */ 1348 } 1349 1350 for (int j = 0; j < nbo; j++) { 1351 if (block->pm4_bo_index[j]) { 1352 /* find relocation */ 1353 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]]; 1354 block->pm4[reloc->bo_pm4_index] = 1355 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage); 1356 r600_context_bo_flush(ctx, 1357 reloc->flush_flags, 1358 reloc->flush_mask, 1359 reloc->bo); 1360 } 1361 } 1362 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; 1363 1364 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4); 1365 ctx->pm4_cdwords += cp_dwords; 1366 1367 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1368 block->nreg_dirty = 0; 1369 LIST_DELINIT(&block->list); 1370} 1371 1372void r600_context_flush_dest_caches(struct r600_context *ctx) 1373{ 1374 struct r600_resource *cb[8]; 1375 struct r600_resource *db; 1376 int i; 1377 1378 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY)) 1379 return; 1380 1381 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE); 1382 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE); 1383 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE); 1384 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE); 1385 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE); 1386 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE); 1387 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE); 1388 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE); 1389 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE); 1390 1391 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH; 1392 /* flush the color buffers */ 1393 for (i = 0; i < 8; i++) { 1394 if (!cb[i]) 1395 continue; 1396 1397 r600_context_bo_flush(ctx, 1398 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) | 1399 S_0085F0_CB_ACTION_ENA(1), 1400 0, cb[i]); 1401 } 1402 if (db) { 1403 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db); 1404 } 1405 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; 1406 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY; 1407} 1408 1409void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) 1410{ 1411 unsigned ndwords = 7; 1412 struct r600_block *dirty_block = NULL; 1413 struct r600_block *next_block; 1414 uint32_t *pm4; 1415 1416 if (draw->indices) { 1417 ndwords = 11; 1418 } 1419 1420 /* queries need some special values */ 1421 if (ctx->num_query_running) { 1422 if (ctx->screen->family >= CHIP_RV770) { 1423 r600_context_reg(ctx, 1424 R_028D0C_DB_RENDER_CONTROL, 1425 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1), 1426 S_028D0C_R700_PERFECT_ZPASS_COUNTS(1)); 1427 } 1428 r600_context_reg(ctx, 1429 R_028D10_DB_RENDER_OVERRIDE, 1430 S_028D10_NOOP_CULL_DISABLE(1), 1431 S_028D10_NOOP_CULL_DISABLE(1)); 1432 } 1433 1434 /* update the max dword count to make sure we have enough space 1435 * reserved for flushing the destination caches */ 1436 ctx->pm4_ndwords = RADEON_MAX_CMDBUF_DWORDS - ctx->num_dest_buffers * 7 - 16; 1437 1438 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) { 1439 /* need to flush */ 1440 r600_context_flush(ctx, RADEON_FLUSH_ASYNC); 1441 } 1442 /* at that point everythings is flushed and ctx->pm4_cdwords = 0 */ 1443 if ((ctx->pm4_dirty_cdwords + ndwords) > ctx->pm4_ndwords) { 1444 R600_ERR("context is too big to be scheduled\n"); 1445 return; 1446 } 1447 /* enough room to copy packet */ 1448 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) { 1449 r600_context_block_emit_dirty(ctx, dirty_block); 1450 } 1451 1452 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty, list) { 1453 r600_context_block_resource_emit_dirty(ctx, dirty_block); 1454 } 1455 1456 /* draw packet */ 1457 pm4 = &ctx->pm4[ctx->pm4_cdwords]; 1458 1459 pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing); 1460 pm4[1] = draw->vgt_index_type; 1461 pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing); 1462 pm4[3] = draw->vgt_num_instances; 1463 if (draw->indices) { 1464 pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing); 1465 pm4[5] = draw->indices_bo_offset; 1466 pm4[6] = 0; 1467 pm4[7] = draw->vgt_num_indices; 1468 pm4[8] = draw->vgt_draw_initiator; 1469 pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing); 1470 pm4[10] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ); 1471 } else { 1472 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing); 1473 pm4[5] = draw->vgt_num_indices; 1474 pm4[6] = draw->vgt_draw_initiator; 1475 } 1476 ctx->pm4_cdwords += ndwords; 1477 1478 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING); 1479 1480 /* all dirty state have been scheduled in current cs */ 1481 ctx->pm4_dirty_cdwords = 0; 1482} 1483 1484void r600_context_flush(struct r600_context *ctx, unsigned flags) 1485{ 1486 struct r600_block *enable_block = NULL; 1487 1488 if (ctx->pm4_cdwords == ctx->init_dwords) 1489 return; 1490 1491 /* suspend queries */ 1492 r600_context_queries_suspend(ctx); 1493 1494 if (ctx->screen->chip_class >= EVERGREEN) 1495 evergreen_context_flush_dest_caches(ctx); 1496 else 1497 r600_context_flush_dest_caches(ctx); 1498 1499 /* partial flush is needed to avoid lockups on some chips with user fences */ 1500 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 1501 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); 1502 1503 /* Flush the CS. */ 1504 ctx->cs->cdw = ctx->pm4_cdwords; 1505 ctx->screen->ws->cs_flush(ctx->cs, flags); 1506 1507 /* We need to get the pointer to the other CS, 1508 * the command streams are double-buffered. */ 1509 ctx->pm4 = ctx->cs->buf; 1510 1511 /* restart */ 1512 for (int i = 0; i < ctx->creloc; i++) { 1513 ctx->bo[i]->cs_buf->last_flush = 0; 1514 pipe_resource_reference((struct pipe_resource**)&ctx->bo[i], NULL); 1515 } 1516 ctx->creloc = 0; 1517 ctx->pm4_dirty_cdwords = 0; 1518 ctx->pm4_cdwords = 0; 1519 ctx->flags = 0; 1520 1521 r600_init_cs(ctx); 1522 1523 /* resume queries */ 1524 r600_context_queries_resume(ctx, TRUE); 1525 1526 /* set all valid group as dirty so they get reemited on 1527 * next draw command 1528 */ 1529 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) { 1530 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) { 1531 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) { 1532 LIST_ADDTAIL(&enable_block->list,&ctx->dirty); 1533 enable_block->status |= R600_BLOCK_STATUS_DIRTY; 1534 } 1535 } else { 1536 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) { 1537 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty); 1538 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1539 } 1540 } 1541 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords + 1542 enable_block->pm4_flush_ndwords; 1543 enable_block->nreg_dirty = enable_block->nreg; 1544 } 1545} 1546 1547void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value) 1548{ 1549 unsigned ndwords = 10; 1550 1551 if ((ctx->pm4_dirty_cdwords + ndwords + ctx->pm4_cdwords) > ctx->pm4_ndwords) { 1552 /* need to flush */ 1553 r600_context_flush(ctx, RADEON_FLUSH_ASYNC); 1554 } 1555 1556 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 1557 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); 1558 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); 1559 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); 1560 ctx->pm4[ctx->pm4_cdwords++] = offset << 2; /* ADDRESS_LO */ 1561 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24); /* DATA_SEL | INT_EN | ADDRESS_HI */ 1562 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */ 1563 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */ 1564 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 1565 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE); 1566} 1567 1568static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait) 1569{ 1570 unsigned results_base = query->results_start; 1571 u32 *map; 1572 1573 map = ctx->screen->ws->buffer_map(query->buffer->buf, ctx->cs, 1574 PIPE_TRANSFER_READ | (wait ? 0 : PIPE_TRANSFER_DONTBLOCK)); 1575 if (!map) 1576 return FALSE; 1577 1578 /* count all results across all data blocks */ 1579 while (results_base != query->results_end) { 1580 u64 start, end; 1581 u32 *current_result = (u32*)((char*)map + results_base); 1582 1583 start = (u64)current_result[0] | (u64)current_result[1] << 32; 1584 end = (u64)current_result[2] | (u64)current_result[3] << 32; 1585 if (((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL)) 1586 || query->type == PIPE_QUERY_TIME_ELAPSED) { 1587 query->result += end - start; 1588 } 1589 1590 results_base += 4 * 4; 1591 if (results_base >= query->buffer->b.b.b.width0) 1592 results_base = 0; 1593 } 1594 1595 query->results_start = query->results_end; 1596 ctx->screen->ws->buffer_unmap(query->buffer->buf); 1597 return TRUE; 1598} 1599 1600void r600_query_begin(struct r600_context *ctx, struct r600_query *query) 1601{ 1602 unsigned required_space, new_results_end; 1603 1604 /* query request needs 6/8 dwords for begin + 6/8 dwords for end */ 1605 switch (query->type) { 1606 case PIPE_QUERY_OCCLUSION_COUNTER: 1607 required_space = 12; 1608 break; 1609 case PIPE_QUERY_TIME_ELAPSED: 1610 required_space = 16; 1611 break; 1612 default: 1613 assert(0); 1614 return; 1615 } 1616 1617 if ((required_space + ctx->pm4_cdwords) > ctx->pm4_ndwords) { 1618 /* need to flush */ 1619 r600_context_flush(ctx, RADEON_FLUSH_ASYNC); 1620 } 1621 1622 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) { 1623 /* Count queries emitted without flushes, and flush if more than 1624 * half of buffer used, to avoid overwriting results which may be 1625 * still in use. */ 1626 if (query->flushed) { 1627 query->queries_emitted = 1; 1628 } else { 1629 if (++query->queries_emitted > query->buffer->b.b.b.width0 / query->result_size / 2) 1630 r600_context_flush(ctx, RADEON_FLUSH_ASYNC); 1631 } 1632 } 1633 1634 new_results_end = query->results_end + query->result_size; 1635 if (new_results_end >= query->buffer->b.b.b.width0) 1636 new_results_end = 0; 1637 1638 /* collect current results if query buffer is full */ 1639 if (new_results_end == query->results_start) { 1640 r600_query_result(ctx, query, TRUE); 1641 } 1642 1643 if (query->type == PIPE_QUERY_OCCLUSION_COUNTER) { 1644 u32 *results; 1645 int i; 1646 1647 results = ctx->screen->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); 1648 if (results) { 1649 results = (u32*)((char*)results + query->results_end); 1650 memset(results, 0, query->result_size); 1651 1652 /* Set top bits for unused backends */ 1653 for (i = 0; i < ctx->max_db; i++) { 1654 if (!(ctx->backend_mask & (1<<i))) { 1655 results[(i * 4)+1] = 0x80000000; 1656 results[(i * 4)+3] = 0x80000000; 1657 } 1658 } 1659 ctx->screen->ws->buffer_unmap(query->buffer->buf); 1660 } 1661 } 1662 1663 /* emit begin query */ 1664 switch (query->type) { 1665 case PIPE_QUERY_OCCLUSION_COUNTER: 1666 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 1667 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); 1668 ctx->pm4[ctx->pm4_cdwords++] = query->results_end; 1669 ctx->pm4[ctx->pm4_cdwords++] = 0; 1670 break; 1671 case PIPE_QUERY_TIME_ELAPSED: 1672 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); 1673 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); 1674 ctx->pm4[ctx->pm4_cdwords++] = query->results_end; 1675 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29); 1676 ctx->pm4[ctx->pm4_cdwords++] = 0; 1677 ctx->pm4[ctx->pm4_cdwords++] = 0; 1678 break; 1679 default: 1680 assert(0); 1681 } 1682 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 1683 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); 1684 1685 ctx->num_query_running++; 1686} 1687 1688void r600_query_end(struct r600_context *ctx, struct r600_query *query) 1689{ 1690 /* emit end query */ 1691 switch (query->type) { 1692 case PIPE_QUERY_OCCLUSION_COUNTER: 1693 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 1694 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); 1695 ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8; 1696 ctx->pm4[ctx->pm4_cdwords++] = 0; 1697 break; 1698 case PIPE_QUERY_TIME_ELAPSED: 1699 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); 1700 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); 1701 ctx->pm4[ctx->pm4_cdwords++] = query->results_end + 8; 1702 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29); 1703 ctx->pm4[ctx->pm4_cdwords++] = 0; 1704 ctx->pm4[ctx->pm4_cdwords++] = 0; 1705 break; 1706 default: 1707 assert(0); 1708 } 1709 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 1710 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); 1711 1712 query->results_end += query->result_size; 1713 if (query->results_end >= query->buffer->b.b.b.width0) 1714 query->results_end = 0; 1715 1716 query->flushed = FALSE; 1717 1718 ctx->num_query_running--; 1719} 1720 1721void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, 1722 int flag_wait) 1723{ 1724 if (operation == PREDICATION_OP_CLEAR) { 1725 if (ctx->pm4_cdwords + 3 > ctx->pm4_ndwords) 1726 r600_context_flush(ctx, RADEON_FLUSH_ASYNC); 1727 1728 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0); 1729 ctx->pm4[ctx->pm4_cdwords++] = 0; 1730 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR); 1731 } else { 1732 unsigned results_base = query->results_start; 1733 unsigned count; 1734 u32 op; 1735 1736 /* find count of the query data blocks */ 1737 count = query->buffer->b.b.b.width0 + query->results_end - query->results_start; 1738 if (count >= query->buffer->b.b.b.width0) { 1739 count -= query->buffer->b.b.b.width0; 1740 } 1741 count /= query->result_size; 1742 1743 if (ctx->pm4_cdwords + 5 * count > ctx->pm4_ndwords) 1744 r600_context_flush(ctx, RADEON_FLUSH_ASYNC); 1745 1746 op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE | 1747 (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW); 1748 1749 /* emit predicate packets for all data blocks */ 1750 while (results_base != query->results_end) { 1751 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0); 1752 ctx->pm4[ctx->pm4_cdwords++] = results_base; 1753 ctx->pm4[ctx->pm4_cdwords++] = op; 1754 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 1755 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer, 1756 RADEON_USAGE_READ); 1757 results_base += query->result_size; 1758 if (results_base >= query->buffer->b.b.b.width0) 1759 results_base = 0; 1760 /* set CONTINUE bit for all packets except the first */ 1761 op |= PREDICATION_CONTINUE; 1762 } 1763 } 1764} 1765 1766struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type) 1767{ 1768 struct r600_query *query; 1769 unsigned buffer_size = 4096; 1770 1771 query = CALLOC_STRUCT(r600_query); 1772 if (query == NULL) 1773 return NULL; 1774 1775 query->type = query_type; 1776 1777 switch (query_type) { 1778 case PIPE_QUERY_OCCLUSION_COUNTER: 1779 query->result_size = 4 * 4 * ctx->max_db; 1780 break; 1781 case PIPE_QUERY_TIME_ELAPSED: 1782 query->result_size = 4 * 4; 1783 break; 1784 default: 1785 assert(0); 1786 FREE(query); 1787 return NULL; 1788 } 1789 1790 /* adjust buffer size to simplify offsets wrapping math */ 1791 buffer_size -= buffer_size % query->result_size; 1792 1793 /* Queries are normally read by the CPU after 1794 * being written by the gpu, hence staging is probably a good 1795 * usage pattern. 1796 */ 1797 query->buffer = (struct r600_resource*) 1798 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING, buffer_size); 1799 if (!query->buffer) { 1800 FREE(query); 1801 return NULL; 1802 } 1803 return query; 1804} 1805 1806void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query) 1807{ 1808 pipe_resource_reference((struct pipe_resource**)&query->buffer, NULL); 1809 free(query); 1810} 1811 1812boolean r600_context_query_result(struct r600_context *ctx, 1813 struct r600_query *query, 1814 boolean wait, void *vresult) 1815{ 1816 uint64_t *result = (uint64_t*)vresult; 1817 1818 if (!r600_query_result(ctx, query, wait)) 1819 return FALSE; 1820 1821 switch (query->type) { 1822 case PIPE_QUERY_OCCLUSION_COUNTER: 1823 *result = query->result; 1824 break; 1825 case PIPE_QUERY_TIME_ELAPSED: 1826 *result = (1000000 * query->result) / ctx->screen->info.r600_clock_crystal_freq; 1827 break; 1828 default: 1829 assert(0); 1830 } 1831 1832 query->result = 0; 1833 return TRUE; 1834} 1835 1836void r600_context_queries_suspend(struct r600_context *ctx) 1837{ 1838 struct r600_query *query; 1839 1840 LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { 1841 r600_query_end(ctx, query); 1842 } 1843} 1844 1845void r600_context_queries_resume(struct r600_context *ctx, boolean flushed) 1846{ 1847 struct r600_query *query; 1848 1849 LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { 1850 if (flushed) 1851 query->flushed = TRUE; 1852 1853 r600_query_begin(ctx, query); 1854 } 1855} 1856