r600_hw_context.c revision 302862defa61b2cee1ae24159aca306f090ca854
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#include "r600_hw_context_priv.h" 27#include "r600_pipe.h" 28#include "r600d.h" 29#include "util/u_memory.h" 30#include <errno.h> 31 32#define GROUP_FORCE_NEW_BLOCK 0 33 34/* Get backends mask */ 35void r600_get_backend_mask(struct r600_context *ctx) 36{ 37 struct r600_resource *buffer; 38 uint32_t *results; 39 unsigned num_backends = ctx->screen->info.r600_num_backends; 40 unsigned i, mask = 0; 41 42 /* if backend_map query is supported by the kernel */ 43 if (ctx->screen->info.r600_backend_map_valid) { 44 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes; 45 unsigned backend_map = ctx->screen->info.r600_backend_map; 46 unsigned item_width, item_mask; 47 48 if (ctx->screen->chip_class >= EVERGREEN) { 49 item_width = 4; 50 item_mask = 0x7; 51 } else { 52 item_width = 2; 53 item_mask = 0x3; 54 } 55 56 while(num_tile_pipes--) { 57 i = backend_map & item_mask; 58 mask |= (1<<i); 59 backend_map >>= item_width; 60 } 61 if (mask != 0) { 62 ctx->backend_mask = mask; 63 return; 64 } 65 } 66 67 /* otherwise backup path for older kernels */ 68 69 /* create buffer for event data */ 70 buffer = (struct r600_resource*) 71 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, 72 PIPE_USAGE_STAGING, ctx->max_db*16); 73 if (!buffer) 74 goto err; 75 76 /* initialize buffer with zeroes */ 77 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); 78 if (results) { 79 memset(results, 0, ctx->max_db * 4 * 4); 80 ctx->ws->buffer_unmap(buffer->buf); 81 82 /* emit EVENT_WRITE for ZPASS_DONE */ 83 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 84 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); 85 ctx->pm4[ctx->pm4_cdwords++] = 0; 86 ctx->pm4[ctx->pm4_cdwords++] = 0; 87 88 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 89 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE); 90 91 /* analyze results */ 92 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_READ); 93 if (results) { 94 for(i = 0; i < ctx->max_db; i++) { 95 /* at least highest bit will be set if backend is used */ 96 if (results[i*4 + 1]) 97 mask |= (1<<i); 98 } 99 ctx->ws->buffer_unmap(buffer->buf); 100 } 101 } 102 103 pipe_resource_reference((struct pipe_resource**)&buffer, NULL); 104 105 if (mask != 0) { 106 ctx->backend_mask = mask; 107 return; 108 } 109 110err: 111 /* fallback to old method - set num_backends lower bits to 1 */ 112 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends); 113 return; 114} 115 116static inline void r600_context_ps_partial_flush(struct r600_context *ctx) 117{ 118 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING)) 119 return; 120 121 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 122 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); 123 124 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING; 125} 126 127void r600_init_cs(struct r600_context *ctx) 128{ 129 /* R6xx requires this packet at the start of each command buffer */ 130 if (ctx->screen->family < CHIP_RV770) { 131 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_START_3D_CMDBUF, 0, 0); 132 ctx->pm4[ctx->pm4_cdwords++] = 0x00000000; 133 } 134 /* All asics require this one */ 135 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_CONTEXT_CONTROL, 1, 0); 136 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000; 137 ctx->pm4[ctx->pm4_cdwords++] = 0x80000000; 138 139 ctx->init_dwords = ctx->pm4_cdwords; 140} 141 142static void r600_init_block(struct r600_context *ctx, 143 struct r600_block *block, 144 const struct r600_reg *reg, int index, int nreg, 145 unsigned opcode, unsigned offset_base) 146{ 147 int i = index; 148 int j, n = nreg; 149 150 /* initialize block */ 151 if (opcode == PKT3_SET_RESOURCE) { 152 block->flags = BLOCK_FLAG_RESOURCE; 153 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */ 154 } else { 155 block->flags = 0; 156 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */ 157 } 158 block->start_offset = reg[i].offset; 159 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0); 160 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2; 161 block->reg = &block->pm4[block->pm4_ndwords]; 162 block->pm4_ndwords += n; 163 block->nreg = n; 164 block->nreg_dirty = n; 165 LIST_INITHEAD(&block->list); 166 LIST_INITHEAD(&block->enable_list); 167 168 for (j = 0; j < n; j++) { 169 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) { 170 block->flags |= REG_FLAG_DIRTY_ALWAYS; 171 } 172 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) { 173 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 174 block->status |= R600_BLOCK_STATUS_ENABLED; 175 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 176 LIST_ADDTAIL(&block->list,&ctx->dirty); 177 } 178 } 179 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) { 180 block->flags |= REG_FLAG_FLUSH_CHANGE; 181 } 182 183 if (reg[i+j].flags & REG_FLAG_NEED_BO) { 184 block->nbo++; 185 assert(block->nbo < R600_BLOCK_MAX_BO); 186 block->pm4_bo_index[j] = block->nbo; 187 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0); 188 block->pm4[block->pm4_ndwords++] = 0x00000000; 189 if (reg[i+j].flags & REG_FLAG_RV6XX_SBU) { 190 block->reloc[block->nbo].flush_flags = 0; 191 block->reloc[block->nbo].flush_mask = 0; 192 } else { 193 block->reloc[block->nbo].flush_flags = reg[i+j].flush_flags; 194 block->reloc[block->nbo].flush_mask = reg[i+j].flush_mask; 195 } 196 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1; 197 } 198 if ((ctx->screen->family > CHIP_R600) && 199 (ctx->screen->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) { 200 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0); 201 block->pm4[block->pm4_ndwords++] = reg[i+j].flush_flags; 202 } 203 } 204 for (j = 0; j < n; j++) { 205 if (reg[i+j].flush_flags) { 206 block->pm4_flush_ndwords += 7; 207 } 208 } 209 /* check that we stay in limit */ 210 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG); 211} 212 213int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg, 214 unsigned opcode, unsigned offset_base) 215{ 216 struct r600_block *block; 217 struct r600_range *range; 218 int offset; 219 220 for (unsigned i = 0, n = 0; i < nreg; i += n) { 221 /* ignore new block balise */ 222 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) { 223 n = 1; 224 continue; 225 } 226 227 /* ignore regs not on R600 on R600 */ 228 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->screen->family == CHIP_R600) { 229 n = 1; 230 continue; 231 } 232 233 /* register that need relocation are in their own group */ 234 /* find number of consecutive registers */ 235 n = 0; 236 offset = reg[i].offset; 237 while (reg[i + n].offset == offset) { 238 n++; 239 offset += 4; 240 if ((n + i) >= nreg) 241 break; 242 if (n >= (R600_BLOCK_MAX_REG - 2)) 243 break; 244 } 245 246 /* allocate new block */ 247 block = calloc(1, sizeof(struct r600_block)); 248 if (block == NULL) { 249 return -ENOMEM; 250 } 251 ctx->nblocks++; 252 for (int j = 0; j < n; j++) { 253 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)]; 254 /* create block table if it doesn't exist */ 255 if (!range->blocks) 256 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *)); 257 if (!range->blocks) 258 return -1; 259 260 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block; 261 } 262 263 r600_init_block(ctx, block, reg, i, n, opcode, offset_base); 264 265 } 266 return 0; 267} 268 269/* R600/R700 configuration */ 270static const struct r600_reg r600_config_reg_list[] = { 271 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0, 0}, 272 {R_008C00_SQ_CONFIG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 273 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 274 {R_008C08_SQ_GPR_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 275 {R_008C0C_SQ_THREAD_RESOURCE_MGMT, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 276 {R_008C10_SQ_STACK_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 277 {R_008C14_SQ_STACK_RESOURCE_MGMT_2, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 278 {R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 279 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 280 {R_009714_VC_ENHANCE, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 281 {R_009830_DB_DEBUG, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 282 {R_009838_DB_WATERMARKS, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0, 0}, 283}; 284 285static const struct r600_reg r600_ctl_const_list[] = { 286 {R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0, 0}, 287 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0, 0}, 288}; 289 290static const struct r600_reg r600_context_reg_list[] = { 291 {R_028350_SX_MISC, 0, 0, 0}, 292 {R_0286C8_SPI_THREAD_GROUPING, 0, 0, 0}, 293 {R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0, 0, 0}, 294 {R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0, 0, 0}, 295 {R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0, 0, 0}, 296 {R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0, 0, 0}, 297 {R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0, 0, 0}, 298 {R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0, 0, 0}, 299 {R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0, 0, 0}, 300 {R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0, 0, 0}, 301 {R_0288C8_SQ_GS_VERT_ITEMSIZE, 0, 0, 0}, 302 {R_028A10_VGT_OUTPUT_PATH_CNTL, 0, 0, 0}, 303 {R_028A14_VGT_HOS_CNTL, 0, 0, 0}, 304 {R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0, 0, 0}, 305 {R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0, 0, 0}, 306 {R_028A20_VGT_HOS_REUSE_DEPTH, 0, 0, 0}, 307 {R_028A24_VGT_GROUP_PRIM_TYPE, 0, 0, 0}, 308 {R_028A28_VGT_GROUP_FIRST_DECR, 0, 0, 0}, 309 {R_028A2C_VGT_GROUP_DECR, 0, 0, 0}, 310 {R_028A30_VGT_GROUP_VECT_0_CNTL, 0, 0, 0}, 311 {R_028A34_VGT_GROUP_VECT_1_CNTL, 0, 0, 0}, 312 {R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0, 0, 0}, 313 {R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0, 0, 0}, 314 {R_028A40_VGT_GS_MODE, 0, 0, 0}, 315 {R_028A4C_PA_SC_MODE_CNTL, 0, 0, 0}, 316 {R_028AB0_VGT_STRMOUT_EN, 0, 0, 0}, 317 {R_028AB4_VGT_REUSE_OFF, 0, 0, 0}, 318 {R_028AB8_VGT_VTX_CNT_EN, 0, 0, 0}, 319 {R_028B20_VGT_STRMOUT_BUFFER_EN, 0, 0, 0}, 320 {R_028028_DB_STENCIL_CLEAR, 0, 0, 0}, 321 {R_02802C_DB_DEPTH_CLEAR, 0, 0, 0}, 322 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 323 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0), 0}, 324 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 325 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 326 {R_028060_CB_COLOR0_SIZE, 0, 0, 0}, 327 {R_028080_CB_COLOR0_VIEW, 0, 0, 0}, 328 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 329 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0, 0}, 330 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 331 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0, 0}, 332 {R_028100_CB_COLOR0_MASK, 0, 0, 0}, 333 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 334 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1), 0}, 335 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 336 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 337 {R_028064_CB_COLOR1_SIZE, 0, 0, 0}, 338 {R_028084_CB_COLOR1_VIEW, 0, 0, 0}, 339 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 340 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0, 0}, 341 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 342 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0, 0}, 343 {R_028104_CB_COLOR1_MASK, 0, 0, 0}, 344 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 345 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2), 0}, 346 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 347 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 348 {R_028068_CB_COLOR2_SIZE, 0, 0, 0}, 349 {R_028088_CB_COLOR2_VIEW, 0, 0, 0}, 350 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 351 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0, 0}, 352 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 353 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0, 0}, 354 {R_028108_CB_COLOR2_MASK, 0, 0, 0}, 355 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 356 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3), 0}, 357 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 358 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 359 {R_02806C_CB_COLOR3_SIZE, 0, 0, 0}, 360 {R_02808C_CB_COLOR3_VIEW, 0, 0, 0}, 361 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 362 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0, 0}, 363 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 364 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0, 0}, 365 {R_02810C_CB_COLOR3_MASK, 0, 0, 0}, 366 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 367 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4), 0}, 368 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 369 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 370 {R_028070_CB_COLOR4_SIZE, 0, 0, 0}, 371 {R_028090_CB_COLOR4_VIEW, 0, 0, 0}, 372 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 373 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0, 0}, 374 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 375 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0, 0}, 376 {R_028110_CB_COLOR4_MASK, 0, 0, 0}, 377 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 378 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5), 0}, 379 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 380 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 381 {R_028074_CB_COLOR5_SIZE, 0, 0, 0}, 382 {R_028094_CB_COLOR5_VIEW, 0, 0, 0}, 383 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 384 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0, 0}, 385 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 386 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0, 0}, 387 {R_028114_CB_COLOR5_MASK, 0, 0, 0}, 388 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6), 0}, 389 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 390 {R_028078_CB_COLOR6_SIZE, 0, 0, 0}, 391 {R_028098_CB_COLOR6_VIEW, 0, 0, 0}, 392 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 393 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0, 0}, 394 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 395 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0, 0}, 396 {R_028118_CB_COLOR6_MASK, 0, 0, 0}, 397 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 398 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7), 0}, 399 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 400 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0, 0xFFFFFFFF}, 401 {R_02807C_CB_COLOR7_SIZE, 0, 0, 0}, 402 {R_02809C_CB_COLOR7_VIEW, 0, 0, 0}, 403 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0, 0}, 404 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0, 0}, 405 {R_02811C_CB_COLOR7_MASK, 0, 0, 0}, 406 {R_028120_CB_CLEAR_RED, 0, 0, 0}, 407 {R_028124_CB_CLEAR_GREEN, 0, 0, 0}, 408 {R_028128_CB_CLEAR_BLUE, 0, 0, 0}, 409 {R_02812C_CB_CLEAR_ALPHA, 0, 0, 0}, 410 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, 411 {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0, 0}, 412 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0, 0}, 413 {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0, 0}, 414 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 415 {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 416 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 417 {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 418 {R_02823C_CB_SHADER_MASK, 0, 0, 0}, 419 {R_028238_CB_TARGET_MASK, 0, 0, 0}, 420 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0, 0}, 421 {R_028414_CB_BLEND_RED, 0, 0, 0}, 422 {R_028418_CB_BLEND_GREEN, 0, 0, 0}, 423 {R_02841C_CB_BLEND_BLUE, 0, 0, 0}, 424 {R_028420_CB_BLEND_ALPHA, 0, 0, 0}, 425 {R_028424_CB_FOG_RED, 0, 0, 0}, 426 {R_028428_CB_FOG_GREEN, 0, 0, 0}, 427 {R_02842C_CB_FOG_BLUE, 0, 0, 0}, 428 {R_028430_DB_STENCILREFMASK, 0, 0, 0}, 429 {R_028434_DB_STENCILREFMASK_BF, 0, 0, 0}, 430 {R_028438_SX_ALPHA_REF, 0, 0, 0}, 431 {R_0286DC_SPI_FOG_CNTL, 0, 0, 0}, 432 {R_0286E0_SPI_FOG_FUNC_SCALE, 0, 0, 0}, 433 {R_0286E4_SPI_FOG_FUNC_BIAS, 0, 0, 0}, 434 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 435 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 436 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 437 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 438 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 439 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 440 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 441 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0, 0}, 442 {R_0287A0_CB_SHADER_CONTROL, 0, 0, 0}, 443 {R_028800_DB_DEPTH_CONTROL, 0, 0, 0}, 444 {R_028804_CB_BLEND_CONTROL, 0, 0, 0}, 445 {R_028808_CB_COLOR_CONTROL, 0, 0, 0}, 446 {R_02880C_DB_SHADER_CONTROL, 0, 0, 0}, 447 {R_028C04_PA_SC_AA_CONFIG, 0, 0, 0}, 448 {R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0, 0, 0}, 449 {R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX, 0, 0, 0}, 450 {R_028C30_CB_CLRCMP_CONTROL, 0, 0, 0}, 451 {R_028C34_CB_CLRCMP_SRC, 0, 0, 0}, 452 {R_028C38_CB_CLRCMP_DST, 0, 0, 0}, 453 {R_028C3C_CB_CLRCMP_MSK, 0, 0, 0}, 454 {R_028C48_PA_SC_AA_MASK, 0, 0, 0}, 455 {R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0, 0, 0}, 456 {R_028D44_DB_ALPHA_TO_MASK, 0, 0, 0}, 457 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH, 0}, 458 {R_028000_DB_DEPTH_SIZE, 0, 0, 0}, 459 {R_028004_DB_DEPTH_VIEW, 0, 0, 0}, 460 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 461 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0, 0}, 462 {R_028D0C_DB_RENDER_CONTROL, 0, 0, 0}, 463 {R_028D10_DB_RENDER_OVERRIDE, 0, 0, 0}, 464 {R_028D24_DB_HTILE_SURFACE, 0, 0, 0}, 465 {R_028D30_DB_PRELOAD_CONTROL, 0, 0, 0}, 466 {R_028D34_DB_PREFETCH_LIMIT, 0, 0, 0}, 467 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0, 0}, 468 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0, 0}, 469 {R_028200_PA_SC_WINDOW_OFFSET, 0, 0, 0}, 470 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0, 0}, 471 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0, 0}, 472 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0, 0}, 473 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0, 0}, 474 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0, 0}, 475 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0, 0}, 476 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0, 0}, 477 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0, 0}, 478 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0, 0}, 479 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0, 0}, 480 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0, 0}, 481 {R_028230_PA_SC_EDGERULE, 0, 0, 0}, 482 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0, 0}, 483 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0, 0}, 484 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0, 0}, 485 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0, 0}, 486 {R_0282D0_PA_SC_VPORT_ZMIN_0, 0, 0, 0}, 487 {R_0282D4_PA_SC_VPORT_ZMAX_0, 0, 0, 0}, 488 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0, 0}, 489 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0, 0}, 490 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0, 0}, 491 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0, 0}, 492 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0, 0}, 493 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0, 0}, 494 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0, 0}, 495 {R_028810_PA_CL_CLIP_CNTL, 0, 0, 0}, 496 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0, 0}, 497 {R_028818_PA_CL_VTE_CNTL, 0, 0, 0}, 498 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0, 0}, 499 {R_028820_PA_CL_NANINF_CNTL, 0, 0, 0}, 500 {R_028A00_PA_SU_POINT_SIZE, 0, 0, 0}, 501 {R_028A04_PA_SU_POINT_MINMAX, 0, 0, 0}, 502 {R_028A08_PA_SU_LINE_CNTL, 0, 0, 0}, 503 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0, 0}, 504 {R_028A48_PA_SC_MPASS_PS_CNTL, 0, 0, 0}, 505 {R_028C00_PA_SC_LINE_CNTL, 0, 0, 0}, 506 {R_028C08_PA_SU_VTX_CNTL, 0, 0, 0}, 507 {R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0, 0, 0}, 508 {R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0, 0, 0}, 509 {R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0, 0, 0}, 510 {R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0, 0, 0}, 511 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0, 0}, 512 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0, 0}, 513 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0, 0}, 514 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0, 0}, 515 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0, 0}, 516 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0, 0}, 517 {R_028E20_PA_CL_UCP0_X, 0, 0, 0}, 518 {R_028E24_PA_CL_UCP0_Y, 0, 0, 0}, 519 {R_028E28_PA_CL_UCP0_Z, 0, 0, 0}, 520 {R_028E2C_PA_CL_UCP0_W, 0, 0, 0}, 521 {R_028E30_PA_CL_UCP1_X, 0, 0, 0}, 522 {R_028E34_PA_CL_UCP1_Y, 0, 0, 0}, 523 {R_028E38_PA_CL_UCP1_Z, 0, 0, 0}, 524 {R_028E3C_PA_CL_UCP1_W, 0, 0, 0}, 525 {R_028E40_PA_CL_UCP2_X, 0, 0, 0}, 526 {R_028E44_PA_CL_UCP2_Y, 0, 0, 0}, 527 {R_028E48_PA_CL_UCP2_Z, 0, 0, 0}, 528 {R_028E4C_PA_CL_UCP2_W, 0, 0, 0}, 529 {R_028E50_PA_CL_UCP3_X, 0, 0, 0}, 530 {R_028E54_PA_CL_UCP3_Y, 0, 0, 0}, 531 {R_028E58_PA_CL_UCP3_Z, 0, 0, 0}, 532 {R_028E5C_PA_CL_UCP3_W, 0, 0, 0}, 533 {R_028E60_PA_CL_UCP4_X, 0, 0, 0}, 534 {R_028E64_PA_CL_UCP4_Y, 0, 0, 0}, 535 {R_028E68_PA_CL_UCP4_Z, 0, 0, 0}, 536 {R_028E6C_PA_CL_UCP4_W, 0, 0, 0}, 537 {R_028E70_PA_CL_UCP5_X, 0, 0, 0}, 538 {R_028E74_PA_CL_UCP5_Y, 0, 0, 0}, 539 {R_028E78_PA_CL_UCP5_Z, 0, 0, 0}, 540 {R_028E7C_PA_CL_UCP5_W, 0, 0, 0}, 541 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0, 0}, 542 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0, 0}, 543 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0, 0}, 544 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0, 0}, 545 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0, 0}, 546 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0, 0}, 547 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0, 0}, 548 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0, 0}, 549 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0, 0}, 550 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0, 0}, 551 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0, 0}, 552 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0, 0}, 553 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0, 0}, 554 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0, 0}, 555 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0, 0}, 556 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0, 0}, 557 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0, 0}, 558 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0, 0}, 559 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0, 0}, 560 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0, 0}, 561 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0, 0}, 562 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0, 0}, 563 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0, 0}, 564 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0, 0}, 565 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0, 0}, 566 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0, 0}, 567 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0, 0}, 568 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0, 0}, 569 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0, 0}, 570 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0, 0}, 571 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0, 0}, 572 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0, 0}, 573 {R_028614_SPI_VS_OUT_ID_0, 0, 0, 0}, 574 {R_028618_SPI_VS_OUT_ID_1, 0, 0, 0}, 575 {R_02861C_SPI_VS_OUT_ID_2, 0, 0, 0}, 576 {R_028620_SPI_VS_OUT_ID_3, 0, 0, 0}, 577 {R_028624_SPI_VS_OUT_ID_4, 0, 0, 0}, 578 {R_028628_SPI_VS_OUT_ID_5, 0, 0, 0}, 579 {R_02862C_SPI_VS_OUT_ID_6, 0, 0, 0}, 580 {R_028630_SPI_VS_OUT_ID_7, 0, 0, 0}, 581 {R_028634_SPI_VS_OUT_ID_8, 0, 0, 0}, 582 {R_028638_SPI_VS_OUT_ID_9, 0, 0, 0}, 583 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0, 0}, 584 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 585 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 586 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 587 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0, 0}, 588 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 589 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 590 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 591 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0, 0}, 592 {R_0288D0_SQ_PGM_CF_OFFSET_VS, 0, 0, 0}, 593 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0, 0}, 594 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0, 0}, 595 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0, 0}, 596 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0, 0}, 597 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0, 0}, 598 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0, 0}, 599 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0, 0}, 600 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0, 0}, 601 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0, 0}, 602 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0, 0}, 603 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0, 0}, 604 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0, 0}, 605 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0, 0}, 606 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0, 0}, 607 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0, 0}, 608 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0, 0}, 609 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0, 0}, 610 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0, 0}, 611 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0, 0}, 612 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0, 0}, 613 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0, 0}, 614 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0, 0}, 615 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0, 0}, 616 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0, 0}, 617 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0, 0}, 618 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0, 0}, 619 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0, 0}, 620 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0, 0}, 621 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0, 0}, 622 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0, 0}, 623 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0, 0}, 624 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0, 0}, 625 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0, 0}, 626 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0, 0}, 627 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0, 0}, 628 {R_0286D8_SPI_INPUT_Z, 0, 0, 0}, 629 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 630 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, S_0085F0_SH_ACTION_ENA(1), 0xFFFFFFFF}, 631 {GROUP_FORCE_NEW_BLOCK, 0, 0, 0}, 632 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0, 0}, 633 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0, 0}, 634 {R_0288CC_SQ_PGM_CF_OFFSET_PS, 0, 0, 0}, 635 {R_028400_VGT_MAX_VTX_INDX, 0, 0, 0}, 636 {R_028404_VGT_MIN_VTX_INDX, 0, 0, 0}, 637 {R_028408_VGT_INDX_OFFSET, 0, 0, 0}, 638 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0, 0}, 639 {R_028A84_VGT_PRIMITIVEID_EN, 0, 0, 0}, 640 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0, 0}, 641 {R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0, 0, 0}, 642 {R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0, 0, 0}, 643}; 644 645/* SHADER RESOURCE R600/R700 */ 646int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base) 647{ 648 int i; 649 struct r600_block *block; 650 range->blocks = calloc(nblocks, sizeof(struct r600_block *)); 651 if (range->blocks == NULL) 652 return -ENOMEM; 653 654 reg[0].offset += offset; 655 for (i = 0; i < nblocks; i++) { 656 block = calloc(1, sizeof(struct r600_block)); 657 if (block == NULL) { 658 return -ENOMEM; 659 } 660 ctx->nblocks++; 661 range->blocks[i] = block; 662 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base); 663 664 reg[0].offset += stride; 665 } 666 return 0; 667} 668 669 670static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride) 671{ 672 struct r600_reg r600_shader_resource[] = { 673 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, 674 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_VC_ACTION_ENA(1), 0xFFFFFFFF}, 675 {R_038008_RESOURCE0_WORD2, 0, 0, 0}, 676 {R_03800C_RESOURCE0_WORD3, 0, 0, 0}, 677 {R_038010_RESOURCE0_WORD4, 0, 0, 0}, 678 {R_038014_RESOURCE0_WORD5, 0, 0, 0}, 679 {R_038018_RESOURCE0_WORD6, 0, 0, 0}, 680 }; 681 unsigned nreg = Elements(r600_shader_resource); 682 683 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET); 684} 685 686/* SHADER SAMPLER R600/R700 */ 687static int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset) 688{ 689 struct r600_reg r600_shader_sampler[] = { 690 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0, 0}, 691 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0, 0}, 692 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0, 0}, 693 }; 694 unsigned nreg = Elements(r600_shader_sampler); 695 696 for (int i = 0; i < nreg; i++) { 697 r600_shader_sampler[i].offset += offset; 698 } 699 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET); 700} 701 702/* SHADER SAMPLER BORDER R600/R700 */ 703static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset) 704{ 705 struct r600_reg r600_shader_sampler_border[] = { 706 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0, 0}, 707 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0, 0}, 708 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0, 0}, 709 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0, 0}, 710 }; 711 unsigned nreg = Elements(r600_shader_sampler_border); 712 713 for (int i = 0; i < nreg; i++) { 714 r600_shader_sampler_border[i].offset += offset; 715 } 716 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); 717} 718 719static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset) 720{ 721 unsigned nreg = 32; 722 struct r600_reg r600_loop_consts[32]; 723 int i; 724 725 for (i = 0; i < nreg; i++) { 726 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4); 727 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS; 728 r600_loop_consts[i].flush_flags = 0; 729 r600_loop_consts[i].flush_mask = 0; 730 } 731 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET); 732} 733 734static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks) 735{ 736 struct r600_block *block; 737 int i; 738 for (i = 0; i < nblocks; i++) { 739 block = range->blocks[i]; 740 if (block) { 741 for (int k = 1; k <= block->nbo; k++) 742 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL); 743 free(block); 744 } 745 } 746 free(range->blocks); 747 748} 749 750/* initialize */ 751void r600_context_fini(struct r600_context *ctx) 752{ 753 struct r600_block *block; 754 struct r600_range *range; 755 756 for (int i = 0; i < NUM_RANGES; i++) { 757 if (!ctx->range[i].blocks) 758 continue; 759 for (int j = 0; j < (1 << HASH_SHIFT); j++) { 760 block = ctx->range[i].blocks[j]; 761 if (block) { 762 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) { 763 range = &ctx->range[CTX_RANGE_ID(offset)]; 764 range->blocks[CTX_BLOCK_ID(offset)] = NULL; 765 } 766 for (int k = 1; k <= block->nbo; k++) { 767 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL); 768 } 769 free(block); 770 } 771 } 772 free(ctx->range[i].blocks); 773 } 774 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources); 775 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources); 776 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources); 777 free(ctx->range); 778 free(ctx->blocks); 779 free(ctx->bo); 780 ctx->ws->cs_destroy(ctx->cs); 781} 782 783static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index) 784{ 785 int c = *index; 786 for (int j = 0; j < num_blocks; j++) { 787 if (!range->blocks[j]) 788 continue; 789 790 ctx->blocks[c++] = range->blocks[j]; 791 } 792 *index = c; 793} 794 795int r600_setup_block_table(struct r600_context *ctx) 796{ 797 /* setup block table */ 798 int c = 0; 799 ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); 800 if (!ctx->blocks) 801 return -ENOMEM; 802 for (int i = 0; i < NUM_RANGES; i++) { 803 if (!ctx->range[i].blocks) 804 continue; 805 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) { 806 if (!ctx->range[i].blocks[j]) 807 continue; 808 809 add = 1; 810 for (int k = 0; k < c; k++) { 811 if (ctx->blocks[k] == ctx->range[i].blocks[j]) { 812 add = 0; 813 break; 814 } 815 } 816 if (add) { 817 assert(c < ctx->nblocks); 818 ctx->blocks[c++] = ctx->range[i].blocks[j]; 819 j += (ctx->range[i].blocks[j]->nreg) - 1; 820 } 821 } 822 } 823 824 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c); 825 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c); 826 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c); 827 return 0; 828} 829 830int r600_context_init(struct r600_context *ctx) 831{ 832 int r; 833 834 LIST_INITHEAD(&ctx->active_query_list); 835 836 /* init dirty list */ 837 LIST_INITHEAD(&ctx->dirty); 838 LIST_INITHEAD(&ctx->resource_dirty); 839 LIST_INITHEAD(&ctx->enable_list); 840 841 ctx->range = calloc(NUM_RANGES, sizeof(struct r600_range)); 842 if (!ctx->range) { 843 r = -ENOMEM; 844 goto out_err; 845 } 846 847 /* add blocks */ 848 r = r600_context_add_block(ctx, r600_config_reg_list, 849 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); 850 if (r) 851 goto out_err; 852 r = r600_context_add_block(ctx, r600_context_reg_list, 853 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET); 854 if (r) 855 goto out_err; 856 r = r600_context_add_block(ctx, r600_ctl_const_list, 857 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET); 858 if (r) 859 goto out_err; 860 861 /* PS SAMPLER BORDER */ 862 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) { 863 r = r600_state_sampler_border_init(ctx, offset); 864 if (r) 865 goto out_err; 866 } 867 868 /* VS SAMPLER BORDER */ 869 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) { 870 r = r600_state_sampler_border_init(ctx, offset); 871 if (r) 872 goto out_err; 873 } 874 /* PS SAMPLER */ 875 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) { 876 r = r600_state_sampler_init(ctx, offset); 877 if (r) 878 goto out_err; 879 } 880 /* VS SAMPLER */ 881 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) { 882 r = r600_state_sampler_init(ctx, offset); 883 if (r) 884 goto out_err; 885 } 886 887 ctx->num_ps_resources = 160; 888 ctx->num_vs_resources = 160; 889 ctx->num_fs_resources = 16; 890 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c); 891 if (r) 892 goto out_err; 893 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c); 894 if (r) 895 goto out_err; 896 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c); 897 if (r) 898 goto out_err; 899 900 /* PS loop const */ 901 r600_loop_const_init(ctx, 0); 902 /* VS loop const */ 903 r600_loop_const_init(ctx, 32); 904 905 r = r600_setup_block_table(ctx); 906 if (r) 907 goto out_err; 908 909 ctx->cs = ctx->ws->cs_create(ctx->ws); 910 911 /* allocate cs variables */ 912 ctx->bo = calloc(RADEON_MAX_CMDBUF_DWORDS, sizeof(void *)); 913 if (ctx->bo == NULL) { 914 r = -ENOMEM; 915 goto out_err; 916 } 917 ctx->pm4 = ctx->cs->buf; 918 919 r600_init_cs(ctx); 920 ctx->max_db = 4; 921 return 0; 922out_err: 923 r600_context_fini(ctx); 924 return r; 925} 926 927void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, 928 boolean count_draw_in) 929{ 930 /* The number of dwords we already used in the CS so far. */ 931 num_dw += ctx->pm4_cdwords; 932 933 if (count_draw_in) { 934 /* The number of dwords all the dirty states would take. */ 935 num_dw += ctx->pm4_dirty_cdwords; 936 937 /* The upper-bound of how much a draw command would take. */ 938 num_dw += R600_MAX_DRAW_CS_DWORDS; 939 } 940 941 /* Count in queries_suspend. */ 942 num_dw += ctx->num_cs_dw_queries_suspend; 943 944 /* Count in streamout_end at the end of CS. */ 945 num_dw += ctx->num_cs_dw_streamout_end; 946 947 /* Count in render_condition(NULL) at the end of CS. */ 948 if (ctx->predicate_drawing) { 949 num_dw += 3; 950 } 951 952 /* Count in framebuffer cache flushes at the end of CS. */ 953 num_dw += ctx->num_dest_buffers * 7; 954 955 /* Save 16 dwords for the fence mechanism. */ 956 num_dw += 16; 957 958 /* Flush if there's not enough space. */ 959 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { 960 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC); 961 } 962} 963 964/* Flushes all surfaces */ 965void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags) 966{ 967 r600_need_cs_space(ctx, 5, FALSE); 968 969 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0); 970 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */ 971 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */ 972 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */ 973 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */ 974} 975 976void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags, 977 unsigned flush_mask, struct r600_resource *bo) 978{ 979 uint64_t va = 0; 980 981 /* if bo has already been flushed */ 982 if (!(~bo->cs_buf->last_flush & flush_flags)) { 983 bo->cs_buf->last_flush &= flush_mask; 984 return; 985 } 986 987 if ((ctx->screen->family < CHIP_RV770) && 988 (G_0085F0_CB_ACTION_ENA(flush_flags) || 989 G_0085F0_DB_ACTION_ENA(flush_flags))) { 990 if (ctx->flags & R600_CONTEXT_CHECK_EVENT_FLUSH) { 991 /* the rv670 seems to fail fbo-generatemipmap unless we flush the CB1 dest base ena */ 992 if ((bo->cs_buf->binding & BO_BOUND_TEXTURE) && 993 (flush_flags & S_0085F0_CB_ACTION_ENA(1))) { 994 if ((ctx->screen->family == CHIP_RV670) || 995 (ctx->screen->family == CHIP_RS780) || 996 (ctx->screen->family == CHIP_RS880)) { 997 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0); 998 ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_CB1_DEST_BASE_ENA(1); /* CP_COHER_CNTL */ 999 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */ 1000 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */ 1001 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */ 1002 } 1003 } 1004 1005 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 1006 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0); 1007 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; 1008 } 1009 } else { 1010 va = r600_resource_va(&ctx->screen->screen, (void *)bo); 1011 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0); 1012 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; 1013 ctx->pm4[ctx->pm4_cdwords++] = (bo->buf->size + 255) >> 8; 1014 ctx->pm4[ctx->pm4_cdwords++] = va >> 8; 1015 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; 1016 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 1017 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, bo, RADEON_USAGE_WRITE); 1018 } 1019 bo->cs_buf->last_flush = (bo->cs_buf->last_flush | flush_flags) & flush_mask; 1020} 1021 1022void r600_context_dirty_block(struct r600_context *ctx, 1023 struct r600_block *block, 1024 int dirty, int index) 1025{ 1026 if ((index + 1) > block->nreg_dirty) 1027 block->nreg_dirty = index + 1; 1028 1029 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) { 1030 block->status |= R600_BLOCK_STATUS_DIRTY; 1031 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; 1032 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 1033 block->status |= R600_BLOCK_STATUS_ENABLED; 1034 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 1035 } 1036 LIST_ADDTAIL(&block->list,&ctx->dirty); 1037 1038 if (block->flags & REG_FLAG_FLUSH_CHANGE) { 1039 r600_context_ps_partial_flush(ctx); 1040 } 1041 } 1042} 1043 1044void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state) 1045{ 1046 struct r600_block *block; 1047 int dirty; 1048 for (int i = 0; i < state->nregs; i++) { 1049 unsigned id, reloc_id; 1050 struct r600_pipe_reg *reg = &state->regs[i]; 1051 1052 block = reg->block; 1053 id = reg->id; 1054 1055 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 1056 1057 if (reg->value != block->reg[id]) { 1058 block->reg[id] = reg->value; 1059 dirty |= R600_BLOCK_STATUS_DIRTY; 1060 } 1061 if (block->flags & REG_FLAG_DIRTY_ALWAYS) 1062 dirty |= R600_BLOCK_STATUS_DIRTY; 1063 if (block->pm4_bo_index[id]) { 1064 /* find relocation */ 1065 reloc_id = block->pm4_bo_index[id]; 1066 pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, ®->bo->b.b.b); 1067 block->reloc[reloc_id].bo_usage = reg->bo_usage; 1068 /* always force dirty for relocs for now */ 1069 dirty |= R600_BLOCK_STATUS_DIRTY; 1070 } 1071 1072 if (dirty) 1073 r600_context_dirty_block(ctx, block, dirty, id); 1074 } 1075} 1076 1077static void r600_context_dirty_resource_block(struct r600_context *ctx, 1078 struct r600_block *block, 1079 int dirty, int index) 1080{ 1081 block->nreg_dirty = index + 1; 1082 1083 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) { 1084 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1085 ctx->pm4_dirty_cdwords += block->pm4_ndwords + block->pm4_flush_ndwords; 1086 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 1087 block->status |= R600_BLOCK_STATUS_ENABLED; 1088 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 1089 } 1090 LIST_ADDTAIL(&block->list,&ctx->resource_dirty); 1091 } 1092} 1093 1094void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block) 1095{ 1096 int dirty; 1097 int num_regs = ctx->screen->chip_class >= EVERGREEN ? 8 : 7; 1098 boolean is_vertex; 1099 1100 if (state == NULL) { 1101 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY); 1102 if (block->reloc[1].bo) 1103 block->reloc[1].bo->cs_buf->binding &= ~BO_BOUND_TEXTURE; 1104 1105 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, NULL); 1106 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL); 1107 LIST_DELINIT(&block->list); 1108 LIST_DELINIT(&block->enable_list); 1109 return; 1110 } 1111 1112 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000); 1113 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY; 1114 1115 if (memcmp(block->reg, state->val, num_regs*4)) { 1116 memcpy(block->reg, state->val, num_regs * 4); 1117 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1118 } 1119 1120 /* if no BOs on block, force dirty */ 1121 if (!block->reloc[1].bo || !block->reloc[2].bo) 1122 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1123 1124 if (!dirty) { 1125 if (is_vertex) { 1126 if (block->reloc[1].bo->buf != state->bo[0]->buf) 1127 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1128 } else { 1129 if ((block->reloc[1].bo->buf != state->bo[0]->buf) || 1130 (block->reloc[2].bo->buf != state->bo[1]->buf)) 1131 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1132 } 1133 } 1134 1135 if (dirty) { 1136 if (is_vertex) { 1137 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so 1138 * we have single case btw VERTEX & TEXTURE resource 1139 */ 1140 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b); 1141 block->reloc[1].bo_usage = state->bo_usage[0]; 1142 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL); 1143 } else { 1144 /* TEXTURE RESOURCE */ 1145 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b); 1146 block->reloc[1].bo_usage = state->bo_usage[0]; 1147 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b.b); 1148 block->reloc[2].bo_usage = state->bo_usage[1]; 1149 state->bo[0]->cs_buf->binding |= BO_BOUND_TEXTURE; 1150 } 1151 1152 if (is_vertex) 1153 block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX; 1154 else 1155 block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX; 1156 1157 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1); 1158 } 1159} 1160 1161void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 1162{ 1163 struct r600_block *block = ctx->ps_resources.blocks[rid]; 1164 1165 r600_context_pipe_state_set_resource(ctx, state, block); 1166} 1167 1168void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 1169{ 1170 struct r600_block *block = ctx->vs_resources.blocks[rid]; 1171 1172 r600_context_pipe_state_set_resource(ctx, state, block); 1173} 1174 1175void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 1176{ 1177 struct r600_block *block = ctx->fs_resources.blocks[rid]; 1178 1179 r600_context_pipe_state_set_resource(ctx, state, block); 1180} 1181 1182static inline void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) 1183{ 1184 struct r600_range *range; 1185 struct r600_block *block; 1186 int i; 1187 int dirty; 1188 1189 range = &ctx->range[CTX_RANGE_ID(offset)]; 1190 block = range->blocks[CTX_BLOCK_ID(offset)]; 1191 if (state == NULL) { 1192 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); 1193 LIST_DELINIT(&block->list); 1194 LIST_DELINIT(&block->enable_list); 1195 return; 1196 } 1197 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 1198 for (i = 0; i < 3; i++) { 1199 if (block->reg[i] != state->regs[i].value) { 1200 block->reg[i] = state->regs[i].value; 1201 dirty |= R600_BLOCK_STATUS_DIRTY; 1202 } 1203 } 1204 1205 if (dirty) 1206 r600_context_dirty_block(ctx, block, dirty, 2); 1207} 1208 1209 1210static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) 1211{ 1212 struct r600_range *range; 1213 struct r600_block *block; 1214 int i; 1215 int dirty; 1216 1217 range = &ctx->range[CTX_RANGE_ID(offset)]; 1218 block = range->blocks[CTX_BLOCK_ID(offset)]; 1219 if (state == NULL) { 1220 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); 1221 LIST_DELINIT(&block->list); 1222 LIST_DELINIT(&block->enable_list); 1223 return; 1224 } 1225 if (state->nregs <= 3) { 1226 return; 1227 } 1228 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 1229 for (i = 0; i < 4; i++) { 1230 if (block->reg[i] != state->regs[i + 3].value) { 1231 block->reg[i] = state->regs[i + 3].value; 1232 dirty |= R600_BLOCK_STATUS_DIRTY; 1233 } 1234 } 1235 1236 /* We have to flush the shaders before we change the border color 1237 * registers, or previous draw commands that haven't completed yet 1238 * will end up using the new border color. */ 1239 if (dirty & R600_BLOCK_STATUS_DIRTY) 1240 r600_context_ps_partial_flush(ctx); 1241 if (dirty) 1242 r600_context_dirty_block(ctx, block, dirty, 3); 1243} 1244 1245void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) 1246{ 1247 unsigned offset; 1248 1249 offset = 0x0003C000 + id * 0xc; 1250 r600_context_pipe_state_set_sampler(ctx, state, offset); 1251 offset = 0x0000A400 + id * 0x10; 1252 r600_context_pipe_state_set_sampler_border(ctx, state, offset); 1253} 1254 1255void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) 1256{ 1257 unsigned offset; 1258 1259 offset = 0x0003C0D8 + id * 0xc; 1260 r600_context_pipe_state_set_sampler(ctx, state, offset); 1261 offset = 0x0000A600 + id * 0x10; 1262 r600_context_pipe_state_set_sampler_border(ctx, state, offset); 1263} 1264 1265struct r600_resource *r600_context_reg_bo(struct r600_context *ctx, unsigned offset) 1266{ 1267 struct r600_range *range; 1268 struct r600_block *block; 1269 unsigned id; 1270 1271 range = &ctx->range[CTX_RANGE_ID(offset)]; 1272 block = range->blocks[CTX_BLOCK_ID(offset)]; 1273 offset -= block->start_offset; 1274 id = block->pm4_bo_index[offset >> 2]; 1275 if (block->reloc[id].bo) { 1276 return block->reloc[id].bo; 1277 } 1278 return NULL; 1279} 1280 1281void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block) 1282{ 1283 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS); 1284 int cp_dwords = block->pm4_ndwords, start_dword = 0; 1285 int new_dwords = 0; 1286 int nbo = block->nbo; 1287 1288 if (block->nreg_dirty == 0 && optional) { 1289 goto out; 1290 } 1291 1292 if (nbo) { 1293 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH; 1294 1295 for (int j = 0; j < block->nreg; j++) { 1296 if (block->pm4_bo_index[j]) { 1297 /* find relocation */ 1298 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]]; 1299 if (reloc->bo) { 1300 block->pm4[reloc->bo_pm4_index] = 1301 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage); 1302 r600_context_bo_flush(ctx, 1303 reloc->flush_flags, 1304 reloc->flush_mask, 1305 reloc->bo); 1306 } else { 1307 block->pm4[reloc->bo_pm4_index] = 0; 1308 } 1309 nbo--; 1310 if (nbo == 0) 1311 break; 1312 1313 } 1314 } 1315 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; 1316 } 1317 1318 optional &= (block->nreg_dirty != block->nreg); 1319 if (optional) { 1320 new_dwords = block->nreg_dirty; 1321 start_dword = ctx->pm4_cdwords; 1322 cp_dwords = new_dwords + 2; 1323 } 1324 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4); 1325 ctx->pm4_cdwords += cp_dwords; 1326 1327 if (optional) { 1328 uint32_t newword; 1329 1330 newword = ctx->pm4[start_dword]; 1331 newword &= PKT_COUNT_C; 1332 newword |= PKT_COUNT_S(new_dwords); 1333 ctx->pm4[start_dword] = newword; 1334 } 1335out: 1336 block->status ^= R600_BLOCK_STATUS_DIRTY; 1337 block->nreg_dirty = 0; 1338 LIST_DELINIT(&block->list); 1339} 1340 1341void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block) 1342{ 1343 int cp_dwords = block->pm4_ndwords; 1344 int nbo = block->nbo; 1345 1346 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH; 1347 1348 if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) { 1349 nbo = 1; 1350 cp_dwords -= 2; /* don't copy the second NOP */ 1351 } 1352 1353 for (int j = 0; j < nbo; j++) { 1354 if (block->pm4_bo_index[j]) { 1355 /* find relocation */ 1356 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]]; 1357 block->pm4[reloc->bo_pm4_index] = 1358 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage); 1359 r600_context_bo_flush(ctx, 1360 reloc->flush_flags, 1361 reloc->flush_mask, 1362 reloc->bo); 1363 } 1364 } 1365 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; 1366 1367 memcpy(&ctx->pm4[ctx->pm4_cdwords], block->pm4, cp_dwords * 4); 1368 ctx->pm4_cdwords += cp_dwords; 1369 1370 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1371 block->nreg_dirty = 0; 1372 LIST_DELINIT(&block->list); 1373} 1374 1375void r600_context_flush_dest_caches(struct r600_context *ctx) 1376{ 1377 struct r600_resource *cb[8]; 1378 struct r600_resource *db; 1379 int i; 1380 1381 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY)) 1382 return; 1383 1384 db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE); 1385 cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE); 1386 cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE); 1387 cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE); 1388 cb[3] = r600_context_reg_bo(ctx, R_02804C_CB_COLOR3_BASE); 1389 cb[4] = r600_context_reg_bo(ctx, R_028050_CB_COLOR4_BASE); 1390 cb[5] = r600_context_reg_bo(ctx, R_028054_CB_COLOR5_BASE); 1391 cb[6] = r600_context_reg_bo(ctx, R_028058_CB_COLOR6_BASE); 1392 cb[7] = r600_context_reg_bo(ctx, R_02805C_CB_COLOR7_BASE); 1393 1394 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH; 1395 /* flush the color buffers */ 1396 for (i = 0; i < 8; i++) { 1397 if (!cb[i]) 1398 continue; 1399 1400 r600_context_bo_flush(ctx, 1401 (S_0085F0_CB0_DEST_BASE_ENA(1) << i) | 1402 S_0085F0_CB_ACTION_ENA(1), 1403 0, cb[i]); 1404 } 1405 if (db) { 1406 r600_context_bo_flush(ctx, S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1), 0, db); 1407 } 1408 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; 1409 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY; 1410} 1411 1412void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw) 1413{ 1414 unsigned ndwords = 7; 1415 struct r600_block *dirty_block = NULL; 1416 struct r600_block *next_block; 1417 uint32_t *pm4; 1418 1419 if (draw->indices) { 1420 ndwords = 11; 1421 } 1422 if (ctx->num_cs_dw_queries_suspend) { 1423 if (ctx->screen->family >= CHIP_RV770) 1424 ndwords += 3; 1425 ndwords += 3; 1426 } 1427 1428 /* when increasing ndwords, bump the max limit too */ 1429 assert(ndwords <= R600_MAX_DRAW_CS_DWORDS); 1430 1431 r600_need_cs_space(ctx, 0, TRUE); 1432 assert(ctx->pm4_cdwords + ctx->pm4_dirty_cdwords + ndwords < RADEON_MAX_CMDBUF_DWORDS); 1433 1434 /* enough room to copy packet */ 1435 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->dirty, list) { 1436 r600_context_block_emit_dirty(ctx, dirty_block); 1437 } 1438 1439 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &ctx->resource_dirty, list) { 1440 r600_context_block_resource_emit_dirty(ctx, dirty_block); 1441 } 1442 1443 /* Enable stream out if needed. */ 1444 if (ctx->streamout_start) { 1445 r600_context_streamout_begin(ctx); 1446 ctx->streamout_start = FALSE; 1447 } 1448 1449 /* queries need some special values 1450 * (this is non-zero if any query is active) */ 1451 if (ctx->num_cs_dw_queries_suspend) { 1452 if (ctx->screen->family >= CHIP_RV770) { 1453 pm4 = &ctx->pm4[ctx->pm4_cdwords]; 1454 pm4[0] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1455 pm4[1] = (R_028D0C_DB_RENDER_CONTROL - R600_CONTEXT_REG_OFFSET) >> 2; 1456 pm4[2] = draw->db_render_control | S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); 1457 ctx->pm4_cdwords += 3; 1458 ndwords -= 3; 1459 } 1460 pm4 = &ctx->pm4[ctx->pm4_cdwords]; 1461 pm4[0] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1462 pm4[1] = (R_028D10_DB_RENDER_OVERRIDE - R600_CONTEXT_REG_OFFSET) >> 2; 1463 pm4[2] = draw->db_render_override | S_028D10_NOOP_CULL_DISABLE(1); 1464 ctx->pm4_cdwords += 3; 1465 ndwords -= 3; 1466 } 1467 1468 /* draw packet */ 1469 pm4 = &ctx->pm4[ctx->pm4_cdwords]; 1470 1471 pm4[0] = PKT3(PKT3_INDEX_TYPE, 0, ctx->predicate_drawing); 1472 pm4[1] = draw->vgt_index_type; 1473 pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx->predicate_drawing); 1474 pm4[3] = draw->vgt_num_instances; 1475 if (draw->indices) { 1476 pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx->predicate_drawing); 1477 pm4[5] = draw->indices_bo_offset; 1478 pm4[6] = 0; 1479 pm4[7] = draw->vgt_num_indices; 1480 pm4[8] = draw->vgt_draw_initiator; 1481 pm4[9] = PKT3(PKT3_NOP, 0, ctx->predicate_drawing); 1482 pm4[10] = r600_context_bo_reloc(ctx, draw->indices, RADEON_USAGE_READ); 1483 } else { 1484 pm4[4] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, ctx->predicate_drawing); 1485 pm4[5] = draw->vgt_num_indices; 1486 pm4[6] = draw->vgt_draw_initiator; 1487 } 1488 ctx->pm4_cdwords += ndwords; 1489 1490 ctx->flags |= (R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING); 1491 1492 /* all dirty state have been scheduled in current cs */ 1493 ctx->pm4_dirty_cdwords = 0; 1494} 1495 1496void r600_context_flush(struct r600_context *ctx, unsigned flags) 1497{ 1498 struct r600_block *enable_block = NULL; 1499 bool queries_suspended = false; 1500 bool streamout_suspended = false; 1501 1502 if (ctx->pm4_cdwords == ctx->init_dwords) 1503 return; 1504 1505 /* suspend queries */ 1506 if (ctx->num_cs_dw_queries_suspend) { 1507 r600_context_queries_suspend(ctx); 1508 queries_suspended = true; 1509 } 1510 1511 if (ctx->num_cs_dw_streamout_end) { 1512 r600_context_streamout_end(ctx); 1513 streamout_suspended = true; 1514 } 1515 1516 if (ctx->screen->chip_class >= EVERGREEN) 1517 evergreen_context_flush_dest_caches(ctx); 1518 else 1519 r600_context_flush_dest_caches(ctx); 1520 1521 /* partial flush is needed to avoid lockups on some chips with user fences */ 1522 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 1523 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); 1524 1525 /* Flush the CS. */ 1526 ctx->cs->cdw = ctx->pm4_cdwords; 1527 ctx->ws->cs_flush(ctx->cs, flags); 1528 1529 /* We need to get the pointer to the other CS, 1530 * the command streams are double-buffered. */ 1531 ctx->pm4 = ctx->cs->buf; 1532 1533 /* restart */ 1534 for (int i = 0; i < ctx->creloc; i++) { 1535 ctx->bo[i]->cs_buf->last_flush = 0; 1536 pipe_resource_reference((struct pipe_resource**)&ctx->bo[i], NULL); 1537 } 1538 ctx->creloc = 0; 1539 ctx->pm4_dirty_cdwords = 0; 1540 ctx->pm4_cdwords = 0; 1541 ctx->flags = 0; 1542 1543 r600_init_cs(ctx); 1544 1545 if (streamout_suspended) { 1546 ctx->streamout_start = TRUE; 1547 ctx->streamout_append_bitmask = ~0; 1548 } 1549 1550 /* resume queries */ 1551 if (queries_suspended) { 1552 r600_context_queries_resume(ctx); 1553 } 1554 1555 /* set all valid group as dirty so they get reemited on 1556 * next draw command 1557 */ 1558 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) { 1559 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) { 1560 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) { 1561 LIST_ADDTAIL(&enable_block->list,&ctx->dirty); 1562 enable_block->status |= R600_BLOCK_STATUS_DIRTY; 1563 } 1564 } else { 1565 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) { 1566 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty); 1567 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1568 } 1569 } 1570 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords + 1571 enable_block->pm4_flush_ndwords; 1572 enable_block->nreg_dirty = enable_block->nreg; 1573 } 1574} 1575 1576void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value) 1577{ 1578 uint64_t va; 1579 1580 r600_need_cs_space(ctx, 10, FALSE); 1581 1582 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo); 1583 va = va + (offset << 2); 1584 1585 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 1586 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); 1587 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); 1588 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); 1589 ctx->pm4[ctx->pm4_cdwords++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */ 1590 /* DATA_SEL | INT_EN | ADDRESS_HI */ 1591 ctx->pm4[ctx->pm4_cdwords++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF); 1592 ctx->pm4[ctx->pm4_cdwords++] = value; /* DATA_LO */ 1593 ctx->pm4[ctx->pm4_cdwords++] = 0; /* DATA_HI */ 1594 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 1595 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE); 1596} 1597 1598static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index, 1599 bool test_status_bit) 1600{ 1601 uint32_t *current_result = (uint32_t*)map; 1602 uint64_t start, end; 1603 1604 start = (uint64_t)current_result[start_index] | 1605 (uint64_t)current_result[start_index+1] << 32; 1606 end = (uint64_t)current_result[end_index] | 1607 (uint64_t)current_result[end_index+1] << 32; 1608 1609 if (!test_status_bit || 1610 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) { 1611 return end - start; 1612 } 1613 return 0; 1614} 1615 1616static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait) 1617{ 1618 unsigned results_base = query->results_start; 1619 char *map; 1620 1621 map = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, 1622 PIPE_TRANSFER_READ | 1623 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK)); 1624 if (!map) 1625 return FALSE; 1626 1627 /* count all results across all data blocks */ 1628 switch (query->type) { 1629 case PIPE_QUERY_OCCLUSION_COUNTER: 1630 while (results_base != query->results_end) { 1631 query->result.u64 += 1632 r600_query_read_result(map + results_base, 0, 2, true); 1633 results_base = (results_base + 16) % query->buffer->b.b.b.width0; 1634 } 1635 break; 1636 case PIPE_QUERY_OCCLUSION_PREDICATE: 1637 while (results_base != query->results_end) { 1638 query->result.b = query->result.b || 1639 r600_query_read_result(map + results_base, 0, 2, true) != 0; 1640 results_base = (results_base + 16) % query->buffer->b.b.b.width0; 1641 } 1642 break; 1643 case PIPE_QUERY_TIME_ELAPSED: 1644 while (results_base != query->results_end) { 1645 query->result.u64 += 1646 r600_query_read_result(map + results_base, 0, 2, false); 1647 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1648 } 1649 break; 1650 case PIPE_QUERY_PRIMITIVES_EMITTED: 1651 /* SAMPLE_STREAMOUTSTATS stores this structure: 1652 * { 1653 * u64 NumPrimitivesWritten; 1654 * u64 PrimitiveStorageNeeded; 1655 * } 1656 * We only need NumPrimitivesWritten here. */ 1657 while (results_base != query->results_end) { 1658 query->result.u64 += 1659 r600_query_read_result(map + results_base, 2, 6, true); 1660 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1661 } 1662 break; 1663 case PIPE_QUERY_PRIMITIVES_GENERATED: 1664 /* Here we read PrimitiveStorageNeeded. */ 1665 while (results_base != query->results_end) { 1666 query->result.u64 += 1667 r600_query_read_result(map + results_base, 0, 4, true); 1668 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1669 } 1670 break; 1671 case PIPE_QUERY_SO_STATISTICS: 1672 while (results_base != query->results_end) { 1673 query->result.so.num_primitives_written += 1674 r600_query_read_result(map + results_base, 2, 6, true); 1675 query->result.so.primitives_storage_needed += 1676 r600_query_read_result(map + results_base, 0, 4, true); 1677 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1678 } 1679 break; 1680 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1681 while (results_base != query->results_end) { 1682 query->result.b = query->result.b || 1683 r600_query_read_result(map + results_base, 2, 6, true) != 1684 r600_query_read_result(map + results_base, 0, 4, true); 1685 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1686 } 1687 break; 1688 default: 1689 assert(0); 1690 } 1691 1692 query->results_start = query->results_end; 1693 ctx->ws->buffer_unmap(query->buffer->buf); 1694 return TRUE; 1695} 1696 1697void r600_query_begin(struct r600_context *ctx, struct r600_query *query) 1698{ 1699 unsigned new_results_end, i; 1700 uint32_t *results; 1701 uint64_t va; 1702 1703 r600_need_cs_space(ctx, query->num_cs_dw * 2, TRUE); 1704 1705 new_results_end = (query->results_end + query->result_size) % query->buffer->b.b.b.width0; 1706 1707 /* collect current results if query buffer is full */ 1708 if (new_results_end == query->results_start) { 1709 r600_query_result(ctx, query, TRUE); 1710 } 1711 1712 switch (query->type) { 1713 case PIPE_QUERY_OCCLUSION_COUNTER: 1714 case PIPE_QUERY_OCCLUSION_PREDICATE: 1715 results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); 1716 if (results) { 1717 results = (uint32_t*)((char*)results + query->results_end); 1718 memset(results, 0, query->result_size); 1719 1720 /* Set top bits for unused backends */ 1721 for (i = 0; i < ctx->max_db; i++) { 1722 if (!(ctx->backend_mask & (1<<i))) { 1723 results[(i * 4)+1] = 0x80000000; 1724 results[(i * 4)+3] = 0x80000000; 1725 } 1726 } 1727 ctx->ws->buffer_unmap(query->buffer->buf); 1728 } 1729 break; 1730 case PIPE_QUERY_TIME_ELAPSED: 1731 break; 1732 case PIPE_QUERY_PRIMITIVES_EMITTED: 1733 case PIPE_QUERY_PRIMITIVES_GENERATED: 1734 case PIPE_QUERY_SO_STATISTICS: 1735 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1736 results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); 1737 results = (uint32_t*)((char*)results + query->results_end); 1738 memset(results, 0, query->result_size); 1739 ctx->ws->buffer_unmap(query->buffer->buf); 1740 break; 1741 default: 1742 assert(0); 1743 } 1744 1745 /* emit begin query */ 1746 va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); 1747 va += query->results_end; 1748 1749 switch (query->type) { 1750 case PIPE_QUERY_OCCLUSION_COUNTER: 1751 case PIPE_QUERY_OCCLUSION_PREDICATE: 1752 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 1753 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); 1754 ctx->pm4[ctx->pm4_cdwords++] = va; 1755 ctx->pm4[ctx->pm4_cdwords++] = (va >> 32UL) & 0xFF; 1756 break; 1757 case PIPE_QUERY_PRIMITIVES_EMITTED: 1758 case PIPE_QUERY_PRIMITIVES_GENERATED: 1759 case PIPE_QUERY_SO_STATISTICS: 1760 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1761 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 1762 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); 1763 ctx->pm4[ctx->pm4_cdwords++] = query->results_end; 1764 ctx->pm4[ctx->pm4_cdwords++] = 0; 1765 break; 1766 case PIPE_QUERY_TIME_ELAPSED: 1767 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); 1768 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); 1769 ctx->pm4[ctx->pm4_cdwords++] = va; 1770 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29) | ((va >> 32UL) & 0xFF); 1771 ctx->pm4[ctx->pm4_cdwords++] = 0; 1772 ctx->pm4[ctx->pm4_cdwords++] = 0; 1773 break; 1774 default: 1775 assert(0); 1776 } 1777 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 1778 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); 1779 1780 ctx->num_cs_dw_queries_suspend += query->num_cs_dw; 1781} 1782 1783void r600_query_end(struct r600_context *ctx, struct r600_query *query) 1784{ 1785 uint64_t va; 1786 1787 va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); 1788 /* emit end query */ 1789 switch (query->type) { 1790 case PIPE_QUERY_OCCLUSION_COUNTER: 1791 case PIPE_QUERY_OCCLUSION_PREDICATE: 1792 va += query->results_end + 8; 1793 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 1794 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); 1795 ctx->pm4[ctx->pm4_cdwords++] = va; 1796 ctx->pm4[ctx->pm4_cdwords++] = (va >> 32UL) & 0xFF; 1797 break; 1798 case PIPE_QUERY_PRIMITIVES_EMITTED: 1799 case PIPE_QUERY_PRIMITIVES_GENERATED: 1800 case PIPE_QUERY_SO_STATISTICS: 1801 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1802 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 1803 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); 1804 ctx->pm4[ctx->pm4_cdwords++] = query->results_end + query->result_size/2; 1805 ctx->pm4[ctx->pm4_cdwords++] = 0; 1806 break; 1807 case PIPE_QUERY_TIME_ELAPSED: 1808 va += query->results_end + query->result_size/2; 1809 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); 1810 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); 1811 ctx->pm4[ctx->pm4_cdwords++] = va; 1812 ctx->pm4[ctx->pm4_cdwords++] = (3 << 29) | ((va >> 32UL) & 0xFF); 1813 ctx->pm4[ctx->pm4_cdwords++] = 0; 1814 ctx->pm4[ctx->pm4_cdwords++] = 0; 1815 break; 1816 default: 1817 assert(0); 1818 } 1819 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 1820 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); 1821 1822 query->results_end = (query->results_end + query->result_size) % query->buffer->b.b.b.width0; 1823 ctx->num_cs_dw_queries_suspend -= query->num_cs_dw; 1824} 1825 1826void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, 1827 int flag_wait) 1828{ 1829 uint64_t va; 1830 1831 if (operation == PREDICATION_OP_CLEAR) { 1832 r600_need_cs_space(ctx, 3, FALSE); 1833 1834 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0); 1835 ctx->pm4[ctx->pm4_cdwords++] = 0; 1836 ctx->pm4[ctx->pm4_cdwords++] = PRED_OP(PREDICATION_OP_CLEAR); 1837 } else { 1838 unsigned results_base = query->results_start; 1839 unsigned count; 1840 uint32_t op; 1841 1842 /* find count of the query data blocks */ 1843 count = (query->buffer->b.b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.b.width0; 1844 count /= query->result_size; 1845 1846 r600_need_cs_space(ctx, 5 * count, TRUE); 1847 1848 op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE | 1849 (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW); 1850 va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); 1851 1852 /* emit predicate packets for all data blocks */ 1853 while (results_base != query->results_end) { 1854 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_PREDICATION, 1, 0); 1855 ctx->pm4[ctx->pm4_cdwords++] = (va + results_base) & 0xFFFFFFFFUL; 1856 ctx->pm4[ctx->pm4_cdwords++] = op | (((va + results_base) >> 32UL) & 0xFF); 1857 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 1858 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, query->buffer, 1859 RADEON_USAGE_READ); 1860 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1861 1862 /* set CONTINUE bit for all packets except the first */ 1863 op |= PREDICATION_CONTINUE; 1864 } 1865 } 1866} 1867 1868struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type) 1869{ 1870 struct r600_query *query; 1871 unsigned buffer_size = 4096; 1872 1873 query = CALLOC_STRUCT(r600_query); 1874 if (query == NULL) 1875 return NULL; 1876 1877 query->type = query_type; 1878 1879 switch (query_type) { 1880 case PIPE_QUERY_OCCLUSION_COUNTER: 1881 case PIPE_QUERY_OCCLUSION_PREDICATE: 1882 query->result_size = 16 * ctx->max_db; 1883 query->num_cs_dw = 6; 1884 break; 1885 case PIPE_QUERY_TIME_ELAPSED: 1886 query->result_size = 16; 1887 query->num_cs_dw = 8; 1888 break; 1889 case PIPE_QUERY_PRIMITIVES_EMITTED: 1890 case PIPE_QUERY_PRIMITIVES_GENERATED: 1891 case PIPE_QUERY_SO_STATISTICS: 1892 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1893 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */ 1894 query->result_size = 32; 1895 query->num_cs_dw = 6; 1896 break; 1897 default: 1898 assert(0); 1899 FREE(query); 1900 return NULL; 1901 } 1902 1903 /* adjust buffer size to simplify offsets wrapping math */ 1904 buffer_size -= buffer_size % query->result_size; 1905 1906 /* Queries are normally read by the CPU after 1907 * being written by the gpu, hence staging is probably a good 1908 * usage pattern. 1909 */ 1910 query->buffer = (struct r600_resource*) 1911 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING, buffer_size); 1912 if (!query->buffer) { 1913 FREE(query); 1914 return NULL; 1915 } 1916 return query; 1917} 1918 1919void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query) 1920{ 1921 pipe_resource_reference((struct pipe_resource**)&query->buffer, NULL); 1922 free(query); 1923} 1924 1925boolean r600_context_query_result(struct r600_context *ctx, 1926 struct r600_query *query, 1927 boolean wait, void *vresult) 1928{ 1929 boolean *result_b = (boolean*)vresult; 1930 uint64_t *result_u64 = (uint64_t*)vresult; 1931 struct pipe_query_data_so_statistics *result_so = 1932 (struct pipe_query_data_so_statistics*)vresult; 1933 1934 if (!r600_query_result(ctx, query, wait)) 1935 return FALSE; 1936 1937 switch (query->type) { 1938 case PIPE_QUERY_OCCLUSION_COUNTER: 1939 case PIPE_QUERY_PRIMITIVES_EMITTED: 1940 case PIPE_QUERY_PRIMITIVES_GENERATED: 1941 *result_u64 = query->result.u64; 1942 break; 1943 case PIPE_QUERY_OCCLUSION_PREDICATE: 1944 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1945 *result_b = query->result.b; 1946 break; 1947 case PIPE_QUERY_TIME_ELAPSED: 1948 *result_u64 = (1000000 * query->result.u64) / ctx->screen->info.r600_clock_crystal_freq; 1949 break; 1950 case PIPE_QUERY_SO_STATISTICS: 1951 *result_so = query->result.so; 1952 break; 1953 default: 1954 assert(0); 1955 } 1956 return TRUE; 1957} 1958 1959void r600_context_queries_suspend(struct r600_context *ctx) 1960{ 1961 struct r600_query *query; 1962 1963 LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { 1964 r600_query_end(ctx, query); 1965 } 1966 assert(ctx->num_cs_dw_queries_suspend == 0); 1967} 1968 1969void r600_context_queries_resume(struct r600_context *ctx) 1970{ 1971 struct r600_query *query; 1972 1973 assert(ctx->num_cs_dw_queries_suspend == 0); 1974 1975 LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { 1976 r600_query_begin(ctx, query); 1977 } 1978} 1979 1980static void r600_flush_vgt_streamout(struct r600_context *ctx) 1981{ 1982 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0); 1983 ctx->pm4[ctx->pm4_cdwords++] = (R_008490_CP_STRMOUT_CNTL - R600_CONFIG_REG_OFFSET) >> 2; 1984 ctx->pm4[ctx->pm4_cdwords++] = 0; 1985 1986 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 1987 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0); 1988 1989 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0); 1990 ctx->pm4[ctx->pm4_cdwords++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */ 1991 ctx->pm4[ctx->pm4_cdwords++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */ 1992 ctx->pm4[ctx->pm4_cdwords++] = 0; 1993 ctx->pm4[ctx->pm4_cdwords++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */ 1994 ctx->pm4[ctx->pm4_cdwords++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */ 1995 ctx->pm4[ctx->pm4_cdwords++] = 4; /* poll interval */ 1996} 1997 1998static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit) 1999{ 2000 if (buffer_enable_bit) { 2001 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 2002 ctx->pm4[ctx->pm4_cdwords++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2; 2003 ctx->pm4[ctx->pm4_cdwords++] = S_028AB0_STREAMOUT(1); 2004 2005 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 2006 ctx->pm4[ctx->pm4_cdwords++] = (R_028B20_VGT_STRMOUT_BUFFER_EN - R600_CONTEXT_REG_OFFSET) >> 2; 2007 ctx->pm4[ctx->pm4_cdwords++] = buffer_enable_bit; 2008 } else { 2009 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 2010 ctx->pm4[ctx->pm4_cdwords++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2; 2011 ctx->pm4[ctx->pm4_cdwords++] = S_028AB0_STREAMOUT(0); 2012 } 2013} 2014 2015void r600_context_streamout_begin(struct r600_context *ctx) 2016{ 2017 struct r600_so_target **t = ctx->so_targets; 2018 unsigned *stride_in_dw = ctx->vs_so_stride_in_dw; 2019 unsigned buffer_en, i, update_flags = 0; 2020 uint64_t va; 2021 2022 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) | 2023 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) | 2024 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) | 2025 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0); 2026 2027 ctx->num_cs_dw_streamout_end = 2028 12 + /* flush_vgt_streamout */ 2029 util_bitcount(buffer_en) * 8 + 2030 8; 2031 2032 r600_need_cs_space(ctx, 2033 12 + /* flush_vgt_streamout */ 2034 6 + /* enables */ 2035 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + 2036 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + 2037 (ctx->screen->family > CHIP_R600 && ctx->screen->family < CHIP_RV770 ? 2 : 0) + 2038 ctx->num_cs_dw_streamout_end, TRUE); 2039 2040 if (ctx->screen->chip_class >= EVERGREEN) { 2041 evergreen_flush_vgt_streamout(ctx); 2042 evergreen_set_streamout_enable(ctx, buffer_en); 2043 } else { 2044 r600_flush_vgt_streamout(ctx); 2045 r600_set_streamout_enable(ctx, buffer_en); 2046 } 2047 2048 for (i = 0; i < ctx->num_so_targets; i++) { 2049 if (t[i]) { 2050 t[i]->stride_in_dw = stride_in_dw[i]; 2051 t[i]->so_index = i; 2052 va = r600_resource_va(&ctx->screen->screen, 2053 (void*)t[i]->b.buffer); 2054 2055 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i); 2056 2057 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0); 2058 ctx->pm4[ctx->pm4_cdwords++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 2059 16*i - R600_CONTEXT_REG_OFFSET) >> 2; 2060 ctx->pm4[ctx->pm4_cdwords++] = (t[i]->b.buffer_offset + 2061 t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */ 2062 ctx->pm4[ctx->pm4_cdwords++] = stride_in_dw[i]; /* VTX_STRIDE (in DW) */ 2063 ctx->pm4[ctx->pm4_cdwords++] = va >> 8; /* BUFFER_BASE */ 2064 2065 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 2066 ctx->pm4[ctx->pm4_cdwords++] = 2067 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer), 2068 RADEON_USAGE_WRITE); 2069 2070 if (ctx->streamout_append_bitmask & (1 << i)) { 2071 va = r600_resource_va(&ctx->screen->screen, 2072 (void*)t[i]->filled_size); 2073 /* Append. */ 2074 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); 2075 ctx->pm4[ctx->pm4_cdwords++] = STRMOUT_SELECT_BUFFER(i) | 2076 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */ 2077 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */ 2078 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */ 2079 ctx->pm4[ctx->pm4_cdwords++] = va & 0xFFFFFFFFUL; /* src address lo */ 2080 ctx->pm4[ctx->pm4_cdwords++] = (va >> 32UL) & 0xFFUL; /* src address hi */ 2081 2082 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 2083 ctx->pm4[ctx->pm4_cdwords++] = 2084 r600_context_bo_reloc(ctx, t[i]->filled_size, 2085 RADEON_USAGE_READ); 2086 } else { 2087 /* Start from the beginning. */ 2088 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); 2089 ctx->pm4[ctx->pm4_cdwords++] = STRMOUT_SELECT_BUFFER(i) | 2090 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */ 2091 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */ 2092 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */ 2093 ctx->pm4[ctx->pm4_cdwords++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */ 2094 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */ 2095 } 2096 } 2097 } 2098 2099 if (ctx->screen->family > CHIP_R600 && ctx->screen->family < CHIP_RV770) { 2100 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0); 2101 ctx->pm4[ctx->pm4_cdwords++] = update_flags; 2102 } 2103} 2104 2105void r600_context_streamout_end(struct r600_context *ctx) 2106{ 2107 struct r600_so_target **t = ctx->so_targets; 2108 unsigned i, flush_flags = 0; 2109 uint64_t va; 2110 2111 if (ctx->screen->chip_class >= EVERGREEN) { 2112 evergreen_flush_vgt_streamout(ctx); 2113 } else { 2114 r600_flush_vgt_streamout(ctx); 2115 } 2116 2117 for (i = 0; i < ctx->num_so_targets; i++) { 2118 if (t[i]) { 2119 va = r600_resource_va(&ctx->screen->screen, 2120 (void*)t[i]->filled_size); 2121 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); 2122 ctx->pm4[ctx->pm4_cdwords++] = STRMOUT_SELECT_BUFFER(i) | 2123 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) | 2124 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */ 2125 ctx->pm4[ctx->pm4_cdwords++] = va & 0xFFFFFFFFUL; /* dst address lo */ 2126 ctx->pm4[ctx->pm4_cdwords++] = (va >> 32UL) & 0xFFUL; /* dst address hi */ 2127 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */ 2128 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */ 2129 2130 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 2131 ctx->pm4[ctx->pm4_cdwords++] = 2132 r600_context_bo_reloc(ctx, t[i]->filled_size, 2133 RADEON_USAGE_WRITE); 2134 2135 flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i; 2136 } 2137 } 2138 2139 if (ctx->screen->chip_class >= EVERGREEN) { 2140 evergreen_set_streamout_enable(ctx, 0); 2141 } else { 2142 r600_set_streamout_enable(ctx, 0); 2143 } 2144 2145 if (ctx->screen->family < CHIP_RV770) { 2146 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 2147 ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0); 2148 } else { 2149 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3, 0); 2150 ctx->pm4[ctx->pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */ 2151 ctx->pm4[ctx->pm4_cdwords++] = 0xffffffff; /* CP_COHER_SIZE */ 2152 ctx->pm4[ctx->pm4_cdwords++] = 0; /* CP_COHER_BASE */ 2153 ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A; /* POLL_INTERVAL */ 2154 } 2155 2156 ctx->num_cs_dw_streamout_end = 0; 2157 2158#if 0 2159 for (i = 0; i < ctx->num_so_targets; i++) { 2160 if (!t[i]) 2161 continue; 2162 2163 uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->buf, ctx->cs, RADEON_USAGE_READ); 2164 printf("FILLED_SIZE%i: %u\n", i, *ptr); 2165 ctx->ws->buffer_unmap(t[i]->filled_size->buf); 2166 } 2167#endif 2168} 2169 2170void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t) 2171{ 2172 uint64_t va = r600_resource_va(&ctx->screen->screen, 2173 (void*)t->filled_size); 2174 2175 r600_need_cs_space(ctx, 14 + 21, TRUE); 2176 2177 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 2178 ctx->pm4[ctx->pm4_cdwords++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - R600_CONTEXT_REG_OFFSET) >> 2; 2179 ctx->pm4[ctx->pm4_cdwords++] = 0; 2180 2181 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 2182 ctx->pm4[ctx->pm4_cdwords++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - R600_CONTEXT_REG_OFFSET) >> 2; 2183 ctx->pm4[ctx->pm4_cdwords++] = t->stride_in_dw; 2184 2185 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_COPY_DW, 4, 0); 2186 ctx->pm4[ctx->pm4_cdwords++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG; 2187 ctx->pm4[ctx->pm4_cdwords++] = va & 0xFFFFFFFFUL; /* src address lo */ 2188 ctx->pm4[ctx->pm4_cdwords++] = (va >> 32UL) & 0xFFUL; /* src address hi */ 2189 ctx->pm4[ctx->pm4_cdwords++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */ 2190 ctx->pm4[ctx->pm4_cdwords++] = 0; /* unused */ 2191 2192 ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0, 0); 2193 ctx->pm4[ctx->pm4_cdwords++] = r600_context_bo_reloc(ctx, t->filled_size, 2194 RADEON_USAGE_READ); 2195} 2196