r600_hw_context.c revision 89293287b8f1a24c1405750007ca20bd32e02eab
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#include "r600_hw_context_priv.h" 27#include "r600_pipe.h" 28#include "r600d.h" 29#include "util/u_memory.h" 30#include <errno.h> 31 32/* Get backends mask */ 33void r600_get_backend_mask(struct r600_context *ctx) 34{ 35 struct radeon_winsys_cs *cs = ctx->cs; 36 struct r600_resource *buffer; 37 uint32_t *results; 38 unsigned num_backends = ctx->screen->info.r600_num_backends; 39 unsigned i, mask = 0; 40 41 /* if backend_map query is supported by the kernel */ 42 if (ctx->screen->info.r600_backend_map_valid) { 43 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes; 44 unsigned backend_map = ctx->screen->info.r600_backend_map; 45 unsigned item_width, item_mask; 46 47 if (ctx->chip_class >= EVERGREEN) { 48 item_width = 4; 49 item_mask = 0x7; 50 } else { 51 item_width = 2; 52 item_mask = 0x3; 53 } 54 55 while(num_tile_pipes--) { 56 i = backend_map & item_mask; 57 mask |= (1<<i); 58 backend_map >>= item_width; 59 } 60 if (mask != 0) { 61 ctx->backend_mask = mask; 62 return; 63 } 64 } 65 66 /* otherwise backup path for older kernels */ 67 68 /* create buffer for event data */ 69 buffer = (struct r600_resource*) 70 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, 71 PIPE_USAGE_STAGING, ctx->max_db*16); 72 if (!buffer) 73 goto err; 74 75 /* initialize buffer with zeroes */ 76 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); 77 if (results) { 78 memset(results, 0, ctx->max_db * 4 * 4); 79 ctx->ws->buffer_unmap(buffer->buf); 80 81 /* emit EVENT_WRITE for ZPASS_DONE */ 82 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 83 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); 84 cs->buf[cs->cdw++] = 0; 85 cs->buf[cs->cdw++] = 0; 86 87 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 88 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE); 89 90 /* analyze results */ 91 results = ctx->ws->buffer_map(buffer->buf, ctx->cs, PIPE_TRANSFER_READ); 92 if (results) { 93 for(i = 0; i < ctx->max_db; i++) { 94 /* at least highest bit will be set if backend is used */ 95 if (results[i*4 + 1]) 96 mask |= (1<<i); 97 } 98 ctx->ws->buffer_unmap(buffer->buf); 99 } 100 } 101 102 pipe_resource_reference((struct pipe_resource**)&buffer, NULL); 103 104 if (mask != 0) { 105 ctx->backend_mask = mask; 106 return; 107 } 108 109err: 110 /* fallback to old method - set num_backends lower bits to 1 */ 111 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends); 112 return; 113} 114 115void r600_context_ps_partial_flush(struct r600_context *ctx) 116{ 117 struct radeon_winsys_cs *cs = ctx->cs; 118 119 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING)) 120 return; 121 122 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 123 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); 124 125 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING; 126} 127 128static void r600_init_block(struct r600_context *ctx, 129 struct r600_block *block, 130 const struct r600_reg *reg, int index, int nreg, 131 unsigned opcode, unsigned offset_base) 132{ 133 int i = index; 134 int j, n = nreg; 135 136 /* initialize block */ 137 if (opcode == PKT3_SET_RESOURCE) { 138 block->flags = BLOCK_FLAG_RESOURCE; 139 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */ 140 } else { 141 block->flags = 0; 142 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */ 143 } 144 block->start_offset = reg[i].offset; 145 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0); 146 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2; 147 block->reg = &block->pm4[block->pm4_ndwords]; 148 block->pm4_ndwords += n; 149 block->nreg = n; 150 block->nreg_dirty = n; 151 LIST_INITHEAD(&block->list); 152 LIST_INITHEAD(&block->enable_list); 153 154 for (j = 0; j < n; j++) { 155 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) { 156 block->flags |= REG_FLAG_DIRTY_ALWAYS; 157 } 158 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) { 159 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 160 block->status |= R600_BLOCK_STATUS_ENABLED; 161 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 162 LIST_ADDTAIL(&block->list,&ctx->dirty); 163 } 164 } 165 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) { 166 block->flags |= REG_FLAG_FLUSH_CHANGE; 167 } 168 169 if (reg[i+j].flags & REG_FLAG_NEED_BO) { 170 block->nbo++; 171 assert(block->nbo < R600_BLOCK_MAX_BO); 172 block->pm4_bo_index[j] = block->nbo; 173 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0); 174 block->pm4[block->pm4_ndwords++] = 0x00000000; 175 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1; 176 } 177 if ((ctx->family > CHIP_R600) && 178 (ctx->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) { 179 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0); 180 block->pm4[block->pm4_ndwords++] = reg[i+j].sbu_flags; 181 } 182 } 183 /* check that we stay in limit */ 184 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG); 185} 186 187int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg, 188 unsigned opcode, unsigned offset_base) 189{ 190 struct r600_block *block; 191 struct r600_range *range; 192 int offset; 193 194 for (unsigned i = 0, n = 0; i < nreg; i += n) { 195 /* ignore new block balise */ 196 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) { 197 n = 1; 198 continue; 199 } 200 201 /* ignore regs not on R600 on R600 */ 202 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->family == CHIP_R600) { 203 n = 1; 204 continue; 205 } 206 207 /* register that need relocation are in their own group */ 208 /* find number of consecutive registers */ 209 n = 0; 210 offset = reg[i].offset; 211 while (reg[i + n].offset == offset) { 212 n++; 213 offset += 4; 214 if ((n + i) >= nreg) 215 break; 216 if (n >= (R600_BLOCK_MAX_REG - 2)) 217 break; 218 } 219 220 /* allocate new block */ 221 block = calloc(1, sizeof(struct r600_block)); 222 if (block == NULL) { 223 return -ENOMEM; 224 } 225 ctx->nblocks++; 226 for (int j = 0; j < n; j++) { 227 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)]; 228 /* create block table if it doesn't exist */ 229 if (!range->blocks) 230 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *)); 231 if (!range->blocks) 232 return -1; 233 234 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block; 235 } 236 237 r600_init_block(ctx, block, reg, i, n, opcode, offset_base); 238 239 } 240 return 0; 241} 242 243/* R600/R700 configuration */ 244static const struct r600_reg r600_config_reg_list[] = { 245 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0}, 246 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, 247 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, 248}; 249 250static const struct r600_reg r600_ctl_const_list[] = { 251 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0}, 252}; 253 254static const struct r600_reg r600_context_reg_list[] = { 255 {R_028A4C_PA_SC_MODE_CNTL, 0, 0}, 256 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 257 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0)}, 258 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 259 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0}, 260 {R_028060_CB_COLOR0_SIZE, 0, 0}, 261 {R_028080_CB_COLOR0_VIEW, 0, 0}, 262 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 263 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0}, 264 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 265 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0}, 266 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 267 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)}, 268 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 269 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0}, 270 {R_028064_CB_COLOR1_SIZE, 0, 0}, 271 {R_028084_CB_COLOR1_VIEW, 0, 0}, 272 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 273 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0}, 274 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 275 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0}, 276 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 277 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)}, 278 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 279 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0}, 280 {R_028068_CB_COLOR2_SIZE, 0, 0}, 281 {R_028088_CB_COLOR2_VIEW, 0, 0}, 282 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 283 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0}, 284 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 285 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0}, 286 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 287 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)}, 288 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 289 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0}, 290 {R_02806C_CB_COLOR3_SIZE, 0, 0}, 291 {R_02808C_CB_COLOR3_VIEW, 0, 0}, 292 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 293 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0}, 294 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 295 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0}, 296 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 297 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)}, 298 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 299 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0}, 300 {R_028070_CB_COLOR4_SIZE, 0, 0}, 301 {R_028090_CB_COLOR4_VIEW, 0, 0}, 302 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 303 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0}, 304 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 305 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0}, 306 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 307 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)}, 308 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 309 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0}, 310 {R_028074_CB_COLOR5_SIZE, 0, 0}, 311 {R_028094_CB_COLOR5_VIEW, 0, 0}, 312 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 313 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0}, 314 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 315 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0}, 316 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)}, 317 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0}, 318 {R_028078_CB_COLOR6_SIZE, 0, 0}, 319 {R_028098_CB_COLOR6_VIEW, 0, 0}, 320 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 321 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0}, 322 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 323 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0}, 324 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 325 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)}, 326 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 327 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0}, 328 {R_02807C_CB_COLOR7_SIZE, 0, 0}, 329 {R_02809C_CB_COLOR7_VIEW, 0, 0}, 330 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0}, 331 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0}, 332 {R_028120_CB_CLEAR_RED, 0, 0}, 333 {R_028124_CB_CLEAR_GREEN, 0, 0}, 334 {R_028128_CB_CLEAR_BLUE, 0, 0}, 335 {R_02812C_CB_CLEAR_ALPHA, 0, 0}, 336 {R_028140_ALU_CONST_BUFFER_SIZE_PS_0, REG_FLAG_DIRTY_ALWAYS, 0}, 337 {R_028144_ALU_CONST_BUFFER_SIZE_PS_1, REG_FLAG_DIRTY_ALWAYS, 0}, 338 {R_028180_ALU_CONST_BUFFER_SIZE_VS_0, REG_FLAG_DIRTY_ALWAYS, 0}, 339 {R_028184_ALU_CONST_BUFFER_SIZE_VS_1, REG_FLAG_DIRTY_ALWAYS, 0}, 340 {R_028940_ALU_CONST_CACHE_PS_0, REG_FLAG_NEED_BO, 0}, 341 {R_028944_ALU_CONST_CACHE_PS_1, REG_FLAG_NEED_BO, 0}, 342 {R_028980_ALU_CONST_CACHE_VS_0, REG_FLAG_NEED_BO, 0}, 343 {R_028984_ALU_CONST_CACHE_VS_1, REG_FLAG_NEED_BO, 0}, 344 {R_02823C_CB_SHADER_MASK, 0, 0}, 345 {R_028238_CB_TARGET_MASK, 0, 0}, 346 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0}, 347 {R_028414_CB_BLEND_RED, 0, 0}, 348 {R_028418_CB_BLEND_GREEN, 0, 0}, 349 {R_02841C_CB_BLEND_BLUE, 0, 0}, 350 {R_028420_CB_BLEND_ALPHA, 0, 0}, 351 {R_028424_CB_FOG_RED, 0, 0}, 352 {R_028428_CB_FOG_GREEN, 0, 0}, 353 {R_02842C_CB_FOG_BLUE, 0, 0}, 354 {R_028430_DB_STENCILREFMASK, 0, 0}, 355 {R_028434_DB_STENCILREFMASK_BF, 0, 0}, 356 {R_028438_SX_ALPHA_REF, 0, 0}, 357 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0}, 358 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0}, 359 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0}, 360 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0}, 361 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0}, 362 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0}, 363 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0}, 364 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0}, 365 {R_0287A0_CB_SHADER_CONTROL, 0, 0}, 366 {R_028800_DB_DEPTH_CONTROL, 0, 0}, 367 {R_028804_CB_BLEND_CONTROL, 0, 0}, 368 {R_028808_CB_COLOR_CONTROL, 0, 0}, 369 {R_02880C_DB_SHADER_CONTROL, 0, 0}, 370 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH}, 371 {R_028000_DB_DEPTH_SIZE, 0, 0}, 372 {R_028004_DB_DEPTH_VIEW, 0, 0}, 373 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 374 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0}, 375 {R_028D24_DB_HTILE_SURFACE, 0, 0}, 376 {R_028D34_DB_PREFETCH_LIMIT, 0, 0}, 377 {R_028030_PA_SC_SCREEN_SCISSOR_TL, 0, 0}, 378 {R_028034_PA_SC_SCREEN_SCISSOR_BR, 0, 0}, 379 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0}, 380 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0}, 381 {R_02820C_PA_SC_CLIPRECT_RULE, 0, 0}, 382 {R_028210_PA_SC_CLIPRECT_0_TL, 0, 0}, 383 {R_028214_PA_SC_CLIPRECT_0_BR, 0, 0}, 384 {R_028218_PA_SC_CLIPRECT_1_TL, 0, 0}, 385 {R_02821C_PA_SC_CLIPRECT_1_BR, 0, 0}, 386 {R_028220_PA_SC_CLIPRECT_2_TL, 0, 0}, 387 {R_028224_PA_SC_CLIPRECT_2_BR, 0, 0}, 388 {R_028228_PA_SC_CLIPRECT_3_TL, 0, 0}, 389 {R_02822C_PA_SC_CLIPRECT_3_BR, 0, 0}, 390 {R_028240_PA_SC_GENERIC_SCISSOR_TL, 0, 0}, 391 {R_028244_PA_SC_GENERIC_SCISSOR_BR, 0, 0}, 392 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0}, 393 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0}, 394 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0}, 395 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0}, 396 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0}, 397 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0}, 398 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0}, 399 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0}, 400 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0}, 401 {R_028810_PA_CL_CLIP_CNTL, 0, 0}, 402 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0}, 403 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0}, 404 {R_028A00_PA_SU_POINT_SIZE, 0, 0}, 405 {R_028A04_PA_SU_POINT_MINMAX, 0, 0}, 406 {R_028A08_PA_SU_LINE_CNTL, 0, 0}, 407 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0}, 408 {R_028C08_PA_SU_VTX_CNTL, 0, 0}, 409 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0}, 410 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0}, 411 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0}, 412 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0}, 413 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0}, 414 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0}, 415 {R_028E20_PA_CL_UCP0_X, 0, 0}, 416 {R_028E24_PA_CL_UCP0_Y, 0, 0}, 417 {R_028E28_PA_CL_UCP0_Z, 0, 0}, 418 {R_028E2C_PA_CL_UCP0_W, 0, 0}, 419 {R_028E30_PA_CL_UCP1_X, 0, 0}, 420 {R_028E34_PA_CL_UCP1_Y, 0, 0}, 421 {R_028E38_PA_CL_UCP1_Z, 0, 0}, 422 {R_028E3C_PA_CL_UCP1_W, 0, 0}, 423 {R_028E40_PA_CL_UCP2_X, 0, 0}, 424 {R_028E44_PA_CL_UCP2_Y, 0, 0}, 425 {R_028E48_PA_CL_UCP2_Z, 0, 0}, 426 {R_028E4C_PA_CL_UCP2_W, 0, 0}, 427 {R_028E50_PA_CL_UCP3_X, 0, 0}, 428 {R_028E54_PA_CL_UCP3_Y, 0, 0}, 429 {R_028E58_PA_CL_UCP3_Z, 0, 0}, 430 {R_028E5C_PA_CL_UCP3_W, 0, 0}, 431 {R_028E60_PA_CL_UCP4_X, 0, 0}, 432 {R_028E64_PA_CL_UCP4_Y, 0, 0}, 433 {R_028E68_PA_CL_UCP4_Z, 0, 0}, 434 {R_028E6C_PA_CL_UCP4_W, 0, 0}, 435 {R_028E70_PA_CL_UCP5_X, 0, 0}, 436 {R_028E74_PA_CL_UCP5_Y, 0, 0}, 437 {R_028E78_PA_CL_UCP5_Z, 0, 0}, 438 {R_028E7C_PA_CL_UCP5_W, 0, 0}, 439 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0}, 440 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0}, 441 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0}, 442 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0}, 443 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0}, 444 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0}, 445 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0}, 446 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0}, 447 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0}, 448 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0}, 449 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0}, 450 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0}, 451 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0}, 452 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0}, 453 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0}, 454 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0}, 455 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0}, 456 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0}, 457 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0}, 458 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0}, 459 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0}, 460 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0}, 461 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0}, 462 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0}, 463 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0}, 464 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0}, 465 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0}, 466 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0}, 467 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0}, 468 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0}, 469 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0}, 470 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0}, 471 {R_028614_SPI_VS_OUT_ID_0, 0, 0}, 472 {R_028618_SPI_VS_OUT_ID_1, 0, 0}, 473 {R_02861C_SPI_VS_OUT_ID_2, 0, 0}, 474 {R_028620_SPI_VS_OUT_ID_3, 0, 0}, 475 {R_028624_SPI_VS_OUT_ID_4, 0, 0}, 476 {R_028628_SPI_VS_OUT_ID_5, 0, 0}, 477 {R_02862C_SPI_VS_OUT_ID_6, 0, 0}, 478 {R_028630_SPI_VS_OUT_ID_7, 0, 0}, 479 {R_028634_SPI_VS_OUT_ID_8, 0, 0}, 480 {R_028638_SPI_VS_OUT_ID_9, 0, 0}, 481 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0}, 482 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 483 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0}, 484 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 485 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0}, 486 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 487 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0}, 488 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 489 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0}, 490 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0}, 491 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0}, 492 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0}, 493 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0}, 494 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0}, 495 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0}, 496 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0}, 497 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0}, 498 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0}, 499 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0}, 500 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0}, 501 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0}, 502 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0}, 503 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0}, 504 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0}, 505 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0}, 506 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0}, 507 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0}, 508 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0}, 509 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0}, 510 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0}, 511 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0}, 512 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0}, 513 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0}, 514 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0}, 515 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0}, 516 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0}, 517 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0}, 518 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0}, 519 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0}, 520 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0}, 521 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0}, 522 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0}, 523 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0}, 524 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0}, 525 {R_0286D8_SPI_INPUT_Z, 0, 0}, 526 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 527 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0}, 528 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 529 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0}, 530 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0}, 531 {R_028408_VGT_INDX_OFFSET, 0, 0}, 532 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0}, 533 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0}, 534}; 535 536/* SHADER RESOURCE R600/R700 */ 537int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base) 538{ 539 int i; 540 struct r600_block *block; 541 range->blocks = calloc(nblocks, sizeof(struct r600_block *)); 542 if (range->blocks == NULL) 543 return -ENOMEM; 544 545 reg[0].offset += offset; 546 for (i = 0; i < nblocks; i++) { 547 block = calloc(1, sizeof(struct r600_block)); 548 if (block == NULL) { 549 return -ENOMEM; 550 } 551 ctx->nblocks++; 552 range->blocks[i] = block; 553 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base); 554 555 reg[0].offset += stride; 556 } 557 return 0; 558} 559 560 561static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride) 562{ 563 struct r600_reg r600_shader_resource[] = { 564 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0}, 565 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0}, 566 {R_038008_RESOURCE0_WORD2, 0, 0}, 567 {R_03800C_RESOURCE0_WORD3, 0, 0}, 568 {R_038010_RESOURCE0_WORD4, 0, 0}, 569 {R_038014_RESOURCE0_WORD5, 0, 0}, 570 {R_038018_RESOURCE0_WORD6, 0, 0}, 571 }; 572 unsigned nreg = Elements(r600_shader_resource); 573 574 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET); 575} 576 577/* SHADER SAMPLER R600/R700/EG/CM */ 578int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset) 579{ 580 struct r600_reg r600_shader_sampler[] = { 581 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0}, 582 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0}, 583 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0}, 584 }; 585 unsigned nreg = Elements(r600_shader_sampler); 586 587 for (int i = 0; i < nreg; i++) { 588 r600_shader_sampler[i].offset += offset; 589 } 590 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET); 591} 592 593/* SHADER SAMPLER BORDER R600/R700 */ 594static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset) 595{ 596 struct r600_reg r600_shader_sampler_border[] = { 597 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0}, 598 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0}, 599 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0}, 600 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0}, 601 }; 602 unsigned nreg = Elements(r600_shader_sampler_border); 603 604 for (int i = 0; i < nreg; i++) { 605 r600_shader_sampler_border[i].offset += offset; 606 } 607 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); 608} 609 610static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset) 611{ 612 unsigned nreg = 32; 613 struct r600_reg r600_loop_consts[32]; 614 int i; 615 616 for (i = 0; i < nreg; i++) { 617 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4); 618 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS; 619 r600_loop_consts[i].sbu_flags = 0; 620 } 621 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET); 622} 623 624static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks) 625{ 626 struct r600_block *block; 627 int i; 628 629 if (!range->blocks) { 630 return; /* nothing to do */ 631 } 632 633 for (i = 0; i < nblocks; i++) { 634 block = range->blocks[i]; 635 if (block) { 636 for (int k = 1; k <= block->nbo; k++) 637 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL); 638 free(block); 639 } 640 } 641 free(range->blocks); 642} 643 644/* initialize */ 645void r600_context_fini(struct r600_context *ctx) 646{ 647 struct r600_block *block; 648 struct r600_range *range; 649 650 if (ctx->range) { 651 for (int i = 0; i < NUM_RANGES; i++) { 652 if (!ctx->range[i].blocks) 653 continue; 654 for (int j = 0; j < (1 << HASH_SHIFT); j++) { 655 block = ctx->range[i].blocks[j]; 656 if (block) { 657 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) { 658 range = &ctx->range[CTX_RANGE_ID(offset)]; 659 range->blocks[CTX_BLOCK_ID(offset)] = NULL; 660 } 661 for (int k = 1; k <= block->nbo; k++) { 662 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL); 663 } 664 free(block); 665 } 666 } 667 free(ctx->range[i].blocks); 668 } 669 } 670 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources); 671 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources); 672 r600_free_resource_range(ctx, &ctx->fs_resources, ctx->num_fs_resources); 673 free(ctx->blocks); 674} 675 676static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index) 677{ 678 int c = *index; 679 for (int j = 0; j < num_blocks; j++) { 680 if (!range->blocks[j]) 681 continue; 682 683 ctx->blocks[c++] = range->blocks[j]; 684 } 685 *index = c; 686} 687 688int r600_setup_block_table(struct r600_context *ctx) 689{ 690 /* setup block table */ 691 int c = 0; 692 ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); 693 if (!ctx->blocks) 694 return -ENOMEM; 695 for (int i = 0; i < NUM_RANGES; i++) { 696 if (!ctx->range[i].blocks) 697 continue; 698 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) { 699 if (!ctx->range[i].blocks[j]) 700 continue; 701 702 add = 1; 703 for (int k = 0; k < c; k++) { 704 if (ctx->blocks[k] == ctx->range[i].blocks[j]) { 705 add = 0; 706 break; 707 } 708 } 709 if (add) { 710 assert(c < ctx->nblocks); 711 ctx->blocks[c++] = ctx->range[i].blocks[j]; 712 j += (ctx->range[i].blocks[j]->nreg) - 1; 713 } 714 } 715 } 716 717 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c); 718 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c); 719 r600_add_resource_block(ctx, &ctx->fs_resources, ctx->num_fs_resources, &c); 720 return 0; 721} 722 723int r600_context_init(struct r600_context *ctx) 724{ 725 int r; 726 727 /* add blocks */ 728 r = r600_context_add_block(ctx, r600_config_reg_list, 729 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); 730 if (r) 731 goto out_err; 732 r = r600_context_add_block(ctx, r600_context_reg_list, 733 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET); 734 if (r) 735 goto out_err; 736 r = r600_context_add_block(ctx, r600_ctl_const_list, 737 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET); 738 if (r) 739 goto out_err; 740 741 /* PS SAMPLER BORDER */ 742 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) { 743 r = r600_state_sampler_border_init(ctx, offset); 744 if (r) 745 goto out_err; 746 } 747 748 /* VS SAMPLER BORDER */ 749 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) { 750 r = r600_state_sampler_border_init(ctx, offset); 751 if (r) 752 goto out_err; 753 } 754 /* PS SAMPLER */ 755 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) { 756 r = r600_state_sampler_init(ctx, offset); 757 if (r) 758 goto out_err; 759 } 760 /* VS SAMPLER */ 761 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) { 762 r = r600_state_sampler_init(ctx, offset); 763 if (r) 764 goto out_err; 765 } 766 767 ctx->num_ps_resources = 160; 768 ctx->num_vs_resources = 160; 769 ctx->num_fs_resources = 16; 770 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c); 771 if (r) 772 goto out_err; 773 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c); 774 if (r) 775 goto out_err; 776 r = r600_resource_range_init(ctx, &ctx->fs_resources, 0x2300, 16, 0x1c); 777 if (r) 778 goto out_err; 779 780 /* PS loop const */ 781 r600_loop_const_init(ctx, 0); 782 /* VS loop const */ 783 r600_loop_const_init(ctx, 32); 784 785 r = r600_setup_block_table(ctx); 786 if (r) 787 goto out_err; 788 789 ctx->max_db = 4; 790 return 0; 791out_err: 792 r600_context_fini(ctx); 793 return r; 794} 795 796void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, 797 boolean count_draw_in) 798{ 799 struct r600_atom *state; 800 801 /* The number of dwords we already used in the CS so far. */ 802 num_dw += ctx->cs->cdw; 803 804 if (count_draw_in) { 805 /* The number of dwords all the dirty states would take. */ 806 LIST_FOR_EACH_ENTRY(state, &ctx->dirty_states, head) { 807 num_dw += state->num_dw; 808 } 809 810 num_dw += ctx->pm4_dirty_cdwords; 811 812 /* The upper-bound of how much a draw command would take. */ 813 num_dw += R600_MAX_DRAW_CS_DWORDS; 814 } 815 816 /* Count in queries_suspend. */ 817 num_dw += ctx->num_cs_dw_queries_suspend; 818 819 /* Count in streamout_end at the end of CS. */ 820 num_dw += ctx->num_cs_dw_streamout_end; 821 822 /* Count in render_condition(NULL) at the end of CS. */ 823 if (ctx->predicate_drawing) { 824 num_dw += 3; 825 } 826 827 /* Count in framebuffer cache flushes at the end of CS. */ 828 num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */ 829 830 /* Save 16 dwords for the fence mechanism. */ 831 num_dw += 16; 832 833 /* Flush if there's not enough space. */ 834 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { 835 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC); 836 } 837} 838 839void r600_context_dirty_block(struct r600_context *ctx, 840 struct r600_block *block, 841 int dirty, int index) 842{ 843 if ((index + 1) > block->nreg_dirty) 844 block->nreg_dirty = index + 1; 845 846 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) { 847 block->status |= R600_BLOCK_STATUS_DIRTY; 848 ctx->pm4_dirty_cdwords += block->pm4_ndwords; 849 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 850 block->status |= R600_BLOCK_STATUS_ENABLED; 851 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 852 } 853 LIST_ADDTAIL(&block->list,&ctx->dirty); 854 855 if (block->flags & REG_FLAG_FLUSH_CHANGE) { 856 r600_context_ps_partial_flush(ctx); 857 } 858 } 859} 860 861void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state) 862{ 863 struct r600_block *block; 864 int dirty; 865 for (int i = 0; i < state->nregs; i++) { 866 unsigned id, reloc_id; 867 struct r600_pipe_reg *reg = &state->regs[i]; 868 869 block = reg->block; 870 id = reg->id; 871 872 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 873 874 if (reg->value != block->reg[id]) { 875 block->reg[id] = reg->value; 876 dirty |= R600_BLOCK_STATUS_DIRTY; 877 } 878 if (block->flags & REG_FLAG_DIRTY_ALWAYS) 879 dirty |= R600_BLOCK_STATUS_DIRTY; 880 if (block->pm4_bo_index[id]) { 881 /* find relocation */ 882 reloc_id = block->pm4_bo_index[id]; 883 pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, ®->bo->b.b.b); 884 block->reloc[reloc_id].bo_usage = reg->bo_usage; 885 /* always force dirty for relocs for now */ 886 dirty |= R600_BLOCK_STATUS_DIRTY; 887 } 888 889 if (dirty) 890 r600_context_dirty_block(ctx, block, dirty, id); 891 } 892} 893 894static void r600_context_dirty_resource_block(struct r600_context *ctx, 895 struct r600_block *block, 896 int dirty, int index) 897{ 898 block->nreg_dirty = index + 1; 899 900 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) { 901 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 902 ctx->pm4_dirty_cdwords += block->pm4_ndwords; 903 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 904 block->status |= R600_BLOCK_STATUS_ENABLED; 905 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 906 } 907 LIST_ADDTAIL(&block->list,&ctx->resource_dirty); 908 } 909} 910 911void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block) 912{ 913 int dirty; 914 int num_regs = ctx->chip_class >= EVERGREEN ? 8 : 7; 915 boolean is_vertex; 916 917 if (state == NULL) { 918 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY); 919 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, NULL); 920 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL); 921 LIST_DELINIT(&block->list); 922 LIST_DELINIT(&block->enable_list); 923 return; 924 } 925 926 is_vertex = ((state->val[num_regs-1] & 0xc0000000) == 0xc0000000); 927 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY; 928 929 if (memcmp(block->reg, state->val, num_regs*4)) { 930 memcpy(block->reg, state->val, num_regs * 4); 931 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 932 } 933 934 /* if no BOs on block, force dirty */ 935 if (!block->reloc[1].bo || !block->reloc[2].bo) 936 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 937 938 if (!dirty) { 939 if (is_vertex) { 940 if (block->reloc[1].bo->buf != state->bo[0]->buf) 941 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 942 } else { 943 if ((block->reloc[1].bo->buf != state->bo[0]->buf) || 944 (block->reloc[2].bo->buf != state->bo[1]->buf)) 945 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 946 } 947 } 948 949 if (dirty) { 950 if (is_vertex) { 951 /* VERTEX RESOURCE, we preted there is 2 bo to relocate so 952 * we have single case btw VERTEX & TEXTURE resource 953 */ 954 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b); 955 block->reloc[1].bo_usage = state->bo_usage[0]; 956 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL); 957 } else { 958 /* TEXTURE RESOURCE */ 959 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b.b); 960 block->reloc[1].bo_usage = state->bo_usage[0]; 961 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b.b); 962 block->reloc[2].bo_usage = state->bo_usage[1]; 963 } 964 965 if (is_vertex) 966 block->status |= R600_BLOCK_STATUS_RESOURCE_VERTEX; 967 else 968 block->status &= ~R600_BLOCK_STATUS_RESOURCE_VERTEX; 969 970 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1); 971 } 972} 973 974void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 975{ 976 struct r600_block *block = ctx->ps_resources.blocks[rid]; 977 978 r600_context_pipe_state_set_resource(ctx, state, block); 979} 980 981void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 982{ 983 struct r600_block *block = ctx->vs_resources.blocks[rid]; 984 985 r600_context_pipe_state_set_resource(ctx, state, block); 986} 987 988void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 989{ 990 struct r600_block *block = ctx->fs_resources.blocks[rid]; 991 992 r600_context_pipe_state_set_resource(ctx, state, block); 993} 994 995void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) 996{ 997 struct r600_range *range; 998 struct r600_block *block; 999 int i; 1000 int dirty; 1001 1002 range = &ctx->range[CTX_RANGE_ID(offset)]; 1003 block = range->blocks[CTX_BLOCK_ID(offset)]; 1004 if (state == NULL) { 1005 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); 1006 LIST_DELINIT(&block->list); 1007 LIST_DELINIT(&block->enable_list); 1008 return; 1009 } 1010 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 1011 1012 for (i = 0; i < 3; i++) { 1013 if (block->reg[i] != state->regs[i].value) { 1014 block->reg[i] = state->regs[i].value; 1015 dirty |= R600_BLOCK_STATUS_DIRTY; 1016 } 1017 } 1018 1019 if (dirty) 1020 r600_context_dirty_block(ctx, block, dirty, 2); 1021} 1022 1023static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) 1024{ 1025 struct r600_range *range; 1026 struct r600_block *block; 1027 int i; 1028 int dirty; 1029 1030 range = &ctx->range[CTX_RANGE_ID(offset)]; 1031 block = range->blocks[CTX_BLOCK_ID(offset)]; 1032 if (state == NULL) { 1033 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); 1034 LIST_DELINIT(&block->list); 1035 LIST_DELINIT(&block->enable_list); 1036 return; 1037 } 1038 if (state->nregs <= 3) { 1039 return; 1040 } 1041 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 1042 for (i = 0; i < 4; i++) { 1043 if (block->reg[i] != state->regs[i + 3].value) { 1044 block->reg[i] = state->regs[i + 3].value; 1045 dirty |= R600_BLOCK_STATUS_DIRTY; 1046 } 1047 } 1048 1049 /* We have to flush the shaders before we change the border color 1050 * registers, or previous draw commands that haven't completed yet 1051 * will end up using the new border color. */ 1052 if (dirty & R600_BLOCK_STATUS_DIRTY) 1053 r600_context_ps_partial_flush(ctx); 1054 if (dirty) 1055 r600_context_dirty_block(ctx, block, dirty, 3); 1056} 1057 1058void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) 1059{ 1060 unsigned offset; 1061 1062 offset = 0x0003C000 + id * 0xc; 1063 r600_context_pipe_state_set_sampler(ctx, state, offset); 1064 offset = 0x0000A400 + id * 0x10; 1065 r600_context_pipe_state_set_sampler_border(ctx, state, offset); 1066} 1067 1068void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) 1069{ 1070 unsigned offset; 1071 1072 offset = 0x0003C0D8 + id * 0xc; 1073 r600_context_pipe_state_set_sampler(ctx, state, offset); 1074 offset = 0x0000A600 + id * 0x10; 1075 r600_context_pipe_state_set_sampler_border(ctx, state, offset); 1076} 1077 1078struct r600_resource *r600_context_reg_bo(struct r600_context *ctx, unsigned offset) 1079{ 1080 struct r600_range *range; 1081 struct r600_block *block; 1082 unsigned id; 1083 1084 range = &ctx->range[CTX_RANGE_ID(offset)]; 1085 block = range->blocks[CTX_BLOCK_ID(offset)]; 1086 offset -= block->start_offset; 1087 id = block->pm4_bo_index[offset >> 2]; 1088 if (block->reloc[id].bo) { 1089 return block->reloc[id].bo; 1090 } 1091 return NULL; 1092} 1093 1094void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block) 1095{ 1096 struct radeon_winsys_cs *cs = ctx->cs; 1097 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS); 1098 int cp_dwords = block->pm4_ndwords, start_dword = 0; 1099 int new_dwords = 0; 1100 int nbo = block->nbo; 1101 1102 if (block->nreg_dirty == 0 && optional) { 1103 goto out; 1104 } 1105 1106 if (nbo) { 1107 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH; 1108 1109 for (int j = 0; j < block->nreg; j++) { 1110 if (block->pm4_bo_index[j]) { 1111 /* find relocation */ 1112 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]]; 1113 if (reloc->bo) { 1114 block->pm4[reloc->bo_pm4_index] = 1115 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage); 1116 } else { 1117 block->pm4[reloc->bo_pm4_index] = 0; 1118 } 1119 nbo--; 1120 if (nbo == 0) 1121 break; 1122 1123 } 1124 } 1125 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; 1126 } 1127 1128 optional &= (block->nreg_dirty != block->nreg); 1129 if (optional) { 1130 new_dwords = block->nreg_dirty; 1131 start_dword = cs->cdw; 1132 cp_dwords = new_dwords + 2; 1133 } 1134 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4); 1135 cs->cdw += cp_dwords; 1136 1137 if (optional) { 1138 uint32_t newword; 1139 1140 newword = cs->buf[start_dword]; 1141 newword &= PKT_COUNT_C; 1142 newword |= PKT_COUNT_S(new_dwords); 1143 cs->buf[start_dword] = newword; 1144 } 1145out: 1146 block->status ^= R600_BLOCK_STATUS_DIRTY; 1147 block->nreg_dirty = 0; 1148 LIST_DELINIT(&block->list); 1149} 1150 1151void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block) 1152{ 1153 struct radeon_winsys_cs *cs = ctx->cs; 1154 int cp_dwords = block->pm4_ndwords; 1155 int nbo = block->nbo; 1156 1157 ctx->flags |= R600_CONTEXT_CHECK_EVENT_FLUSH; 1158 1159 if (block->status & R600_BLOCK_STATUS_RESOURCE_VERTEX) { 1160 nbo = 1; 1161 cp_dwords -= 2; /* don't copy the second NOP */ 1162 } 1163 1164 for (int j = 0; j < nbo; j++) { 1165 if (block->pm4_bo_index[j]) { 1166 /* find relocation */ 1167 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]]; 1168 block->pm4[reloc->bo_pm4_index] = 1169 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage); 1170 } 1171 } 1172 ctx->flags &= ~R600_CONTEXT_CHECK_EVENT_FLUSH; 1173 1174 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4); 1175 cs->cdw += cp_dwords; 1176 1177 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1178 block->nreg_dirty = 0; 1179 LIST_DELINIT(&block->list); 1180} 1181 1182void r600_inval_shader_cache(struct r600_context *ctx) 1183{ 1184 ctx->atom_surface_sync.flush_flags |= S_0085F0_SH_ACTION_ENA(1); 1185 r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); 1186} 1187 1188void r600_inval_texture_cache(struct r600_context *ctx) 1189{ 1190 ctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1); 1191 r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); 1192} 1193 1194void r600_inval_vertex_cache(struct r600_context *ctx) 1195{ 1196 if (ctx->family == CHIP_RV610 || 1197 ctx->family == CHIP_RV620 || 1198 ctx->family == CHIP_RS780 || 1199 ctx->family == CHIP_RS880 || 1200 ctx->family == CHIP_RV710 || 1201 ctx->family == CHIP_CEDAR || 1202 ctx->family == CHIP_PALM || 1203 ctx->family == CHIP_SUMO || 1204 ctx->family == CHIP_SUMO2 || 1205 ctx->family == CHIP_CAICOS || 1206 ctx->family == CHIP_CAYMAN) { 1207 /* Some GPUs don't have the vertex cache and must use the texture cache instead. */ 1208 ctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1); 1209 } else { 1210 ctx->atom_surface_sync.flush_flags |= S_0085F0_VC_ACTION_ENA(1); 1211 } 1212 r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); 1213} 1214 1215void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now) 1216{ 1217 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY)) 1218 return; 1219 1220 ctx->atom_surface_sync.flush_flags |= 1221 r600_get_cb_flush_flags(ctx) | 1222 (ctx->framebuffer.zsbuf ? S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1) : 0); 1223 1224 if (flush_now) { 1225 r600_emit_atom(ctx, &ctx->atom_surface_sync.atom); 1226 } else { 1227 r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); 1228 } 1229 1230 /* Also add a complete cache flush to work around broken flushing on R6xx. */ 1231 if (ctx->chip_class == R600) { 1232 if (flush_now) { 1233 r600_emit_atom(ctx, &ctx->atom_r6xx_flush_and_inv); 1234 } else { 1235 r600_atom_dirty(ctx, &ctx->atom_r6xx_flush_and_inv); 1236 } 1237 } 1238 1239 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY; 1240} 1241 1242void r600_context_flush(struct r600_context *ctx, unsigned flags) 1243{ 1244 struct radeon_winsys_cs *cs = ctx->cs; 1245 struct r600_block *enable_block = NULL; 1246 bool queries_suspended = false; 1247 bool streamout_suspended = false; 1248 1249 if (cs->cdw == ctx->atom_start_cs.atom.num_dw) 1250 return; 1251 1252 /* suspend queries */ 1253 if (ctx->num_cs_dw_queries_suspend) { 1254 r600_context_queries_suspend(ctx); 1255 queries_suspended = true; 1256 } 1257 1258 if (ctx->num_cs_dw_streamout_end) { 1259 r600_context_streamout_end(ctx); 1260 streamout_suspended = true; 1261 } 1262 1263 r600_flush_framebuffer(ctx, true); 1264 1265 /* partial flush is needed to avoid lockups on some chips with user fences */ 1266 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 1267 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); 1268 1269 /* force to keep tiling flags */ 1270 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS; 1271 1272 /* Flush the CS. */ 1273 ctx->ws->cs_flush(ctx->cs, flags); 1274 1275 ctx->pm4_dirty_cdwords = 0; 1276 ctx->flags = 0; 1277 1278 r600_emit_atom(ctx, &ctx->atom_start_cs.atom); 1279 r600_atom_dirty(ctx, &ctx->atom_db_misc_state.atom); 1280 1281 if (streamout_suspended) { 1282 ctx->streamout_start = TRUE; 1283 ctx->streamout_append_bitmask = ~0; 1284 } 1285 1286 /* resume queries */ 1287 if (queries_suspended) { 1288 r600_context_queries_resume(ctx); 1289 } 1290 1291 /* set all valid group as dirty so they get reemited on 1292 * next draw command 1293 */ 1294 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) { 1295 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) { 1296 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) { 1297 LIST_ADDTAIL(&enable_block->list,&ctx->dirty); 1298 enable_block->status |= R600_BLOCK_STATUS_DIRTY; 1299 } 1300 } else { 1301 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) { 1302 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty); 1303 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1304 } 1305 } 1306 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords; 1307 enable_block->nreg_dirty = enable_block->nreg; 1308 } 1309} 1310 1311void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value) 1312{ 1313 struct radeon_winsys_cs *cs = ctx->cs; 1314 uint64_t va; 1315 1316 r600_need_cs_space(ctx, 10, FALSE); 1317 1318 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo); 1319 va = va + (offset << 2); 1320 1321 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 1322 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); 1323 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); 1324 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); 1325 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */ 1326 /* DATA_SEL | INT_EN | ADDRESS_HI */ 1327 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF); 1328 cs->buf[cs->cdw++] = value; /* DATA_LO */ 1329 cs->buf[cs->cdw++] = 0; /* DATA_HI */ 1330 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1331 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE); 1332} 1333 1334static unsigned r600_query_read_result(char *map, unsigned start_index, unsigned end_index, 1335 bool test_status_bit) 1336{ 1337 uint32_t *current_result = (uint32_t*)map; 1338 uint64_t start, end; 1339 1340 start = (uint64_t)current_result[start_index] | 1341 (uint64_t)current_result[start_index+1] << 32; 1342 end = (uint64_t)current_result[end_index] | 1343 (uint64_t)current_result[end_index+1] << 32; 1344 1345 if (!test_status_bit || 1346 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) { 1347 return end - start; 1348 } 1349 return 0; 1350} 1351 1352static boolean r600_query_result(struct r600_context *ctx, struct r600_query *query, boolean wait) 1353{ 1354 unsigned results_base = query->results_start; 1355 char *map; 1356 1357 map = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, 1358 PIPE_TRANSFER_READ | 1359 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK)); 1360 if (!map) 1361 return FALSE; 1362 1363 /* count all results across all data blocks */ 1364 switch (query->type) { 1365 case PIPE_QUERY_OCCLUSION_COUNTER: 1366 while (results_base != query->results_end) { 1367 query->result.u64 += 1368 r600_query_read_result(map + results_base, 0, 2, true); 1369 results_base = (results_base + 16) % query->buffer->b.b.b.width0; 1370 } 1371 break; 1372 case PIPE_QUERY_OCCLUSION_PREDICATE: 1373 while (results_base != query->results_end) { 1374 query->result.b = query->result.b || 1375 r600_query_read_result(map + results_base, 0, 2, true) != 0; 1376 results_base = (results_base + 16) % query->buffer->b.b.b.width0; 1377 } 1378 break; 1379 case PIPE_QUERY_TIME_ELAPSED: 1380 while (results_base != query->results_end) { 1381 query->result.u64 += 1382 r600_query_read_result(map + results_base, 0, 2, false); 1383 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1384 } 1385 break; 1386 case PIPE_QUERY_PRIMITIVES_EMITTED: 1387 /* SAMPLE_STREAMOUTSTATS stores this structure: 1388 * { 1389 * u64 NumPrimitivesWritten; 1390 * u64 PrimitiveStorageNeeded; 1391 * } 1392 * We only need NumPrimitivesWritten here. */ 1393 while (results_base != query->results_end) { 1394 query->result.u64 += 1395 r600_query_read_result(map + results_base, 2, 6, true); 1396 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1397 } 1398 break; 1399 case PIPE_QUERY_PRIMITIVES_GENERATED: 1400 /* Here we read PrimitiveStorageNeeded. */ 1401 while (results_base != query->results_end) { 1402 query->result.u64 += 1403 r600_query_read_result(map + results_base, 0, 4, true); 1404 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1405 } 1406 break; 1407 case PIPE_QUERY_SO_STATISTICS: 1408 while (results_base != query->results_end) { 1409 query->result.so.num_primitives_written += 1410 r600_query_read_result(map + results_base, 2, 6, true); 1411 query->result.so.primitives_storage_needed += 1412 r600_query_read_result(map + results_base, 0, 4, true); 1413 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1414 } 1415 break; 1416 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1417 while (results_base != query->results_end) { 1418 query->result.b = query->result.b || 1419 r600_query_read_result(map + results_base, 2, 6, true) != 1420 r600_query_read_result(map + results_base, 0, 4, true); 1421 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1422 } 1423 break; 1424 default: 1425 assert(0); 1426 } 1427 1428 query->results_start = query->results_end; 1429 ctx->ws->buffer_unmap(query->buffer->buf); 1430 return TRUE; 1431} 1432 1433void r600_query_begin(struct r600_context *ctx, struct r600_query *query) 1434{ 1435 struct radeon_winsys_cs *cs = ctx->cs; 1436 unsigned new_results_end, i; 1437 uint32_t *results; 1438 uint64_t va; 1439 1440 r600_need_cs_space(ctx, query->num_cs_dw * 2, TRUE); 1441 1442 new_results_end = (query->results_end + query->result_size) % query->buffer->b.b.b.width0; 1443 1444 /* collect current results if query buffer is full */ 1445 if (new_results_end == query->results_start) { 1446 r600_query_result(ctx, query, TRUE); 1447 } 1448 1449 switch (query->type) { 1450 case PIPE_QUERY_OCCLUSION_COUNTER: 1451 case PIPE_QUERY_OCCLUSION_PREDICATE: 1452 results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); 1453 if (results) { 1454 results = (uint32_t*)((char*)results + query->results_end); 1455 memset(results, 0, query->result_size); 1456 1457 /* Set top bits for unused backends */ 1458 for (i = 0; i < ctx->max_db; i++) { 1459 if (!(ctx->backend_mask & (1<<i))) { 1460 results[(i * 4)+1] = 0x80000000; 1461 results[(i * 4)+3] = 0x80000000; 1462 } 1463 } 1464 ctx->ws->buffer_unmap(query->buffer->buf); 1465 } 1466 break; 1467 case PIPE_QUERY_TIME_ELAPSED: 1468 break; 1469 case PIPE_QUERY_PRIMITIVES_EMITTED: 1470 case PIPE_QUERY_PRIMITIVES_GENERATED: 1471 case PIPE_QUERY_SO_STATISTICS: 1472 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1473 results = ctx->ws->buffer_map(query->buffer->buf, ctx->cs, PIPE_TRANSFER_WRITE); 1474 results = (uint32_t*)((char*)results + query->results_end); 1475 memset(results, 0, query->result_size); 1476 ctx->ws->buffer_unmap(query->buffer->buf); 1477 break; 1478 default: 1479 assert(0); 1480 } 1481 1482 /* emit begin query */ 1483 va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); 1484 va += query->results_end; 1485 1486 switch (query->type) { 1487 case PIPE_QUERY_OCCLUSION_COUNTER: 1488 case PIPE_QUERY_OCCLUSION_PREDICATE: 1489 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 1490 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); 1491 cs->buf[cs->cdw++] = va; 1492 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; 1493 break; 1494 case PIPE_QUERY_PRIMITIVES_EMITTED: 1495 case PIPE_QUERY_PRIMITIVES_GENERATED: 1496 case PIPE_QUERY_SO_STATISTICS: 1497 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1498 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 1499 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); 1500 cs->buf[cs->cdw++] = query->results_end; 1501 cs->buf[cs->cdw++] = 0; 1502 break; 1503 case PIPE_QUERY_TIME_ELAPSED: 1504 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); 1505 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); 1506 cs->buf[cs->cdw++] = va; 1507 cs->buf[cs->cdw++] = (3 << 29) | ((va >> 32UL) & 0xFF); 1508 cs->buf[cs->cdw++] = 0; 1509 cs->buf[cs->cdw++] = 0; 1510 break; 1511 default: 1512 assert(0); 1513 } 1514 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1515 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); 1516 1517 ctx->num_cs_dw_queries_suspend += query->num_cs_dw; 1518} 1519 1520void r600_query_end(struct r600_context *ctx, struct r600_query *query) 1521{ 1522 struct radeon_winsys_cs *cs = ctx->cs; 1523 uint64_t va; 1524 1525 va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); 1526 /* emit end query */ 1527 switch (query->type) { 1528 case PIPE_QUERY_OCCLUSION_COUNTER: 1529 case PIPE_QUERY_OCCLUSION_PREDICATE: 1530 va += query->results_end + 8; 1531 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 1532 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); 1533 cs->buf[cs->cdw++] = va; 1534 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; 1535 break; 1536 case PIPE_QUERY_PRIMITIVES_EMITTED: 1537 case PIPE_QUERY_PRIMITIVES_GENERATED: 1538 case PIPE_QUERY_SO_STATISTICS: 1539 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1540 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 1541 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); 1542 cs->buf[cs->cdw++] = query->results_end + query->result_size/2; 1543 cs->buf[cs->cdw++] = 0; 1544 break; 1545 case PIPE_QUERY_TIME_ELAPSED: 1546 va += query->results_end + query->result_size/2; 1547 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); 1548 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); 1549 cs->buf[cs->cdw++] = va; 1550 cs->buf[cs->cdw++] = (3 << 29) | ((va >> 32UL) & 0xFF); 1551 cs->buf[cs->cdw++] = 0; 1552 cs->buf[cs->cdw++] = 0; 1553 break; 1554 default: 1555 assert(0); 1556 } 1557 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1558 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, RADEON_USAGE_WRITE); 1559 1560 query->results_end = (query->results_end + query->result_size) % query->buffer->b.b.b.width0; 1561 ctx->num_cs_dw_queries_suspend -= query->num_cs_dw; 1562} 1563 1564void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation, 1565 int flag_wait) 1566{ 1567 struct radeon_winsys_cs *cs = ctx->cs; 1568 uint64_t va; 1569 1570 if (operation == PREDICATION_OP_CLEAR) { 1571 r600_need_cs_space(ctx, 3, FALSE); 1572 1573 cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0); 1574 cs->buf[cs->cdw++] = 0; 1575 cs->buf[cs->cdw++] = PRED_OP(PREDICATION_OP_CLEAR); 1576 } else { 1577 unsigned results_base = query->results_start; 1578 unsigned count; 1579 uint32_t op; 1580 1581 /* find count of the query data blocks */ 1582 count = (query->buffer->b.b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.b.width0; 1583 count /= query->result_size; 1584 1585 r600_need_cs_space(ctx, 5 * count, TRUE); 1586 1587 op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE | 1588 (flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW); 1589 va = r600_resource_va(&ctx->screen->screen, (void*)query->buffer); 1590 1591 /* emit predicate packets for all data blocks */ 1592 while (results_base != query->results_end) { 1593 cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0); 1594 cs->buf[cs->cdw++] = (va + results_base) & 0xFFFFFFFFUL; 1595 cs->buf[cs->cdw++] = op | (((va + results_base) >> 32UL) & 0xFF); 1596 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1597 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, query->buffer, 1598 RADEON_USAGE_READ); 1599 results_base = (results_base + query->result_size) % query->buffer->b.b.b.width0; 1600 1601 /* set CONTINUE bit for all packets except the first */ 1602 op |= PREDICATION_CONTINUE; 1603 } 1604 } 1605} 1606 1607struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type) 1608{ 1609 struct r600_query *query; 1610 unsigned buffer_size = 4096; 1611 1612 query = CALLOC_STRUCT(r600_query); 1613 if (query == NULL) 1614 return NULL; 1615 1616 query->type = query_type; 1617 1618 switch (query_type) { 1619 case PIPE_QUERY_OCCLUSION_COUNTER: 1620 case PIPE_QUERY_OCCLUSION_PREDICATE: 1621 query->result_size = 16 * ctx->max_db; 1622 query->num_cs_dw = 6; 1623 break; 1624 case PIPE_QUERY_TIME_ELAPSED: 1625 query->result_size = 16; 1626 query->num_cs_dw = 8; 1627 break; 1628 case PIPE_QUERY_PRIMITIVES_EMITTED: 1629 case PIPE_QUERY_PRIMITIVES_GENERATED: 1630 case PIPE_QUERY_SO_STATISTICS: 1631 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1632 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */ 1633 query->result_size = 32; 1634 query->num_cs_dw = 6; 1635 break; 1636 default: 1637 assert(0); 1638 FREE(query); 1639 return NULL; 1640 } 1641 1642 /* adjust buffer size to simplify offsets wrapping math */ 1643 buffer_size -= buffer_size % query->result_size; 1644 1645 /* Queries are normally read by the CPU after 1646 * being written by the gpu, hence staging is probably a good 1647 * usage pattern. 1648 */ 1649 query->buffer = (struct r600_resource*) 1650 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STAGING, buffer_size); 1651 if (!query->buffer) { 1652 FREE(query); 1653 return NULL; 1654 } 1655 return query; 1656} 1657 1658void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query) 1659{ 1660 pipe_resource_reference((struct pipe_resource**)&query->buffer, NULL); 1661 free(query); 1662} 1663 1664boolean r600_context_query_result(struct r600_context *ctx, 1665 struct r600_query *query, 1666 boolean wait, void *vresult) 1667{ 1668 boolean *result_b = (boolean*)vresult; 1669 uint64_t *result_u64 = (uint64_t*)vresult; 1670 struct pipe_query_data_so_statistics *result_so = 1671 (struct pipe_query_data_so_statistics*)vresult; 1672 1673 if (!r600_query_result(ctx, query, wait)) 1674 return FALSE; 1675 1676 switch (query->type) { 1677 case PIPE_QUERY_OCCLUSION_COUNTER: 1678 case PIPE_QUERY_PRIMITIVES_EMITTED: 1679 case PIPE_QUERY_PRIMITIVES_GENERATED: 1680 *result_u64 = query->result.u64; 1681 break; 1682 case PIPE_QUERY_OCCLUSION_PREDICATE: 1683 case PIPE_QUERY_SO_OVERFLOW_PREDICATE: 1684 *result_b = query->result.b; 1685 break; 1686 case PIPE_QUERY_TIME_ELAPSED: 1687 *result_u64 = (1000000 * query->result.u64) / ctx->screen->info.r600_clock_crystal_freq; 1688 break; 1689 case PIPE_QUERY_SO_STATISTICS: 1690 *result_so = query->result.so; 1691 break; 1692 default: 1693 assert(0); 1694 } 1695 return TRUE; 1696} 1697 1698void r600_context_queries_suspend(struct r600_context *ctx) 1699{ 1700 struct r600_query *query; 1701 1702 LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { 1703 r600_query_end(ctx, query); 1704 } 1705 assert(ctx->num_cs_dw_queries_suspend == 0); 1706} 1707 1708void r600_context_queries_resume(struct r600_context *ctx) 1709{ 1710 struct r600_query *query; 1711 1712 assert(ctx->num_cs_dw_queries_suspend == 0); 1713 1714 LIST_FOR_EACH_ENTRY(query, &ctx->active_query_list, list) { 1715 r600_query_begin(ctx, query); 1716 } 1717} 1718 1719static void r600_flush_vgt_streamout(struct r600_context *ctx) 1720{ 1721 struct radeon_winsys_cs *cs = ctx->cs; 1722 1723 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0); 1724 cs->buf[cs->cdw++] = (R_008490_CP_STRMOUT_CNTL - R600_CONFIG_REG_OFFSET) >> 2; 1725 cs->buf[cs->cdw++] = 0; 1726 1727 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 1728 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0); 1729 1730 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0); 1731 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */ 1732 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */ 1733 cs->buf[cs->cdw++] = 0; 1734 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */ 1735 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */ 1736 cs->buf[cs->cdw++] = 4; /* poll interval */ 1737} 1738 1739static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit) 1740{ 1741 struct radeon_winsys_cs *cs = ctx->cs; 1742 1743 if (buffer_enable_bit) { 1744 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1745 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2; 1746 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(1); 1747 1748 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1749 cs->buf[cs->cdw++] = (R_028B20_VGT_STRMOUT_BUFFER_EN - R600_CONTEXT_REG_OFFSET) >> 2; 1750 cs->buf[cs->cdw++] = buffer_enable_bit; 1751 } else { 1752 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1753 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2; 1754 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(0); 1755 } 1756} 1757 1758void r600_context_streamout_begin(struct r600_context *ctx) 1759{ 1760 struct radeon_winsys_cs *cs = ctx->cs; 1761 struct r600_so_target **t = ctx->so_targets; 1762 unsigned *stride_in_dw = ctx->vs_shader->so.stride; 1763 unsigned buffer_en, i, update_flags = 0; 1764 uint64_t va; 1765 1766 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) | 1767 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) | 1768 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) | 1769 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0); 1770 1771 ctx->num_cs_dw_streamout_end = 1772 12 + /* flush_vgt_streamout */ 1773 util_bitcount(buffer_en) * 8 + 1774 3; 1775 1776 r600_need_cs_space(ctx, 1777 12 + /* flush_vgt_streamout */ 1778 6 + /* enables */ 1779 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + 1780 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + 1781 (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770 ? 2 : 0) + 1782 ctx->num_cs_dw_streamout_end, TRUE); 1783 1784 if (ctx->chip_class >= EVERGREEN) { 1785 evergreen_flush_vgt_streamout(ctx); 1786 evergreen_set_streamout_enable(ctx, buffer_en); 1787 } else { 1788 r600_flush_vgt_streamout(ctx); 1789 r600_set_streamout_enable(ctx, buffer_en); 1790 } 1791 1792 for (i = 0; i < ctx->num_so_targets; i++) { 1793 if (t[i]) { 1794 t[i]->stride_in_dw = stride_in_dw[i]; 1795 t[i]->so_index = i; 1796 va = r600_resource_va(&ctx->screen->screen, 1797 (void*)t[i]->b.buffer); 1798 1799 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i); 1800 1801 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0); 1802 cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 1803 16*i - R600_CONTEXT_REG_OFFSET) >> 2; 1804 cs->buf[cs->cdw++] = (t[i]->b.buffer_offset + 1805 t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */ 1806 cs->buf[cs->cdw++] = stride_in_dw[i]; /* VTX_STRIDE (in DW) */ 1807 cs->buf[cs->cdw++] = va >> 8; /* BUFFER_BASE */ 1808 1809 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1810 cs->buf[cs->cdw++] = 1811 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer), 1812 RADEON_USAGE_WRITE); 1813 1814 if (ctx->streamout_append_bitmask & (1 << i)) { 1815 va = r600_resource_va(&ctx->screen->screen, 1816 (void*)t[i]->filled_size); 1817 /* Append. */ 1818 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); 1819 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | 1820 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */ 1821 cs->buf[cs->cdw++] = 0; /* unused */ 1822 cs->buf[cs->cdw++] = 0; /* unused */ 1823 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */ 1824 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */ 1825 1826 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1827 cs->buf[cs->cdw++] = 1828 r600_context_bo_reloc(ctx, t[i]->filled_size, 1829 RADEON_USAGE_READ); 1830 } else { 1831 /* Start from the beginning. */ 1832 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); 1833 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | 1834 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */ 1835 cs->buf[cs->cdw++] = 0; /* unused */ 1836 cs->buf[cs->cdw++] = 0; /* unused */ 1837 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */ 1838 cs->buf[cs->cdw++] = 0; /* unused */ 1839 } 1840 } 1841 } 1842 1843 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) { 1844 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0); 1845 cs->buf[cs->cdw++] = update_flags; 1846 } 1847} 1848 1849void r600_context_streamout_end(struct r600_context *ctx) 1850{ 1851 struct radeon_winsys_cs *cs = ctx->cs; 1852 struct r600_so_target **t = ctx->so_targets; 1853 unsigned i, flush_flags = 0; 1854 uint64_t va; 1855 1856 if (ctx->chip_class >= EVERGREEN) { 1857 evergreen_flush_vgt_streamout(ctx); 1858 } else { 1859 r600_flush_vgt_streamout(ctx); 1860 } 1861 1862 for (i = 0; i < ctx->num_so_targets; i++) { 1863 if (t[i]) { 1864 va = r600_resource_va(&ctx->screen->screen, 1865 (void*)t[i]->filled_size); 1866 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); 1867 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | 1868 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) | 1869 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */ 1870 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */ 1871 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */ 1872 cs->buf[cs->cdw++] = 0; /* unused */ 1873 cs->buf[cs->cdw++] = 0; /* unused */ 1874 1875 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1876 cs->buf[cs->cdw++] = 1877 r600_context_bo_reloc(ctx, t[i]->filled_size, 1878 RADEON_USAGE_WRITE); 1879 1880 flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i; 1881 } 1882 } 1883 1884 if (ctx->chip_class >= EVERGREEN) { 1885 evergreen_set_streamout_enable(ctx, 0); 1886 } else { 1887 r600_set_streamout_enable(ctx, 0); 1888 } 1889 1890 if (ctx->chip_class < R700) { 1891 r600_atom_dirty(ctx, &ctx->atom_r6xx_flush_and_inv); 1892 } else { 1893 ctx->atom_surface_sync.flush_flags |= flush_flags; 1894 r600_atom_dirty(ctx, &ctx->atom_surface_sync.atom); 1895 } 1896 1897 ctx->num_cs_dw_streamout_end = 0; 1898 1899#if 0 1900 for (i = 0; i < ctx->num_so_targets; i++) { 1901 if (!t[i]) 1902 continue; 1903 1904 uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->buf, ctx->cs, RADEON_USAGE_READ); 1905 printf("FILLED_SIZE%i: %u\n", i, *ptr); 1906 ctx->ws->buffer_unmap(t[i]->filled_size->buf); 1907 } 1908#endif 1909} 1910 1911void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t) 1912{ 1913 struct radeon_winsys_cs *cs = ctx->cs; 1914 uint64_t va = r600_resource_va(&ctx->screen->screen, 1915 (void*)t->filled_size); 1916 1917 r600_need_cs_space(ctx, 14 + 21, TRUE); 1918 1919 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1920 cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - R600_CONTEXT_REG_OFFSET) >> 2; 1921 cs->buf[cs->cdw++] = 0; 1922 1923 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1924 cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - R600_CONTEXT_REG_OFFSET) >> 2; 1925 cs->buf[cs->cdw++] = t->stride_in_dw; 1926 1927 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0); 1928 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG; 1929 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */ 1930 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */ 1931 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */ 1932 cs->buf[cs->cdw++] = 0; /* unused */ 1933 1934 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1935 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ); 1936} 1937