r600_hw_context.c revision bb07e251318d1b224fb78fc0bd4200216c42a5cf
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#include "r600_hw_context_priv.h" 27#include "r600d.h" 28#include "util/u_memory.h" 29#include <errno.h> 30 31/* Get backends mask */ 32void r600_get_backend_mask(struct r600_context *ctx) 33{ 34 struct radeon_winsys_cs *cs = ctx->cs; 35 struct r600_resource *buffer; 36 uint32_t *results; 37 unsigned num_backends = ctx->screen->info.r600_num_backends; 38 unsigned i, mask = 0; 39 uint64_t va; 40 41 /* if backend_map query is supported by the kernel */ 42 if (ctx->screen->info.r600_backend_map_valid) { 43 unsigned num_tile_pipes = ctx->screen->info.r600_num_tile_pipes; 44 unsigned backend_map = ctx->screen->info.r600_backend_map; 45 unsigned item_width, item_mask; 46 47 if (ctx->chip_class >= EVERGREEN) { 48 item_width = 4; 49 item_mask = 0x7; 50 } else { 51 item_width = 2; 52 item_mask = 0x3; 53 } 54 55 while(num_tile_pipes--) { 56 i = backend_map & item_mask; 57 mask |= (1<<i); 58 backend_map >>= item_width; 59 } 60 if (mask != 0) { 61 ctx->backend_mask = mask; 62 return; 63 } 64 } 65 66 /* otherwise backup path for older kernels */ 67 68 /* create buffer for event data */ 69 buffer = (struct r600_resource*) 70 pipe_buffer_create(&ctx->screen->screen, PIPE_BIND_CUSTOM, 71 PIPE_USAGE_STAGING, ctx->max_db*16); 72 if (!buffer) 73 goto err; 74 75 va = r600_resource_va(&ctx->screen->screen, (void*)buffer); 76 77 /* initialize buffer with zeroes */ 78 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_WRITE); 79 if (results) { 80 memset(results, 0, ctx->max_db * 4 * 4); 81 ctx->ws->buffer_unmap(buffer->cs_buf); 82 83 /* emit EVENT_WRITE for ZPASS_DONE */ 84 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); 85 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1); 86 cs->buf[cs->cdw++] = va; 87 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; 88 89 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 90 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, buffer, RADEON_USAGE_WRITE); 91 92 /* analyze results */ 93 results = ctx->ws->buffer_map(buffer->cs_buf, ctx->cs, PIPE_TRANSFER_READ); 94 if (results) { 95 for(i = 0; i < ctx->max_db; i++) { 96 /* at least highest bit will be set if backend is used */ 97 if (results[i*4 + 1]) 98 mask |= (1<<i); 99 } 100 ctx->ws->buffer_unmap(buffer->cs_buf); 101 } 102 } 103 104 pipe_resource_reference((struct pipe_resource**)&buffer, NULL); 105 106 if (mask != 0) { 107 ctx->backend_mask = mask; 108 return; 109 } 110 111err: 112 /* fallback to old method - set num_backends lower bits to 1 */ 113 ctx->backend_mask = (~((uint32_t)0))>>(32-num_backends); 114 return; 115} 116 117void r600_context_ps_partial_flush(struct r600_context *ctx) 118{ 119 struct radeon_winsys_cs *cs = ctx->cs; 120 121 if (!(ctx->flags & R600_CONTEXT_DRAW_PENDING)) 122 return; 123 124 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 125 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); 126 127 ctx->flags &= ~R600_CONTEXT_DRAW_PENDING; 128} 129 130static void r600_init_block(struct r600_context *ctx, 131 struct r600_block *block, 132 const struct r600_reg *reg, int index, int nreg, 133 unsigned opcode, unsigned offset_base) 134{ 135 int i = index; 136 int j, n = nreg; 137 138 /* initialize block */ 139 if (opcode == PKT3_SET_RESOURCE) { 140 block->flags = BLOCK_FLAG_RESOURCE; 141 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; /* dirty all blocks at start */ 142 } else { 143 block->flags = 0; 144 block->status |= R600_BLOCK_STATUS_DIRTY; /* dirty all blocks at start */ 145 } 146 block->start_offset = reg[i].offset; 147 block->pm4[block->pm4_ndwords++] = PKT3(opcode, n, 0); 148 block->pm4[block->pm4_ndwords++] = (block->start_offset - offset_base) >> 2; 149 block->reg = &block->pm4[block->pm4_ndwords]; 150 block->pm4_ndwords += n; 151 block->nreg = n; 152 block->nreg_dirty = n; 153 LIST_INITHEAD(&block->list); 154 LIST_INITHEAD(&block->enable_list); 155 156 for (j = 0; j < n; j++) { 157 if (reg[i+j].flags & REG_FLAG_DIRTY_ALWAYS) { 158 block->flags |= REG_FLAG_DIRTY_ALWAYS; 159 } 160 if (reg[i+j].flags & REG_FLAG_ENABLE_ALWAYS) { 161 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 162 block->status |= R600_BLOCK_STATUS_ENABLED; 163 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 164 LIST_ADDTAIL(&block->list,&ctx->dirty); 165 } 166 } 167 if (reg[i+j].flags & REG_FLAG_FLUSH_CHANGE) { 168 block->flags |= REG_FLAG_FLUSH_CHANGE; 169 } 170 171 if (reg[i+j].flags & REG_FLAG_NEED_BO) { 172 block->nbo++; 173 assert(block->nbo < R600_BLOCK_MAX_BO); 174 block->pm4_bo_index[j] = block->nbo; 175 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_NOP, 0, 0); 176 block->pm4[block->pm4_ndwords++] = 0x00000000; 177 block->reloc[block->nbo].bo_pm4_index = block->pm4_ndwords - 1; 178 } 179 if ((ctx->family > CHIP_R600) && 180 (ctx->family < CHIP_RV770) && reg[i+j].flags & REG_FLAG_RV6XX_SBU) { 181 block->pm4[block->pm4_ndwords++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0); 182 block->pm4[block->pm4_ndwords++] = reg[i+j].sbu_flags; 183 } 184 } 185 /* check that we stay in limit */ 186 assert(block->pm4_ndwords < R600_BLOCK_MAX_REG); 187} 188 189int r600_context_add_block(struct r600_context *ctx, const struct r600_reg *reg, unsigned nreg, 190 unsigned opcode, unsigned offset_base) 191{ 192 struct r600_block *block; 193 struct r600_range *range; 194 int offset; 195 196 for (unsigned i = 0, n = 0; i < nreg; i += n) { 197 /* ignore new block balise */ 198 if (reg[i].offset == GROUP_FORCE_NEW_BLOCK) { 199 n = 1; 200 continue; 201 } 202 203 /* ignore regs not on R600 on R600 */ 204 if ((reg[i].flags & REG_FLAG_NOT_R600) && ctx->family == CHIP_R600) { 205 n = 1; 206 continue; 207 } 208 209 /* register that need relocation are in their own group */ 210 /* find number of consecutive registers */ 211 n = 0; 212 offset = reg[i].offset; 213 while (reg[i + n].offset == offset) { 214 n++; 215 offset += 4; 216 if ((n + i) >= nreg) 217 break; 218 if (n >= (R600_BLOCK_MAX_REG - 2)) 219 break; 220 } 221 222 /* allocate new block */ 223 block = calloc(1, sizeof(struct r600_block)); 224 if (block == NULL) { 225 return -ENOMEM; 226 } 227 ctx->nblocks++; 228 for (int j = 0; j < n; j++) { 229 range = &ctx->range[CTX_RANGE_ID(reg[i + j].offset)]; 230 /* create block table if it doesn't exist */ 231 if (!range->blocks) 232 range->blocks = calloc(1 << HASH_SHIFT, sizeof(void *)); 233 if (!range->blocks) 234 return -1; 235 236 range->blocks[CTX_BLOCK_ID(reg[i + j].offset)] = block; 237 } 238 239 r600_init_block(ctx, block, reg, i, n, opcode, offset_base); 240 241 } 242 return 0; 243} 244 245/* R600/R700 configuration */ 246static const struct r600_reg r600_config_reg_list[] = { 247 {R_008958_VGT_PRIMITIVE_TYPE, 0, 0}, 248 {R_008C04_SQ_GPR_RESOURCE_MGMT_1, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, 249 {R_009508_TA_CNTL_AUX, REG_FLAG_ENABLE_ALWAYS | REG_FLAG_FLUSH_CHANGE, 0}, 250}; 251 252static const struct r600_reg r600_ctl_const_list[] = { 253 {R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0}, 254}; 255 256static const struct r600_reg r600_context_reg_list[] = { 257 {R_028A4C_PA_SC_MODE_CNTL, 0, 0}, 258 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 259 {R_028040_CB_COLOR0_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(0)}, 260 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 261 {R_0280A0_CB_COLOR0_INFO, REG_FLAG_NEED_BO, 0}, 262 {R_028060_CB_COLOR0_SIZE, 0, 0}, 263 {R_028080_CB_COLOR0_VIEW, 0, 0}, 264 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 265 {R_0280E0_CB_COLOR0_FRAG, REG_FLAG_NEED_BO, 0}, 266 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 267 {R_0280C0_CB_COLOR0_TILE, REG_FLAG_NEED_BO, 0}, 268 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 269 {R_028044_CB_COLOR1_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(1)}, 270 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 271 {R_0280A4_CB_COLOR1_INFO, REG_FLAG_NEED_BO, 0}, 272 {R_028064_CB_COLOR1_SIZE, 0, 0}, 273 {R_028084_CB_COLOR1_VIEW, 0, 0}, 274 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 275 {R_0280E4_CB_COLOR1_FRAG, REG_FLAG_NEED_BO, 0}, 276 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 277 {R_0280C4_CB_COLOR1_TILE, REG_FLAG_NEED_BO, 0}, 278 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 279 {R_028048_CB_COLOR2_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(2)}, 280 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 281 {R_0280A8_CB_COLOR2_INFO, REG_FLAG_NEED_BO, 0}, 282 {R_028068_CB_COLOR2_SIZE, 0, 0}, 283 {R_028088_CB_COLOR2_VIEW, 0, 0}, 284 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 285 {R_0280E8_CB_COLOR2_FRAG, REG_FLAG_NEED_BO, 0}, 286 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 287 {R_0280C8_CB_COLOR2_TILE, REG_FLAG_NEED_BO, 0}, 288 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 289 {R_02804C_CB_COLOR3_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(3)}, 290 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 291 {R_0280AC_CB_COLOR3_INFO, REG_FLAG_NEED_BO, 0}, 292 {R_02806C_CB_COLOR3_SIZE, 0, 0}, 293 {R_02808C_CB_COLOR3_VIEW, 0, 0}, 294 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 295 {R_0280EC_CB_COLOR3_FRAG, REG_FLAG_NEED_BO, 0}, 296 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 297 {R_0280CC_CB_COLOR3_TILE, REG_FLAG_NEED_BO, 0}, 298 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 299 {R_028050_CB_COLOR4_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(4)}, 300 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 301 {R_0280B0_CB_COLOR4_INFO, REG_FLAG_NEED_BO, 0}, 302 {R_028070_CB_COLOR4_SIZE, 0, 0}, 303 {R_028090_CB_COLOR4_VIEW, 0, 0}, 304 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 305 {R_0280F0_CB_COLOR4_FRAG, REG_FLAG_NEED_BO, 0}, 306 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 307 {R_0280D0_CB_COLOR4_TILE, REG_FLAG_NEED_BO, 0}, 308 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 309 {R_028054_CB_COLOR5_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(5)}, 310 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 311 {R_0280B4_CB_COLOR5_INFO, REG_FLAG_NEED_BO, 0}, 312 {R_028074_CB_COLOR5_SIZE, 0, 0}, 313 {R_028094_CB_COLOR5_VIEW, 0, 0}, 314 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 315 {R_0280F4_CB_COLOR5_FRAG, REG_FLAG_NEED_BO, 0}, 316 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 317 {R_0280D4_CB_COLOR5_TILE, REG_FLAG_NEED_BO, 0}, 318 {R_028058_CB_COLOR6_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(6)}, 319 {R_0280B8_CB_COLOR6_INFO, REG_FLAG_NEED_BO, 0}, 320 {R_028078_CB_COLOR6_SIZE, 0, 0}, 321 {R_028098_CB_COLOR6_VIEW, 0, 0}, 322 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 323 {R_0280F8_CB_COLOR6_FRAG, REG_FLAG_NEED_BO, 0}, 324 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 325 {R_0280D8_CB_COLOR6_TILE, REG_FLAG_NEED_BO, 0}, 326 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 327 {R_02805C_CB_COLOR7_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_COLOR(7)}, 328 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 329 {R_0280BC_CB_COLOR7_INFO, REG_FLAG_NEED_BO, 0}, 330 {R_02807C_CB_COLOR7_SIZE, 0, 0}, 331 {R_02809C_CB_COLOR7_VIEW, 0, 0}, 332 {R_0280FC_CB_COLOR7_FRAG, REG_FLAG_NEED_BO, 0}, 333 {R_0280DC_CB_COLOR7_TILE, REG_FLAG_NEED_BO, 0}, 334 {R_028120_CB_CLEAR_RED, 0, 0}, 335 {R_028124_CB_CLEAR_GREEN, 0, 0}, 336 {R_028128_CB_CLEAR_BLUE, 0, 0}, 337 {R_02812C_CB_CLEAR_ALPHA, 0, 0}, 338 {R_02823C_CB_SHADER_MASK, 0, 0}, 339 {R_028238_CB_TARGET_MASK, 0, 0}, 340 {R_028410_SX_ALPHA_TEST_CONTROL, 0, 0}, 341 {R_028414_CB_BLEND_RED, 0, 0}, 342 {R_028418_CB_BLEND_GREEN, 0, 0}, 343 {R_02841C_CB_BLEND_BLUE, 0, 0}, 344 {R_028420_CB_BLEND_ALPHA, 0, 0}, 345 {R_028424_CB_FOG_RED, 0, 0}, 346 {R_028428_CB_FOG_GREEN, 0, 0}, 347 {R_02842C_CB_FOG_BLUE, 0, 0}, 348 {R_028430_DB_STENCILREFMASK, 0, 0}, 349 {R_028434_DB_STENCILREFMASK_BF, 0, 0}, 350 {R_028438_SX_ALPHA_REF, 0, 0}, 351 {R_028780_CB_BLEND0_CONTROL, REG_FLAG_NOT_R600, 0}, 352 {R_028784_CB_BLEND1_CONTROL, REG_FLAG_NOT_R600, 0}, 353 {R_028788_CB_BLEND2_CONTROL, REG_FLAG_NOT_R600, 0}, 354 {R_02878C_CB_BLEND3_CONTROL, REG_FLAG_NOT_R600, 0}, 355 {R_028790_CB_BLEND4_CONTROL, REG_FLAG_NOT_R600, 0}, 356 {R_028794_CB_BLEND5_CONTROL, REG_FLAG_NOT_R600, 0}, 357 {R_028798_CB_BLEND6_CONTROL, REG_FLAG_NOT_R600, 0}, 358 {R_02879C_CB_BLEND7_CONTROL, REG_FLAG_NOT_R600, 0}, 359 {R_0287A0_CB_SHADER_CONTROL, 0, 0}, 360 {R_028800_DB_DEPTH_CONTROL, 0, 0}, 361 {R_028804_CB_BLEND_CONTROL, 0, 0}, 362 {R_028808_CB_COLOR_CONTROL, 0, 0}, 363 {R_02880C_DB_SHADER_CONTROL, 0, 0}, 364 {R_02800C_DB_DEPTH_BASE, REG_FLAG_NEED_BO|REG_FLAG_RV6XX_SBU, SURFACE_BASE_UPDATE_DEPTH}, 365 {R_028000_DB_DEPTH_SIZE, 0, 0}, 366 {R_028004_DB_DEPTH_VIEW, 0, 0}, 367 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 368 {R_028010_DB_DEPTH_INFO, REG_FLAG_NEED_BO, 0}, 369 {R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0, 0}, 370 {R_028D24_DB_HTILE_SURFACE, 0, 0}, 371 {R_028D34_DB_PREFETCH_LIMIT, 0, 0}, 372 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0}, 373 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0}, 374 {R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0}, 375 {R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0}, 376 {R_02843C_PA_CL_VPORT_XSCALE_0, 0, 0}, 377 {R_028440_PA_CL_VPORT_XOFFSET_0, 0, 0}, 378 {R_028444_PA_CL_VPORT_YSCALE_0, 0, 0}, 379 {R_028448_PA_CL_VPORT_YOFFSET_0, 0, 0}, 380 {R_02844C_PA_CL_VPORT_ZSCALE_0, 0, 0}, 381 {R_028450_PA_CL_VPORT_ZOFFSET_0, 0, 0}, 382 {R_0286D4_SPI_INTERP_CONTROL_0, 0, 0}, 383 {R_028810_PA_CL_CLIP_CNTL, 0, 0}, 384 {R_028814_PA_SU_SC_MODE_CNTL, 0, 0}, 385 {R_02881C_PA_CL_VS_OUT_CNTL, 0, 0}, 386 {R_028A00_PA_SU_POINT_SIZE, 0, 0}, 387 {R_028A04_PA_SU_POINT_MINMAX, 0, 0}, 388 {R_028A08_PA_SU_LINE_CNTL, 0, 0}, 389 {R_028A0C_PA_SC_LINE_STIPPLE, 0, 0}, 390 {R_028C08_PA_SU_VTX_CNTL, 0, 0}, 391 {R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 0, 0}, 392 {R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0, 0}, 393 {R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 0, 0}, 394 {R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 0, 0}, 395 {R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 0, 0}, 396 {R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 0, 0}, 397 {R_028E20_PA_CL_UCP0_X, 0, 0}, 398 {R_028E24_PA_CL_UCP0_Y, 0, 0}, 399 {R_028E28_PA_CL_UCP0_Z, 0, 0}, 400 {R_028E2C_PA_CL_UCP0_W, 0, 0}, 401 {R_028E30_PA_CL_UCP1_X, 0, 0}, 402 {R_028E34_PA_CL_UCP1_Y, 0, 0}, 403 {R_028E38_PA_CL_UCP1_Z, 0, 0}, 404 {R_028E3C_PA_CL_UCP1_W, 0, 0}, 405 {R_028E40_PA_CL_UCP2_X, 0, 0}, 406 {R_028E44_PA_CL_UCP2_Y, 0, 0}, 407 {R_028E48_PA_CL_UCP2_Z, 0, 0}, 408 {R_028E4C_PA_CL_UCP2_W, 0, 0}, 409 {R_028E50_PA_CL_UCP3_X, 0, 0}, 410 {R_028E54_PA_CL_UCP3_Y, 0, 0}, 411 {R_028E58_PA_CL_UCP3_Z, 0, 0}, 412 {R_028E5C_PA_CL_UCP3_W, 0, 0}, 413 {R_028E60_PA_CL_UCP4_X, 0, 0}, 414 {R_028E64_PA_CL_UCP4_Y, 0, 0}, 415 {R_028E68_PA_CL_UCP4_Z, 0, 0}, 416 {R_028E6C_PA_CL_UCP4_W, 0, 0}, 417 {R_028E70_PA_CL_UCP5_X, 0, 0}, 418 {R_028E74_PA_CL_UCP5_Y, 0, 0}, 419 {R_028E78_PA_CL_UCP5_Z, 0, 0}, 420 {R_028E7C_PA_CL_UCP5_W, 0, 0}, 421 {R_028350_SX_MISC, 0, 0}, 422 {R_028380_SQ_VTX_SEMANTIC_0, 0, 0}, 423 {R_028384_SQ_VTX_SEMANTIC_1, 0, 0}, 424 {R_028388_SQ_VTX_SEMANTIC_2, 0, 0}, 425 {R_02838C_SQ_VTX_SEMANTIC_3, 0, 0}, 426 {R_028390_SQ_VTX_SEMANTIC_4, 0, 0}, 427 {R_028394_SQ_VTX_SEMANTIC_5, 0, 0}, 428 {R_028398_SQ_VTX_SEMANTIC_6, 0, 0}, 429 {R_02839C_SQ_VTX_SEMANTIC_7, 0, 0}, 430 {R_0283A0_SQ_VTX_SEMANTIC_8, 0, 0}, 431 {R_0283A4_SQ_VTX_SEMANTIC_9, 0, 0}, 432 {R_0283A8_SQ_VTX_SEMANTIC_10, 0, 0}, 433 {R_0283AC_SQ_VTX_SEMANTIC_11, 0, 0}, 434 {R_0283B0_SQ_VTX_SEMANTIC_12, 0, 0}, 435 {R_0283B4_SQ_VTX_SEMANTIC_13, 0, 0}, 436 {R_0283B8_SQ_VTX_SEMANTIC_14, 0, 0}, 437 {R_0283BC_SQ_VTX_SEMANTIC_15, 0, 0}, 438 {R_0283C0_SQ_VTX_SEMANTIC_16, 0, 0}, 439 {R_0283C4_SQ_VTX_SEMANTIC_17, 0, 0}, 440 {R_0283C8_SQ_VTX_SEMANTIC_18, 0, 0}, 441 {R_0283CC_SQ_VTX_SEMANTIC_19, 0, 0}, 442 {R_0283D0_SQ_VTX_SEMANTIC_20, 0, 0}, 443 {R_0283D4_SQ_VTX_SEMANTIC_21, 0, 0}, 444 {R_0283D8_SQ_VTX_SEMANTIC_22, 0, 0}, 445 {R_0283DC_SQ_VTX_SEMANTIC_23, 0, 0}, 446 {R_0283E0_SQ_VTX_SEMANTIC_24, 0, 0}, 447 {R_0283E4_SQ_VTX_SEMANTIC_25, 0, 0}, 448 {R_0283E8_SQ_VTX_SEMANTIC_26, 0, 0}, 449 {R_0283EC_SQ_VTX_SEMANTIC_27, 0, 0}, 450 {R_0283F0_SQ_VTX_SEMANTIC_28, 0, 0}, 451 {R_0283F4_SQ_VTX_SEMANTIC_29, 0, 0}, 452 {R_0283F8_SQ_VTX_SEMANTIC_30, 0, 0}, 453 {R_0283FC_SQ_VTX_SEMANTIC_31, 0, 0}, 454 {R_028614_SPI_VS_OUT_ID_0, 0, 0}, 455 {R_028618_SPI_VS_OUT_ID_1, 0, 0}, 456 {R_02861C_SPI_VS_OUT_ID_2, 0, 0}, 457 {R_028620_SPI_VS_OUT_ID_3, 0, 0}, 458 {R_028624_SPI_VS_OUT_ID_4, 0, 0}, 459 {R_028628_SPI_VS_OUT_ID_5, 0, 0}, 460 {R_02862C_SPI_VS_OUT_ID_6, 0, 0}, 461 {R_028630_SPI_VS_OUT_ID_7, 0, 0}, 462 {R_028634_SPI_VS_OUT_ID_8, 0, 0}, 463 {R_028638_SPI_VS_OUT_ID_9, 0, 0}, 464 {R_0286C4_SPI_VS_OUT_CONFIG, 0, 0}, 465 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 466 {R_028858_SQ_PGM_START_VS, REG_FLAG_NEED_BO, 0}, 467 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 468 {R_028868_SQ_PGM_RESOURCES_VS, 0, 0}, 469 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 470 {R_028894_SQ_PGM_START_FS, REG_FLAG_NEED_BO, 0}, 471 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 472 {R_0288A4_SQ_PGM_RESOURCES_FS, 0, 0}, 473 {R_0288DC_SQ_PGM_CF_OFFSET_FS, 0, 0}, 474 {R_028644_SPI_PS_INPUT_CNTL_0, 0, 0}, 475 {R_028648_SPI_PS_INPUT_CNTL_1, 0, 0}, 476 {R_02864C_SPI_PS_INPUT_CNTL_2, 0, 0}, 477 {R_028650_SPI_PS_INPUT_CNTL_3, 0, 0}, 478 {R_028654_SPI_PS_INPUT_CNTL_4, 0, 0}, 479 {R_028658_SPI_PS_INPUT_CNTL_5, 0, 0}, 480 {R_02865C_SPI_PS_INPUT_CNTL_6, 0, 0}, 481 {R_028660_SPI_PS_INPUT_CNTL_7, 0, 0}, 482 {R_028664_SPI_PS_INPUT_CNTL_8, 0, 0}, 483 {R_028668_SPI_PS_INPUT_CNTL_9, 0, 0}, 484 {R_02866C_SPI_PS_INPUT_CNTL_10, 0, 0}, 485 {R_028670_SPI_PS_INPUT_CNTL_11, 0, 0}, 486 {R_028674_SPI_PS_INPUT_CNTL_12, 0, 0}, 487 {R_028678_SPI_PS_INPUT_CNTL_13, 0, 0}, 488 {R_02867C_SPI_PS_INPUT_CNTL_14, 0, 0}, 489 {R_028680_SPI_PS_INPUT_CNTL_15, 0, 0}, 490 {R_028684_SPI_PS_INPUT_CNTL_16, 0, 0}, 491 {R_028688_SPI_PS_INPUT_CNTL_17, 0, 0}, 492 {R_02868C_SPI_PS_INPUT_CNTL_18, 0, 0}, 493 {R_028690_SPI_PS_INPUT_CNTL_19, 0, 0}, 494 {R_028694_SPI_PS_INPUT_CNTL_20, 0, 0}, 495 {R_028698_SPI_PS_INPUT_CNTL_21, 0, 0}, 496 {R_02869C_SPI_PS_INPUT_CNTL_22, 0, 0}, 497 {R_0286A0_SPI_PS_INPUT_CNTL_23, 0, 0}, 498 {R_0286A4_SPI_PS_INPUT_CNTL_24, 0, 0}, 499 {R_0286A8_SPI_PS_INPUT_CNTL_25, 0, 0}, 500 {R_0286AC_SPI_PS_INPUT_CNTL_26, 0, 0}, 501 {R_0286B0_SPI_PS_INPUT_CNTL_27, 0, 0}, 502 {R_0286B4_SPI_PS_INPUT_CNTL_28, 0, 0}, 503 {R_0286B8_SPI_PS_INPUT_CNTL_29, 0, 0}, 504 {R_0286BC_SPI_PS_INPUT_CNTL_30, 0, 0}, 505 {R_0286C0_SPI_PS_INPUT_CNTL_31, 0, 0}, 506 {R_0286CC_SPI_PS_IN_CONTROL_0, 0, 0}, 507 {R_0286D0_SPI_PS_IN_CONTROL_1, 0, 0}, 508 {R_0286D8_SPI_INPUT_Z, 0, 0}, 509 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 510 {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0}, 511 {GROUP_FORCE_NEW_BLOCK, 0, 0}, 512 {R_028850_SQ_PGM_RESOURCES_PS, 0, 0}, 513 {R_028854_SQ_PGM_EXPORTS_PS, 0, 0}, 514 {R_028408_VGT_INDX_OFFSET, 0, 0}, 515 {R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0, 0}, 516 {R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0, 0}, 517}; 518 519/* SHADER RESOURCE R600/R700 */ 520int r600_resource_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride, struct r600_reg *reg, int nreg, unsigned offset_base) 521{ 522 int i; 523 struct r600_block *block; 524 range->blocks = calloc(nblocks, sizeof(struct r600_block *)); 525 if (range->blocks == NULL) 526 return -ENOMEM; 527 528 reg[0].offset += offset; 529 for (i = 0; i < nblocks; i++) { 530 block = calloc(1, sizeof(struct r600_block)); 531 if (block == NULL) { 532 return -ENOMEM; 533 } 534 ctx->nblocks++; 535 range->blocks[i] = block; 536 r600_init_block(ctx, block, reg, 0, nreg, PKT3_SET_RESOURCE, offset_base); 537 538 reg[0].offset += stride; 539 } 540 return 0; 541} 542 543 544static int r600_resource_range_init(struct r600_context *ctx, struct r600_range *range, unsigned offset, unsigned nblocks, unsigned stride) 545{ 546 struct r600_reg r600_shader_resource[] = { 547 {R_038000_RESOURCE0_WORD0, REG_FLAG_NEED_BO, 0}, 548 {R_038004_RESOURCE0_WORD1, REG_FLAG_NEED_BO, 0}, 549 {R_038008_RESOURCE0_WORD2, 0, 0}, 550 {R_03800C_RESOURCE0_WORD3, 0, 0}, 551 {R_038010_RESOURCE0_WORD4, 0, 0}, 552 {R_038014_RESOURCE0_WORD5, 0, 0}, 553 {R_038018_RESOURCE0_WORD6, 0, 0}, 554 }; 555 unsigned nreg = Elements(r600_shader_resource); 556 557 return r600_resource_init(ctx, range, offset, nblocks, stride, r600_shader_resource, nreg, R600_RESOURCE_OFFSET); 558} 559 560/* SHADER SAMPLER R600/R700/EG/CM */ 561int r600_state_sampler_init(struct r600_context *ctx, uint32_t offset) 562{ 563 struct r600_reg r600_shader_sampler[] = { 564 {R_03C000_SQ_TEX_SAMPLER_WORD0_0, 0, 0}, 565 {R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0}, 566 {R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0}, 567 }; 568 unsigned nreg = Elements(r600_shader_sampler); 569 570 for (int i = 0; i < nreg; i++) { 571 r600_shader_sampler[i].offset += offset; 572 } 573 return r600_context_add_block(ctx, r600_shader_sampler, nreg, PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET); 574} 575 576/* SHADER SAMPLER BORDER R600/R700 */ 577static int r600_state_sampler_border_init(struct r600_context *ctx, uint32_t offset) 578{ 579 struct r600_reg r600_shader_sampler_border[] = { 580 {R_00A400_TD_PS_SAMPLER0_BORDER_RED, 0, 0}, 581 {R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0}, 582 {R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0}, 583 {R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0}, 584 }; 585 unsigned nreg = Elements(r600_shader_sampler_border); 586 587 for (int i = 0; i < nreg; i++) { 588 r600_shader_sampler_border[i].offset += offset; 589 } 590 return r600_context_add_block(ctx, r600_shader_sampler_border, nreg, PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); 591} 592 593static int r600_loop_const_init(struct r600_context *ctx, uint32_t offset) 594{ 595 unsigned nreg = 32; 596 struct r600_reg r600_loop_consts[32]; 597 int i; 598 599 for (i = 0; i < nreg; i++) { 600 r600_loop_consts[i].offset = R600_LOOP_CONST_OFFSET + ((offset + i) * 4); 601 r600_loop_consts[i].flags = REG_FLAG_DIRTY_ALWAYS; 602 r600_loop_consts[i].sbu_flags = 0; 603 } 604 return r600_context_add_block(ctx, r600_loop_consts, nreg, PKT3_SET_LOOP_CONST, R600_LOOP_CONST_OFFSET); 605} 606 607static void r600_free_resource_range(struct r600_context *ctx, struct r600_range *range, int nblocks) 608{ 609 struct r600_block *block; 610 int i; 611 612 if (!range->blocks) { 613 return; /* nothing to do */ 614 } 615 616 for (i = 0; i < nblocks; i++) { 617 block = range->blocks[i]; 618 if (block) { 619 for (int k = 1; k <= block->nbo; k++) 620 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL); 621 free(block); 622 } 623 } 624 free(range->blocks); 625} 626 627/* initialize */ 628void r600_context_fini(struct r600_context *ctx) 629{ 630 struct r600_block *block; 631 struct r600_range *range; 632 633 if (ctx->range) { 634 for (int i = 0; i < NUM_RANGES; i++) { 635 if (!ctx->range[i].blocks) 636 continue; 637 for (int j = 0; j < (1 << HASH_SHIFT); j++) { 638 block = ctx->range[i].blocks[j]; 639 if (block) { 640 for (int k = 0, offset = block->start_offset; k < block->nreg; k++, offset += 4) { 641 range = &ctx->range[CTX_RANGE_ID(offset)]; 642 range->blocks[CTX_BLOCK_ID(offset)] = NULL; 643 } 644 for (int k = 1; k <= block->nbo; k++) { 645 pipe_resource_reference((struct pipe_resource**)&block->reloc[k].bo, NULL); 646 } 647 free(block); 648 } 649 } 650 free(ctx->range[i].blocks); 651 } 652 } 653 r600_free_resource_range(ctx, &ctx->ps_resources, ctx->num_ps_resources); 654 r600_free_resource_range(ctx, &ctx->vs_resources, ctx->num_vs_resources); 655 free(ctx->blocks); 656} 657 658static void r600_add_resource_block(struct r600_context *ctx, struct r600_range *range, int num_blocks, int *index) 659{ 660 int c = *index; 661 for (int j = 0; j < num_blocks; j++) { 662 if (!range->blocks[j]) 663 continue; 664 665 ctx->blocks[c++] = range->blocks[j]; 666 } 667 *index = c; 668} 669 670int r600_setup_block_table(struct r600_context *ctx) 671{ 672 /* setup block table */ 673 int c = 0; 674 ctx->blocks = calloc(ctx->nblocks, sizeof(void*)); 675 if (!ctx->blocks) 676 return -ENOMEM; 677 for (int i = 0; i < NUM_RANGES; i++) { 678 if (!ctx->range[i].blocks) 679 continue; 680 for (int j = 0, add; j < (1 << HASH_SHIFT); j++) { 681 if (!ctx->range[i].blocks[j]) 682 continue; 683 684 add = 1; 685 for (int k = 0; k < c; k++) { 686 if (ctx->blocks[k] == ctx->range[i].blocks[j]) { 687 add = 0; 688 break; 689 } 690 } 691 if (add) { 692 assert(c < ctx->nblocks); 693 ctx->blocks[c++] = ctx->range[i].blocks[j]; 694 j += (ctx->range[i].blocks[j]->nreg) - 1; 695 } 696 } 697 } 698 699 r600_add_resource_block(ctx, &ctx->ps_resources, ctx->num_ps_resources, &c); 700 r600_add_resource_block(ctx, &ctx->vs_resources, ctx->num_vs_resources, &c); 701 return 0; 702} 703 704int r600_context_init(struct r600_context *ctx) 705{ 706 int r; 707 708 /* add blocks */ 709 r = r600_context_add_block(ctx, r600_config_reg_list, 710 Elements(r600_config_reg_list), PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET); 711 if (r) 712 goto out_err; 713 r = r600_context_add_block(ctx, r600_context_reg_list, 714 Elements(r600_context_reg_list), PKT3_SET_CONTEXT_REG, R600_CONTEXT_REG_OFFSET); 715 if (r) 716 goto out_err; 717 r = r600_context_add_block(ctx, r600_ctl_const_list, 718 Elements(r600_ctl_const_list), PKT3_SET_CTL_CONST, R600_CTL_CONST_OFFSET); 719 if (r) 720 goto out_err; 721 722 /* PS SAMPLER BORDER */ 723 for (int j = 0, offset = 0; j < 18; j++, offset += 0x10) { 724 r = r600_state_sampler_border_init(ctx, offset); 725 if (r) 726 goto out_err; 727 } 728 729 /* VS SAMPLER BORDER */ 730 for (int j = 0, offset = 0x200; j < 18; j++, offset += 0x10) { 731 r = r600_state_sampler_border_init(ctx, offset); 732 if (r) 733 goto out_err; 734 } 735 /* PS SAMPLER */ 736 for (int j = 0, offset = 0; j < 18; j++, offset += 0xC) { 737 r = r600_state_sampler_init(ctx, offset); 738 if (r) 739 goto out_err; 740 } 741 /* VS SAMPLER */ 742 for (int j = 0, offset = 0xD8; j < 18; j++, offset += 0xC) { 743 r = r600_state_sampler_init(ctx, offset); 744 if (r) 745 goto out_err; 746 } 747 748 ctx->num_ps_resources = 160; 749 ctx->num_vs_resources = 160; 750 r = r600_resource_range_init(ctx, &ctx->ps_resources, 0, 160, 0x1c); 751 if (r) 752 goto out_err; 753 r = r600_resource_range_init(ctx, &ctx->vs_resources, 0x1180, 160, 0x1c); 754 if (r) 755 goto out_err; 756 757 /* PS loop const */ 758 r600_loop_const_init(ctx, 0); 759 /* VS loop const */ 760 r600_loop_const_init(ctx, 32); 761 762 r = r600_setup_block_table(ctx); 763 if (r) 764 goto out_err; 765 766 ctx->max_db = 4; 767 return 0; 768out_err: 769 r600_context_fini(ctx); 770 return r; 771} 772 773void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, 774 boolean count_draw_in) 775{ 776 struct r600_atom *state; 777 778 /* The number of dwords we already used in the CS so far. */ 779 num_dw += ctx->cs->cdw; 780 781 if (count_draw_in) { 782 /* The number of dwords all the dirty states would take. */ 783 LIST_FOR_EACH_ENTRY(state, &ctx->dirty_states, head) { 784 num_dw += state->num_dw; 785 } 786 787 num_dw += ctx->pm4_dirty_cdwords; 788 789 /* The upper-bound of how much a draw command would take. */ 790 num_dw += R600_MAX_DRAW_CS_DWORDS; 791 } 792 793 /* Count in queries_suspend. */ 794 num_dw += ctx->num_cs_dw_nontimer_queries_suspend; 795 num_dw += ctx->num_cs_dw_timer_queries_suspend; 796 797 /* Count in streamout_end at the end of CS. */ 798 num_dw += ctx->num_cs_dw_streamout_end; 799 800 /* Count in render_condition(NULL) at the end of CS. */ 801 if (ctx->predicate_drawing) { 802 num_dw += 3; 803 } 804 805 /* Count in framebuffer cache flushes at the end of CS. */ 806 num_dw += 7; /* one SURFACE_SYNC and CACHE_FLUSH_AND_INV (r6xx-only) */ 807 808 /* Save 16 dwords for the fence mechanism. */ 809 num_dw += 16; 810 811 /* Flush if there's not enough space. */ 812 if (num_dw > RADEON_MAX_CMDBUF_DWORDS) { 813 r600_flush(&ctx->context, NULL, RADEON_FLUSH_ASYNC); 814 } 815} 816 817void r600_context_dirty_block(struct r600_context *ctx, 818 struct r600_block *block, 819 int dirty, int index) 820{ 821 if ((index + 1) > block->nreg_dirty) 822 block->nreg_dirty = index + 1; 823 824 if ((dirty != (block->status & R600_BLOCK_STATUS_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) { 825 block->status |= R600_BLOCK_STATUS_DIRTY; 826 ctx->pm4_dirty_cdwords += block->pm4_ndwords; 827 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 828 block->status |= R600_BLOCK_STATUS_ENABLED; 829 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 830 } 831 LIST_ADDTAIL(&block->list,&ctx->dirty); 832 833 if (block->flags & REG_FLAG_FLUSH_CHANGE) { 834 r600_context_ps_partial_flush(ctx); 835 } 836 } 837} 838 839void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state) 840{ 841 struct r600_block *block; 842 int dirty; 843 for (int i = 0; i < state->nregs; i++) { 844 unsigned id, reloc_id; 845 struct r600_pipe_reg *reg = &state->regs[i]; 846 847 block = reg->block; 848 id = reg->id; 849 850 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 851 852 if (reg->value != block->reg[id]) { 853 block->reg[id] = reg->value; 854 dirty |= R600_BLOCK_STATUS_DIRTY; 855 } 856 if (block->flags & REG_FLAG_DIRTY_ALWAYS) 857 dirty |= R600_BLOCK_STATUS_DIRTY; 858 if (block->pm4_bo_index[id]) { 859 /* find relocation */ 860 reloc_id = block->pm4_bo_index[id]; 861 pipe_resource_reference((struct pipe_resource**)&block->reloc[reloc_id].bo, ®->bo->b.b); 862 block->reloc[reloc_id].bo_usage = reg->bo_usage; 863 /* always force dirty for relocs for now */ 864 dirty |= R600_BLOCK_STATUS_DIRTY; 865 } 866 867 if (dirty) 868 r600_context_dirty_block(ctx, block, dirty, id); 869 } 870} 871 872static void r600_context_dirty_resource_block(struct r600_context *ctx, 873 struct r600_block *block, 874 int dirty, int index) 875{ 876 block->nreg_dirty = index + 1; 877 878 if ((dirty != (block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) || !(block->status & R600_BLOCK_STATUS_ENABLED)) { 879 block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 880 ctx->pm4_dirty_cdwords += block->pm4_ndwords; 881 if (!(block->status & R600_BLOCK_STATUS_ENABLED)) { 882 block->status |= R600_BLOCK_STATUS_ENABLED; 883 LIST_ADDTAIL(&block->enable_list, &ctx->enable_list); 884 } 885 LIST_ADDTAIL(&block->list,&ctx->resource_dirty); 886 } 887} 888 889void r600_context_pipe_state_set_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, struct r600_block *block) 890{ 891 int dirty; 892 int num_regs = ctx->chip_class >= EVERGREEN ? 8 : 7; 893 894 if (state == NULL) { 895 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_RESOURCE_DIRTY); 896 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, NULL); 897 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, NULL); 898 LIST_DELINIT(&block->list); 899 LIST_DELINIT(&block->enable_list); 900 return; 901 } 902 903 dirty = block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY; 904 905 if (memcmp(block->reg, state->val, num_regs*4)) { 906 memcpy(block->reg, state->val, num_regs * 4); 907 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 908 } 909 910 /* if no BOs on block, force dirty */ 911 if (!block->reloc[1].bo || !block->reloc[2].bo) 912 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 913 914 if (!dirty) { 915 if ((block->reloc[1].bo->buf != state->bo[0]->buf) || 916 (block->reloc[2].bo->buf != state->bo[1]->buf)) 917 dirty |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 918 } 919 920 if (dirty) { 921 /* TEXTURE RESOURCE */ 922 pipe_resource_reference((struct pipe_resource**)&block->reloc[1].bo, &state->bo[0]->b.b); 923 block->reloc[1].bo_usage = state->bo_usage[0]; 924 pipe_resource_reference((struct pipe_resource**)&block->reloc[2].bo, &state->bo[1]->b.b); 925 block->reloc[2].bo_usage = state->bo_usage[1]; 926 927 r600_context_dirty_resource_block(ctx, block, dirty, num_regs - 1); 928 } 929} 930 931void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 932{ 933 struct r600_block *block = ctx->ps_resources.blocks[rid]; 934 935 r600_context_pipe_state_set_resource(ctx, state, block); 936} 937 938void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_resource_state *state, unsigned rid) 939{ 940 struct r600_block *block = ctx->vs_resources.blocks[rid]; 941 942 r600_context_pipe_state_set_resource(ctx, state, block); 943} 944 945void r600_context_pipe_state_set_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) 946{ 947 struct r600_range *range; 948 struct r600_block *block; 949 int i; 950 int dirty; 951 952 range = &ctx->range[CTX_RANGE_ID(offset)]; 953 block = range->blocks[CTX_BLOCK_ID(offset)]; 954 if (state == NULL) { 955 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); 956 LIST_DELINIT(&block->list); 957 LIST_DELINIT(&block->enable_list); 958 return; 959 } 960 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 961 962 for (i = 0; i < 3; i++) { 963 if (block->reg[i] != state->regs[i].value) { 964 block->reg[i] = state->regs[i].value; 965 dirty |= R600_BLOCK_STATUS_DIRTY; 966 } 967 } 968 969 if (dirty) 970 r600_context_dirty_block(ctx, block, dirty, 2); 971} 972 973static inline void r600_context_pipe_state_set_sampler_border(struct r600_context *ctx, struct r600_pipe_state *state, unsigned offset) 974{ 975 struct r600_range *range; 976 struct r600_block *block; 977 int i; 978 int dirty; 979 980 range = &ctx->range[CTX_RANGE_ID(offset)]; 981 block = range->blocks[CTX_BLOCK_ID(offset)]; 982 if (state == NULL) { 983 block->status &= ~(R600_BLOCK_STATUS_ENABLED | R600_BLOCK_STATUS_DIRTY); 984 LIST_DELINIT(&block->list); 985 LIST_DELINIT(&block->enable_list); 986 return; 987 } 988 if (state->nregs <= 3) { 989 return; 990 } 991 dirty = block->status & R600_BLOCK_STATUS_DIRTY; 992 for (i = 0; i < 4; i++) { 993 if (block->reg[i] != state->regs[i + 3].value) { 994 block->reg[i] = state->regs[i + 3].value; 995 dirty |= R600_BLOCK_STATUS_DIRTY; 996 } 997 } 998 999 /* We have to flush the shaders before we change the border color 1000 * registers, or previous draw commands that haven't completed yet 1001 * will end up using the new border color. */ 1002 if (dirty & R600_BLOCK_STATUS_DIRTY) 1003 r600_context_ps_partial_flush(ctx); 1004 if (dirty) 1005 r600_context_dirty_block(ctx, block, dirty, 3); 1006} 1007 1008void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) 1009{ 1010 unsigned offset; 1011 1012 offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*id; 1013 r600_context_pipe_state_set_sampler(ctx, state, offset); 1014 offset = R_00A400_TD_PS_SAMPLER0_BORDER_RED + 16*id; 1015 r600_context_pipe_state_set_sampler_border(ctx, state, offset); 1016} 1017 1018void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id) 1019{ 1020 unsigned offset; 1021 1022 offset = R_03C000_SQ_TEX_SAMPLER_WORD0_0 + 12*(id + 18); 1023 r600_context_pipe_state_set_sampler(ctx, state, offset); 1024 offset = R_00A600_TD_VS_SAMPLER0_BORDER_RED + 16*id; 1025 r600_context_pipe_state_set_sampler_border(ctx, state, offset); 1026} 1027 1028void r600_context_block_emit_dirty(struct r600_context *ctx, struct r600_block *block) 1029{ 1030 struct radeon_winsys_cs *cs = ctx->cs; 1031 int optional = block->nbo == 0 && !(block->flags & REG_FLAG_DIRTY_ALWAYS); 1032 int cp_dwords = block->pm4_ndwords, start_dword = 0; 1033 int new_dwords = 0; 1034 int nbo = block->nbo; 1035 1036 if (block->nreg_dirty == 0 && optional) { 1037 goto out; 1038 } 1039 1040 if (nbo) { 1041 for (int j = 0; j < block->nreg; j++) { 1042 if (block->pm4_bo_index[j]) { 1043 /* find relocation */ 1044 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]]; 1045 if (reloc->bo) { 1046 block->pm4[reloc->bo_pm4_index] = 1047 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage); 1048 } else { 1049 block->pm4[reloc->bo_pm4_index] = 0; 1050 } 1051 nbo--; 1052 if (nbo == 0) 1053 break; 1054 1055 } 1056 } 1057 } 1058 1059 optional &= (block->nreg_dirty != block->nreg); 1060 if (optional) { 1061 new_dwords = block->nreg_dirty; 1062 start_dword = cs->cdw; 1063 cp_dwords = new_dwords + 2; 1064 } 1065 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4); 1066 cs->cdw += cp_dwords; 1067 1068 if (optional) { 1069 uint32_t newword; 1070 1071 newword = cs->buf[start_dword]; 1072 newword &= PKT_COUNT_C; 1073 newword |= PKT_COUNT_S(new_dwords); 1074 cs->buf[start_dword] = newword; 1075 } 1076out: 1077 block->status ^= R600_BLOCK_STATUS_DIRTY; 1078 block->nreg_dirty = 0; 1079 LIST_DELINIT(&block->list); 1080} 1081 1082void r600_context_block_resource_emit_dirty(struct r600_context *ctx, struct r600_block *block) 1083{ 1084 struct radeon_winsys_cs *cs = ctx->cs; 1085 int cp_dwords = block->pm4_ndwords; 1086 int nbo = block->nbo; 1087 1088 for (int j = 0; j < nbo; j++) { 1089 if (block->pm4_bo_index[j]) { 1090 /* find relocation */ 1091 struct r600_block_reloc *reloc = &block->reloc[block->pm4_bo_index[j]]; 1092 block->pm4[reloc->bo_pm4_index] = 1093 r600_context_bo_reloc(ctx, reloc->bo, reloc->bo_usage); 1094 } 1095 } 1096 1097 memcpy(&cs->buf[cs->cdw], block->pm4, cp_dwords * 4); 1098 cs->cdw += cp_dwords; 1099 1100 block->status ^= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1101 block->nreg_dirty = 0; 1102 LIST_DELINIT(&block->list); 1103} 1104 1105void r600_inval_shader_cache(struct r600_context *ctx) 1106{ 1107 ctx->surface_sync_cmd.flush_flags |= S_0085F0_SH_ACTION_ENA(1); 1108 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom); 1109} 1110 1111void r600_inval_texture_cache(struct r600_context *ctx) 1112{ 1113 ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1); 1114 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom); 1115} 1116 1117void r600_inval_vertex_cache(struct r600_context *ctx) 1118{ 1119 if (ctx->has_vertex_cache) { 1120 ctx->surface_sync_cmd.flush_flags |= S_0085F0_VC_ACTION_ENA(1); 1121 } else { 1122 /* Some GPUs don't have the vertex cache and must use the texture cache instead. */ 1123 ctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1); 1124 } 1125 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom); 1126} 1127 1128void r600_flush_framebuffer(struct r600_context *ctx, bool flush_now) 1129{ 1130 if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY)) 1131 return; 1132 1133 ctx->surface_sync_cmd.flush_flags |= 1134 r600_get_cb_flush_flags(ctx) | 1135 (ctx->framebuffer.zsbuf ? S_0085F0_DB_ACTION_ENA(1) | S_0085F0_DB_DEST_BASE_ENA(1) : 0); 1136 1137 if (flush_now) { 1138 r600_emit_atom(ctx, &ctx->surface_sync_cmd.atom); 1139 } else { 1140 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom); 1141 } 1142 1143 /* Also add a complete cache flush to work around broken flushing on R6xx. */ 1144 if (ctx->chip_class == R600) { 1145 if (flush_now) { 1146 r600_emit_atom(ctx, &ctx->r6xx_flush_and_inv_cmd); 1147 } else { 1148 r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd); 1149 } 1150 } 1151 1152 ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY; 1153} 1154 1155void r600_context_flush(struct r600_context *ctx, unsigned flags) 1156{ 1157 struct radeon_winsys_cs *cs = ctx->cs; 1158 struct r600_block *enable_block = NULL; 1159 bool timer_queries_suspended = false; 1160 bool nontimer_queries_suspended = false; 1161 bool streamout_suspended = false; 1162 1163 if (cs->cdw == ctx->start_cs_cmd.atom.num_dw) 1164 return; 1165 1166 /* suspend queries */ 1167 if (ctx->num_cs_dw_timer_queries_suspend) { 1168 r600_suspend_timer_queries(ctx); 1169 timer_queries_suspended = true; 1170 } 1171 if (ctx->num_cs_dw_nontimer_queries_suspend) { 1172 r600_suspend_nontimer_queries(ctx); 1173 nontimer_queries_suspended = true; 1174 } 1175 1176 if (ctx->num_cs_dw_streamout_end) { 1177 r600_context_streamout_end(ctx); 1178 streamout_suspended = true; 1179 } 1180 1181 r600_flush_framebuffer(ctx, true); 1182 1183 /* partial flush is needed to avoid lockups on some chips with user fences */ 1184 r600_context_ps_partial_flush(ctx); 1185 1186 /* old kernels and userspace don't set SX_MISC, so we must reset it to 0 here */ 1187 if (ctx->chip_class <= R700) { 1188 r600_write_context_reg(cs, R_028350_SX_MISC, 0); 1189 } 1190 1191 /* force to keep tiling flags */ 1192 flags |= RADEON_FLUSH_KEEP_TILING_FLAGS; 1193 1194 /* Flush the CS. */ 1195 ctx->ws->cs_flush(ctx->cs, flags); 1196 1197 ctx->pm4_dirty_cdwords = 0; 1198 ctx->flags = 0; 1199 1200 /* Begin a new CS. */ 1201 r600_emit_atom(ctx, &ctx->start_cs_cmd.atom); 1202 1203 /* Invalidate caches. */ 1204 r600_inval_vertex_cache(ctx); 1205 r600_inval_texture_cache(ctx); 1206 r600_inval_shader_cache(ctx); 1207 r600_flush_framebuffer(ctx, false); 1208 1209 /* Re-emit states. */ 1210 r600_atom_dirty(ctx, &ctx->db_misc_state.atom); 1211 r600_atom_dirty(ctx, &ctx->vertex_buffer_state); 1212 1213 ctx->vs_constbuf_state.dirty_mask = ctx->vs_constbuf_state.enabled_mask; 1214 ctx->ps_constbuf_state.dirty_mask = ctx->ps_constbuf_state.enabled_mask; 1215 r600_constant_buffers_dirty(ctx, &ctx->vs_constbuf_state); 1216 r600_constant_buffers_dirty(ctx, &ctx->ps_constbuf_state); 1217 1218 if (streamout_suspended) { 1219 ctx->streamout_start = TRUE; 1220 ctx->streamout_append_bitmask = ~0; 1221 } 1222 1223 /* resume queries */ 1224 if (timer_queries_suspended) { 1225 r600_resume_timer_queries(ctx); 1226 } 1227 if (nontimer_queries_suspended) { 1228 r600_resume_nontimer_queries(ctx); 1229 } 1230 1231 /* set all valid group as dirty so they get reemited on 1232 * next draw command 1233 */ 1234 LIST_FOR_EACH_ENTRY(enable_block, &ctx->enable_list, enable_list) { 1235 if (!(enable_block->flags & BLOCK_FLAG_RESOURCE)) { 1236 if(!(enable_block->status & R600_BLOCK_STATUS_DIRTY)) { 1237 LIST_ADDTAIL(&enable_block->list,&ctx->dirty); 1238 enable_block->status |= R600_BLOCK_STATUS_DIRTY; 1239 } 1240 } else { 1241 if(!(enable_block->status & R600_BLOCK_STATUS_RESOURCE_DIRTY)) { 1242 LIST_ADDTAIL(&enable_block->list,&ctx->resource_dirty); 1243 enable_block->status |= R600_BLOCK_STATUS_RESOURCE_DIRTY; 1244 } 1245 } 1246 ctx->pm4_dirty_cdwords += enable_block->pm4_ndwords; 1247 enable_block->nreg_dirty = enable_block->nreg; 1248 } 1249} 1250 1251void r600_context_emit_fence(struct r600_context *ctx, struct r600_resource *fence_bo, unsigned offset, unsigned value) 1252{ 1253 struct radeon_winsys_cs *cs = ctx->cs; 1254 uint64_t va; 1255 1256 r600_need_cs_space(ctx, 10, FALSE); 1257 1258 va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo); 1259 va = va + (offset << 2); 1260 1261 r600_context_ps_partial_flush(ctx); 1262 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE_EOP, 4, 0); 1263 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); 1264 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* ADDRESS_LO */ 1265 /* DATA_SEL | INT_EN | ADDRESS_HI */ 1266 cs->buf[cs->cdw++] = (1 << 29) | (0 << 24) | ((va >> 32UL) & 0xFF); 1267 cs->buf[cs->cdw++] = value; /* DATA_LO */ 1268 cs->buf[cs->cdw++] = 0; /* DATA_HI */ 1269 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1270 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, fence_bo, RADEON_USAGE_WRITE); 1271} 1272 1273static void r600_flush_vgt_streamout(struct r600_context *ctx) 1274{ 1275 struct radeon_winsys_cs *cs = ctx->cs; 1276 1277 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, 1, 0); 1278 cs->buf[cs->cdw++] = (R_008490_CP_STRMOUT_CNTL - R600_CONFIG_REG_OFFSET) >> 2; 1279 cs->buf[cs->cdw++] = 0; 1280 1281 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 1282 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SO_VGTSTREAMOUT_FLUSH) | EVENT_INDEX(0); 1283 1284 cs->buf[cs->cdw++] = PKT3(PKT3_WAIT_REG_MEM, 5, 0); 1285 cs->buf[cs->cdw++] = WAIT_REG_MEM_EQUAL; /* wait until the register is equal to the reference value */ 1286 cs->buf[cs->cdw++] = R_008490_CP_STRMOUT_CNTL >> 2; /* register */ 1287 cs->buf[cs->cdw++] = 0; 1288 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* reference value */ 1289 cs->buf[cs->cdw++] = S_008490_OFFSET_UPDATE_DONE(1); /* mask */ 1290 cs->buf[cs->cdw++] = 4; /* poll interval */ 1291} 1292 1293static void r600_set_streamout_enable(struct r600_context *ctx, unsigned buffer_enable_bit) 1294{ 1295 struct radeon_winsys_cs *cs = ctx->cs; 1296 1297 if (buffer_enable_bit) { 1298 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1299 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2; 1300 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(1); 1301 1302 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1303 cs->buf[cs->cdw++] = (R_028B20_VGT_STRMOUT_BUFFER_EN - R600_CONTEXT_REG_OFFSET) >> 2; 1304 cs->buf[cs->cdw++] = buffer_enable_bit; 1305 } else { 1306 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1307 cs->buf[cs->cdw++] = (R_028AB0_VGT_STRMOUT_EN - R600_CONTEXT_REG_OFFSET) >> 2; 1308 cs->buf[cs->cdw++] = S_028AB0_STREAMOUT(0); 1309 } 1310} 1311 1312void r600_context_streamout_begin(struct r600_context *ctx) 1313{ 1314 struct radeon_winsys_cs *cs = ctx->cs; 1315 struct r600_so_target **t = ctx->so_targets; 1316 unsigned *stride_in_dw = ctx->vs_shader->so.stride; 1317 unsigned buffer_en, i, update_flags = 0; 1318 uint64_t va; 1319 1320 buffer_en = (ctx->num_so_targets >= 1 && t[0] ? 1 : 0) | 1321 (ctx->num_so_targets >= 2 && t[1] ? 2 : 0) | 1322 (ctx->num_so_targets >= 3 && t[2] ? 4 : 0) | 1323 (ctx->num_so_targets >= 4 && t[3] ? 8 : 0); 1324 1325 ctx->num_cs_dw_streamout_end = 1326 12 + /* flush_vgt_streamout */ 1327 util_bitcount(buffer_en) * 8 + 1328 3; 1329 1330 r600_need_cs_space(ctx, 1331 12 + /* flush_vgt_streamout */ 1332 6 + /* enables */ 1333 util_bitcount(buffer_en & ctx->streamout_append_bitmask) * 8 + 1334 util_bitcount(buffer_en & ~ctx->streamout_append_bitmask) * 6 + 1335 (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770 ? 2 : 0) + 1336 ctx->num_cs_dw_streamout_end, TRUE); 1337 1338 if (ctx->chip_class >= EVERGREEN) { 1339 evergreen_flush_vgt_streamout(ctx); 1340 evergreen_set_streamout_enable(ctx, buffer_en); 1341 } else { 1342 r600_flush_vgt_streamout(ctx); 1343 r600_set_streamout_enable(ctx, buffer_en); 1344 } 1345 1346 for (i = 0; i < ctx->num_so_targets; i++) { 1347 if (t[i]) { 1348 t[i]->stride_in_dw = stride_in_dw[i]; 1349 t[i]->so_index = i; 1350 va = r600_resource_va(&ctx->screen->screen, 1351 (void*)t[i]->b.buffer); 1352 1353 update_flags |= SURFACE_BASE_UPDATE_STRMOUT(i); 1354 1355 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 3, 0); 1356 cs->buf[cs->cdw++] = (R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 1357 16*i - R600_CONTEXT_REG_OFFSET) >> 2; 1358 cs->buf[cs->cdw++] = (t[i]->b.buffer_offset + 1359 t[i]->b.buffer_size) >> 2; /* BUFFER_SIZE (in DW) */ 1360 cs->buf[cs->cdw++] = stride_in_dw[i]; /* VTX_STRIDE (in DW) */ 1361 cs->buf[cs->cdw++] = va >> 8; /* BUFFER_BASE */ 1362 1363 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1364 cs->buf[cs->cdw++] = 1365 r600_context_bo_reloc(ctx, r600_resource(t[i]->b.buffer), 1366 RADEON_USAGE_WRITE); 1367 1368 if (ctx->streamout_append_bitmask & (1 << i)) { 1369 va = r600_resource_va(&ctx->screen->screen, 1370 (void*)t[i]->filled_size); 1371 /* Append. */ 1372 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); 1373 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | 1374 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_MEM); /* control */ 1375 cs->buf[cs->cdw++] = 0; /* unused */ 1376 cs->buf[cs->cdw++] = 0; /* unused */ 1377 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */ 1378 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */ 1379 1380 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1381 cs->buf[cs->cdw++] = 1382 r600_context_bo_reloc(ctx, t[i]->filled_size, 1383 RADEON_USAGE_READ); 1384 } else { 1385 /* Start from the beginning. */ 1386 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); 1387 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | 1388 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_FROM_PACKET); /* control */ 1389 cs->buf[cs->cdw++] = 0; /* unused */ 1390 cs->buf[cs->cdw++] = 0; /* unused */ 1391 cs->buf[cs->cdw++] = t[i]->b.buffer_offset >> 2; /* buffer offset in DW */ 1392 cs->buf[cs->cdw++] = 0; /* unused */ 1393 } 1394 } 1395 } 1396 1397 if (ctx->family > CHIP_R600 && ctx->family < CHIP_RV770) { 1398 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_BASE_UPDATE, 0, 0); 1399 cs->buf[cs->cdw++] = update_flags; 1400 } 1401} 1402 1403void r600_context_streamout_end(struct r600_context *ctx) 1404{ 1405 struct radeon_winsys_cs *cs = ctx->cs; 1406 struct r600_so_target **t = ctx->so_targets; 1407 unsigned i, flush_flags = 0; 1408 uint64_t va; 1409 1410 if (ctx->chip_class >= EVERGREEN) { 1411 evergreen_flush_vgt_streamout(ctx); 1412 } else { 1413 r600_flush_vgt_streamout(ctx); 1414 } 1415 1416 for (i = 0; i < ctx->num_so_targets; i++) { 1417 if (t[i]) { 1418 va = r600_resource_va(&ctx->screen->screen, 1419 (void*)t[i]->filled_size); 1420 cs->buf[cs->cdw++] = PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0); 1421 cs->buf[cs->cdw++] = STRMOUT_SELECT_BUFFER(i) | 1422 STRMOUT_OFFSET_SOURCE(STRMOUT_OFFSET_NONE) | 1423 STRMOUT_STORE_BUFFER_FILLED_SIZE; /* control */ 1424 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* dst address lo */ 1425 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* dst address hi */ 1426 cs->buf[cs->cdw++] = 0; /* unused */ 1427 cs->buf[cs->cdw++] = 0; /* unused */ 1428 1429 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1430 cs->buf[cs->cdw++] = 1431 r600_context_bo_reloc(ctx, t[i]->filled_size, 1432 RADEON_USAGE_WRITE); 1433 1434 flush_flags |= S_0085F0_SO0_DEST_BASE_ENA(1) << i; 1435 } 1436 } 1437 1438 if (ctx->chip_class >= EVERGREEN) { 1439 evergreen_set_streamout_enable(ctx, 0); 1440 } else { 1441 r600_set_streamout_enable(ctx, 0); 1442 } 1443 1444 /* This is needed to fix cache flushes on r600. */ 1445 if (ctx->chip_class == R600) { 1446 if (ctx->family == CHIP_RV670 || 1447 ctx->family == CHIP_RS780 || 1448 ctx->family == CHIP_RS880) { 1449 flush_flags |= S_0085F0_DEST_BASE_0_ENA(1); 1450 } 1451 1452 r600_atom_dirty(ctx, &ctx->r6xx_flush_and_inv_cmd); 1453 } 1454 1455 /* Flush streamout caches. */ 1456 ctx->surface_sync_cmd.flush_flags |= 1457 S_0085F0_SMX_ACTION_ENA(1) | flush_flags; 1458 r600_atom_dirty(ctx, &ctx->surface_sync_cmd.atom); 1459 1460 ctx->num_cs_dw_streamout_end = 0; 1461 1462#if 0 1463 for (i = 0; i < ctx->num_so_targets; i++) { 1464 if (!t[i]) 1465 continue; 1466 1467 uint32_t *ptr = ctx->ws->buffer_map(t[i]->filled_size->buf, ctx->cs, RADEON_USAGE_READ); 1468 printf("FILLED_SIZE%i: %u\n", i, *ptr); 1469 ctx->ws->buffer_unmap(t[i]->filled_size->buf); 1470 } 1471#endif 1472} 1473 1474void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t) 1475{ 1476 struct radeon_winsys_cs *cs = ctx->cs; 1477 uint64_t va = r600_resource_va(&ctx->screen->screen, 1478 (void*)t->filled_size); 1479 1480 r600_need_cs_space(ctx, 14 + 21, TRUE); 1481 1482 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1483 cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - R600_CONTEXT_REG_OFFSET) >> 2; 1484 cs->buf[cs->cdw++] = 0; 1485 1486 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0); 1487 cs->buf[cs->cdw++] = (R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE - R600_CONTEXT_REG_OFFSET) >> 2; 1488 cs->buf[cs->cdw++] = t->stride_in_dw; 1489 1490 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0); 1491 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG; 1492 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */ 1493 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */ 1494 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */ 1495 cs->buf[cs->cdw++] = 0; /* unused */ 1496 1497 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1498 cs->buf[cs->cdw++] = r600_context_bo_reloc(ctx, t->filled_size, RADEON_USAGE_READ); 1499} 1500