r600_pipe.c revision 0f86915c5322b096b7154b6c84e21288074b775d
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_pipe.h" 24#include "r600_public.h" 25 26#include <errno.h> 27#include "pipe/p_shader_tokens.h" 28#include "util/u_blitter.h" 29#include "util/u_format_s3tc.h" 30#include "util/u_simple_shaders.h" 31#include "util/u_upload_mgr.h" 32#include "vl/vl_decoder.h" 33#include "vl/vl_video_buffer.h" 34#include "os/os_time.h" 35 36/* 37 * pipe_context 38 */ 39static struct r600_fence *r600_create_fence(struct r600_context *rctx) 40{ 41 struct r600_screen *rscreen = rctx->screen; 42 struct r600_fence *fence = NULL; 43 44 pipe_mutex_lock(rscreen->fences.mutex); 45 46 if (!rscreen->fences.bo) { 47 /* Create the shared buffer object */ 48 rscreen->fences.bo = (struct r600_resource*) 49 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM, 50 PIPE_USAGE_STAGING, 4096); 51 if (!rscreen->fences.bo) { 52 R600_ERR("r600: failed to create bo for fence objects\n"); 53 goto out; 54 } 55 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf, 56 rctx->cs, 57 PIPE_TRANSFER_READ_WRITE); 58 } 59 60 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) { 61 struct r600_fence *entry; 62 63 /* Try to find a freed fence that has been signalled */ 64 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) { 65 if (rscreen->fences.data[entry->index] != 0) { 66 LIST_DELINIT(&entry->head); 67 fence = entry; 68 break; 69 } 70 } 71 } 72 73 if (!fence) { 74 /* Allocate a new fence */ 75 struct r600_fence_block *block; 76 unsigned index; 77 78 if ((rscreen->fences.next_index + 1) >= 1024) { 79 R600_ERR("r600: too many concurrent fences\n"); 80 goto out; 81 } 82 83 index = rscreen->fences.next_index++; 84 85 if (!(index % FENCE_BLOCK_SIZE)) { 86 /* Allocate a new block */ 87 block = CALLOC_STRUCT(r600_fence_block); 88 if (block == NULL) 89 goto out; 90 91 LIST_ADD(&block->head, &rscreen->fences.blocks); 92 } else { 93 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head); 94 } 95 96 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 97 fence->index = index; 98 } 99 100 pipe_reference_init(&fence->reference, 1); 101 102 rscreen->fences.data[fence->index] = 0; 103 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1); 104 105 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */ 106 fence->sleep_bo = (struct r600_resource*) 107 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM, 108 PIPE_USAGE_STAGING, 1); 109 /* Add the fence as a dummy relocation. */ 110 r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE); 111 112out: 113 pipe_mutex_unlock(rscreen->fences.mutex); 114 return fence; 115} 116 117 118void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 119 unsigned flags) 120{ 121 struct r600_context *rctx = (struct r600_context *)ctx; 122 struct r600_fence **rfence = (struct r600_fence**)fence; 123 struct pipe_query *render_cond = NULL; 124 unsigned render_cond_mode = 0; 125 126 if (rfence) 127 *rfence = r600_create_fence(rctx); 128 129 /* Disable render condition. */ 130 if (rctx->current_render_cond) { 131 render_cond = rctx->current_render_cond; 132 render_cond_mode = rctx->current_render_cond_mode; 133 ctx->render_condition(ctx, NULL, 0); 134 } 135 136 r600_context_flush(rctx, flags); 137 138 /* Re-enable render condition. */ 139 if (render_cond) { 140 ctx->render_condition(ctx, render_cond, render_cond_mode); 141 } 142} 143 144static void r600_flush_from_st(struct pipe_context *ctx, 145 struct pipe_fence_handle **fence) 146{ 147 r600_flush(ctx, fence, 0); 148} 149 150static void r600_flush_from_winsys(void *ctx, unsigned flags) 151{ 152 r600_flush((struct pipe_context*)ctx, NULL, flags); 153} 154 155static void r600_destroy_context(struct pipe_context *context) 156{ 157 struct r600_context *rctx = (struct r600_context *)context; 158 159 if (rctx->dummy_pixel_shader) { 160 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader); 161 } 162 if (rctx->custom_dsa_flush) { 163 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 164 } 165 if (rctx->custom_blend_resolve) { 166 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve); 167 } 168 util_unreference_framebuffer_state(&rctx->framebuffer); 169 170 r600_context_fini(rctx); 171 172 if (rctx->blitter) { 173 util_blitter_destroy(rctx->blitter); 174 } 175 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 176 free(rctx->states[i]); 177 } 178 179 if (rctx->uploader) { 180 u_upload_destroy(rctx->uploader); 181 } 182 util_slab_destroy(&rctx->pool_transfers); 183 184 r600_release_command_buffer(&rctx->start_cs_cmd); 185 186 if (rctx->cs) { 187 rctx->ws->cs_destroy(rctx->cs); 188 } 189 190 FREE(rctx->range); 191 FREE(rctx); 192} 193 194static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 195{ 196 struct r600_context *rctx = CALLOC_STRUCT(r600_context); 197 struct r600_screen* rscreen = (struct r600_screen *)screen; 198 199 if (rctx == NULL) 200 return NULL; 201 202 util_slab_create(&rctx->pool_transfers, 203 sizeof(struct r600_transfer), 64, 204 UTIL_SLAB_SINGLETHREADED); 205 206 rctx->context.screen = screen; 207 rctx->context.priv = priv; 208 rctx->context.destroy = r600_destroy_context; 209 rctx->context.flush = r600_flush_from_st; 210 211 /* Easy accessing of screen/winsys. */ 212 rctx->screen = rscreen; 213 rctx->ws = rscreen->ws; 214 rctx->family = rscreen->family; 215 rctx->chip_class = rscreen->chip_class; 216 217 LIST_INITHEAD(&rctx->dirty_states); 218 LIST_INITHEAD(&rctx->active_timer_queries); 219 LIST_INITHEAD(&rctx->active_nontimer_queries); 220 LIST_INITHEAD(&rctx->dirty); 221 LIST_INITHEAD(&rctx->enable_list); 222 223 rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range)); 224 if (!rctx->range) 225 goto fail; 226 227 r600_init_blit_functions(rctx); 228 r600_init_query_functions(rctx); 229 r600_init_context_resource_functions(rctx); 230 r600_init_surface_functions(rctx); 231 rctx->context.draw_vbo = r600_draw_vbo; 232 233 rctx->context.create_video_decoder = vl_create_decoder; 234 rctx->context.create_video_buffer = vl_video_buffer_create; 235 236 r600_init_common_atoms(rctx); 237 238 switch (rctx->chip_class) { 239 case R600: 240 case R700: 241 r600_init_state_functions(rctx); 242 r600_init_atom_start_cs(rctx); 243 if (r600_context_init(rctx)) 244 goto fail; 245 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 246 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 || 247 rctx->family == CHIP_RV620 || 248 rctx->family == CHIP_RS780 || 249 rctx->family == CHIP_RS880 || 250 rctx->family == CHIP_RV710); 251 break; 252 case EVERGREEN: 253 case CAYMAN: 254 evergreen_init_state_functions(rctx); 255 evergreen_init_atom_start_cs(rctx); 256 evergreen_init_atom_start_compute_cs(rctx); 257 if (evergreen_context_init(rctx)) 258 goto fail; 259 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 260 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx); 261 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR || 262 rctx->family == CHIP_PALM || 263 rctx->family == CHIP_SUMO || 264 rctx->family == CHIP_SUMO2 || 265 rctx->family == CHIP_CAICOS || 266 rctx->family == CHIP_CAYMAN || 267 rctx->family == CHIP_ARUBA); 268 break; 269 default: 270 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); 271 goto fail; 272 } 273 274 rctx->cs = rctx->ws->cs_create(rctx->ws); 275 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx); 276 r600_emit_atom(rctx, &rctx->start_cs_cmd.atom); 277 278 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256, 279 PIPE_BIND_INDEX_BUFFER | 280 PIPE_BIND_CONSTANT_BUFFER); 281 if (!rctx->uploader) 282 goto fail; 283 284 rctx->blitter = util_blitter_create(&rctx->context); 285 if (rctx->blitter == NULL) 286 goto fail; 287 288 r600_get_backend_mask(rctx); /* this emits commands and must be last */ 289 290 if (rctx->chip_class == R600) 291 r600_set_max_scissor(rctx); 292 293 rctx->dummy_pixel_shader = 294 util_make_fragment_cloneinput_shader(&rctx->context, 0, 295 TGSI_SEMANTIC_GENERIC, 296 TGSI_INTERPOLATE_CONSTANT); 297 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader); 298 299 return &rctx->context; 300 301fail: 302 r600_destroy_context(&rctx->context); 303 return NULL; 304} 305 306/* 307 * pipe_screen 308 */ 309static const char* r600_get_vendor(struct pipe_screen* pscreen) 310{ 311 return "X.Org"; 312} 313 314static const char *r600_get_family_name(enum radeon_family family) 315{ 316 switch(family) { 317 case CHIP_R600: return "AMD R600"; 318 case CHIP_RV610: return "AMD RV610"; 319 case CHIP_RV630: return "AMD RV630"; 320 case CHIP_RV670: return "AMD RV670"; 321 case CHIP_RV620: return "AMD RV620"; 322 case CHIP_RV635: return "AMD RV635"; 323 case CHIP_RS780: return "AMD RS780"; 324 case CHIP_RS880: return "AMD RS880"; 325 case CHIP_RV770: return "AMD RV770"; 326 case CHIP_RV730: return "AMD RV730"; 327 case CHIP_RV710: return "AMD RV710"; 328 case CHIP_RV740: return "AMD RV740"; 329 case CHIP_CEDAR: return "AMD CEDAR"; 330 case CHIP_REDWOOD: return "AMD REDWOOD"; 331 case CHIP_JUNIPER: return "AMD JUNIPER"; 332 case CHIP_CYPRESS: return "AMD CYPRESS"; 333 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 334 case CHIP_PALM: return "AMD PALM"; 335 case CHIP_SUMO: return "AMD SUMO"; 336 case CHIP_SUMO2: return "AMD SUMO2"; 337 case CHIP_BARTS: return "AMD BARTS"; 338 case CHIP_TURKS: return "AMD TURKS"; 339 case CHIP_CAICOS: return "AMD CAICOS"; 340 case CHIP_CAYMAN: return "AMD CAYMAN"; 341 case CHIP_ARUBA: return "AMD ARUBA"; 342 default: return "AMD unknown"; 343 } 344} 345 346static const char* r600_get_name(struct pipe_screen* pscreen) 347{ 348 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 349 350 return r600_get_family_name(rscreen->family); 351} 352 353static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 354{ 355 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 356 enum radeon_family family = rscreen->family; 357 358 switch (param) { 359 /* Supported features (boolean caps). */ 360 case PIPE_CAP_NPOT_TEXTURES: 361 case PIPE_CAP_TWO_SIDED_STENCIL: 362 case PIPE_CAP_ANISOTROPIC_FILTER: 363 case PIPE_CAP_POINT_SPRITE: 364 case PIPE_CAP_OCCLUSION_QUERY: 365 case PIPE_CAP_TEXTURE_SHADOW_MAP: 366 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 367 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 368 case PIPE_CAP_TEXTURE_SWIZZLE: 369 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 370 case PIPE_CAP_DEPTH_CLIP_DISABLE: 371 case PIPE_CAP_SHADER_STENCIL_EXPORT: 372 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 373 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 374 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 375 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 376 case PIPE_CAP_SM3: 377 case PIPE_CAP_SEAMLESS_CUBE_MAP: 378 case PIPE_CAP_PRIMITIVE_RESTART: 379 case PIPE_CAP_CONDITIONAL_RENDER: 380 case PIPE_CAP_TEXTURE_BARRIER: 381 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 382 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 383 case PIPE_CAP_TGSI_INSTANCEID: 384 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 385 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 386 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 387 case PIPE_CAP_USER_INDEX_BUFFERS: 388 case PIPE_CAP_USER_CONSTANT_BUFFERS: 389 case PIPE_CAP_COMPUTE: 390 case PIPE_CAP_START_INSTANCE: 391 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 392 return 1; 393 394 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 395 return 256; 396 397 case PIPE_CAP_GLSL_FEATURE_LEVEL: 398 return 130; 399 400 /* Supported except the original R600. */ 401 case PIPE_CAP_INDEP_BLEND_ENABLE: 402 case PIPE_CAP_INDEP_BLEND_FUNC: 403 /* R600 doesn't support per-MRT blends */ 404 return family == CHIP_R600 ? 0 : 1; 405 406 /* Supported on Evergreen. */ 407 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 408 return family >= CHIP_CEDAR ? 1 : 0; 409 410 /* Unsupported features. */ 411 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 412 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 413 case PIPE_CAP_SCALED_RESOLVE: 414 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 415 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 416 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 417 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 418 case PIPE_CAP_USER_VERTEX_BUFFERS: 419 case PIPE_CAP_QUERY_TIMESTAMP: 420 return 0; 421 422 /* Stream output. */ 423 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 424 return rscreen->has_streamout ? 4 : 0; 425 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 426 return rscreen->has_streamout ? 1 : 0; 427 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 428 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 429 return 16*4; 430 431 /* Texturing. */ 432 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 433 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 434 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 435 if (family >= CHIP_CEDAR) 436 return 15; 437 else 438 return 14; 439 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 440 return rscreen->info.drm_minor >= 9 ? 441 (family >= CHIP_CEDAR ? 16384 : 8192) : 0; 442 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 443 return 32; 444 445 /* Render targets. */ 446 case PIPE_CAP_MAX_RENDER_TARGETS: 447 /* XXX some r6xx are buggy and can only do 4 */ 448 return 8; 449 450 /* Timer queries, present when the clock frequency is non zero. */ 451 case PIPE_CAP_TIMER_QUERY: 452 return rscreen->info.r600_clock_crystal_freq != 0; 453 454 case PIPE_CAP_MIN_TEXEL_OFFSET: 455 return -8; 456 457 case PIPE_CAP_MAX_TEXEL_OFFSET: 458 return 7; 459 } 460 return 0; 461} 462 463static float r600_get_paramf(struct pipe_screen* pscreen, 464 enum pipe_capf param) 465{ 466 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 467 enum radeon_family family = rscreen->family; 468 469 switch (param) { 470 case PIPE_CAPF_MAX_LINE_WIDTH: 471 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 472 case PIPE_CAPF_MAX_POINT_WIDTH: 473 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 474 if (family >= CHIP_CEDAR) 475 return 16384.0f; 476 else 477 return 8192.0f; 478 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 479 return 16.0f; 480 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 481 return 16.0f; 482 case PIPE_CAPF_GUARD_BAND_LEFT: 483 case PIPE_CAPF_GUARD_BAND_TOP: 484 case PIPE_CAPF_GUARD_BAND_RIGHT: 485 case PIPE_CAPF_GUARD_BAND_BOTTOM: 486 return 0.0f; 487 } 488 return 0.0f; 489} 490 491static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 492{ 493 switch(shader) 494 { 495 case PIPE_SHADER_FRAGMENT: 496 case PIPE_SHADER_VERTEX: 497 case PIPE_SHADER_COMPUTE: 498 break; 499 case PIPE_SHADER_GEOMETRY: 500 /* XXX: support and enable geometry programs */ 501 return 0; 502 default: 503 /* XXX: support tessellation on Evergreen */ 504 return 0; 505 } 506 507 /* XXX: all these should be fixed, since r600 surely supports much more! */ 508 switch (param) { 509 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 510 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 511 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 512 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 513 return 16384; 514 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 515 return 8; /* XXX */ 516 case PIPE_SHADER_CAP_MAX_INPUTS: 517 if(shader == PIPE_SHADER_FRAGMENT) 518 return 34; 519 else 520 return 32; 521 case PIPE_SHADER_CAP_MAX_TEMPS: 522 return 256; /* Max native temporaries. */ 523 case PIPE_SHADER_CAP_MAX_ADDRS: 524 /* XXX Isn't this equal to TEMPS? */ 525 return 1; /* Max native address registers */ 526 case PIPE_SHADER_CAP_MAX_CONSTS: 527 return R600_MAX_CONST_BUFFER_SIZE; 528 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 529 return R600_MAX_CONST_BUFFERS-1; 530 case PIPE_SHADER_CAP_MAX_PREDS: 531 return 0; /* nothing uses this */ 532 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 533 return 1; 534 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 535 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 536 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 537 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 538 return 1; 539 case PIPE_SHADER_CAP_SUBROUTINES: 540 return 0; 541 case PIPE_SHADER_CAP_INTEGERS: 542 return 1; 543 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 544 return 16; 545 case PIPE_SHADER_CAP_PREFERRED_IR: 546 if (shader == PIPE_SHADER_COMPUTE) { 547 return PIPE_SHADER_IR_LLVM; 548 } else { 549 return PIPE_SHADER_IR_TGSI; 550 } 551 } 552 return 0; 553} 554 555static int r600_get_video_param(struct pipe_screen *screen, 556 enum pipe_video_profile profile, 557 enum pipe_video_cap param) 558{ 559 switch (param) { 560 case PIPE_VIDEO_CAP_SUPPORTED: 561 return vl_profile_supported(screen, profile); 562 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 563 return 1; 564 case PIPE_VIDEO_CAP_MAX_WIDTH: 565 case PIPE_VIDEO_CAP_MAX_HEIGHT: 566 return vl_video_buffer_max_size(screen); 567 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 568 return PIPE_FORMAT_NV12; 569 case PIPE_VIDEO_CAP_PREFERS_INTERLACED: 570 return false; 571 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: 572 return false; 573 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: 574 return true; 575 default: 576 return 0; 577 } 578} 579 580static int r600_get_compute_param(struct pipe_screen *screen, 581 enum pipe_compute_cap param, 582 void *ret) 583{ 584 //TODO: select these params by asic 585 switch (param) { 586 case PIPE_COMPUTE_CAP_IR_TARGET: 587 if (ret) { 588 strcpy(ret, "r600--"); 589 } 590 return 7 * sizeof(char); 591 592 case PIPE_COMPUTE_CAP_GRID_DIMENSION: 593 if (ret) { 594 uint64_t * grid_dimension = ret; 595 grid_dimension[0] = 3; 596 } 597 return 1 * sizeof(uint64_t); 598 599 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: 600 if (ret) { 601 uint64_t * grid_size = ret; 602 grid_size[0] = 65535; 603 grid_size[1] = 65535; 604 grid_size[2] = 1; 605 } 606 return 3 * sizeof(uint64_t) ; 607 608 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: 609 if (ret) { 610 uint64_t * block_size = ret; 611 block_size[0] = 256; 612 block_size[1] = 256; 613 block_size[2] = 256; 614 } 615 return 3 * sizeof(uint64_t); 616 617 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: 618 if (ret) { 619 uint64_t * max_threads_per_block = ret; 620 *max_threads_per_block = 256; 621 } 622 return sizeof(uint64_t); 623 624 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: 625 if (ret) { 626 uint64_t * max_global_size = ret; 627 /* XXX: This is 64kb for now until we get the 628 * compute memory pool working correctly. 629 */ 630 *max_global_size = 1024 * 16 * 4; 631 } 632 return sizeof(uint64_t); 633 634 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: 635 if (ret) { 636 uint64_t * max_input_size = ret; 637 *max_input_size = 1024; 638 } 639 return sizeof(uint64_t); 640 641 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: 642 if (ret) { 643 uint64_t * max_local_size = ret; 644 /* XXX: This is what the proprietary driver reports, we 645 * may want to use a different value. */ 646 *max_local_size = 32768; 647 } 648 return sizeof(uint64_t); 649 650 default: 651 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param); 652 return 0; 653 } 654} 655 656static void r600_destroy_screen(struct pipe_screen* pscreen) 657{ 658 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 659 660 if (rscreen == NULL) 661 return; 662 663 if (rscreen->global_pool) { 664 compute_memory_pool_delete(rscreen->global_pool); 665 } 666 667 if (rscreen->fences.bo) { 668 struct r600_fence_block *entry, *tmp; 669 670 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) { 671 LIST_DEL(&entry->head); 672 FREE(entry); 673 } 674 675 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf); 676 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL); 677 } 678 pipe_mutex_destroy(rscreen->fences.mutex); 679 680 rscreen->ws->destroy(rscreen->ws); 681 FREE(rscreen); 682} 683 684static void r600_fence_reference(struct pipe_screen *pscreen, 685 struct pipe_fence_handle **ptr, 686 struct pipe_fence_handle *fence) 687{ 688 struct r600_fence **oldf = (struct r600_fence**)ptr; 689 struct r600_fence *newf = (struct r600_fence*)fence; 690 691 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 692 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 693 pipe_mutex_lock(rscreen->fences.mutex); 694 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL); 695 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool); 696 pipe_mutex_unlock(rscreen->fences.mutex); 697 } 698 699 *ptr = fence; 700} 701 702static boolean r600_fence_signalled(struct pipe_screen *pscreen, 703 struct pipe_fence_handle *fence) 704{ 705 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 706 struct r600_fence *rfence = (struct r600_fence*)fence; 707 708 return rscreen->fences.data[rfence->index]; 709} 710 711static boolean r600_fence_finish(struct pipe_screen *pscreen, 712 struct pipe_fence_handle *fence, 713 uint64_t timeout) 714{ 715 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 716 struct r600_fence *rfence = (struct r600_fence*)fence; 717 int64_t start_time = 0; 718 unsigned spins = 0; 719 720 if (timeout != PIPE_TIMEOUT_INFINITE) { 721 start_time = os_time_get(); 722 723 /* Convert to microseconds. */ 724 timeout /= 1000; 725 } 726 727 while (rscreen->fences.data[rfence->index] == 0) { 728 /* Special-case infinite timeout - wait for the dummy BO to become idle */ 729 if (timeout == PIPE_TIMEOUT_INFINITE) { 730 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE); 731 break; 732 } 733 734 /* The dummy BO will be busy until the CS including the fence has completed, or 735 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */ 736 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE)) 737 break; 738 739 if (++spins % 256) 740 continue; 741#ifdef PIPE_OS_UNIX 742 sched_yield(); 743#else 744 os_time_sleep(10); 745#endif 746 if (timeout != PIPE_TIMEOUT_INFINITE && 747 os_time_get() - start_time >= timeout) { 748 break; 749 } 750 } 751 752 return rscreen->fences.data[rfence->index] != 0; 753} 754 755static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 756{ 757 switch ((tiling_config & 0xe) >> 1) { 758 case 0: 759 rscreen->tiling_info.num_channels = 1; 760 break; 761 case 1: 762 rscreen->tiling_info.num_channels = 2; 763 break; 764 case 2: 765 rscreen->tiling_info.num_channels = 4; 766 break; 767 case 3: 768 rscreen->tiling_info.num_channels = 8; 769 break; 770 default: 771 return -EINVAL; 772 } 773 774 switch ((tiling_config & 0x30) >> 4) { 775 case 0: 776 rscreen->tiling_info.num_banks = 4; 777 break; 778 case 1: 779 rscreen->tiling_info.num_banks = 8; 780 break; 781 default: 782 return -EINVAL; 783 784 } 785 switch ((tiling_config & 0xc0) >> 6) { 786 case 0: 787 rscreen->tiling_info.group_bytes = 256; 788 break; 789 case 1: 790 rscreen->tiling_info.group_bytes = 512; 791 break; 792 default: 793 return -EINVAL; 794 } 795 return 0; 796} 797 798static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 799{ 800 switch (tiling_config & 0xf) { 801 case 0: 802 rscreen->tiling_info.num_channels = 1; 803 break; 804 case 1: 805 rscreen->tiling_info.num_channels = 2; 806 break; 807 case 2: 808 rscreen->tiling_info.num_channels = 4; 809 break; 810 case 3: 811 rscreen->tiling_info.num_channels = 8; 812 break; 813 default: 814 return -EINVAL; 815 } 816 817 switch ((tiling_config & 0xf0) >> 4) { 818 case 0: 819 rscreen->tiling_info.num_banks = 4; 820 break; 821 case 1: 822 rscreen->tiling_info.num_banks = 8; 823 break; 824 case 2: 825 rscreen->tiling_info.num_banks = 16; 826 break; 827 default: 828 return -EINVAL; 829 } 830 831 switch ((tiling_config & 0xf00) >> 8) { 832 case 0: 833 rscreen->tiling_info.group_bytes = 256; 834 break; 835 case 1: 836 rscreen->tiling_info.group_bytes = 512; 837 break; 838 default: 839 return -EINVAL; 840 } 841 return 0; 842} 843 844static int r600_init_tiling(struct r600_screen *rscreen) 845{ 846 uint32_t tiling_config = rscreen->info.r600_tiling_config; 847 848 /* set default group bytes, overridden by tiling info ioctl */ 849 if (rscreen->chip_class <= R700) { 850 rscreen->tiling_info.group_bytes = 256; 851 } else { 852 rscreen->tiling_info.group_bytes = 512; 853 } 854 855 if (!tiling_config) 856 return 0; 857 858 if (rscreen->chip_class <= R700) { 859 return r600_interpret_tiling(rscreen, tiling_config); 860 } else { 861 return evergreen_interpret_tiling(rscreen, tiling_config); 862 } 863} 864 865static unsigned radeon_family_from_device(unsigned device) 866{ 867 switch (device) { 868#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; 869#include "pci_ids/r600_pci_ids.h" 870#undef CHIPSET 871 default: 872 return CHIP_UNKNOWN; 873 } 874} 875 876struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) 877{ 878 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); 879 880 if (rscreen == NULL) { 881 return NULL; 882 } 883 884 rscreen->ws = ws; 885 ws->query_info(ws, &rscreen->info); 886 887 rscreen->family = radeon_family_from_device(rscreen->info.pci_id); 888 if (rscreen->family == CHIP_UNKNOWN) { 889 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); 890 FREE(rscreen); 891 return NULL; 892 } 893 894 /* setup class */ 895 if (rscreen->family >= CHIP_CAYMAN) { 896 rscreen->chip_class = CAYMAN; 897 } else if (rscreen->family >= CHIP_CEDAR) { 898 rscreen->chip_class = EVERGREEN; 899 } else if (rscreen->family >= CHIP_RV770) { 900 rscreen->chip_class = R700; 901 } else { 902 rscreen->chip_class = R600; 903 } 904 905 /* Figure out streamout kernel support. */ 906 switch (rscreen->chip_class) { 907 case R600: 908 case EVERGREEN: 909 rscreen->has_streamout = rscreen->info.drm_minor >= 14; 910 break; 911 case R700: 912 rscreen->has_streamout = rscreen->info.drm_minor >= 17; 913 break; 914 /* TODO: Cayman */ 915 default: 916 rscreen->has_streamout = debug_get_bool_option("R600_STREAMOUT", FALSE); 917 } 918 919 if (r600_init_tiling(rscreen)) { 920 FREE(rscreen); 921 return NULL; 922 } 923 924 rscreen->screen.destroy = r600_destroy_screen; 925 rscreen->screen.get_name = r600_get_name; 926 rscreen->screen.get_vendor = r600_get_vendor; 927 rscreen->screen.get_param = r600_get_param; 928 rscreen->screen.get_shader_param = r600_get_shader_param; 929 rscreen->screen.get_paramf = r600_get_paramf; 930 rscreen->screen.get_video_param = r600_get_video_param; 931 rscreen->screen.get_compute_param = r600_get_compute_param; 932 933 if (rscreen->chip_class >= EVERGREEN) { 934 rscreen->screen.is_format_supported = evergreen_is_format_supported; 935 } else { 936 rscreen->screen.is_format_supported = r600_is_format_supported; 937 } 938 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; 939 rscreen->screen.context_create = r600_create_context; 940 rscreen->screen.fence_reference = r600_fence_reference; 941 rscreen->screen.fence_signalled = r600_fence_signalled; 942 rscreen->screen.fence_finish = r600_fence_finish; 943 r600_init_screen_resource_functions(&rscreen->screen); 944 945 util_format_s3tc_init(); 946 947 rscreen->fences.bo = NULL; 948 rscreen->fences.data = NULL; 949 rscreen->fences.next_index = 0; 950 LIST_INITHEAD(&rscreen->fences.pool); 951 LIST_INITHEAD(&rscreen->fences.blocks); 952 pipe_mutex_init(rscreen->fences.mutex); 953 954 rscreen->global_pool = compute_memory_pool_new(rscreen); 955 956 return &rscreen->screen; 957} 958