r600_pipe.c revision 187d7fb2fec7da889f25366696faaac4c2e8f9c4
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_pipe.h" 24#include "r600_public.h" 25 26#include <errno.h> 27#include "pipe/p_shader_tokens.h" 28#include "util/u_blitter.h" 29#include "util/u_format_s3tc.h" 30#include "util/u_simple_shaders.h" 31#include "util/u_upload_mgr.h" 32#include "vl/vl_decoder.h" 33#include "vl/vl_video_buffer.h" 34#include "os/os_time.h" 35 36/* 37 * pipe_context 38 */ 39static struct r600_fence *r600_create_fence(struct r600_context *rctx) 40{ 41 struct r600_screen *rscreen = rctx->screen; 42 struct r600_fence *fence = NULL; 43 44 pipe_mutex_lock(rscreen->fences.mutex); 45 46 if (!rscreen->fences.bo) { 47 /* Create the shared buffer object */ 48 rscreen->fences.bo = (struct r600_resource*) 49 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM, 50 PIPE_USAGE_STAGING, 4096); 51 if (!rscreen->fences.bo) { 52 R600_ERR("r600: failed to create bo for fence objects\n"); 53 goto out; 54 } 55 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf, 56 rctx->cs, 57 PIPE_TRANSFER_READ_WRITE); 58 } 59 60 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) { 61 struct r600_fence *entry; 62 63 /* Try to find a freed fence that has been signalled */ 64 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) { 65 if (rscreen->fences.data[entry->index] != 0) { 66 LIST_DELINIT(&entry->head); 67 fence = entry; 68 break; 69 } 70 } 71 } 72 73 if (!fence) { 74 /* Allocate a new fence */ 75 struct r600_fence_block *block; 76 unsigned index; 77 78 if ((rscreen->fences.next_index + 1) >= 1024) { 79 R600_ERR("r600: too many concurrent fences\n"); 80 goto out; 81 } 82 83 index = rscreen->fences.next_index++; 84 85 if (!(index % FENCE_BLOCK_SIZE)) { 86 /* Allocate a new block */ 87 block = CALLOC_STRUCT(r600_fence_block); 88 if (block == NULL) 89 goto out; 90 91 LIST_ADD(&block->head, &rscreen->fences.blocks); 92 } else { 93 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head); 94 } 95 96 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 97 fence->index = index; 98 } 99 100 pipe_reference_init(&fence->reference, 1); 101 102 rscreen->fences.data[fence->index] = 0; 103 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1); 104 105 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */ 106 fence->sleep_bo = (struct r600_resource*) 107 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM, 108 PIPE_USAGE_STAGING, 1); 109 /* Add the fence as a dummy relocation. */ 110 r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE); 111 112out: 113 pipe_mutex_unlock(rscreen->fences.mutex); 114 return fence; 115} 116 117 118void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 119 unsigned flags) 120{ 121 struct r600_context *rctx = (struct r600_context *)ctx; 122 struct r600_fence **rfence = (struct r600_fence**)fence; 123 struct pipe_query *render_cond = NULL; 124 unsigned render_cond_mode = 0; 125 126 if (rfence) 127 *rfence = r600_create_fence(rctx); 128 129 /* Disable render condition. */ 130 if (rctx->current_render_cond) { 131 render_cond = rctx->current_render_cond; 132 render_cond_mode = rctx->current_render_cond_mode; 133 ctx->render_condition(ctx, NULL, 0); 134 } 135 136 r600_context_flush(rctx, flags); 137 138 /* Re-enable render condition. */ 139 if (render_cond) { 140 ctx->render_condition(ctx, render_cond, render_cond_mode); 141 } 142} 143 144static void r600_flush_from_st(struct pipe_context *ctx, 145 struct pipe_fence_handle **fence) 146{ 147 r600_flush(ctx, fence, 0); 148} 149 150static void r600_flush_from_winsys(void *ctx, unsigned flags) 151{ 152 r600_flush((struct pipe_context*)ctx, NULL, flags); 153} 154 155static void r600_destroy_context(struct pipe_context *context) 156{ 157 struct r600_context *rctx = (struct r600_context *)context; 158 159 if (rctx->no_blend) { 160 rctx->context.delete_blend_state(&rctx->context, rctx->no_blend); 161 } 162 if (rctx->dummy_pixel_shader) { 163 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader); 164 } 165 if (rctx->custom_dsa_flush) { 166 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 167 } 168 if (rctx->custom_blend_resolve) { 169 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve); 170 } 171 if (rctx->custom_blend_decompress) { 172 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress); 173 } 174 util_unreference_framebuffer_state(&rctx->framebuffer); 175 176 r600_context_fini(rctx); 177 178 if (rctx->blitter) { 179 util_blitter_destroy(rctx->blitter); 180 } 181 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 182 free(rctx->states[i]); 183 } 184 185 if (rctx->uploader) { 186 u_upload_destroy(rctx->uploader); 187 } 188 util_slab_destroy(&rctx->pool_transfers); 189 190 r600_release_command_buffer(&rctx->start_cs_cmd); 191 192 if (rctx->cs) { 193 rctx->ws->cs_destroy(rctx->cs); 194 } 195 196 FREE(rctx->range); 197 FREE(rctx); 198} 199 200static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 201{ 202 struct r600_context *rctx = CALLOC_STRUCT(r600_context); 203 struct r600_screen* rscreen = (struct r600_screen *)screen; 204 struct pipe_blend_state no_blend = {}; 205 206 if (rctx == NULL) 207 return NULL; 208 209 util_slab_create(&rctx->pool_transfers, 210 sizeof(struct r600_transfer), 64, 211 UTIL_SLAB_SINGLETHREADED); 212 213 rctx->context.screen = screen; 214 rctx->context.priv = priv; 215 rctx->context.destroy = r600_destroy_context; 216 rctx->context.flush = r600_flush_from_st; 217 218 /* Easy accessing of screen/winsys. */ 219 rctx->screen = rscreen; 220 rctx->ws = rscreen->ws; 221 rctx->family = rscreen->family; 222 rctx->chip_class = rscreen->chip_class; 223 224 LIST_INITHEAD(&rctx->dirty_states); 225 LIST_INITHEAD(&rctx->active_timer_queries); 226 LIST_INITHEAD(&rctx->active_nontimer_queries); 227 LIST_INITHEAD(&rctx->dirty); 228 LIST_INITHEAD(&rctx->enable_list); 229 230 rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range)); 231 if (!rctx->range) 232 goto fail; 233 234 r600_init_blit_functions(rctx); 235 r600_init_query_functions(rctx); 236 r600_init_context_resource_functions(rctx); 237 r600_init_surface_functions(rctx); 238 rctx->context.draw_vbo = r600_draw_vbo; 239 240 rctx->context.create_video_decoder = vl_create_decoder; 241 rctx->context.create_video_buffer = vl_video_buffer_create; 242 243 r600_init_common_atoms(rctx); 244 245 switch (rctx->chip_class) { 246 case R600: 247 case R700: 248 r600_init_state_functions(rctx); 249 r600_init_atom_start_cs(rctx); 250 if (r600_context_init(rctx)) 251 goto fail; 252 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 253 rctx->custom_blend_resolve = r600_create_resolve_blend(rctx); 254 rctx->custom_blend_decompress = r600_create_decompress_blend(rctx); 255 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 || 256 rctx->family == CHIP_RV620 || 257 rctx->family == CHIP_RS780 || 258 rctx->family == CHIP_RS880 || 259 rctx->family == CHIP_RV710); 260 break; 261 case EVERGREEN: 262 case CAYMAN: 263 evergreen_init_state_functions(rctx); 264 evergreen_init_atom_start_cs(rctx); 265 evergreen_init_atom_start_compute_cs(rctx); 266 if (evergreen_context_init(rctx)) 267 goto fail; 268 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 269 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx); 270 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx); 271 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR || 272 rctx->family == CHIP_PALM || 273 rctx->family == CHIP_SUMO || 274 rctx->family == CHIP_SUMO2 || 275 rctx->family == CHIP_CAICOS || 276 rctx->family == CHIP_CAYMAN || 277 rctx->family == CHIP_ARUBA); 278 break; 279 default: 280 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); 281 goto fail; 282 } 283 284 rctx->cs = rctx->ws->cs_create(rctx->ws); 285 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx); 286 r600_emit_atom(rctx, &rctx->start_cs_cmd.atom); 287 288 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256, 289 PIPE_BIND_INDEX_BUFFER | 290 PIPE_BIND_CONSTANT_BUFFER); 291 if (!rctx->uploader) 292 goto fail; 293 294 rctx->blitter = util_blitter_create(&rctx->context); 295 if (rctx->blitter == NULL) 296 goto fail; 297 rctx->blitter->draw_rectangle = r600_draw_rectangle; 298 299 r600_get_backend_mask(rctx); /* this emits commands and must be last */ 300 301 if (rctx->chip_class == R600) 302 r600_set_max_scissor(rctx); 303 304 rctx->dummy_pixel_shader = 305 util_make_fragment_cloneinput_shader(&rctx->context, 0, 306 TGSI_SEMANTIC_GENERIC, 307 TGSI_INTERPOLATE_CONSTANT); 308 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader); 309 310 no_blend.rt[0].colormask = 0xF; 311 rctx->no_blend = rctx->context.create_blend_state(&rctx->context, &no_blend); 312 313 return &rctx->context; 314 315fail: 316 r600_destroy_context(&rctx->context); 317 return NULL; 318} 319 320/* 321 * pipe_screen 322 */ 323static const char* r600_get_vendor(struct pipe_screen* pscreen) 324{ 325 return "X.Org"; 326} 327 328static const char *r600_get_family_name(enum radeon_family family) 329{ 330 switch(family) { 331 case CHIP_R600: return "AMD R600"; 332 case CHIP_RV610: return "AMD RV610"; 333 case CHIP_RV630: return "AMD RV630"; 334 case CHIP_RV670: return "AMD RV670"; 335 case CHIP_RV620: return "AMD RV620"; 336 case CHIP_RV635: return "AMD RV635"; 337 case CHIP_RS780: return "AMD RS780"; 338 case CHIP_RS880: return "AMD RS880"; 339 case CHIP_RV770: return "AMD RV770"; 340 case CHIP_RV730: return "AMD RV730"; 341 case CHIP_RV710: return "AMD RV710"; 342 case CHIP_RV740: return "AMD RV740"; 343 case CHIP_CEDAR: return "AMD CEDAR"; 344 case CHIP_REDWOOD: return "AMD REDWOOD"; 345 case CHIP_JUNIPER: return "AMD JUNIPER"; 346 case CHIP_CYPRESS: return "AMD CYPRESS"; 347 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 348 case CHIP_PALM: return "AMD PALM"; 349 case CHIP_SUMO: return "AMD SUMO"; 350 case CHIP_SUMO2: return "AMD SUMO2"; 351 case CHIP_BARTS: return "AMD BARTS"; 352 case CHIP_TURKS: return "AMD TURKS"; 353 case CHIP_CAICOS: return "AMD CAICOS"; 354 case CHIP_CAYMAN: return "AMD CAYMAN"; 355 case CHIP_ARUBA: return "AMD ARUBA"; 356 default: return "AMD unknown"; 357 } 358} 359 360static const char* r600_get_name(struct pipe_screen* pscreen) 361{ 362 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 363 364 return r600_get_family_name(rscreen->family); 365} 366 367static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 368{ 369 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 370 enum radeon_family family = rscreen->family; 371 372 switch (param) { 373 /* Supported features (boolean caps). */ 374 case PIPE_CAP_NPOT_TEXTURES: 375 case PIPE_CAP_TWO_SIDED_STENCIL: 376 case PIPE_CAP_ANISOTROPIC_FILTER: 377 case PIPE_CAP_POINT_SPRITE: 378 case PIPE_CAP_OCCLUSION_QUERY: 379 case PIPE_CAP_TEXTURE_SHADOW_MAP: 380 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 381 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 382 case PIPE_CAP_TEXTURE_SWIZZLE: 383 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 384 case PIPE_CAP_DEPTH_CLIP_DISABLE: 385 case PIPE_CAP_SHADER_STENCIL_EXPORT: 386 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 387 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 388 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 389 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 390 case PIPE_CAP_SM3: 391 case PIPE_CAP_SEAMLESS_CUBE_MAP: 392 case PIPE_CAP_PRIMITIVE_RESTART: 393 case PIPE_CAP_CONDITIONAL_RENDER: 394 case PIPE_CAP_TEXTURE_BARRIER: 395 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 396 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 397 case PIPE_CAP_TGSI_INSTANCEID: 398 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 399 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 400 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 401 case PIPE_CAP_USER_INDEX_BUFFERS: 402 case PIPE_CAP_USER_CONSTANT_BUFFERS: 403 case PIPE_CAP_COMPUTE: 404 case PIPE_CAP_START_INSTANCE: 405 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 406 return 1; 407 408 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 409 return 256; 410 411 case PIPE_CAP_GLSL_FEATURE_LEVEL: 412 return 130; 413 414 /* Supported except the original R600. */ 415 case PIPE_CAP_INDEP_BLEND_ENABLE: 416 case PIPE_CAP_INDEP_BLEND_FUNC: 417 /* R600 doesn't support per-MRT blends */ 418 return family == CHIP_R600 ? 0 : 1; 419 420 /* Supported on Evergreen. */ 421 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 422 return family >= CHIP_CEDAR ? 1 : 0; 423 424 /* Unsupported features. */ 425 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 426 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 427 case PIPE_CAP_SCALED_RESOLVE: 428 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 429 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 430 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 431 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 432 case PIPE_CAP_USER_VERTEX_BUFFERS: 433 return 0; 434 435 /* Stream output. */ 436 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 437 return rscreen->has_streamout ? 4 : 0; 438 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 439 return rscreen->has_streamout ? 1 : 0; 440 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 441 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 442 return 16*4; 443 444 /* Texturing. */ 445 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 446 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 447 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 448 if (family >= CHIP_CEDAR) 449 return 15; 450 else 451 return 14; 452 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 453 return rscreen->info.drm_minor >= 9 ? 454 (family >= CHIP_CEDAR ? 16384 : 8192) : 0; 455 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 456 return 32; 457 458 /* Render targets. */ 459 case PIPE_CAP_MAX_RENDER_TARGETS: 460 /* XXX some r6xx are buggy and can only do 4 */ 461 return 8; 462 463 /* Timer queries, present when the clock frequency is non zero. */ 464 case PIPE_CAP_TIMER_QUERY: 465 return rscreen->info.r600_clock_crystal_freq != 0; 466 case PIPE_CAP_QUERY_TIMESTAMP: 467 return rscreen->info.drm_minor >= 20 && 468 rscreen->info.r600_clock_crystal_freq != 0; 469 470 case PIPE_CAP_MIN_TEXEL_OFFSET: 471 return -8; 472 473 case PIPE_CAP_MAX_TEXEL_OFFSET: 474 return 7; 475 } 476 return 0; 477} 478 479static float r600_get_paramf(struct pipe_screen* pscreen, 480 enum pipe_capf param) 481{ 482 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 483 enum radeon_family family = rscreen->family; 484 485 switch (param) { 486 case PIPE_CAPF_MAX_LINE_WIDTH: 487 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 488 case PIPE_CAPF_MAX_POINT_WIDTH: 489 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 490 if (family >= CHIP_CEDAR) 491 return 16384.0f; 492 else 493 return 8192.0f; 494 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 495 return 16.0f; 496 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 497 return 16.0f; 498 case PIPE_CAPF_GUARD_BAND_LEFT: 499 case PIPE_CAPF_GUARD_BAND_TOP: 500 case PIPE_CAPF_GUARD_BAND_RIGHT: 501 case PIPE_CAPF_GUARD_BAND_BOTTOM: 502 return 0.0f; 503 } 504 return 0.0f; 505} 506 507static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 508{ 509 switch(shader) 510 { 511 case PIPE_SHADER_FRAGMENT: 512 case PIPE_SHADER_VERTEX: 513 case PIPE_SHADER_COMPUTE: 514 break; 515 case PIPE_SHADER_GEOMETRY: 516 /* XXX: support and enable geometry programs */ 517 return 0; 518 default: 519 /* XXX: support tessellation on Evergreen */ 520 return 0; 521 } 522 523 /* XXX: all these should be fixed, since r600 surely supports much more! */ 524 switch (param) { 525 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 526 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 527 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 528 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 529 return 16384; 530 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 531 return 8; /* XXX */ 532 case PIPE_SHADER_CAP_MAX_INPUTS: 533 if(shader == PIPE_SHADER_FRAGMENT) 534 return 34; 535 else 536 return 32; 537 case PIPE_SHADER_CAP_MAX_TEMPS: 538 return 256; /* Max native temporaries. */ 539 case PIPE_SHADER_CAP_MAX_ADDRS: 540 /* XXX Isn't this equal to TEMPS? */ 541 return 1; /* Max native address registers */ 542 case PIPE_SHADER_CAP_MAX_CONSTS: 543 return R600_MAX_CONST_BUFFER_SIZE; 544 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 545 return R600_MAX_CONST_BUFFERS-1; 546 case PIPE_SHADER_CAP_MAX_PREDS: 547 return 0; /* nothing uses this */ 548 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 549 return 1; 550 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 551 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 552 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 553 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 554 return 1; 555 case PIPE_SHADER_CAP_SUBROUTINES: 556 return 0; 557 case PIPE_SHADER_CAP_INTEGERS: 558 return 1; 559 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 560 return 16; 561 case PIPE_SHADER_CAP_PREFERRED_IR: 562 if (shader == PIPE_SHADER_COMPUTE) { 563 return PIPE_SHADER_IR_LLVM; 564 } else { 565 return PIPE_SHADER_IR_TGSI; 566 } 567 } 568 return 0; 569} 570 571static int r600_get_video_param(struct pipe_screen *screen, 572 enum pipe_video_profile profile, 573 enum pipe_video_cap param) 574{ 575 switch (param) { 576 case PIPE_VIDEO_CAP_SUPPORTED: 577 return vl_profile_supported(screen, profile); 578 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 579 return 1; 580 case PIPE_VIDEO_CAP_MAX_WIDTH: 581 case PIPE_VIDEO_CAP_MAX_HEIGHT: 582 return vl_video_buffer_max_size(screen); 583 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 584 return PIPE_FORMAT_NV12; 585 case PIPE_VIDEO_CAP_PREFERS_INTERLACED: 586 return false; 587 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: 588 return false; 589 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: 590 return true; 591 default: 592 return 0; 593 } 594} 595 596static int r600_get_compute_param(struct pipe_screen *screen, 597 enum pipe_compute_cap param, 598 void *ret) 599{ 600 //TODO: select these params by asic 601 switch (param) { 602 case PIPE_COMPUTE_CAP_IR_TARGET: 603 if (ret) { 604 strcpy(ret, "r600--"); 605 } 606 return 7 * sizeof(char); 607 608 case PIPE_COMPUTE_CAP_GRID_DIMENSION: 609 if (ret) { 610 uint64_t * grid_dimension = ret; 611 grid_dimension[0] = 3; 612 } 613 return 1 * sizeof(uint64_t); 614 615 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: 616 if (ret) { 617 uint64_t * grid_size = ret; 618 grid_size[0] = 65535; 619 grid_size[1] = 65535; 620 grid_size[2] = 1; 621 } 622 return 3 * sizeof(uint64_t) ; 623 624 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: 625 if (ret) { 626 uint64_t * block_size = ret; 627 block_size[0] = 256; 628 block_size[1] = 256; 629 block_size[2] = 256; 630 } 631 return 3 * sizeof(uint64_t); 632 633 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: 634 if (ret) { 635 uint64_t * max_threads_per_block = ret; 636 *max_threads_per_block = 256; 637 } 638 return sizeof(uint64_t); 639 640 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: 641 if (ret) { 642 uint64_t * max_global_size = ret; 643 /* XXX: This is 64kb for now until we get the 644 * compute memory pool working correctly. 645 */ 646 *max_global_size = 1024 * 16 * 4; 647 } 648 return sizeof(uint64_t); 649 650 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: 651 if (ret) { 652 uint64_t * max_input_size = ret; 653 *max_input_size = 1024; 654 } 655 return sizeof(uint64_t); 656 657 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: 658 if (ret) { 659 uint64_t * max_local_size = ret; 660 /* XXX: This is what the proprietary driver reports, we 661 * may want to use a different value. */ 662 *max_local_size = 32768; 663 } 664 return sizeof(uint64_t); 665 666 default: 667 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param); 668 return 0; 669 } 670} 671 672static void r600_destroy_screen(struct pipe_screen* pscreen) 673{ 674 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 675 676 if (rscreen == NULL) 677 return; 678 679 if (rscreen->global_pool) { 680 compute_memory_pool_delete(rscreen->global_pool); 681 } 682 683 if (rscreen->fences.bo) { 684 struct r600_fence_block *entry, *tmp; 685 686 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) { 687 LIST_DEL(&entry->head); 688 FREE(entry); 689 } 690 691 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf); 692 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL); 693 } 694 pipe_mutex_destroy(rscreen->fences.mutex); 695 696 rscreen->ws->destroy(rscreen->ws); 697 FREE(rscreen); 698} 699 700static void r600_fence_reference(struct pipe_screen *pscreen, 701 struct pipe_fence_handle **ptr, 702 struct pipe_fence_handle *fence) 703{ 704 struct r600_fence **oldf = (struct r600_fence**)ptr; 705 struct r600_fence *newf = (struct r600_fence*)fence; 706 707 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 708 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 709 pipe_mutex_lock(rscreen->fences.mutex); 710 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL); 711 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool); 712 pipe_mutex_unlock(rscreen->fences.mutex); 713 } 714 715 *ptr = fence; 716} 717 718static boolean r600_fence_signalled(struct pipe_screen *pscreen, 719 struct pipe_fence_handle *fence) 720{ 721 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 722 struct r600_fence *rfence = (struct r600_fence*)fence; 723 724 return rscreen->fences.data[rfence->index]; 725} 726 727static boolean r600_fence_finish(struct pipe_screen *pscreen, 728 struct pipe_fence_handle *fence, 729 uint64_t timeout) 730{ 731 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 732 struct r600_fence *rfence = (struct r600_fence*)fence; 733 int64_t start_time = 0; 734 unsigned spins = 0; 735 736 if (timeout != PIPE_TIMEOUT_INFINITE) { 737 start_time = os_time_get(); 738 739 /* Convert to microseconds. */ 740 timeout /= 1000; 741 } 742 743 while (rscreen->fences.data[rfence->index] == 0) { 744 /* Special-case infinite timeout - wait for the dummy BO to become idle */ 745 if (timeout == PIPE_TIMEOUT_INFINITE) { 746 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE); 747 break; 748 } 749 750 /* The dummy BO will be busy until the CS including the fence has completed, or 751 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */ 752 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE)) 753 break; 754 755 if (++spins % 256) 756 continue; 757#ifdef PIPE_OS_UNIX 758 sched_yield(); 759#else 760 os_time_sleep(10); 761#endif 762 if (timeout != PIPE_TIMEOUT_INFINITE && 763 os_time_get() - start_time >= timeout) { 764 break; 765 } 766 } 767 768 return rscreen->fences.data[rfence->index] != 0; 769} 770 771static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 772{ 773 switch ((tiling_config & 0xe) >> 1) { 774 case 0: 775 rscreen->tiling_info.num_channels = 1; 776 break; 777 case 1: 778 rscreen->tiling_info.num_channels = 2; 779 break; 780 case 2: 781 rscreen->tiling_info.num_channels = 4; 782 break; 783 case 3: 784 rscreen->tiling_info.num_channels = 8; 785 break; 786 default: 787 return -EINVAL; 788 } 789 790 switch ((tiling_config & 0x30) >> 4) { 791 case 0: 792 rscreen->tiling_info.num_banks = 4; 793 break; 794 case 1: 795 rscreen->tiling_info.num_banks = 8; 796 break; 797 default: 798 return -EINVAL; 799 800 } 801 switch ((tiling_config & 0xc0) >> 6) { 802 case 0: 803 rscreen->tiling_info.group_bytes = 256; 804 break; 805 case 1: 806 rscreen->tiling_info.group_bytes = 512; 807 break; 808 default: 809 return -EINVAL; 810 } 811 return 0; 812} 813 814static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 815{ 816 switch (tiling_config & 0xf) { 817 case 0: 818 rscreen->tiling_info.num_channels = 1; 819 break; 820 case 1: 821 rscreen->tiling_info.num_channels = 2; 822 break; 823 case 2: 824 rscreen->tiling_info.num_channels = 4; 825 break; 826 case 3: 827 rscreen->tiling_info.num_channels = 8; 828 break; 829 default: 830 return -EINVAL; 831 } 832 833 switch ((tiling_config & 0xf0) >> 4) { 834 case 0: 835 rscreen->tiling_info.num_banks = 4; 836 break; 837 case 1: 838 rscreen->tiling_info.num_banks = 8; 839 break; 840 case 2: 841 rscreen->tiling_info.num_banks = 16; 842 break; 843 default: 844 return -EINVAL; 845 } 846 847 switch ((tiling_config & 0xf00) >> 8) { 848 case 0: 849 rscreen->tiling_info.group_bytes = 256; 850 break; 851 case 1: 852 rscreen->tiling_info.group_bytes = 512; 853 break; 854 default: 855 return -EINVAL; 856 } 857 return 0; 858} 859 860static int r600_init_tiling(struct r600_screen *rscreen) 861{ 862 uint32_t tiling_config = rscreen->info.r600_tiling_config; 863 864 /* set default group bytes, overridden by tiling info ioctl */ 865 if (rscreen->chip_class <= R700) { 866 rscreen->tiling_info.group_bytes = 256; 867 } else { 868 rscreen->tiling_info.group_bytes = 512; 869 } 870 871 if (!tiling_config) 872 return 0; 873 874 if (rscreen->chip_class <= R700) { 875 return r600_interpret_tiling(rscreen, tiling_config); 876 } else { 877 return evergreen_interpret_tiling(rscreen, tiling_config); 878 } 879} 880 881static unsigned radeon_family_from_device(unsigned device) 882{ 883 switch (device) { 884#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; 885#include "pci_ids/r600_pci_ids.h" 886#undef CHIPSET 887 default: 888 return CHIP_UNKNOWN; 889 } 890} 891 892static uint64_t r600_get_timestamp(struct pipe_screen *screen) 893{ 894 struct r600_screen *rscreen = (struct r600_screen*)screen; 895 896 return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) / 897 rscreen->info.r600_clock_crystal_freq; 898} 899 900struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) 901{ 902 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); 903 904 if (rscreen == NULL) { 905 return NULL; 906 } 907 908 rscreen->ws = ws; 909 ws->query_info(ws, &rscreen->info); 910 911 rscreen->family = radeon_family_from_device(rscreen->info.pci_id); 912 if (rscreen->family == CHIP_UNKNOWN) { 913 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); 914 FREE(rscreen); 915 return NULL; 916 } 917 918 /* setup class */ 919 if (rscreen->family >= CHIP_CAYMAN) { 920 rscreen->chip_class = CAYMAN; 921 } else if (rscreen->family >= CHIP_CEDAR) { 922 rscreen->chip_class = EVERGREEN; 923 } else if (rscreen->family >= CHIP_RV770) { 924 rscreen->chip_class = R700; 925 } else { 926 rscreen->chip_class = R600; 927 } 928 929 /* Figure out streamout kernel support. */ 930 switch (rscreen->chip_class) { 931 case R600: 932 case EVERGREEN: 933 rscreen->has_streamout = rscreen->info.drm_minor >= 14; 934 break; 935 case R700: 936 rscreen->has_streamout = rscreen->info.drm_minor >= 17; 937 break; 938 /* TODO: Cayman */ 939 default: 940 rscreen->has_streamout = debug_get_bool_option("R600_STREAMOUT", FALSE); 941 } 942 943 if (r600_init_tiling(rscreen)) { 944 FREE(rscreen); 945 return NULL; 946 } 947 948 rscreen->screen.destroy = r600_destroy_screen; 949 rscreen->screen.get_name = r600_get_name; 950 rscreen->screen.get_vendor = r600_get_vendor; 951 rscreen->screen.get_param = r600_get_param; 952 rscreen->screen.get_shader_param = r600_get_shader_param; 953 rscreen->screen.get_paramf = r600_get_paramf; 954 rscreen->screen.get_video_param = r600_get_video_param; 955 rscreen->screen.get_compute_param = r600_get_compute_param; 956 rscreen->screen.get_timestamp = r600_get_timestamp; 957 958 if (rscreen->chip_class >= EVERGREEN) { 959 rscreen->screen.is_format_supported = evergreen_is_format_supported; 960 } else { 961 rscreen->screen.is_format_supported = r600_is_format_supported; 962 } 963 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; 964 rscreen->screen.context_create = r600_create_context; 965 rscreen->screen.fence_reference = r600_fence_reference; 966 rscreen->screen.fence_signalled = r600_fence_signalled; 967 rscreen->screen.fence_finish = r600_fence_finish; 968 r600_init_screen_resource_functions(&rscreen->screen); 969 970 util_format_s3tc_init(); 971 972 rscreen->fences.bo = NULL; 973 rscreen->fences.data = NULL; 974 rscreen->fences.next_index = 0; 975 LIST_INITHEAD(&rscreen->fences.pool); 976 LIST_INITHEAD(&rscreen->fences.blocks); 977 pipe_mutex_init(rscreen->fences.mutex); 978 979 rscreen->global_pool = compute_memory_pool_new(rscreen); 980 981 return &rscreen->screen; 982} 983