r600_pipe.c revision a3d9d7ec79d6f7205fab2324e47d8ea185431de0
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_pipe.h" 24#include "r600_public.h" 25 26#include <errno.h> 27#include "pipe/p_shader_tokens.h" 28#include "util/u_blitter.h" 29#include "util/u_format_s3tc.h" 30#include "util/u_simple_shaders.h" 31#include "util/u_upload_mgr.h" 32#include "vl/vl_decoder.h" 33#include "vl/vl_video_buffer.h" 34#include "os/os_time.h" 35 36/* 37 * pipe_context 38 */ 39static struct r600_fence *r600_create_fence(struct r600_context *rctx) 40{ 41 struct r600_screen *rscreen = rctx->screen; 42 struct r600_fence *fence = NULL; 43 44 pipe_mutex_lock(rscreen->fences.mutex); 45 46 if (!rscreen->fences.bo) { 47 /* Create the shared buffer object */ 48 rscreen->fences.bo = (struct r600_resource*) 49 pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM, 50 PIPE_USAGE_STAGING, 4096); 51 if (!rscreen->fences.bo) { 52 R600_ERR("r600: failed to create bo for fence objects\n"); 53 goto out; 54 } 55 rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->cs_buf, 56 rctx->cs, 57 PIPE_TRANSFER_READ_WRITE); 58 } 59 60 if (!LIST_IS_EMPTY(&rscreen->fences.pool)) { 61 struct r600_fence *entry; 62 63 /* Try to find a freed fence that has been signalled */ 64 LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) { 65 if (rscreen->fences.data[entry->index] != 0) { 66 LIST_DELINIT(&entry->head); 67 fence = entry; 68 break; 69 } 70 } 71 } 72 73 if (!fence) { 74 /* Allocate a new fence */ 75 struct r600_fence_block *block; 76 unsigned index; 77 78 if ((rscreen->fences.next_index + 1) >= 1024) { 79 R600_ERR("r600: too many concurrent fences\n"); 80 goto out; 81 } 82 83 index = rscreen->fences.next_index++; 84 85 if (!(index % FENCE_BLOCK_SIZE)) { 86 /* Allocate a new block */ 87 block = CALLOC_STRUCT(r600_fence_block); 88 if (block == NULL) 89 goto out; 90 91 LIST_ADD(&block->head, &rscreen->fences.blocks); 92 } else { 93 block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head); 94 } 95 96 fence = &block->fences[index % FENCE_BLOCK_SIZE]; 97 fence->index = index; 98 } 99 100 pipe_reference_init(&fence->reference, 1); 101 102 rscreen->fences.data[fence->index] = 0; 103 r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1); 104 105 /* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */ 106 fence->sleep_bo = (struct r600_resource*) 107 pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM, 108 PIPE_USAGE_STAGING, 1); 109 /* Add the fence as a dummy relocation. */ 110 r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE); 111 112out: 113 pipe_mutex_unlock(rscreen->fences.mutex); 114 return fence; 115} 116 117 118void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 119 unsigned flags) 120{ 121 struct r600_context *rctx = (struct r600_context *)ctx; 122 struct r600_fence **rfence = (struct r600_fence**)fence; 123 struct pipe_query *render_cond = NULL; 124 unsigned render_cond_mode = 0; 125 126 if (rfence) 127 *rfence = r600_create_fence(rctx); 128 129 /* Disable render condition. */ 130 if (rctx->current_render_cond) { 131 render_cond = rctx->current_render_cond; 132 render_cond_mode = rctx->current_render_cond_mode; 133 ctx->render_condition(ctx, NULL, 0); 134 } 135 136 r600_context_flush(rctx, flags); 137 138 /* Re-enable render condition. */ 139 if (render_cond) { 140 ctx->render_condition(ctx, render_cond, render_cond_mode); 141 } 142} 143 144static void r600_flush_from_st(struct pipe_context *ctx, 145 struct pipe_fence_handle **fence) 146{ 147 r600_flush(ctx, fence, 0); 148} 149 150static void r600_flush_from_winsys(void *ctx, unsigned flags) 151{ 152 r600_flush((struct pipe_context*)ctx, NULL, flags); 153} 154 155static void r600_destroy_context(struct pipe_context *context) 156{ 157 struct r600_context *rctx = (struct r600_context *)context; 158 159 if (rctx->no_blend) { 160 rctx->context.delete_blend_state(&rctx->context, rctx->no_blend); 161 } 162 if (rctx->dummy_pixel_shader) { 163 rctx->context.delete_fs_state(&rctx->context, rctx->dummy_pixel_shader); 164 } 165 if (rctx->custom_dsa_flush) { 166 rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush); 167 } 168 if (rctx->custom_blend_resolve) { 169 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_resolve); 170 } 171 if (rctx->custom_blend_decompress) { 172 rctx->context.delete_blend_state(&rctx->context, rctx->custom_blend_decompress); 173 } 174 util_unreference_framebuffer_state(&rctx->framebuffer); 175 176 r600_context_fini(rctx); 177 178 if (rctx->blitter) { 179 util_blitter_destroy(rctx->blitter); 180 } 181 for (int i = 0; i < R600_PIPE_NSTATES; i++) { 182 free(rctx->states[i]); 183 } 184 185 if (rctx->uploader) { 186 u_upload_destroy(rctx->uploader); 187 } 188 util_slab_destroy(&rctx->pool_transfers); 189 190 r600_release_command_buffer(&rctx->start_cs_cmd); 191 192 if (rctx->cs) { 193 rctx->ws->cs_destroy(rctx->cs); 194 } 195 196 FREE(rctx->range); 197 FREE(rctx); 198} 199 200static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv) 201{ 202 struct r600_context *rctx = CALLOC_STRUCT(r600_context); 203 struct r600_screen* rscreen = (struct r600_screen *)screen; 204 struct pipe_blend_state no_blend = {}; 205 206 if (rctx == NULL) 207 return NULL; 208 209 util_slab_create(&rctx->pool_transfers, 210 sizeof(struct r600_transfer), 64, 211 UTIL_SLAB_SINGLETHREADED); 212 213 rctx->context.screen = screen; 214 rctx->context.priv = priv; 215 rctx->context.destroy = r600_destroy_context; 216 rctx->context.flush = r600_flush_from_st; 217 218 /* Easy accessing of screen/winsys. */ 219 rctx->screen = rscreen; 220 rctx->ws = rscreen->ws; 221 rctx->family = rscreen->family; 222 rctx->chip_class = rscreen->chip_class; 223 224 LIST_INITHEAD(&rctx->dirty_states); 225 LIST_INITHEAD(&rctx->active_timer_queries); 226 LIST_INITHEAD(&rctx->active_nontimer_queries); 227 LIST_INITHEAD(&rctx->dirty); 228 LIST_INITHEAD(&rctx->enable_list); 229 230 rctx->range = CALLOC(NUM_RANGES, sizeof(struct r600_range)); 231 if (!rctx->range) 232 goto fail; 233 234 r600_init_blit_functions(rctx); 235 r600_init_query_functions(rctx); 236 r600_init_context_resource_functions(rctx); 237 r600_init_surface_functions(rctx); 238 rctx->context.draw_vbo = r600_draw_vbo; 239 240 rctx->context.create_video_decoder = vl_create_decoder; 241 rctx->context.create_video_buffer = vl_video_buffer_create; 242 243 r600_init_common_atoms(rctx); 244 245 switch (rctx->chip_class) { 246 case R600: 247 case R700: 248 r600_init_state_functions(rctx); 249 r600_init_atom_start_cs(rctx); 250 if (r600_context_init(rctx)) 251 goto fail; 252 rctx->custom_dsa_flush = r600_create_db_flush_dsa(rctx); 253 rctx->has_vertex_cache = !(rctx->family == CHIP_RV610 || 254 rctx->family == CHIP_RV620 || 255 rctx->family == CHIP_RS780 || 256 rctx->family == CHIP_RS880 || 257 rctx->family == CHIP_RV710); 258 break; 259 case EVERGREEN: 260 case CAYMAN: 261 evergreen_init_state_functions(rctx); 262 evergreen_init_atom_start_cs(rctx); 263 evergreen_init_atom_start_compute_cs(rctx); 264 if (evergreen_context_init(rctx)) 265 goto fail; 266 rctx->custom_dsa_flush = evergreen_create_db_flush_dsa(rctx); 267 rctx->custom_blend_resolve = evergreen_create_resolve_blend(rctx); 268 rctx->custom_blend_decompress = evergreen_create_decompress_blend(rctx); 269 rctx->has_vertex_cache = !(rctx->family == CHIP_CEDAR || 270 rctx->family == CHIP_PALM || 271 rctx->family == CHIP_SUMO || 272 rctx->family == CHIP_SUMO2 || 273 rctx->family == CHIP_CAICOS || 274 rctx->family == CHIP_CAYMAN || 275 rctx->family == CHIP_ARUBA); 276 break; 277 default: 278 R600_ERR("Unsupported chip class %d.\n", rctx->chip_class); 279 goto fail; 280 } 281 282 rctx->cs = rctx->ws->cs_create(rctx->ws); 283 rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx); 284 r600_emit_atom(rctx, &rctx->start_cs_cmd.atom); 285 286 rctx->uploader = u_upload_create(&rctx->context, 1024 * 1024, 256, 287 PIPE_BIND_INDEX_BUFFER | 288 PIPE_BIND_CONSTANT_BUFFER); 289 if (!rctx->uploader) 290 goto fail; 291 292 rctx->blitter = util_blitter_create(&rctx->context); 293 if (rctx->blitter == NULL) 294 goto fail; 295 296 r600_get_backend_mask(rctx); /* this emits commands and must be last */ 297 298 if (rctx->chip_class == R600) 299 r600_set_max_scissor(rctx); 300 301 rctx->dummy_pixel_shader = 302 util_make_fragment_cloneinput_shader(&rctx->context, 0, 303 TGSI_SEMANTIC_GENERIC, 304 TGSI_INTERPOLATE_CONSTANT); 305 rctx->context.bind_fs_state(&rctx->context, rctx->dummy_pixel_shader); 306 307 no_blend.rt[0].colormask = 0xF; 308 rctx->no_blend = rctx->context.create_blend_state(&rctx->context, &no_blend); 309 310 return &rctx->context; 311 312fail: 313 r600_destroy_context(&rctx->context); 314 return NULL; 315} 316 317/* 318 * pipe_screen 319 */ 320static const char* r600_get_vendor(struct pipe_screen* pscreen) 321{ 322 return "X.Org"; 323} 324 325static const char *r600_get_family_name(enum radeon_family family) 326{ 327 switch(family) { 328 case CHIP_R600: return "AMD R600"; 329 case CHIP_RV610: return "AMD RV610"; 330 case CHIP_RV630: return "AMD RV630"; 331 case CHIP_RV670: return "AMD RV670"; 332 case CHIP_RV620: return "AMD RV620"; 333 case CHIP_RV635: return "AMD RV635"; 334 case CHIP_RS780: return "AMD RS780"; 335 case CHIP_RS880: return "AMD RS880"; 336 case CHIP_RV770: return "AMD RV770"; 337 case CHIP_RV730: return "AMD RV730"; 338 case CHIP_RV710: return "AMD RV710"; 339 case CHIP_RV740: return "AMD RV740"; 340 case CHIP_CEDAR: return "AMD CEDAR"; 341 case CHIP_REDWOOD: return "AMD REDWOOD"; 342 case CHIP_JUNIPER: return "AMD JUNIPER"; 343 case CHIP_CYPRESS: return "AMD CYPRESS"; 344 case CHIP_HEMLOCK: return "AMD HEMLOCK"; 345 case CHIP_PALM: return "AMD PALM"; 346 case CHIP_SUMO: return "AMD SUMO"; 347 case CHIP_SUMO2: return "AMD SUMO2"; 348 case CHIP_BARTS: return "AMD BARTS"; 349 case CHIP_TURKS: return "AMD TURKS"; 350 case CHIP_CAICOS: return "AMD CAICOS"; 351 case CHIP_CAYMAN: return "AMD CAYMAN"; 352 case CHIP_ARUBA: return "AMD ARUBA"; 353 default: return "AMD unknown"; 354 } 355} 356 357static const char* r600_get_name(struct pipe_screen* pscreen) 358{ 359 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 360 361 return r600_get_family_name(rscreen->family); 362} 363 364static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) 365{ 366 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 367 enum radeon_family family = rscreen->family; 368 369 switch (param) { 370 /* Supported features (boolean caps). */ 371 case PIPE_CAP_NPOT_TEXTURES: 372 case PIPE_CAP_TWO_SIDED_STENCIL: 373 case PIPE_CAP_ANISOTROPIC_FILTER: 374 case PIPE_CAP_POINT_SPRITE: 375 case PIPE_CAP_OCCLUSION_QUERY: 376 case PIPE_CAP_TEXTURE_SHADOW_MAP: 377 case PIPE_CAP_TEXTURE_MIRROR_CLAMP: 378 case PIPE_CAP_BLEND_EQUATION_SEPARATE: 379 case PIPE_CAP_TEXTURE_SWIZZLE: 380 case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE: 381 case PIPE_CAP_DEPTH_CLIP_DISABLE: 382 case PIPE_CAP_SHADER_STENCIL_EXPORT: 383 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: 384 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: 385 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: 386 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: 387 case PIPE_CAP_SM3: 388 case PIPE_CAP_SEAMLESS_CUBE_MAP: 389 case PIPE_CAP_PRIMITIVE_RESTART: 390 case PIPE_CAP_CONDITIONAL_RENDER: 391 case PIPE_CAP_TEXTURE_BARRIER: 392 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: 393 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: 394 case PIPE_CAP_TGSI_INSTANCEID: 395 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: 396 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: 397 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: 398 case PIPE_CAP_USER_INDEX_BUFFERS: 399 case PIPE_CAP_USER_CONSTANT_BUFFERS: 400 case PIPE_CAP_COMPUTE: 401 case PIPE_CAP_START_INSTANCE: 402 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: 403 return 1; 404 405 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: 406 return 256; 407 408 case PIPE_CAP_GLSL_FEATURE_LEVEL: 409 return 130; 410 411 /* Supported except the original R600. */ 412 case PIPE_CAP_INDEP_BLEND_ENABLE: 413 case PIPE_CAP_INDEP_BLEND_FUNC: 414 /* R600 doesn't support per-MRT blends */ 415 return family == CHIP_R600 ? 0 : 1; 416 417 /* Supported on Evergreen. */ 418 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: 419 return family >= CHIP_CEDAR ? 1 : 0; 420 421 /* Unsupported features. */ 422 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: 423 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: 424 case PIPE_CAP_SCALED_RESOLVE: 425 case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS: 426 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: 427 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: 428 case PIPE_CAP_VERTEX_COLOR_CLAMPED: 429 case PIPE_CAP_USER_VERTEX_BUFFERS: 430 return 0; 431 432 /* Stream output. */ 433 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: 434 return rscreen->has_streamout ? 4 : 0; 435 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: 436 return rscreen->has_streamout ? 1 : 0; 437 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: 438 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: 439 return 16*4; 440 441 /* Texturing. */ 442 case PIPE_CAP_MAX_TEXTURE_2D_LEVELS: 443 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS: 444 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS: 445 if (family >= CHIP_CEDAR) 446 return 15; 447 else 448 return 14; 449 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: 450 return rscreen->info.drm_minor >= 9 ? 451 (family >= CHIP_CEDAR ? 16384 : 8192) : 0; 452 case PIPE_CAP_MAX_COMBINED_SAMPLERS: 453 return 32; 454 455 /* Render targets. */ 456 case PIPE_CAP_MAX_RENDER_TARGETS: 457 /* XXX some r6xx are buggy and can only do 4 */ 458 return 8; 459 460 /* Timer queries, present when the clock frequency is non zero. */ 461 case PIPE_CAP_TIMER_QUERY: 462 return rscreen->info.r600_clock_crystal_freq != 0; 463 case PIPE_CAP_QUERY_TIMESTAMP: 464 return rscreen->info.drm_minor >= 20 && 465 rscreen->info.r600_clock_crystal_freq != 0; 466 467 case PIPE_CAP_MIN_TEXEL_OFFSET: 468 return -8; 469 470 case PIPE_CAP_MAX_TEXEL_OFFSET: 471 return 7; 472 } 473 return 0; 474} 475 476static float r600_get_paramf(struct pipe_screen* pscreen, 477 enum pipe_capf param) 478{ 479 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 480 enum radeon_family family = rscreen->family; 481 482 switch (param) { 483 case PIPE_CAPF_MAX_LINE_WIDTH: 484 case PIPE_CAPF_MAX_LINE_WIDTH_AA: 485 case PIPE_CAPF_MAX_POINT_WIDTH: 486 case PIPE_CAPF_MAX_POINT_WIDTH_AA: 487 if (family >= CHIP_CEDAR) 488 return 16384.0f; 489 else 490 return 8192.0f; 491 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY: 492 return 16.0f; 493 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS: 494 return 16.0f; 495 case PIPE_CAPF_GUARD_BAND_LEFT: 496 case PIPE_CAPF_GUARD_BAND_TOP: 497 case PIPE_CAPF_GUARD_BAND_RIGHT: 498 case PIPE_CAPF_GUARD_BAND_BOTTOM: 499 return 0.0f; 500 } 501 return 0.0f; 502} 503 504static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param) 505{ 506 switch(shader) 507 { 508 case PIPE_SHADER_FRAGMENT: 509 case PIPE_SHADER_VERTEX: 510 case PIPE_SHADER_COMPUTE: 511 break; 512 case PIPE_SHADER_GEOMETRY: 513 /* XXX: support and enable geometry programs */ 514 return 0; 515 default: 516 /* XXX: support tessellation on Evergreen */ 517 return 0; 518 } 519 520 /* XXX: all these should be fixed, since r600 surely supports much more! */ 521 switch (param) { 522 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS: 523 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS: 524 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS: 525 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS: 526 return 16384; 527 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: 528 return 8; /* XXX */ 529 case PIPE_SHADER_CAP_MAX_INPUTS: 530 if(shader == PIPE_SHADER_FRAGMENT) 531 return 34; 532 else 533 return 32; 534 case PIPE_SHADER_CAP_MAX_TEMPS: 535 return 256; /* Max native temporaries. */ 536 case PIPE_SHADER_CAP_MAX_ADDRS: 537 /* XXX Isn't this equal to TEMPS? */ 538 return 1; /* Max native address registers */ 539 case PIPE_SHADER_CAP_MAX_CONSTS: 540 return R600_MAX_CONST_BUFFER_SIZE; 541 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: 542 return R600_MAX_CONST_BUFFERS-1; 543 case PIPE_SHADER_CAP_MAX_PREDS: 544 return 0; /* nothing uses this */ 545 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: 546 return 1; 547 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: 548 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: 549 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR: 550 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR: 551 return 1; 552 case PIPE_SHADER_CAP_SUBROUTINES: 553 return 0; 554 case PIPE_SHADER_CAP_INTEGERS: 555 return 1; 556 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS: 557 return 16; 558 case PIPE_SHADER_CAP_PREFERRED_IR: 559 if (shader == PIPE_SHADER_COMPUTE) { 560 return PIPE_SHADER_IR_LLVM; 561 } else { 562 return PIPE_SHADER_IR_TGSI; 563 } 564 } 565 return 0; 566} 567 568static int r600_get_video_param(struct pipe_screen *screen, 569 enum pipe_video_profile profile, 570 enum pipe_video_cap param) 571{ 572 switch (param) { 573 case PIPE_VIDEO_CAP_SUPPORTED: 574 return vl_profile_supported(screen, profile); 575 case PIPE_VIDEO_CAP_NPOT_TEXTURES: 576 return 1; 577 case PIPE_VIDEO_CAP_MAX_WIDTH: 578 case PIPE_VIDEO_CAP_MAX_HEIGHT: 579 return vl_video_buffer_max_size(screen); 580 case PIPE_VIDEO_CAP_PREFERED_FORMAT: 581 return PIPE_FORMAT_NV12; 582 case PIPE_VIDEO_CAP_PREFERS_INTERLACED: 583 return false; 584 case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED: 585 return false; 586 case PIPE_VIDEO_CAP_SUPPORTS_PROGRESSIVE: 587 return true; 588 default: 589 return 0; 590 } 591} 592 593static int r600_get_compute_param(struct pipe_screen *screen, 594 enum pipe_compute_cap param, 595 void *ret) 596{ 597 //TODO: select these params by asic 598 switch (param) { 599 case PIPE_COMPUTE_CAP_IR_TARGET: 600 if (ret) { 601 strcpy(ret, "r600--"); 602 } 603 return 7 * sizeof(char); 604 605 case PIPE_COMPUTE_CAP_GRID_DIMENSION: 606 if (ret) { 607 uint64_t * grid_dimension = ret; 608 grid_dimension[0] = 3; 609 } 610 return 1 * sizeof(uint64_t); 611 612 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE: 613 if (ret) { 614 uint64_t * grid_size = ret; 615 grid_size[0] = 65535; 616 grid_size[1] = 65535; 617 grid_size[2] = 1; 618 } 619 return 3 * sizeof(uint64_t) ; 620 621 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE: 622 if (ret) { 623 uint64_t * block_size = ret; 624 block_size[0] = 256; 625 block_size[1] = 256; 626 block_size[2] = 256; 627 } 628 return 3 * sizeof(uint64_t); 629 630 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK: 631 if (ret) { 632 uint64_t * max_threads_per_block = ret; 633 *max_threads_per_block = 256; 634 } 635 return sizeof(uint64_t); 636 637 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: 638 if (ret) { 639 uint64_t * max_global_size = ret; 640 /* XXX: This is 64kb for now until we get the 641 * compute memory pool working correctly. 642 */ 643 *max_global_size = 1024 * 16 * 4; 644 } 645 return sizeof(uint64_t); 646 647 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: 648 if (ret) { 649 uint64_t * max_input_size = ret; 650 *max_input_size = 1024; 651 } 652 return sizeof(uint64_t); 653 654 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: 655 if (ret) { 656 uint64_t * max_local_size = ret; 657 /* XXX: This is what the proprietary driver reports, we 658 * may want to use a different value. */ 659 *max_local_size = 32768; 660 } 661 return sizeof(uint64_t); 662 663 default: 664 fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param); 665 return 0; 666 } 667} 668 669static void r600_destroy_screen(struct pipe_screen* pscreen) 670{ 671 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 672 673 if (rscreen == NULL) 674 return; 675 676 if (rscreen->global_pool) { 677 compute_memory_pool_delete(rscreen->global_pool); 678 } 679 680 if (rscreen->fences.bo) { 681 struct r600_fence_block *entry, *tmp; 682 683 LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) { 684 LIST_DEL(&entry->head); 685 FREE(entry); 686 } 687 688 rscreen->ws->buffer_unmap(rscreen->fences.bo->cs_buf); 689 pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL); 690 } 691 pipe_mutex_destroy(rscreen->fences.mutex); 692 693 rscreen->ws->destroy(rscreen->ws); 694 FREE(rscreen); 695} 696 697static void r600_fence_reference(struct pipe_screen *pscreen, 698 struct pipe_fence_handle **ptr, 699 struct pipe_fence_handle *fence) 700{ 701 struct r600_fence **oldf = (struct r600_fence**)ptr; 702 struct r600_fence *newf = (struct r600_fence*)fence; 703 704 if (pipe_reference(&(*oldf)->reference, &newf->reference)) { 705 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 706 pipe_mutex_lock(rscreen->fences.mutex); 707 pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL); 708 LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool); 709 pipe_mutex_unlock(rscreen->fences.mutex); 710 } 711 712 *ptr = fence; 713} 714 715static boolean r600_fence_signalled(struct pipe_screen *pscreen, 716 struct pipe_fence_handle *fence) 717{ 718 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 719 struct r600_fence *rfence = (struct r600_fence*)fence; 720 721 return rscreen->fences.data[rfence->index]; 722} 723 724static boolean r600_fence_finish(struct pipe_screen *pscreen, 725 struct pipe_fence_handle *fence, 726 uint64_t timeout) 727{ 728 struct r600_screen *rscreen = (struct r600_screen *)pscreen; 729 struct r600_fence *rfence = (struct r600_fence*)fence; 730 int64_t start_time = 0; 731 unsigned spins = 0; 732 733 if (timeout != PIPE_TIMEOUT_INFINITE) { 734 start_time = os_time_get(); 735 736 /* Convert to microseconds. */ 737 timeout /= 1000; 738 } 739 740 while (rscreen->fences.data[rfence->index] == 0) { 741 /* Special-case infinite timeout - wait for the dummy BO to become idle */ 742 if (timeout == PIPE_TIMEOUT_INFINITE) { 743 rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE); 744 break; 745 } 746 747 /* The dummy BO will be busy until the CS including the fence has completed, or 748 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */ 749 if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE)) 750 break; 751 752 if (++spins % 256) 753 continue; 754#ifdef PIPE_OS_UNIX 755 sched_yield(); 756#else 757 os_time_sleep(10); 758#endif 759 if (timeout != PIPE_TIMEOUT_INFINITE && 760 os_time_get() - start_time >= timeout) { 761 break; 762 } 763 } 764 765 return rscreen->fences.data[rfence->index] != 0; 766} 767 768static int r600_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 769{ 770 switch ((tiling_config & 0xe) >> 1) { 771 case 0: 772 rscreen->tiling_info.num_channels = 1; 773 break; 774 case 1: 775 rscreen->tiling_info.num_channels = 2; 776 break; 777 case 2: 778 rscreen->tiling_info.num_channels = 4; 779 break; 780 case 3: 781 rscreen->tiling_info.num_channels = 8; 782 break; 783 default: 784 return -EINVAL; 785 } 786 787 switch ((tiling_config & 0x30) >> 4) { 788 case 0: 789 rscreen->tiling_info.num_banks = 4; 790 break; 791 case 1: 792 rscreen->tiling_info.num_banks = 8; 793 break; 794 default: 795 return -EINVAL; 796 797 } 798 switch ((tiling_config & 0xc0) >> 6) { 799 case 0: 800 rscreen->tiling_info.group_bytes = 256; 801 break; 802 case 1: 803 rscreen->tiling_info.group_bytes = 512; 804 break; 805 default: 806 return -EINVAL; 807 } 808 return 0; 809} 810 811static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config) 812{ 813 switch (tiling_config & 0xf) { 814 case 0: 815 rscreen->tiling_info.num_channels = 1; 816 break; 817 case 1: 818 rscreen->tiling_info.num_channels = 2; 819 break; 820 case 2: 821 rscreen->tiling_info.num_channels = 4; 822 break; 823 case 3: 824 rscreen->tiling_info.num_channels = 8; 825 break; 826 default: 827 return -EINVAL; 828 } 829 830 switch ((tiling_config & 0xf0) >> 4) { 831 case 0: 832 rscreen->tiling_info.num_banks = 4; 833 break; 834 case 1: 835 rscreen->tiling_info.num_banks = 8; 836 break; 837 case 2: 838 rscreen->tiling_info.num_banks = 16; 839 break; 840 default: 841 return -EINVAL; 842 } 843 844 switch ((tiling_config & 0xf00) >> 8) { 845 case 0: 846 rscreen->tiling_info.group_bytes = 256; 847 break; 848 case 1: 849 rscreen->tiling_info.group_bytes = 512; 850 break; 851 default: 852 return -EINVAL; 853 } 854 return 0; 855} 856 857static int r600_init_tiling(struct r600_screen *rscreen) 858{ 859 uint32_t tiling_config = rscreen->info.r600_tiling_config; 860 861 /* set default group bytes, overridden by tiling info ioctl */ 862 if (rscreen->chip_class <= R700) { 863 rscreen->tiling_info.group_bytes = 256; 864 } else { 865 rscreen->tiling_info.group_bytes = 512; 866 } 867 868 if (!tiling_config) 869 return 0; 870 871 if (rscreen->chip_class <= R700) { 872 return r600_interpret_tiling(rscreen, tiling_config); 873 } else { 874 return evergreen_interpret_tiling(rscreen, tiling_config); 875 } 876} 877 878static unsigned radeon_family_from_device(unsigned device) 879{ 880 switch (device) { 881#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family; 882#include "pci_ids/r600_pci_ids.h" 883#undef CHIPSET 884 default: 885 return CHIP_UNKNOWN; 886 } 887} 888 889static uint64_t r600_get_timestamp(struct pipe_screen *screen) 890{ 891 struct r600_screen *rscreen = (struct r600_screen*)screen; 892 893 return 1000000 * rscreen->ws->query_timestamp(rscreen->ws) / 894 rscreen->info.r600_clock_crystal_freq; 895} 896 897struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) 898{ 899 struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen); 900 901 if (rscreen == NULL) { 902 return NULL; 903 } 904 905 rscreen->ws = ws; 906 ws->query_info(ws, &rscreen->info); 907 908 rscreen->family = radeon_family_from_device(rscreen->info.pci_id); 909 if (rscreen->family == CHIP_UNKNOWN) { 910 fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id); 911 FREE(rscreen); 912 return NULL; 913 } 914 915 /* setup class */ 916 if (rscreen->family >= CHIP_CAYMAN) { 917 rscreen->chip_class = CAYMAN; 918 } else if (rscreen->family >= CHIP_CEDAR) { 919 rscreen->chip_class = EVERGREEN; 920 } else if (rscreen->family >= CHIP_RV770) { 921 rscreen->chip_class = R700; 922 } else { 923 rscreen->chip_class = R600; 924 } 925 926 /* Figure out streamout kernel support. */ 927 switch (rscreen->chip_class) { 928 case R600: 929 case EVERGREEN: 930 rscreen->has_streamout = rscreen->info.drm_minor >= 14; 931 break; 932 case R700: 933 rscreen->has_streamout = rscreen->info.drm_minor >= 17; 934 break; 935 /* TODO: Cayman */ 936 default: 937 rscreen->has_streamout = debug_get_bool_option("R600_STREAMOUT", FALSE); 938 } 939 940 if (r600_init_tiling(rscreen)) { 941 FREE(rscreen); 942 return NULL; 943 } 944 945 rscreen->screen.destroy = r600_destroy_screen; 946 rscreen->screen.get_name = r600_get_name; 947 rscreen->screen.get_vendor = r600_get_vendor; 948 rscreen->screen.get_param = r600_get_param; 949 rscreen->screen.get_shader_param = r600_get_shader_param; 950 rscreen->screen.get_paramf = r600_get_paramf; 951 rscreen->screen.get_video_param = r600_get_video_param; 952 rscreen->screen.get_compute_param = r600_get_compute_param; 953 rscreen->screen.get_timestamp = r600_get_timestamp; 954 955 if (rscreen->chip_class >= EVERGREEN) { 956 rscreen->screen.is_format_supported = evergreen_is_format_supported; 957 } else { 958 rscreen->screen.is_format_supported = r600_is_format_supported; 959 } 960 rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported; 961 rscreen->screen.context_create = r600_create_context; 962 rscreen->screen.fence_reference = r600_fence_reference; 963 rscreen->screen.fence_signalled = r600_fence_signalled; 964 rscreen->screen.fence_finish = r600_fence_finish; 965 r600_init_screen_resource_functions(&rscreen->screen); 966 967 util_format_s3tc_init(); 968 969 rscreen->fences.bo = NULL; 970 rscreen->fences.data = NULL; 971 rscreen->fences.next_index = 0; 972 LIST_INITHEAD(&rscreen->fences.pool); 973 LIST_INITHEAD(&rscreen->fences.blocks); 974 pipe_mutex_init(rscreen->fences.mutex); 975 976 rscreen->global_pool = compute_memory_pool_new(rscreen); 977 978 return &rscreen->screen; 979} 980