r600_pipe.h revision 59361d76a5b0b6b77d6e6bc976e02df2e8df9ec3
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71 unsigned pkt_flags; 72}; 73 74struct r600_surface_sync_cmd { 75 struct r600_atom atom; 76 unsigned flush_flags; /* CP_COHER_CNTL */ 77}; 78 79struct r600_db_misc_state { 80 struct r600_atom atom; 81 bool occlusion_query_enabled; 82 bool flush_depthstencil_through_cb; 83 bool copy_depth, copy_stencil; 84 unsigned copy_sample; 85}; 86 87struct r600_cb_misc_state { 88 struct r600_atom atom; 89 unsigned cb_color_control; /* this comes from blend state */ 90 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 91 unsigned nr_cbufs; 92 unsigned nr_ps_color_outputs; 93 bool multiwrite; 94 bool dual_src_blend; 95}; 96 97struct r600_alphatest_state { 98 struct r600_atom atom; 99 unsigned sx_alpha_test_control; /* this comes from dsa state */ 100 unsigned sx_alpha_ref; /* this comes from dsa state */ 101 bool bypass; 102 bool cb0_export_16bpc; /* from set_framebuffer_state */ 103}; 104 105struct r600_cs_shader_state { 106 struct r600_atom atom; 107 struct r600_pipe_compute *shader; 108}; 109 110struct r600_sample_mask { 111 struct r600_atom atom; 112 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */ 113}; 114 115enum r600_pipe_state_id { 116 R600_PIPE_STATE_BLEND = 0, 117 R600_PIPE_STATE_BLEND_COLOR, 118 R600_PIPE_STATE_CONFIG, 119 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 120 R600_PIPE_STATE_CLIP, 121 R600_PIPE_STATE_SCISSOR, 122 R600_PIPE_STATE_VIEWPORT, 123 R600_PIPE_STATE_RASTERIZER, 124 R600_PIPE_STATE_VGT, 125 R600_PIPE_STATE_FRAMEBUFFER, 126 R600_PIPE_STATE_DSA, 127 R600_PIPE_STATE_STENCIL_REF, 128 R600_PIPE_STATE_PS_SHADER, 129 R600_PIPE_STATE_VS_SHADER, 130 R600_PIPE_STATE_CONSTANT, 131 R600_PIPE_STATE_SAMPLER, 132 R600_PIPE_STATE_RESOURCE, 133 R600_PIPE_STATE_POLYGON_OFFSET, 134 R600_PIPE_STATE_FETCH_SHADER, 135 R600_PIPE_STATE_SPI, 136 R600_PIPE_NSTATES 137}; 138 139struct compute_memory_pool; 140void compute_memory_pool_delete(struct compute_memory_pool* pool); 141struct compute_memory_pool* compute_memory_pool_new( 142 struct r600_screen *rscreen); 143 144struct r600_pipe_fences { 145 struct r600_resource *bo; 146 unsigned *data; 147 unsigned next_index; 148 /* linked list of preallocated blocks */ 149 struct list_head blocks; 150 /* linked list of freed fences */ 151 struct list_head pool; 152 pipe_mutex mutex; 153}; 154 155struct r600_screen { 156 struct pipe_screen screen; 157 struct radeon_winsys *ws; 158 unsigned family; 159 enum chip_class chip_class; 160 struct radeon_info info; 161 bool has_streamout; 162 struct r600_tiling_info tiling_info; 163 struct r600_pipe_fences fences; 164 165 /*for compute global memory binding, we allocate stuff here, instead of 166 * buffers. 167 * XXX: Not sure if this is the best place for global_pool. Also, 168 * it's not thread safe, so it won't work with multiple contexts. */ 169 struct compute_memory_pool *global_pool; 170}; 171 172struct r600_pipe_sampler_view { 173 struct pipe_sampler_view base; 174 struct r600_resource *tex_resource; 175 uint32_t tex_resource_words[8]; 176}; 177 178struct r600_pipe_rasterizer { 179 struct r600_pipe_state rstate; 180 boolean flatshade; 181 boolean two_side; 182 unsigned sprite_coord_enable; 183 unsigned clip_plane_enable; 184 unsigned pa_sc_line_stipple; 185 unsigned pa_cl_clip_cntl; 186 float offset_units; 187 float offset_scale; 188 bool scissor_enable; 189 bool multisample_enable; 190}; 191 192struct r600_pipe_blend { 193 struct r600_pipe_state rstate; 194 unsigned cb_target_mask; 195 unsigned cb_color_control; 196 bool dual_src_blend; 197 bool alpha_to_one; 198}; 199 200struct r600_pipe_dsa { 201 struct r600_pipe_state rstate; 202 unsigned alpha_ref; 203 ubyte valuemask[2]; 204 ubyte writemask[2]; 205 unsigned sx_alpha_test_control; 206}; 207 208struct r600_vertex_element 209{ 210 unsigned count; 211 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 212 struct r600_resource *fetch_shader; 213 unsigned fs_size; 214 struct r600_pipe_state rstate; 215}; 216 217struct r600_pipe_shader; 218 219struct r600_pipe_shader_selector { 220 struct r600_pipe_shader *current; 221 222 struct tgsi_token *tokens; 223 struct pipe_stream_output_info so; 224 225 unsigned num_shaders; 226 227 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 228 unsigned type; 229 230 unsigned nr_ps_max_color_exports; 231}; 232 233struct r600_pipe_shader { 234 struct r600_pipe_shader_selector *selector; 235 struct r600_pipe_shader *next_variant; 236 struct r600_shader shader; 237 struct r600_pipe_state rstate; 238 struct r600_resource *bo; 239 struct r600_resource *bo_fetch; 240 struct r600_vertex_element vertex_elements; 241 unsigned sprite_coord_enable; 242 unsigned flatshade; 243 unsigned pa_cl_vs_out_cntl; 244 unsigned nr_ps_color_outputs; 245 unsigned key; 246 unsigned db_shader_control; 247 unsigned ps_depth_export; 248}; 249 250struct r600_pipe_sampler_state { 251 uint32_t tex_sampler_words[3]; 252 uint32_t border_color[4]; 253 bool border_color_use; 254 bool seamless_cube_map; 255}; 256 257/* needed for blitter save */ 258#define NUM_TEX_UNITS 16 259 260struct r600_seamless_cube_map { 261 struct r600_atom atom; 262 bool enabled; 263}; 264 265struct r600_samplerview_state { 266 struct r600_atom atom; 267 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 268 uint32_t enabled_mask; 269 uint32_t dirty_mask; 270 uint32_t depth_texture_mask; /* which textures are depth */ 271}; 272 273struct r600_textures_info { 274 struct r600_samplerview_state views; 275 struct r600_atom atom_sampler; 276 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 277 unsigned n_samplers; 278 bool is_array_sampler[NUM_TEX_UNITS]; 279}; 280 281struct r600_fence { 282 struct pipe_reference reference; 283 unsigned index; /* in the shared bo */ 284 struct r600_resource *sleep_bo; 285 struct list_head head; 286}; 287 288#define FENCE_BLOCK_SIZE 16 289 290struct r600_fence_block { 291 struct r600_fence fences[FENCE_BLOCK_SIZE]; 292 struct list_head head; 293}; 294 295#define R600_CONSTANT_ARRAY_SIZE 256 296#define R600_RESOURCE_ARRAY_SIZE 160 297 298struct r600_stencil_ref 299{ 300 ubyte ref_value[2]; 301 ubyte valuemask[2]; 302 ubyte writemask[2]; 303}; 304 305struct r600_constbuf_state 306{ 307 struct r600_atom atom; 308 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 309 uint32_t enabled_mask; 310 uint32_t dirty_mask; 311}; 312 313struct r600_vertexbuf_state 314{ 315 struct r600_atom atom; 316 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 317 uint32_t enabled_mask; /* non-NULL buffers */ 318 uint32_t dirty_mask; 319}; 320 321struct r600_context { 322 struct pipe_context context; 323 struct blitter_context *blitter; 324 enum radeon_family family; 325 enum chip_class chip_class; 326 boolean has_vertex_cache; 327 unsigned r6xx_num_clause_temp_gprs; 328 void *custom_dsa_flush; 329 void *custom_blend_resolve; 330 331 struct r600_screen *screen; 332 struct radeon_winsys *ws; 333 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 334 struct r600_vertex_element *vertex_elements; 335 struct pipe_framebuffer_state framebuffer; 336 unsigned compute_cb_target_mask; 337 unsigned db_shader_control; 338 unsigned pa_sc_line_stipple; 339 unsigned pa_cl_clip_cntl; 340 /* for saving when using blitter */ 341 struct pipe_stencil_ref stencil_ref; 342 struct pipe_viewport_state viewport; 343 struct pipe_clip_state clip; 344 struct r600_pipe_shader_selector *ps_shader; 345 struct r600_pipe_shader_selector *vs_shader; 346 struct r600_pipe_rasterizer *rasterizer; 347 struct r600_pipe_state vgt; 348 struct r600_pipe_state spi; 349 struct pipe_query *current_render_cond; 350 unsigned current_render_cond_mode; 351 struct pipe_query *saved_render_cond; 352 unsigned saved_render_cond_mode; 353 /* shader information */ 354 boolean two_side; 355 boolean spi_dirty; 356 unsigned sprite_coord_enable; 357 boolean flatshade; 358 boolean export_16bpc; 359 unsigned nr_cbufs; 360 bool alpha_to_one; 361 bool multisample_enable; 362 bool cb0_is_integer; 363 364 struct u_upload_mgr *uploader; 365 struct util_slab_mempool pool_transfers; 366 367 unsigned default_ps_gprs, default_vs_gprs; 368 369 /* States based on r600_atom. */ 370 struct list_head dirty_states; 371 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 372 /** Compute specific registers initializations. The start_cs_cmd atom 373 * must be emitted before start_compute_cs_cmd. */ 374 struct r600_command_buffer start_compute_cs_cmd; 375 struct r600_surface_sync_cmd surface_sync_cmd; 376 struct r600_atom r6xx_flush_and_inv_cmd; 377 struct r600_alphatest_state alphatest_state; 378 struct r600_cb_misc_state cb_misc_state; 379 struct r600_db_misc_state db_misc_state; 380 /** Vertex buffers for fetch shaders */ 381 struct r600_vertexbuf_state vertex_buffer_state; 382 /** Vertex buffers for compute shaders */ 383 struct r600_vertexbuf_state cs_vertex_buffer_state; 384 struct r600_constbuf_state vs_constbuf_state; 385 struct r600_constbuf_state ps_constbuf_state; 386 struct r600_textures_info vs_samplers; 387 struct r600_textures_info ps_samplers; 388 struct r600_seamless_cube_map seamless_cube_map; 389 struct r600_cs_shader_state cs_shader_state; 390 struct r600_sample_mask sample_mask; 391 392 struct radeon_winsys_cs *cs; 393 394 struct r600_range *range; 395 unsigned nblocks; 396 struct r600_block **blocks; 397 struct list_head dirty; 398 struct list_head enable_list; 399 unsigned pm4_dirty_cdwords; 400 unsigned ctx_pm4_ndwords; 401 402 /* The list of active queries. Only one query of each type can be active. */ 403 int num_occlusion_queries; 404 405 /* Manage queries in two separate groups: 406 * The timer ones and the others (streamout, occlusion). 407 * 408 * We do this because we should only suspend non-timer queries for u_blitter, 409 * and later if the non-timer queries are suspended, the context flush should 410 * only suspend and resume the timer queries. */ 411 struct list_head active_timer_queries; 412 unsigned num_cs_dw_timer_queries_suspend; 413 struct list_head active_nontimer_queries; 414 unsigned num_cs_dw_nontimer_queries_suspend; 415 416 unsigned num_cs_dw_streamout_end; 417 418 unsigned backend_mask; 419 unsigned max_db; /* for OQ */ 420 unsigned flags; 421 boolean predicate_drawing; 422 423 unsigned num_so_targets; 424 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 425 boolean streamout_start; 426 unsigned streamout_append_bitmask; 427 428 /* There is no scissor enable bit on r6xx, so we must use a workaround. 429 * These track the current scissor state. */ 430 bool scissor_enable; 431 struct pipe_scissor_state scissor_state; 432 433 /* With rasterizer discard, there doesn't have to be a pixel shader. 434 * In that case, we bind this one: */ 435 void *dummy_pixel_shader; 436 437 boolean dual_src_blend; 438 439 /* Index buffer. */ 440 struct pipe_index_buffer index_buffer; 441}; 442 443static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 444{ 445 atom->emit(rctx, atom); 446 atom->dirty = false; 447 if (atom->head.next && atom->head.prev) 448 LIST_DELINIT(&atom->head); 449} 450 451static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 452{ 453 if (!state->dirty) { 454 if (state->flags & EMIT_EARLY) { 455 LIST_ADD(&state->head, &rctx->dirty_states); 456 } else { 457 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 458 } 459 state->dirty = true; 460 } 461} 462 463/* evergreen_state.c */ 464void evergreen_init_common_regs(struct r600_command_buffer *cb, 465 enum chip_class ctx_chip_class, 466 enum radeon_family ctx_family, 467 int ctx_drm_minor); 468 469void evergreen_init_state_functions(struct r600_context *rctx); 470void evergreen_init_atom_start_cs(struct r600_context *rctx); 471void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 472void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 473void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 474void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 475void *evergreen_create_resolve_blend(struct r600_context *rctx); 476void evergreen_polygon_offset_update(struct r600_context *rctx); 477boolean evergreen_is_format_supported(struct pipe_screen *screen, 478 enum pipe_format format, 479 enum pipe_texture_target target, 480 unsigned sample_count, 481 unsigned usage); 482void evergreen_init_color_surface(struct r600_context *rctx, 483 struct r600_surface *surf); 484void evergreen_update_dual_export_state(struct r600_context * rctx); 485 486/* r600_blit.c */ 487void r600_copy_buffer(struct pipe_context *ctx, struct 488 pipe_resource *dst, unsigned dstx, 489 struct pipe_resource *src, const struct pipe_box *src_box); 490void r600_init_blit_functions(struct r600_context *rctx); 491void r600_blit_uncompress_depth(struct pipe_context *ctx, 492 struct r600_texture *texture, 493 struct r600_texture *staging, 494 unsigned first_level, unsigned last_level, 495 unsigned first_layer, unsigned last_layer, 496 unsigned first_sample, unsigned last_sample); 497void r600_flush_depth_textures(struct r600_context *rctx, 498 struct r600_samplerview_state *textures); 499 500/* r600_buffer.c */ 501bool r600_init_resource(struct r600_screen *rscreen, 502 struct r600_resource *res, 503 unsigned size, unsigned alignment, 504 unsigned bind, unsigned usage); 505struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 506 const struct pipe_resource *templ); 507 508/* r600_pipe.c */ 509void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 510 unsigned flags); 511 512/* r600_query.c */ 513void r600_init_query_functions(struct r600_context *rctx); 514void r600_suspend_nontimer_queries(struct r600_context *ctx); 515void r600_resume_nontimer_queries(struct r600_context *ctx); 516void r600_suspend_timer_queries(struct r600_context *ctx); 517void r600_resume_timer_queries(struct r600_context *ctx); 518 519/* r600_resource.c */ 520void r600_init_context_resource_functions(struct r600_context *r600); 521 522/* r600_shader.c */ 523int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 524#ifdef HAVE_OPENCL 525int r600_compute_shader_create(struct pipe_context * ctx, 526 LLVMModuleRef mod, struct r600_bytecode * bytecode); 527#endif 528void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 529 530/* r600_state.c */ 531void r600_set_scissor_state(struct r600_context *rctx, 532 const struct pipe_scissor_state *state); 533void r600_init_state_functions(struct r600_context *rctx); 534void r600_init_atom_start_cs(struct r600_context *rctx); 535void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 536void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 537void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 538void *r600_create_db_flush_dsa(struct r600_context *rctx); 539void r600_polygon_offset_update(struct r600_context *rctx); 540void r600_adjust_gprs(struct r600_context *rctx); 541boolean r600_is_format_supported(struct pipe_screen *screen, 542 enum pipe_format format, 543 enum pipe_texture_target target, 544 unsigned sample_count, 545 unsigned usage); 546void r600_update_dual_export_state(struct r600_context * rctx); 547 548/* r600_texture.c */ 549void r600_init_screen_texture_functions(struct pipe_screen *screen); 550void r600_init_surface_functions(struct r600_context *r600); 551uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 552 const unsigned char *swizzle_view, 553 uint32_t *word4_p, uint32_t *yuv_format_p); 554unsigned r600_texture_get_offset(struct r600_texture *rtex, 555 unsigned level, unsigned layer); 556 557/* r600_translate.c */ 558void r600_translate_index_buffer(struct r600_context *r600, 559 struct pipe_index_buffer *ib, 560 unsigned count); 561 562/* r600_state_common.c */ 563void r600_init_atom(struct r600_atom *atom, 564 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 565 unsigned num_dw, enum r600_atom_flags flags); 566void r600_init_common_atoms(struct r600_context *rctx); 567unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 568void r600_texture_barrier(struct pipe_context *ctx); 569void r600_set_index_buffer(struct pipe_context *ctx, 570 const struct pipe_index_buffer *ib); 571void r600_vertex_buffers_dirty(struct r600_context *rctx); 572void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 573 const struct pipe_vertex_buffer *input); 574void r600_sampler_views_dirty(struct r600_context *rctx, 575 struct r600_samplerview_state *state); 576void r600_set_sampler_views(struct pipe_context *pipe, 577 unsigned shader, 578 unsigned start, 579 unsigned count, 580 struct pipe_sampler_view **views); 581void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states); 582void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states); 583void *r600_create_vertex_elements(struct pipe_context *ctx, 584 unsigned count, 585 const struct pipe_vertex_element *elements); 586void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 587void r600_bind_blend_state(struct pipe_context *ctx, void *state); 588void r600_set_blend_color(struct pipe_context *ctx, 589 const struct pipe_blend_color *state); 590void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 591void r600_set_max_scissor(struct r600_context *rctx); 592void r600_bind_rs_state(struct pipe_context *ctx, void *state); 593void r600_delete_rs_state(struct pipe_context *ctx, void *state); 594void r600_sampler_view_destroy(struct pipe_context *ctx, 595 struct pipe_sampler_view *state); 596void r600_delete_sampler(struct pipe_context *ctx, void *state); 597void r600_delete_state(struct pipe_context *ctx, void *state); 598void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 599void *r600_create_shader_state_ps(struct pipe_context *ctx, 600 const struct pipe_shader_state *state); 601void *r600_create_shader_state_vs(struct pipe_context *ctx, 602 const struct pipe_shader_state *state); 603void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 604void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 605void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 606void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 607void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 608void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 609 struct pipe_constant_buffer *cb); 610struct pipe_stream_output_target * 611r600_create_so_target(struct pipe_context *ctx, 612 struct pipe_resource *buffer, 613 unsigned buffer_offset, 614 unsigned buffer_size); 615void r600_so_target_destroy(struct pipe_context *ctx, 616 struct pipe_stream_output_target *target); 617void r600_set_so_targets(struct pipe_context *ctx, 618 unsigned num_targets, 619 struct pipe_stream_output_target **targets, 620 unsigned append_bitmask); 621void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask); 622void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 623 const struct pipe_stencil_ref *state); 624void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 625uint32_t r600_translate_stencil_op(int s_op); 626uint32_t r600_translate_fill(uint32_t func); 627unsigned r600_tex_wrap(unsigned wrap); 628unsigned r600_tex_filter(unsigned filter); 629unsigned r600_tex_mipfilter(unsigned filter); 630unsigned r600_tex_compare(unsigned compare); 631 632/* 633 * Helpers for building command buffers 634 */ 635 636#define PKT3_SET_CONFIG_REG 0x68 637#define PKT3_SET_CONTEXT_REG 0x69 638#define PKT3_SET_CTL_CONST 0x6F 639#define PKT3_SET_LOOP_CONST 0x6C 640 641#define R600_CONFIG_REG_OFFSET 0x08000 642#define R600_CONTEXT_REG_OFFSET 0x28000 643#define R600_CTL_CONST_OFFSET 0x3CFF0 644#define R600_LOOP_CONST_OFFSET 0X0003E200 645#define EG_LOOP_CONST_OFFSET 0x0003A200 646 647#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 648#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 649#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 650#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 651#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 652 653#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 654 655/*Evergreen Compute packet3*/ 656#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE) 657 658static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 659{ 660 cb->buf[cb->atom.num_dw++] = value; 661} 662 663static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 664{ 665 assert(reg < R600_CONTEXT_REG_OFFSET); 666 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 667 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 668 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 669} 670 671/** 672 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 673 * shaders. 674 */ 675static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 676{ 677 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 678 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 679 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 680 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 681} 682 683/** 684 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 685 * shaders. 686 */ 687static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 688{ 689 assert(reg >= R600_CTL_CONST_OFFSET); 690 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 691 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 692 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 693} 694 695static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 696{ 697 assert(reg >= R600_LOOP_CONST_OFFSET); 698 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 699 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 700 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 701} 702 703/** 704 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 705 * shaders. 706 */ 707static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 708{ 709 assert(reg >= EG_LOOP_CONST_OFFSET); 710 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 711 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 712 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 713} 714 715static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 716{ 717 r600_store_config_reg_seq(cb, reg, 1); 718 r600_store_value(cb, value); 719} 720 721static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 722{ 723 r600_store_context_reg_seq(cb, reg, 1); 724 r600_store_value(cb, value); 725} 726 727static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 728{ 729 r600_store_ctl_const_seq(cb, reg, 1); 730 r600_store_value(cb, value); 731} 732 733static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 734{ 735 r600_store_loop_const_seq(cb, reg, 1); 736 r600_store_value(cb, value); 737} 738 739static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 740{ 741 eg_store_loop_const_seq(cb, reg, 1); 742 r600_store_value(cb, value); 743} 744 745void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 746void r600_release_command_buffer(struct r600_command_buffer *cb); 747 748/* 749 * Helpers for emitting state into a command stream directly. 750 */ 751 752static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 753 enum radeon_bo_usage usage) 754{ 755 assert(usage); 756 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 757} 758 759static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 760{ 761 cs->buf[cs->cdw++] = value; 762} 763 764static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr) 765{ 766 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS); 767 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0])); 768 cs->cdw += num; 769} 770 771static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 772{ 773 assert(reg < R600_CONTEXT_REG_OFFSET); 774 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 775 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 776 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 777} 778 779static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 780{ 781 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 782 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 783 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 784 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 785} 786 787static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 788{ 789 r600_write_context_reg_seq(cs, reg, num); 790 /* Set the compute bit on the packet header */ 791 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; 792} 793 794static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 795{ 796 assert(reg >= R600_CTL_CONST_OFFSET); 797 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 798 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 799 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 800} 801 802static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 803{ 804 r600_write_config_reg_seq(cs, reg, 1); 805 r600_write_value(cs, value); 806} 807 808static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 809{ 810 r600_write_context_reg_seq(cs, reg, 1); 811 r600_write_value(cs, value); 812} 813 814static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 815{ 816 r600_write_compute_context_reg_seq(cs, reg, 1); 817 r600_write_value(cs, value); 818} 819 820static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 821{ 822 r600_write_ctl_const_seq(cs, reg, 1); 823 r600_write_value(cs, value); 824} 825 826/* 827 * common helpers 828 */ 829static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 830{ 831 return value * (1 << frac_bits); 832} 833#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 834 835static inline unsigned r600_tex_aniso_filter(unsigned filter) 836{ 837 if (filter <= 1) return 0; 838 if (filter <= 2) return 1; 839 if (filter <= 4) return 2; 840 if (filter <= 8) return 3; 841 /* else */ return 4; 842} 843 844/* 12.4 fixed-point */ 845static INLINE unsigned r600_pack_float_12p4(float x) 846{ 847 return x <= 0 ? 0 : 848 x >= 4096 ? 0xffff : x * 16; 849} 850 851static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 852{ 853 struct r600_screen *rscreen = (struct r600_screen*)screen; 854 struct r600_resource *rresource = (struct r600_resource*)resource; 855 856 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 857} 858 859#endif 860