r600_pipe.h revision 78354011f99c4103345f8f32e10b0b4b884ebdaf
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_blitter.h" 30#include "util/u_slab.h" 31#include "r600.h" 32#include "r600_llvm.h" 33#include "r600_public.h" 34#include "r600_shader.h" 35#include "r600_resource.h" 36#include "evergreen_compute.h" 37 38#define R600_MAX_CONST_BUFFERS 2 39#define R600_MAX_CONST_BUFFER_SIZE 4096 40 41#ifdef PIPE_ARCH_BIG_ENDIAN 42#define R600_BIG_ENDIAN 1 43#else 44#define R600_BIG_ENDIAN 0 45#endif 46 47enum r600_atom_flags { 48 /* When set, atoms are added at the beginning of the dirty list 49 * instead of the end. */ 50 EMIT_EARLY = (1 << 0) 51}; 52 53/* This encapsulates a state or an operation which can emitted into the GPU 54 * command stream. It's not limited to states only, it can be used for anything 55 * that wants to write commands into the CS (e.g. cache flushes). */ 56struct r600_atom { 57 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 58 59 unsigned num_dw; 60 enum r600_atom_flags flags; 61 bool dirty; 62 63 struct list_head head; 64}; 65 66/* This is an atom containing GPU commands that never change. 67 * This is supposed to be copied directly into the CS. */ 68struct r600_command_buffer { 69 struct r600_atom atom; 70 uint32_t *buf; 71 unsigned max_num_dw; 72 unsigned pkt_flags; 73}; 74 75struct r600_surface_sync_cmd { 76 struct r600_atom atom; 77 unsigned flush_flags; /* CP_COHER_CNTL */ 78}; 79 80struct r600_db_misc_state { 81 struct r600_atom atom; 82 bool occlusion_query_enabled; 83 bool flush_depthstencil_through_cb; 84 bool copy_depth, copy_stencil; 85 unsigned copy_sample; 86}; 87 88struct r600_cb_misc_state { 89 struct r600_atom atom; 90 unsigned cb_color_control; /* this comes from blend state */ 91 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 92 unsigned nr_cbufs; 93 unsigned nr_ps_color_outputs; 94 bool multiwrite; 95 bool dual_src_blend; 96}; 97 98struct r600_alphatest_state { 99 struct r600_atom atom; 100 unsigned sx_alpha_test_control; /* this comes from dsa state */ 101 unsigned sx_alpha_ref; /* this comes from dsa state */ 102 bool bypass; 103 bool cb0_export_16bpc; /* from set_framebuffer_state */ 104}; 105 106struct r600_cs_shader_state { 107 struct r600_atom atom; 108 struct r600_pipe_compute *shader; 109}; 110 111struct r600_sample_mask { 112 struct r600_atom atom; 113 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */ 114}; 115 116enum r600_pipe_state_id { 117 R600_PIPE_STATE_BLEND = 0, 118 R600_PIPE_STATE_BLEND_COLOR, 119 R600_PIPE_STATE_CONFIG, 120 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 121 R600_PIPE_STATE_CLIP, 122 R600_PIPE_STATE_SCISSOR, 123 R600_PIPE_STATE_VIEWPORT, 124 R600_PIPE_STATE_RASTERIZER, 125 R600_PIPE_STATE_VGT, 126 R600_PIPE_STATE_FRAMEBUFFER, 127 R600_PIPE_STATE_DSA, 128 R600_PIPE_STATE_STENCIL_REF, 129 R600_PIPE_STATE_PS_SHADER, 130 R600_PIPE_STATE_VS_SHADER, 131 R600_PIPE_STATE_CONSTANT, 132 R600_PIPE_STATE_SAMPLER, 133 R600_PIPE_STATE_RESOURCE, 134 R600_PIPE_STATE_POLYGON_OFFSET, 135 R600_PIPE_STATE_FETCH_SHADER, 136 R600_PIPE_STATE_SPI, 137 R600_PIPE_NSTATES 138}; 139 140struct compute_memory_pool; 141void compute_memory_pool_delete(struct compute_memory_pool* pool); 142struct compute_memory_pool* compute_memory_pool_new( 143 struct r600_screen *rscreen); 144 145struct r600_pipe_fences { 146 struct r600_resource *bo; 147 unsigned *data; 148 unsigned next_index; 149 /* linked list of preallocated blocks */ 150 struct list_head blocks; 151 /* linked list of freed fences */ 152 struct list_head pool; 153 pipe_mutex mutex; 154}; 155 156struct r600_screen { 157 struct pipe_screen screen; 158 struct radeon_winsys *ws; 159 unsigned family; 160 enum chip_class chip_class; 161 struct radeon_info info; 162 bool has_streamout; 163 struct r600_tiling_info tiling_info; 164 struct r600_pipe_fences fences; 165 166 /*for compute global memory binding, we allocate stuff here, instead of 167 * buffers. 168 * XXX: Not sure if this is the best place for global_pool. Also, 169 * it's not thread safe, so it won't work with multiple contexts. */ 170 struct compute_memory_pool *global_pool; 171}; 172 173struct r600_pipe_sampler_view { 174 struct pipe_sampler_view base; 175 struct r600_resource *tex_resource; 176 uint32_t tex_resource_words[8]; 177}; 178 179struct r600_pipe_rasterizer { 180 struct r600_pipe_state rstate; 181 boolean flatshade; 182 boolean two_side; 183 unsigned sprite_coord_enable; 184 unsigned clip_plane_enable; 185 unsigned pa_sc_line_stipple; 186 unsigned pa_cl_clip_cntl; 187 float offset_units; 188 float offset_scale; 189 bool scissor_enable; 190 bool multisample_enable; 191}; 192 193struct r600_pipe_blend { 194 struct r600_pipe_state rstate; 195 unsigned cb_target_mask; 196 unsigned cb_color_control; 197 bool dual_src_blend; 198 bool alpha_to_one; 199}; 200 201struct r600_pipe_dsa { 202 struct r600_pipe_state rstate; 203 unsigned alpha_ref; 204 ubyte valuemask[2]; 205 ubyte writemask[2]; 206 unsigned sx_alpha_test_control; 207}; 208 209struct r600_vertex_element 210{ 211 unsigned count; 212 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 213 struct r600_resource *fetch_shader; 214 unsigned fs_size; 215 struct r600_pipe_state rstate; 216}; 217 218struct r600_pipe_shader; 219 220struct r600_pipe_shader_selector { 221 struct r600_pipe_shader *current; 222 223 struct tgsi_token *tokens; 224 struct pipe_stream_output_info so; 225 226 unsigned num_shaders; 227 228 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 229 unsigned type; 230 231 unsigned nr_ps_max_color_exports; 232}; 233 234struct r600_pipe_shader { 235 struct r600_pipe_shader_selector *selector; 236 struct r600_pipe_shader *next_variant; 237 struct r600_shader shader; 238 struct r600_pipe_state rstate; 239 struct r600_resource *bo; 240 struct r600_resource *bo_fetch; 241 struct r600_vertex_element vertex_elements; 242 unsigned sprite_coord_enable; 243 unsigned flatshade; 244 unsigned pa_cl_vs_out_cntl; 245 unsigned nr_ps_color_outputs; 246 unsigned key; 247 unsigned db_shader_control; 248 unsigned ps_depth_export; 249}; 250 251struct r600_pipe_sampler_state { 252 uint32_t tex_sampler_words[3]; 253 uint32_t border_color[4]; 254 bool border_color_use; 255 bool seamless_cube_map; 256}; 257 258/* needed for blitter save */ 259#define NUM_TEX_UNITS 16 260 261struct r600_seamless_cube_map { 262 struct r600_atom atom; 263 bool enabled; 264}; 265 266struct r600_samplerview_state { 267 struct r600_atom atom; 268 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 269 uint32_t enabled_mask; 270 uint32_t dirty_mask; 271 uint32_t compressed_depthtex_mask; /* which textures are depth */ 272 uint32_t compressed_colortex_mask; 273}; 274 275struct r600_textures_info { 276 struct r600_samplerview_state views; 277 struct r600_atom atom_sampler; 278 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 279 unsigned n_samplers; 280 bool is_array_sampler[NUM_TEX_UNITS]; 281}; 282 283struct r600_fence { 284 struct pipe_reference reference; 285 unsigned index; /* in the shared bo */ 286 struct r600_resource *sleep_bo; 287 struct list_head head; 288}; 289 290#define FENCE_BLOCK_SIZE 16 291 292struct r600_fence_block { 293 struct r600_fence fences[FENCE_BLOCK_SIZE]; 294 struct list_head head; 295}; 296 297#define R600_CONSTANT_ARRAY_SIZE 256 298#define R600_RESOURCE_ARRAY_SIZE 160 299 300struct r600_stencil_ref 301{ 302 ubyte ref_value[2]; 303 ubyte valuemask[2]; 304 ubyte writemask[2]; 305}; 306 307struct r600_constbuf_state 308{ 309 struct r600_atom atom; 310 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 311 uint32_t enabled_mask; 312 uint32_t dirty_mask; 313}; 314 315struct r600_vertexbuf_state 316{ 317 struct r600_atom atom; 318 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 319 uint32_t enabled_mask; /* non-NULL buffers */ 320 uint32_t dirty_mask; 321}; 322 323struct r600_context { 324 struct pipe_context context; 325 struct blitter_context *blitter; 326 enum radeon_family family; 327 enum chip_class chip_class; 328 boolean has_vertex_cache; 329 unsigned r6xx_num_clause_temp_gprs; 330 void *custom_dsa_flush; 331 void *custom_blend_resolve; 332 void *custom_blend_decompress; 333 334 struct r600_screen *screen; 335 struct radeon_winsys *ws; 336 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 337 struct r600_vertex_element *vertex_elements; 338 struct pipe_framebuffer_state framebuffer; 339 unsigned compressed_cb_mask; 340 unsigned compute_cb_target_mask; 341 unsigned db_shader_control; 342 unsigned pa_sc_line_stipple; 343 unsigned pa_cl_clip_cntl; 344 /* for saving when using blitter */ 345 struct pipe_stencil_ref stencil_ref; 346 struct pipe_viewport_state viewport; 347 struct pipe_clip_state clip; 348 struct r600_pipe_shader_selector *ps_shader; 349 struct r600_pipe_shader_selector *vs_shader; 350 struct r600_pipe_rasterizer *rasterizer; 351 struct r600_pipe_state vgt; 352 struct r600_pipe_state spi; 353 struct pipe_query *current_render_cond; 354 unsigned current_render_cond_mode; 355 struct pipe_query *saved_render_cond; 356 unsigned saved_render_cond_mode; 357 /* shader information */ 358 boolean two_side; 359 boolean spi_dirty; 360 unsigned sprite_coord_enable; 361 boolean flatshade; 362 boolean export_16bpc; 363 unsigned nr_cbufs; 364 bool alpha_to_one; 365 bool multisample_enable; 366 bool cb0_is_integer; 367 368 struct u_upload_mgr *uploader; 369 struct util_slab_mempool pool_transfers; 370 371 unsigned default_ps_gprs, default_vs_gprs; 372 373 /* States based on r600_atom. */ 374 struct list_head dirty_states; 375 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 376 /** Compute specific registers initializations. The start_cs_cmd atom 377 * must be emitted before start_compute_cs_cmd. */ 378 struct r600_command_buffer start_compute_cs_cmd; 379 struct r600_surface_sync_cmd surface_sync_cmd; 380 struct r600_atom r6xx_flush_and_inv_cmd; 381 struct r600_alphatest_state alphatest_state; 382 struct r600_cb_misc_state cb_misc_state; 383 struct r600_db_misc_state db_misc_state; 384 /** Vertex buffers for fetch shaders */ 385 struct r600_vertexbuf_state vertex_buffer_state; 386 /** Vertex buffers for compute shaders */ 387 struct r600_vertexbuf_state cs_vertex_buffer_state; 388 struct r600_constbuf_state vs_constbuf_state; 389 struct r600_constbuf_state ps_constbuf_state; 390 struct r600_textures_info vs_samplers; 391 struct r600_textures_info ps_samplers; 392 struct r600_seamless_cube_map seamless_cube_map; 393 struct r600_cs_shader_state cs_shader_state; 394 struct r600_sample_mask sample_mask; 395 396 /* current external blend state (from state tracker) */ 397 struct r600_pipe_blend *blend; 398 /* state with disabled blending - used internally with blend_override */ 399 struct r600_pipe_blend *no_blend; 400 401 /* 1 - override current blend state with no_blend, 0 - use external state */ 402 unsigned blend_override; 403 404 struct radeon_winsys_cs *cs; 405 406 struct r600_range *range; 407 unsigned nblocks; 408 struct r600_block **blocks; 409 struct list_head dirty; 410 struct list_head enable_list; 411 unsigned pm4_dirty_cdwords; 412 unsigned ctx_pm4_ndwords; 413 414 /* The list of active queries. Only one query of each type can be active. */ 415 int num_occlusion_queries; 416 417 /* Manage queries in two separate groups: 418 * The timer ones and the others (streamout, occlusion). 419 * 420 * We do this because we should only suspend non-timer queries for u_blitter, 421 * and later if the non-timer queries are suspended, the context flush should 422 * only suspend and resume the timer queries. */ 423 struct list_head active_timer_queries; 424 unsigned num_cs_dw_timer_queries_suspend; 425 struct list_head active_nontimer_queries; 426 unsigned num_cs_dw_nontimer_queries_suspend; 427 428 unsigned num_cs_dw_streamout_end; 429 430 unsigned backend_mask; 431 unsigned max_db; /* for OQ */ 432 unsigned flags; 433 boolean predicate_drawing; 434 435 unsigned num_so_targets; 436 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 437 boolean streamout_start; 438 unsigned streamout_append_bitmask; 439 440 /* There is no scissor enable bit on r6xx, so we must use a workaround. 441 * These track the current scissor state. */ 442 bool scissor_enable; 443 struct pipe_scissor_state scissor_state; 444 445 /* With rasterizer discard, there doesn't have to be a pixel shader. 446 * In that case, we bind this one: */ 447 void *dummy_pixel_shader; 448 449 boolean dual_src_blend; 450 451 /* Index buffer. */ 452 struct pipe_index_buffer index_buffer; 453 454 /* Dummy CMASK and FMASK buffers used to get around the R6xx hardware 455 * bug where valid CMASK and FMASK are required to be present to avoid 456 * a hardlock in certain operations but aren't actually used 457 * for anything useful. */ 458 struct r600_resource *dummy_fmask; 459 struct r600_resource *dummy_cmask; 460}; 461 462static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 463{ 464 atom->emit(rctx, atom); 465 atom->dirty = false; 466 if (atom->head.next && atom->head.prev) 467 LIST_DELINIT(&atom->head); 468} 469 470static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 471{ 472 if (!state->dirty) { 473 if (state->flags & EMIT_EARLY) { 474 LIST_ADD(&state->head, &rctx->dirty_states); 475 } else { 476 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 477 } 478 state->dirty = true; 479 } 480} 481 482/* evergreen_state.c */ 483void evergreen_init_common_regs(struct r600_command_buffer *cb, 484 enum chip_class ctx_chip_class, 485 enum radeon_family ctx_family, 486 int ctx_drm_minor); 487 488void evergreen_init_state_functions(struct r600_context *rctx); 489void evergreen_init_atom_start_cs(struct r600_context *rctx); 490void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 491void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 492void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 493void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 494void *evergreen_create_resolve_blend(struct r600_context *rctx); 495void *evergreen_create_decompress_blend(struct r600_context *rctx); 496void evergreen_polygon_offset_update(struct r600_context *rctx); 497boolean evergreen_is_format_supported(struct pipe_screen *screen, 498 enum pipe_format format, 499 enum pipe_texture_target target, 500 unsigned sample_count, 501 unsigned usage); 502void evergreen_init_color_surface(struct r600_context *rctx, 503 struct r600_surface *surf); 504void evergreen_update_dual_export_state(struct r600_context * rctx); 505 506/* r600_blit.c */ 507void r600_copy_buffer(struct pipe_context *ctx, struct 508 pipe_resource *dst, unsigned dstx, 509 struct pipe_resource *src, const struct pipe_box *src_box); 510void r600_init_blit_functions(struct r600_context *rctx); 511void r600_blit_decompress_depth(struct pipe_context *ctx, 512 struct r600_texture *texture, 513 struct r600_texture *staging, 514 unsigned first_level, unsigned last_level, 515 unsigned first_layer, unsigned last_layer, 516 unsigned first_sample, unsigned last_sample); 517void r600_decompress_depth_textures(struct r600_context *rctx, 518 struct r600_samplerview_state *textures); 519void r600_decompress_color_textures(struct r600_context *rctx, 520 struct r600_samplerview_state *textures); 521 522/* r600_buffer.c */ 523bool r600_init_resource(struct r600_screen *rscreen, 524 struct r600_resource *res, 525 unsigned size, unsigned alignment, 526 unsigned bind, unsigned usage); 527struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 528 const struct pipe_resource *templ, 529 unsigned alignment); 530 531/* r600_pipe.c */ 532void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 533 unsigned flags); 534 535/* r600_query.c */ 536void r600_init_query_functions(struct r600_context *rctx); 537void r600_suspend_nontimer_queries(struct r600_context *ctx); 538void r600_resume_nontimer_queries(struct r600_context *ctx); 539void r600_suspend_timer_queries(struct r600_context *ctx); 540void r600_resume_timer_queries(struct r600_context *ctx); 541 542/* r600_resource.c */ 543void r600_init_context_resource_functions(struct r600_context *r600); 544 545/* r600_shader.c */ 546int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 547#ifdef HAVE_OPENCL 548int r600_compute_shader_create(struct pipe_context * ctx, 549 LLVMModuleRef mod, struct r600_bytecode * bytecode); 550#endif 551void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 552 553/* r600_state.c */ 554void r600_set_scissor_state(struct r600_context *rctx, 555 const struct pipe_scissor_state *state); 556void r600_init_state_functions(struct r600_context *rctx); 557void r600_init_atom_start_cs(struct r600_context *rctx); 558void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 559void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 560void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 561void *r600_create_db_flush_dsa(struct r600_context *rctx); 562void *r600_create_resolve_blend(struct r600_context *rctx); 563void *r700_create_resolve_blend(struct r600_context *rctx); 564void *r600_create_decompress_blend(struct r600_context *rctx); 565void r600_polygon_offset_update(struct r600_context *rctx); 566void r600_adjust_gprs(struct r600_context *rctx); 567boolean r600_is_format_supported(struct pipe_screen *screen, 568 enum pipe_format format, 569 enum pipe_texture_target target, 570 unsigned sample_count, 571 unsigned usage); 572void r600_update_dual_export_state(struct r600_context * rctx); 573 574/* r600_texture.c */ 575void r600_init_screen_texture_functions(struct pipe_screen *screen); 576void r600_init_surface_functions(struct r600_context *r600); 577uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 578 const unsigned char *swizzle_view, 579 uint32_t *word4_p, uint32_t *yuv_format_p); 580unsigned r600_texture_get_offset(struct r600_texture *rtex, 581 unsigned level, unsigned layer); 582 583/* r600_translate.c */ 584void r600_translate_index_buffer(struct r600_context *r600, 585 struct pipe_index_buffer *ib, 586 unsigned count); 587 588/* r600_state_common.c */ 589void r600_init_atom(struct r600_atom *atom, 590 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 591 unsigned num_dw, enum r600_atom_flags flags); 592void r600_init_common_atoms(struct r600_context *rctx); 593unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 594void r600_texture_barrier(struct pipe_context *ctx); 595void r600_set_index_buffer(struct pipe_context *ctx, 596 const struct pipe_index_buffer *ib); 597void r600_vertex_buffers_dirty(struct r600_context *rctx); 598void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 599 const struct pipe_vertex_buffer *input); 600void r600_sampler_views_dirty(struct r600_context *rctx, 601 struct r600_samplerview_state *state); 602void r600_set_sampler_views(struct pipe_context *pipe, 603 unsigned shader, 604 unsigned start, 605 unsigned count, 606 struct pipe_sampler_view **views); 607void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states); 608void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states); 609void *r600_create_vertex_elements(struct pipe_context *ctx, 610 unsigned count, 611 const struct pipe_vertex_element *elements); 612void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 613void r600_bind_blend_state(struct pipe_context *ctx, void *state); 614void r600_set_blend_color(struct pipe_context *ctx, 615 const struct pipe_blend_color *state); 616void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 617void r600_set_max_scissor(struct r600_context *rctx); 618void r600_bind_rs_state(struct pipe_context *ctx, void *state); 619void r600_delete_rs_state(struct pipe_context *ctx, void *state); 620void r600_sampler_view_destroy(struct pipe_context *ctx, 621 struct pipe_sampler_view *state); 622void r600_delete_sampler(struct pipe_context *ctx, void *state); 623void r600_delete_state(struct pipe_context *ctx, void *state); 624void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 625void *r600_create_shader_state_ps(struct pipe_context *ctx, 626 const struct pipe_shader_state *state); 627void *r600_create_shader_state_vs(struct pipe_context *ctx, 628 const struct pipe_shader_state *state); 629void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 630void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 631void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 632void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 633void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 634void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 635 struct pipe_constant_buffer *cb); 636struct pipe_stream_output_target * 637r600_create_so_target(struct pipe_context *ctx, 638 struct pipe_resource *buffer, 639 unsigned buffer_offset, 640 unsigned buffer_size); 641void r600_so_target_destroy(struct pipe_context *ctx, 642 struct pipe_stream_output_target *target); 643void r600_set_so_targets(struct pipe_context *ctx, 644 unsigned num_targets, 645 struct pipe_stream_output_target **targets, 646 unsigned append_bitmask); 647void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask); 648void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 649 const struct pipe_stencil_ref *state); 650void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 651void r600_draw_rectangle(struct blitter_context *blitter, 652 unsigned x1, unsigned y1, unsigned x2, unsigned y2, float depth, 653 enum blitter_attrib_type type, const union pipe_color_union *attrib); 654uint32_t r600_translate_stencil_op(int s_op); 655uint32_t r600_translate_fill(uint32_t func); 656unsigned r600_tex_wrap(unsigned wrap); 657unsigned r600_tex_filter(unsigned filter); 658unsigned r600_tex_mipfilter(unsigned filter); 659unsigned r600_tex_compare(unsigned compare); 660 661/* 662 * Helpers for building command buffers 663 */ 664 665#define PKT3_SET_CONFIG_REG 0x68 666#define PKT3_SET_CONTEXT_REG 0x69 667#define PKT3_SET_CTL_CONST 0x6F 668#define PKT3_SET_LOOP_CONST 0x6C 669 670#define R600_CONFIG_REG_OFFSET 0x08000 671#define R600_CONTEXT_REG_OFFSET 0x28000 672#define R600_CTL_CONST_OFFSET 0x3CFF0 673#define R600_LOOP_CONST_OFFSET 0X0003E200 674#define EG_LOOP_CONST_OFFSET 0x0003A200 675 676#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 677#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 678#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 679#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 680#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 681 682#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 683 684/*Evergreen Compute packet3*/ 685#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE) 686 687static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 688{ 689 cb->buf[cb->atom.num_dw++] = value; 690} 691 692static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 693{ 694 assert(reg < R600_CONTEXT_REG_OFFSET); 695 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 696 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 697 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 698} 699 700/** 701 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 702 * shaders. 703 */ 704static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 705{ 706 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 707 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 708 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 709 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 710} 711 712/** 713 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 714 * shaders. 715 */ 716static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 717{ 718 assert(reg >= R600_CTL_CONST_OFFSET); 719 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 720 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 721 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 722} 723 724static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 725{ 726 assert(reg >= R600_LOOP_CONST_OFFSET); 727 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 728 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 729 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 730} 731 732/** 733 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 734 * shaders. 735 */ 736static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 737{ 738 assert(reg >= EG_LOOP_CONST_OFFSET); 739 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 740 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 741 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 742} 743 744static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 745{ 746 r600_store_config_reg_seq(cb, reg, 1); 747 r600_store_value(cb, value); 748} 749 750static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 751{ 752 r600_store_context_reg_seq(cb, reg, 1); 753 r600_store_value(cb, value); 754} 755 756static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 757{ 758 r600_store_ctl_const_seq(cb, reg, 1); 759 r600_store_value(cb, value); 760} 761 762static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 763{ 764 r600_store_loop_const_seq(cb, reg, 1); 765 r600_store_value(cb, value); 766} 767 768static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 769{ 770 eg_store_loop_const_seq(cb, reg, 1); 771 r600_store_value(cb, value); 772} 773 774void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 775void r600_release_command_buffer(struct r600_command_buffer *cb); 776 777/* 778 * Helpers for emitting state into a command stream directly. 779 */ 780 781static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 782 enum radeon_bo_usage usage) 783{ 784 assert(usage); 785 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 786} 787 788static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 789{ 790 cs->buf[cs->cdw++] = value; 791} 792 793static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr) 794{ 795 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS); 796 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0])); 797 cs->cdw += num; 798} 799 800static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 801{ 802 assert(reg < R600_CONTEXT_REG_OFFSET); 803 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 804 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 805 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 806} 807 808static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 809{ 810 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 811 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 812 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 813 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 814} 815 816static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 817{ 818 r600_write_context_reg_seq(cs, reg, num); 819 /* Set the compute bit on the packet header */ 820 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; 821} 822 823static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 824{ 825 assert(reg >= R600_CTL_CONST_OFFSET); 826 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 827 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 828 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 829} 830 831static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 832{ 833 r600_write_config_reg_seq(cs, reg, 1); 834 r600_write_value(cs, value); 835} 836 837static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 838{ 839 r600_write_context_reg_seq(cs, reg, 1); 840 r600_write_value(cs, value); 841} 842 843static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 844{ 845 r600_write_compute_context_reg_seq(cs, reg, 1); 846 r600_write_value(cs, value); 847} 848 849static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 850{ 851 r600_write_ctl_const_seq(cs, reg, 1); 852 r600_write_value(cs, value); 853} 854 855/* 856 * common helpers 857 */ 858static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 859{ 860 return value * (1 << frac_bits); 861} 862#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 863 864static inline unsigned r600_tex_aniso_filter(unsigned filter) 865{ 866 if (filter <= 1) return 0; 867 if (filter <= 2) return 1; 868 if (filter <= 4) return 2; 869 if (filter <= 8) return 3; 870 /* else */ return 4; 871} 872 873/* 12.4 fixed-point */ 874static INLINE unsigned r600_pack_float_12p4(float x) 875{ 876 return x <= 0 ? 0 : 877 x >= 4096 ? 0xffff : x * 16; 878} 879 880static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 881{ 882 struct r600_screen *rscreen = (struct r600_screen*)screen; 883 struct r600_resource *rresource = (struct r600_resource*)resource; 884 885 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 886} 887 888#endif 889