r600_pipe.h revision 94b634eca0e2bd32d4b5bd92d06d510eae8a5625
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71 unsigned pkt_flags; 72}; 73 74struct r600_surface_sync_cmd { 75 struct r600_atom atom; 76 unsigned flush_flags; /* CP_COHER_CNTL */ 77}; 78 79struct r600_db_misc_state { 80 struct r600_atom atom; 81 bool occlusion_query_enabled; 82 bool flush_depthstencil_through_cb; 83 bool copy_depth, copy_stencil; 84 unsigned copy_sample; 85}; 86 87struct r600_cb_misc_state { 88 struct r600_atom atom; 89 unsigned cb_color_control; /* this comes from blend state */ 90 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 91 unsigned nr_cbufs; 92 unsigned nr_ps_color_outputs; 93 bool multiwrite; 94 bool dual_src_blend; 95}; 96 97struct r600_alphatest_state { 98 struct r600_atom atom; 99 unsigned sx_alpha_test_control; /* this comes from dsa state */ 100 unsigned sx_alpha_ref; /* this comes from dsa state */ 101 bool bypass; 102 bool cb0_export_16bpc; /* from set_framebuffer_state */ 103}; 104 105struct r600_cs_shader_state { 106 struct r600_atom atom; 107 struct r600_pipe_compute *shader; 108}; 109 110struct r600_sample_mask { 111 struct r600_atom atom; 112 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */ 113}; 114 115enum r600_pipe_state_id { 116 R600_PIPE_STATE_BLEND = 0, 117 R600_PIPE_STATE_BLEND_COLOR, 118 R600_PIPE_STATE_CONFIG, 119 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 120 R600_PIPE_STATE_CLIP, 121 R600_PIPE_STATE_SCISSOR, 122 R600_PIPE_STATE_VIEWPORT, 123 R600_PIPE_STATE_RASTERIZER, 124 R600_PIPE_STATE_VGT, 125 R600_PIPE_STATE_FRAMEBUFFER, 126 R600_PIPE_STATE_DSA, 127 R600_PIPE_STATE_STENCIL_REF, 128 R600_PIPE_STATE_PS_SHADER, 129 R600_PIPE_STATE_VS_SHADER, 130 R600_PIPE_STATE_CONSTANT, 131 R600_PIPE_STATE_SAMPLER, 132 R600_PIPE_STATE_RESOURCE, 133 R600_PIPE_STATE_POLYGON_OFFSET, 134 R600_PIPE_STATE_FETCH_SHADER, 135 R600_PIPE_STATE_SPI, 136 R600_PIPE_NSTATES 137}; 138 139struct compute_memory_pool; 140void compute_memory_pool_delete(struct compute_memory_pool* pool); 141struct compute_memory_pool* compute_memory_pool_new( 142 struct r600_screen *rscreen); 143 144struct r600_pipe_fences { 145 struct r600_resource *bo; 146 unsigned *data; 147 unsigned next_index; 148 /* linked list of preallocated blocks */ 149 struct list_head blocks; 150 /* linked list of freed fences */ 151 struct list_head pool; 152 pipe_mutex mutex; 153}; 154 155struct r600_screen { 156 struct pipe_screen screen; 157 struct radeon_winsys *ws; 158 unsigned family; 159 enum chip_class chip_class; 160 struct radeon_info info; 161 bool has_streamout; 162 struct r600_tiling_info tiling_info; 163 struct r600_pipe_fences fences; 164 165 /*for compute global memory binding, we allocate stuff here, instead of 166 * buffers. 167 * XXX: Not sure if this is the best place for global_pool. Also, 168 * it's not thread safe, so it won't work with multiple contexts. */ 169 struct compute_memory_pool *global_pool; 170}; 171 172struct r600_pipe_sampler_view { 173 struct pipe_sampler_view base; 174 struct r600_resource *tex_resource; 175 uint32_t tex_resource_words[8]; 176}; 177 178struct r600_pipe_rasterizer { 179 struct r600_pipe_state rstate; 180 boolean flatshade; 181 boolean two_side; 182 unsigned sprite_coord_enable; 183 unsigned clip_plane_enable; 184 unsigned pa_sc_line_stipple; 185 unsigned pa_cl_clip_cntl; 186 float offset_units; 187 float offset_scale; 188 bool scissor_enable; 189 bool multisample_enable; 190}; 191 192struct r600_pipe_blend { 193 struct r600_pipe_state rstate; 194 unsigned cb_target_mask; 195 unsigned cb_color_control; 196 bool dual_src_blend; 197 bool alpha_to_one; 198}; 199 200struct r600_pipe_dsa { 201 struct r600_pipe_state rstate; 202 unsigned alpha_ref; 203 ubyte valuemask[2]; 204 ubyte writemask[2]; 205 unsigned sx_alpha_test_control; 206}; 207 208struct r600_vertex_element 209{ 210 unsigned count; 211 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 212 struct r600_resource *fetch_shader; 213 unsigned fs_size; 214 struct r600_pipe_state rstate; 215}; 216 217struct r600_pipe_shader; 218 219struct r600_pipe_shader_selector { 220 struct r600_pipe_shader *current; 221 222 struct tgsi_token *tokens; 223 struct pipe_stream_output_info so; 224 225 unsigned num_shaders; 226 227 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 228 unsigned type; 229 230 unsigned nr_ps_max_color_exports; 231}; 232 233struct r600_pipe_shader { 234 struct r600_pipe_shader_selector *selector; 235 struct r600_pipe_shader *next_variant; 236 struct r600_shader shader; 237 struct r600_pipe_state rstate; 238 struct r600_resource *bo; 239 struct r600_resource *bo_fetch; 240 struct r600_vertex_element vertex_elements; 241 unsigned sprite_coord_enable; 242 unsigned flatshade; 243 unsigned pa_cl_vs_out_cntl; 244 unsigned nr_ps_color_outputs; 245 unsigned key; 246 unsigned db_shader_control; 247 unsigned ps_depth_export; 248}; 249 250struct r600_pipe_sampler_state { 251 uint32_t tex_sampler_words[3]; 252 uint32_t border_color[4]; 253 bool border_color_use; 254 bool seamless_cube_map; 255}; 256 257/* needed for blitter save */ 258#define NUM_TEX_UNITS 16 259 260struct r600_seamless_cube_map { 261 struct r600_atom atom; 262 bool enabled; 263}; 264 265struct r600_samplerview_state { 266 struct r600_atom atom; 267 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 268 uint32_t enabled_mask; 269 uint32_t dirty_mask; 270 uint32_t depth_texture_mask; /* which textures are depth */ 271}; 272 273struct r600_textures_info { 274 struct r600_samplerview_state views; 275 struct r600_atom atom_sampler; 276 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 277 unsigned n_samplers; 278 bool is_array_sampler[NUM_TEX_UNITS]; 279}; 280 281struct r600_fence { 282 struct pipe_reference reference; 283 unsigned index; /* in the shared bo */ 284 struct r600_resource *sleep_bo; 285 struct list_head head; 286}; 287 288#define FENCE_BLOCK_SIZE 16 289 290struct r600_fence_block { 291 struct r600_fence fences[FENCE_BLOCK_SIZE]; 292 struct list_head head; 293}; 294 295#define R600_CONSTANT_ARRAY_SIZE 256 296#define R600_RESOURCE_ARRAY_SIZE 160 297 298struct r600_stencil_ref 299{ 300 ubyte ref_value[2]; 301 ubyte valuemask[2]; 302 ubyte writemask[2]; 303}; 304 305struct r600_constbuf_state 306{ 307 struct r600_atom atom; 308 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 309 uint32_t enabled_mask; 310 uint32_t dirty_mask; 311}; 312 313struct r600_vertexbuf_state 314{ 315 struct r600_atom atom; 316 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 317 uint32_t enabled_mask; /* non-NULL buffers */ 318 uint32_t dirty_mask; 319}; 320 321struct r600_context { 322 struct pipe_context context; 323 struct blitter_context *blitter; 324 enum radeon_family family; 325 enum chip_class chip_class; 326 boolean has_vertex_cache; 327 unsigned r6xx_num_clause_temp_gprs; 328 void *custom_dsa_flush; 329 struct r600_screen *screen; 330 struct radeon_winsys *ws; 331 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 332 struct r600_vertex_element *vertex_elements; 333 struct pipe_framebuffer_state framebuffer; 334 unsigned compute_cb_target_mask; 335 unsigned db_shader_control; 336 unsigned pa_sc_line_stipple; 337 unsigned pa_cl_clip_cntl; 338 /* for saving when using blitter */ 339 struct pipe_stencil_ref stencil_ref; 340 struct pipe_viewport_state viewport; 341 struct pipe_clip_state clip; 342 struct r600_pipe_shader_selector *ps_shader; 343 struct r600_pipe_shader_selector *vs_shader; 344 struct r600_pipe_rasterizer *rasterizer; 345 struct r600_pipe_state vgt; 346 struct r600_pipe_state spi; 347 struct pipe_query *current_render_cond; 348 unsigned current_render_cond_mode; 349 struct pipe_query *saved_render_cond; 350 unsigned saved_render_cond_mode; 351 /* shader information */ 352 boolean two_side; 353 boolean spi_dirty; 354 unsigned sprite_coord_enable; 355 boolean flatshade; 356 boolean export_16bpc; 357 unsigned nr_cbufs; 358 bool alpha_to_one; 359 bool multisample_enable; 360 bool cb0_is_integer; 361 362 struct u_upload_mgr *uploader; 363 struct util_slab_mempool pool_transfers; 364 365 unsigned default_ps_gprs, default_vs_gprs; 366 367 /* States based on r600_atom. */ 368 struct list_head dirty_states; 369 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 370 /** Compute specific registers initializations. The start_cs_cmd atom 371 * must be emitted before start_compute_cs_cmd. */ 372 struct r600_command_buffer start_compute_cs_cmd; 373 struct r600_surface_sync_cmd surface_sync_cmd; 374 struct r600_atom r6xx_flush_and_inv_cmd; 375 struct r600_alphatest_state alphatest_state; 376 struct r600_cb_misc_state cb_misc_state; 377 struct r600_db_misc_state db_misc_state; 378 /** Vertex buffers for fetch shaders */ 379 struct r600_vertexbuf_state vertex_buffer_state; 380 /** Vertex buffers for compute shaders */ 381 struct r600_vertexbuf_state cs_vertex_buffer_state; 382 struct r600_constbuf_state vs_constbuf_state; 383 struct r600_constbuf_state ps_constbuf_state; 384 struct r600_textures_info vs_samplers; 385 struct r600_textures_info ps_samplers; 386 struct r600_seamless_cube_map seamless_cube_map; 387 struct r600_cs_shader_state cs_shader_state; 388 struct r600_sample_mask sample_mask; 389 390 struct radeon_winsys_cs *cs; 391 392 struct r600_range *range; 393 unsigned nblocks; 394 struct r600_block **blocks; 395 struct list_head dirty; 396 struct list_head enable_list; 397 unsigned pm4_dirty_cdwords; 398 unsigned ctx_pm4_ndwords; 399 400 /* The list of active queries. Only one query of each type can be active. */ 401 int num_occlusion_queries; 402 403 /* Manage queries in two separate groups: 404 * The timer ones and the others (streamout, occlusion). 405 * 406 * We do this because we should only suspend non-timer queries for u_blitter, 407 * and later if the non-timer queries are suspended, the context flush should 408 * only suspend and resume the timer queries. */ 409 struct list_head active_timer_queries; 410 unsigned num_cs_dw_timer_queries_suspend; 411 struct list_head active_nontimer_queries; 412 unsigned num_cs_dw_nontimer_queries_suspend; 413 414 unsigned num_cs_dw_streamout_end; 415 416 unsigned backend_mask; 417 unsigned max_db; /* for OQ */ 418 unsigned flags; 419 boolean predicate_drawing; 420 421 unsigned num_so_targets; 422 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 423 boolean streamout_start; 424 unsigned streamout_append_bitmask; 425 426 /* There is no scissor enable bit on r6xx, so we must use a workaround. 427 * These track the current scissor state. */ 428 bool scissor_enable; 429 struct pipe_scissor_state scissor_state; 430 431 /* With rasterizer discard, there doesn't have to be a pixel shader. 432 * In that case, we bind this one: */ 433 void *dummy_pixel_shader; 434 435 boolean dual_src_blend; 436 437 /* Index buffer. */ 438 struct pipe_index_buffer index_buffer; 439}; 440 441static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 442{ 443 atom->emit(rctx, atom); 444 atom->dirty = false; 445 if (atom->head.next && atom->head.prev) 446 LIST_DELINIT(&atom->head); 447} 448 449static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 450{ 451 if (!state->dirty) { 452 if (state->flags & EMIT_EARLY) { 453 LIST_ADD(&state->head, &rctx->dirty_states); 454 } else { 455 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 456 } 457 state->dirty = true; 458 } 459} 460 461/* evergreen_state.c */ 462void evergreen_init_state_functions(struct r600_context *rctx); 463void evergreen_init_atom_start_cs(struct r600_context *rctx); 464void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 465void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 466void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 467void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 468void evergreen_polygon_offset_update(struct r600_context *rctx); 469boolean evergreen_is_format_supported(struct pipe_screen *screen, 470 enum pipe_format format, 471 enum pipe_texture_target target, 472 unsigned sample_count, 473 unsigned usage); 474void evergreen_init_color_surface(struct r600_context *rctx, 475 struct r600_surface *surf); 476void evergreen_update_dual_export_state(struct r600_context * rctx); 477 478/* r600_blit.c */ 479void r600_copy_buffer(struct pipe_context *ctx, struct 480 pipe_resource *dst, unsigned dstx, 481 struct pipe_resource *src, const struct pipe_box *src_box); 482void r600_init_blit_functions(struct r600_context *rctx); 483void r600_blit_uncompress_depth(struct pipe_context *ctx, 484 struct r600_resource_texture *texture, 485 struct r600_resource_texture *staging, 486 unsigned first_level, unsigned last_level, 487 unsigned first_layer, unsigned last_layer, 488 unsigned first_sample, unsigned last_sample); 489void r600_flush_depth_textures(struct r600_context *rctx, 490 struct r600_samplerview_state *textures); 491 492/* r600_buffer.c */ 493bool r600_init_resource(struct r600_screen *rscreen, 494 struct r600_resource *res, 495 unsigned size, unsigned alignment, 496 unsigned bind, unsigned usage); 497struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 498 const struct pipe_resource *templ); 499 500/* r600_pipe.c */ 501void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 502 unsigned flags); 503 504/* r600_query.c */ 505void r600_init_query_functions(struct r600_context *rctx); 506void r600_suspend_nontimer_queries(struct r600_context *ctx); 507void r600_resume_nontimer_queries(struct r600_context *ctx); 508void r600_suspend_timer_queries(struct r600_context *ctx); 509void r600_resume_timer_queries(struct r600_context *ctx); 510 511/* r600_resource.c */ 512void r600_init_context_resource_functions(struct r600_context *r600); 513 514/* r600_shader.c */ 515int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 516#ifdef HAVE_OPENCL 517int r600_compute_shader_create(struct pipe_context * ctx, 518 LLVMModuleRef mod, struct r600_bytecode * bytecode); 519#endif 520void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 521 522/* r600_state.c */ 523void r600_set_scissor_state(struct r600_context *rctx, 524 const struct pipe_scissor_state *state); 525void r600_init_state_functions(struct r600_context *rctx); 526void r600_init_atom_start_cs(struct r600_context *rctx); 527void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 528void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 529void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 530void *r600_create_db_flush_dsa(struct r600_context *rctx); 531void r600_polygon_offset_update(struct r600_context *rctx); 532void r600_adjust_gprs(struct r600_context *rctx); 533boolean r600_is_format_supported(struct pipe_screen *screen, 534 enum pipe_format format, 535 enum pipe_texture_target target, 536 unsigned sample_count, 537 unsigned usage); 538void r600_update_dual_export_state(struct r600_context * rctx); 539 540/* r600_texture.c */ 541void r600_init_screen_texture_functions(struct pipe_screen *screen); 542void r600_init_surface_functions(struct r600_context *r600); 543uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 544 const unsigned char *swizzle_view, 545 uint32_t *word4_p, uint32_t *yuv_format_p); 546unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 547 unsigned level, unsigned layer); 548 549/* r600_translate.c */ 550void r600_translate_index_buffer(struct r600_context *r600, 551 struct pipe_index_buffer *ib, 552 unsigned count); 553 554/* r600_state_common.c */ 555void r600_init_atom(struct r600_atom *atom, 556 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 557 unsigned num_dw, enum r600_atom_flags flags); 558void r600_init_common_atoms(struct r600_context *rctx); 559unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 560void r600_texture_barrier(struct pipe_context *ctx); 561void r600_set_index_buffer(struct pipe_context *ctx, 562 const struct pipe_index_buffer *ib); 563void r600_vertex_buffers_dirty(struct r600_context *rctx); 564void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 565 const struct pipe_vertex_buffer *input); 566void r600_sampler_views_dirty(struct r600_context *rctx, 567 struct r600_samplerview_state *state); 568void r600_set_sampler_views(struct r600_context *rctx, 569 struct r600_textures_info *dst, 570 unsigned count, 571 struct pipe_sampler_view **views); 572void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states); 573void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states); 574void *r600_create_vertex_elements(struct pipe_context *ctx, 575 unsigned count, 576 const struct pipe_vertex_element *elements); 577void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 578void r600_bind_blend_state(struct pipe_context *ctx, void *state); 579void r600_set_blend_color(struct pipe_context *ctx, 580 const struct pipe_blend_color *state); 581void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 582void r600_set_max_scissor(struct r600_context *rctx); 583void r600_bind_rs_state(struct pipe_context *ctx, void *state); 584void r600_delete_rs_state(struct pipe_context *ctx, void *state); 585void r600_sampler_view_destroy(struct pipe_context *ctx, 586 struct pipe_sampler_view *state); 587void r600_delete_sampler(struct pipe_context *ctx, void *state); 588void r600_delete_state(struct pipe_context *ctx, void *state); 589void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 590void *r600_create_shader_state_ps(struct pipe_context *ctx, 591 const struct pipe_shader_state *state); 592void *r600_create_shader_state_vs(struct pipe_context *ctx, 593 const struct pipe_shader_state *state); 594void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 595void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 596void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 597void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 598void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 599void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 600 struct pipe_constant_buffer *cb); 601struct pipe_stream_output_target * 602r600_create_so_target(struct pipe_context *ctx, 603 struct pipe_resource *buffer, 604 unsigned buffer_offset, 605 unsigned buffer_size); 606void r600_so_target_destroy(struct pipe_context *ctx, 607 struct pipe_stream_output_target *target); 608void r600_set_so_targets(struct pipe_context *ctx, 609 unsigned num_targets, 610 struct pipe_stream_output_target **targets, 611 unsigned append_bitmask); 612void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask); 613void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 614 const struct pipe_stencil_ref *state); 615void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 616uint32_t r600_translate_stencil_op(int s_op); 617uint32_t r600_translate_fill(uint32_t func); 618unsigned r600_tex_wrap(unsigned wrap); 619unsigned r600_tex_filter(unsigned filter); 620unsigned r600_tex_mipfilter(unsigned filter); 621unsigned r600_tex_compare(unsigned compare); 622 623/* 624 * Helpers for building command buffers 625 */ 626 627#define PKT3_SET_CONFIG_REG 0x68 628#define PKT3_SET_CONTEXT_REG 0x69 629#define PKT3_SET_CTL_CONST 0x6F 630#define PKT3_SET_LOOP_CONST 0x6C 631 632#define R600_CONFIG_REG_OFFSET 0x08000 633#define R600_CONTEXT_REG_OFFSET 0x28000 634#define R600_CTL_CONST_OFFSET 0x3CFF0 635#define R600_LOOP_CONST_OFFSET 0X0003E200 636#define EG_LOOP_CONST_OFFSET 0x0003A200 637 638#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 639#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 640#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 641#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 642#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 643 644#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 645 646/*Evergreen Compute packet3*/ 647#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE) 648 649static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 650{ 651 cb->buf[cb->atom.num_dw++] = value; 652} 653 654static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 655{ 656 assert(reg < R600_CONTEXT_REG_OFFSET); 657 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 658 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 659 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 660} 661 662/** 663 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 664 * shaders. 665 */ 666static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 667{ 668 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 669 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 670 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 671 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 672} 673 674/** 675 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 676 * shaders. 677 */ 678static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 679{ 680 assert(reg >= R600_CTL_CONST_OFFSET); 681 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 682 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 683 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 684} 685 686static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 687{ 688 assert(reg >= R600_LOOP_CONST_OFFSET); 689 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 690 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 691 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 692} 693 694/** 695 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 696 * shaders. 697 */ 698static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 699{ 700 assert(reg >= EG_LOOP_CONST_OFFSET); 701 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 702 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 703 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 704} 705 706static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 707{ 708 r600_store_config_reg_seq(cb, reg, 1); 709 r600_store_value(cb, value); 710} 711 712static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 713{ 714 r600_store_context_reg_seq(cb, reg, 1); 715 r600_store_value(cb, value); 716} 717 718static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 719{ 720 r600_store_ctl_const_seq(cb, reg, 1); 721 r600_store_value(cb, value); 722} 723 724static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 725{ 726 r600_store_loop_const_seq(cb, reg, 1); 727 r600_store_value(cb, value); 728} 729 730static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 731{ 732 eg_store_loop_const_seq(cb, reg, 1); 733 r600_store_value(cb, value); 734} 735 736void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 737void r600_release_command_buffer(struct r600_command_buffer *cb); 738 739/* 740 * Helpers for emitting state into a command stream directly. 741 */ 742 743static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 744 enum radeon_bo_usage usage) 745{ 746 assert(usage); 747 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 748} 749 750static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 751{ 752 cs->buf[cs->cdw++] = value; 753} 754 755static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr) 756{ 757 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS); 758 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0])); 759 cs->cdw += num; 760} 761 762static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 763{ 764 assert(reg < R600_CONTEXT_REG_OFFSET); 765 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 766 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 767 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 768} 769 770static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 771{ 772 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 773 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 774 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 775 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 776} 777 778static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 779{ 780 r600_write_context_reg_seq(cs, reg, num); 781 /* Set the compute bit on the packet header */ 782 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; 783} 784 785static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 786{ 787 assert(reg >= R600_CTL_CONST_OFFSET); 788 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 789 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 790 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 791} 792 793static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 794{ 795 r600_write_config_reg_seq(cs, reg, 1); 796 r600_write_value(cs, value); 797} 798 799static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 800{ 801 r600_write_context_reg_seq(cs, reg, 1); 802 r600_write_value(cs, value); 803} 804 805static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 806{ 807 r600_write_compute_context_reg_seq(cs, reg, 1); 808 r600_write_value(cs, value); 809} 810 811static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 812{ 813 r600_write_ctl_const_seq(cs, reg, 1); 814 r600_write_value(cs, value); 815} 816 817/* 818 * common helpers 819 */ 820static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 821{ 822 return value * (1 << frac_bits); 823} 824#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 825 826static inline unsigned r600_tex_aniso_filter(unsigned filter) 827{ 828 if (filter <= 1) return 0; 829 if (filter <= 2) return 1; 830 if (filter <= 4) return 2; 831 if (filter <= 8) return 3; 832 /* else */ return 4; 833} 834 835/* 12.4 fixed-point */ 836static INLINE unsigned r600_pack_float_12p4(float x) 837{ 838 return x <= 0 ? 0 : 839 x >= 4096 ? 0xffff : x * 16; 840} 841 842static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 843{ 844 struct r600_screen *rscreen = (struct r600_screen*)screen; 845 struct r600_resource *rresource = (struct r600_resource*)resource; 846 847 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 848} 849 850#endif 851