r600_pipe.h revision a01791add08fbcb5386e0e9209ba21ed58fbdc42
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26#ifndef R600_PIPE_H 27#define R600_PIPE_H 28 29#include "util/u_slab.h" 30#include "r600.h" 31#include "r600_llvm.h" 32#include "r600_public.h" 33#include "r600_shader.h" 34#include "r600_resource.h" 35#include "evergreen_compute.h" 36 37#define R600_MAX_CONST_BUFFERS 2 38#define R600_MAX_CONST_BUFFER_SIZE 4096 39 40#ifdef PIPE_ARCH_BIG_ENDIAN 41#define R600_BIG_ENDIAN 1 42#else 43#define R600_BIG_ENDIAN 0 44#endif 45 46enum r600_atom_flags { 47 /* When set, atoms are added at the beginning of the dirty list 48 * instead of the end. */ 49 EMIT_EARLY = (1 << 0) 50}; 51 52/* This encapsulates a state or an operation which can emitted into the GPU 53 * command stream. It's not limited to states only, it can be used for anything 54 * that wants to write commands into the CS (e.g. cache flushes). */ 55struct r600_atom { 56 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 57 58 unsigned num_dw; 59 enum r600_atom_flags flags; 60 bool dirty; 61 62 struct list_head head; 63}; 64 65/* This is an atom containing GPU commands that never change. 66 * This is supposed to be copied directly into the CS. */ 67struct r600_command_buffer { 68 struct r600_atom atom; 69 uint32_t *buf; 70 unsigned max_num_dw; 71 unsigned pkt_flags; 72}; 73 74struct r600_surface_sync_cmd { 75 struct r600_atom atom; 76 unsigned flush_flags; /* CP_COHER_CNTL */ 77}; 78 79struct r600_db_misc_state { 80 struct r600_atom atom; 81 bool occlusion_query_enabled; 82 bool flush_depthstencil_through_cb; 83 bool copy_depth, copy_stencil; 84}; 85 86struct r600_cb_misc_state { 87 struct r600_atom atom; 88 unsigned cb_color_control; /* this comes from blend state */ 89 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 90 unsigned nr_cbufs; 91 unsigned nr_ps_color_outputs; 92 bool multiwrite; 93 bool dual_src_blend; 94}; 95 96struct r600_alphatest_state { 97 struct r600_atom atom; 98 unsigned sx_alpha_test_control; /* this comes from dsa state */ 99 unsigned sx_alpha_ref; /* this comes from dsa state */ 100 bool bypass; 101 bool cb0_export_16bpc; /* from set_framebuffer_state */ 102}; 103 104struct r600_cs_shader_state { 105 struct r600_atom atom; 106 struct r600_pipe_compute *shader; 107}; 108 109struct r600_sample_mask { 110 struct r600_atom atom; 111 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */ 112}; 113 114enum r600_pipe_state_id { 115 R600_PIPE_STATE_BLEND = 0, 116 R600_PIPE_STATE_BLEND_COLOR, 117 R600_PIPE_STATE_CONFIG, 118 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 119 R600_PIPE_STATE_CLIP, 120 R600_PIPE_STATE_SCISSOR, 121 R600_PIPE_STATE_VIEWPORT, 122 R600_PIPE_STATE_RASTERIZER, 123 R600_PIPE_STATE_VGT, 124 R600_PIPE_STATE_FRAMEBUFFER, 125 R600_PIPE_STATE_DSA, 126 R600_PIPE_STATE_STENCIL_REF, 127 R600_PIPE_STATE_PS_SHADER, 128 R600_PIPE_STATE_VS_SHADER, 129 R600_PIPE_STATE_CONSTANT, 130 R600_PIPE_STATE_SAMPLER, 131 R600_PIPE_STATE_RESOURCE, 132 R600_PIPE_STATE_POLYGON_OFFSET, 133 R600_PIPE_STATE_FETCH_SHADER, 134 R600_PIPE_STATE_SPI, 135 R600_PIPE_NSTATES 136}; 137 138struct compute_memory_pool; 139void compute_memory_pool_delete(struct compute_memory_pool* pool); 140struct compute_memory_pool* compute_memory_pool_new( 141 struct r600_screen *rscreen); 142 143struct r600_pipe_fences { 144 struct r600_resource *bo; 145 unsigned *data; 146 unsigned next_index; 147 /* linked list of preallocated blocks */ 148 struct list_head blocks; 149 /* linked list of freed fences */ 150 struct list_head pool; 151 pipe_mutex mutex; 152}; 153 154struct r600_screen { 155 struct pipe_screen screen; 156 struct radeon_winsys *ws; 157 unsigned family; 158 enum chip_class chip_class; 159 struct radeon_info info; 160 bool has_streamout; 161 struct r600_tiling_info tiling_info; 162 struct r600_pipe_fences fences; 163 164 /*for compute global memory binding, we allocate stuff here, instead of 165 * buffers. 166 * XXX: Not sure if this is the best place for global_pool. Also, 167 * it's not thread safe, so it won't work with multiple contexts. */ 168 struct compute_memory_pool *global_pool; 169}; 170 171struct r600_pipe_sampler_view { 172 struct pipe_sampler_view base; 173 struct r600_resource *tex_resource; 174 uint32_t tex_resource_words[8]; 175}; 176 177struct r600_pipe_rasterizer { 178 struct r600_pipe_state rstate; 179 boolean flatshade; 180 boolean two_side; 181 unsigned sprite_coord_enable; 182 unsigned clip_plane_enable; 183 unsigned pa_sc_line_stipple; 184 unsigned pa_cl_clip_cntl; 185 float offset_units; 186 float offset_scale; 187 bool scissor_enable; 188 bool multisample_enable; 189}; 190 191struct r600_pipe_blend { 192 struct r600_pipe_state rstate; 193 unsigned cb_target_mask; 194 unsigned cb_color_control; 195 bool dual_src_blend; 196 bool alpha_to_one; 197}; 198 199struct r600_pipe_dsa { 200 struct r600_pipe_state rstate; 201 unsigned alpha_ref; 202 ubyte valuemask[2]; 203 ubyte writemask[2]; 204 unsigned sx_alpha_test_control; 205}; 206 207struct r600_vertex_element 208{ 209 unsigned count; 210 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 211 struct r600_resource *fetch_shader; 212 unsigned fs_size; 213 struct r600_pipe_state rstate; 214}; 215 216struct r600_pipe_shader; 217 218struct r600_pipe_shader_selector { 219 struct r600_pipe_shader *current; 220 221 struct tgsi_token *tokens; 222 struct pipe_stream_output_info so; 223 224 unsigned num_shaders; 225 226 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 227 unsigned type; 228 229 unsigned nr_ps_max_color_exports; 230}; 231 232struct r600_pipe_shader { 233 struct r600_pipe_shader_selector *selector; 234 struct r600_pipe_shader *next_variant; 235 struct r600_shader shader; 236 struct r600_pipe_state rstate; 237 struct r600_resource *bo; 238 struct r600_resource *bo_fetch; 239 struct r600_vertex_element vertex_elements; 240 unsigned sprite_coord_enable; 241 unsigned flatshade; 242 unsigned pa_cl_vs_out_cntl; 243 unsigned nr_ps_color_outputs; 244 unsigned key; 245 unsigned db_shader_control; 246 unsigned ps_depth_export; 247}; 248 249struct r600_pipe_sampler_state { 250 uint32_t tex_sampler_words[3]; 251 uint32_t border_color[4]; 252 bool border_color_use; 253 bool seamless_cube_map; 254}; 255 256/* needed for blitter save */ 257#define NUM_TEX_UNITS 16 258 259struct r600_seamless_cube_map { 260 struct r600_atom atom; 261 bool enabled; 262}; 263 264struct r600_samplerview_state { 265 struct r600_atom atom; 266 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 267 uint32_t enabled_mask; 268 uint32_t dirty_mask; 269 uint32_t depth_texture_mask; /* which textures are depth */ 270}; 271 272struct r600_textures_info { 273 struct r600_samplerview_state views; 274 struct r600_atom atom_sampler; 275 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 276 unsigned n_samplers; 277 bool is_array_sampler[NUM_TEX_UNITS]; 278}; 279 280struct r600_fence { 281 struct pipe_reference reference; 282 unsigned index; /* in the shared bo */ 283 struct r600_resource *sleep_bo; 284 struct list_head head; 285}; 286 287#define FENCE_BLOCK_SIZE 16 288 289struct r600_fence_block { 290 struct r600_fence fences[FENCE_BLOCK_SIZE]; 291 struct list_head head; 292}; 293 294#define R600_CONSTANT_ARRAY_SIZE 256 295#define R600_RESOURCE_ARRAY_SIZE 160 296 297struct r600_stencil_ref 298{ 299 ubyte ref_value[2]; 300 ubyte valuemask[2]; 301 ubyte writemask[2]; 302}; 303 304struct r600_constbuf_state 305{ 306 struct r600_atom atom; 307 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 308 uint32_t enabled_mask; 309 uint32_t dirty_mask; 310}; 311 312struct r600_vertexbuf_state 313{ 314 struct r600_atom atom; 315 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 316 uint32_t enabled_mask; /* non-NULL buffers */ 317 uint32_t dirty_mask; 318}; 319 320struct r600_context { 321 struct pipe_context context; 322 struct blitter_context *blitter; 323 enum radeon_family family; 324 enum chip_class chip_class; 325 boolean has_vertex_cache; 326 unsigned r6xx_num_clause_temp_gprs; 327 void *custom_dsa_flush; 328 struct r600_screen *screen; 329 struct radeon_winsys *ws; 330 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 331 struct r600_vertex_element *vertex_elements; 332 struct pipe_framebuffer_state framebuffer; 333 unsigned compute_cb_target_mask; 334 unsigned db_shader_control; 335 unsigned pa_sc_line_stipple; 336 unsigned pa_cl_clip_cntl; 337 /* for saving when using blitter */ 338 struct pipe_stencil_ref stencil_ref; 339 struct pipe_viewport_state viewport; 340 struct pipe_clip_state clip; 341 struct r600_pipe_shader_selector *ps_shader; 342 struct r600_pipe_shader_selector *vs_shader; 343 struct r600_pipe_rasterizer *rasterizer; 344 struct r600_pipe_state vgt; 345 struct r600_pipe_state spi; 346 struct pipe_query *current_render_cond; 347 unsigned current_render_cond_mode; 348 struct pipe_query *saved_render_cond; 349 unsigned saved_render_cond_mode; 350 /* shader information */ 351 boolean two_side; 352 boolean spi_dirty; 353 unsigned sprite_coord_enable; 354 boolean flatshade; 355 boolean export_16bpc; 356 unsigned nr_cbufs; 357 bool alpha_to_one; 358 bool multisample_enable; 359 bool cb0_is_integer; 360 361 struct u_upload_mgr *uploader; 362 struct util_slab_mempool pool_transfers; 363 364 unsigned default_ps_gprs, default_vs_gprs; 365 366 /* States based on r600_atom. */ 367 struct list_head dirty_states; 368 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 369 /** Compute specific registers initializations. The start_cs_cmd atom 370 * must be emitted before start_compute_cs_cmd. */ 371 struct r600_command_buffer start_compute_cs_cmd; 372 struct r600_surface_sync_cmd surface_sync_cmd; 373 struct r600_atom r6xx_flush_and_inv_cmd; 374 struct r600_alphatest_state alphatest_state; 375 struct r600_cb_misc_state cb_misc_state; 376 struct r600_db_misc_state db_misc_state; 377 /** Vertex buffers for fetch shaders */ 378 struct r600_vertexbuf_state vertex_buffer_state; 379 /** Vertex buffers for compute shaders */ 380 struct r600_vertexbuf_state cs_vertex_buffer_state; 381 struct r600_constbuf_state vs_constbuf_state; 382 struct r600_constbuf_state ps_constbuf_state; 383 struct r600_textures_info vs_samplers; 384 struct r600_textures_info ps_samplers; 385 struct r600_seamless_cube_map seamless_cube_map; 386 struct r600_cs_shader_state cs_shader_state; 387 struct r600_sample_mask sample_mask; 388 389 struct radeon_winsys_cs *cs; 390 391 struct r600_range *range; 392 unsigned nblocks; 393 struct r600_block **blocks; 394 struct list_head dirty; 395 struct list_head enable_list; 396 unsigned pm4_dirty_cdwords; 397 unsigned ctx_pm4_ndwords; 398 399 /* The list of active queries. Only one query of each type can be active. */ 400 int num_occlusion_queries; 401 402 /* Manage queries in two separate groups: 403 * The timer ones and the others (streamout, occlusion). 404 * 405 * We do this because we should only suspend non-timer queries for u_blitter, 406 * and later if the non-timer queries are suspended, the context flush should 407 * only suspend and resume the timer queries. */ 408 struct list_head active_timer_queries; 409 unsigned num_cs_dw_timer_queries_suspend; 410 struct list_head active_nontimer_queries; 411 unsigned num_cs_dw_nontimer_queries_suspend; 412 413 unsigned num_cs_dw_streamout_end; 414 415 unsigned backend_mask; 416 unsigned max_db; /* for OQ */ 417 unsigned flags; 418 boolean predicate_drawing; 419 420 unsigned num_so_targets; 421 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 422 boolean streamout_start; 423 unsigned streamout_append_bitmask; 424 425 /* There is no scissor enable bit on r6xx, so we must use a workaround. 426 * These track the current scissor state. */ 427 bool scissor_enable; 428 struct pipe_scissor_state scissor_state; 429 430 /* With rasterizer discard, there doesn't have to be a pixel shader. 431 * In that case, we bind this one: */ 432 void *dummy_pixel_shader; 433 434 boolean dual_src_blend; 435 436 /* Index buffer. */ 437 struct pipe_index_buffer index_buffer; 438}; 439 440static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 441{ 442 atom->emit(rctx, atom); 443 atom->dirty = false; 444 if (atom->head.next && atom->head.prev) 445 LIST_DELINIT(&atom->head); 446} 447 448static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 449{ 450 if (!state->dirty) { 451 if (state->flags & EMIT_EARLY) { 452 LIST_ADD(&state->head, &rctx->dirty_states); 453 } else { 454 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 455 } 456 state->dirty = true; 457 } 458} 459 460/* evergreen_state.c */ 461void evergreen_init_state_functions(struct r600_context *rctx); 462void evergreen_init_atom_start_cs(struct r600_context *rctx); 463void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 464void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 465void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 466void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 467void evergreen_polygon_offset_update(struct r600_context *rctx); 468boolean evergreen_is_format_supported(struct pipe_screen *screen, 469 enum pipe_format format, 470 enum pipe_texture_target target, 471 unsigned sample_count, 472 unsigned usage); 473void evergreen_init_color_surface(struct r600_context *rctx, 474 struct r600_surface *surf); 475void evergreen_update_dual_export_state(struct r600_context * rctx); 476 477/* r600_blit.c */ 478void r600_copy_buffer(struct pipe_context *ctx, struct 479 pipe_resource *dst, unsigned dstx, 480 struct pipe_resource *src, const struct pipe_box *src_box); 481void r600_init_blit_functions(struct r600_context *rctx); 482void r600_blit_uncompress_depth(struct pipe_context *ctx, 483 struct r600_resource_texture *texture, 484 struct r600_resource_texture *staging, 485 unsigned first_level, unsigned last_level, 486 unsigned first_layer, unsigned last_layer); 487void r600_flush_depth_textures(struct r600_context *rctx, 488 struct r600_samplerview_state *textures); 489/* r600_buffer.c */ 490bool r600_init_resource(struct r600_screen *rscreen, 491 struct r600_resource *res, 492 unsigned size, unsigned alignment, 493 unsigned bind, unsigned usage); 494struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 495 const struct pipe_resource *templ); 496 497/* r600_pipe.c */ 498void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 499 unsigned flags); 500 501/* r600_query.c */ 502void r600_init_query_functions(struct r600_context *rctx); 503void r600_suspend_nontimer_queries(struct r600_context *ctx); 504void r600_resume_nontimer_queries(struct r600_context *ctx); 505void r600_suspend_timer_queries(struct r600_context *ctx); 506void r600_resume_timer_queries(struct r600_context *ctx); 507 508/* r600_resource.c */ 509void r600_init_context_resource_functions(struct r600_context *r600); 510 511/* r600_shader.c */ 512int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 513#ifdef HAVE_OPENCL 514int r600_compute_shader_create(struct pipe_context * ctx, 515 LLVMModuleRef mod, struct r600_bytecode * bytecode); 516#endif 517void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 518 519/* r600_state.c */ 520void r600_set_scissor_state(struct r600_context *rctx, 521 const struct pipe_scissor_state *state); 522void r600_init_state_functions(struct r600_context *rctx); 523void r600_init_atom_start_cs(struct r600_context *rctx); 524void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 525void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 526void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 527void *r600_create_db_flush_dsa(struct r600_context *rctx); 528void r600_polygon_offset_update(struct r600_context *rctx); 529void r600_adjust_gprs(struct r600_context *rctx); 530boolean r600_is_format_supported(struct pipe_screen *screen, 531 enum pipe_format format, 532 enum pipe_texture_target target, 533 unsigned sample_count, 534 unsigned usage); 535void r600_update_dual_export_state(struct r600_context * rctx); 536 537/* r600_texture.c */ 538void r600_init_screen_texture_functions(struct pipe_screen *screen); 539void r600_init_surface_functions(struct r600_context *r600); 540uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 541 const unsigned char *swizzle_view, 542 uint32_t *word4_p, uint32_t *yuv_format_p); 543unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 544 unsigned level, unsigned layer); 545 546/* r600_translate.c */ 547void r600_translate_index_buffer(struct r600_context *r600, 548 struct pipe_index_buffer *ib, 549 unsigned count); 550 551/* r600_state_common.c */ 552void r600_init_atom(struct r600_atom *atom, 553 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 554 unsigned num_dw, enum r600_atom_flags flags); 555void r600_init_common_atoms(struct r600_context *rctx); 556unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 557void r600_texture_barrier(struct pipe_context *ctx); 558void r600_set_index_buffer(struct pipe_context *ctx, 559 const struct pipe_index_buffer *ib); 560void r600_vertex_buffers_dirty(struct r600_context *rctx); 561void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 562 const struct pipe_vertex_buffer *input); 563void r600_sampler_views_dirty(struct r600_context *rctx, 564 struct r600_samplerview_state *state); 565void r600_set_sampler_views(struct r600_context *rctx, 566 struct r600_textures_info *dst, 567 unsigned count, 568 struct pipe_sampler_view **views); 569void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states); 570void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states); 571void *r600_create_vertex_elements(struct pipe_context *ctx, 572 unsigned count, 573 const struct pipe_vertex_element *elements); 574void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 575void r600_bind_blend_state(struct pipe_context *ctx, void *state); 576void r600_set_blend_color(struct pipe_context *ctx, 577 const struct pipe_blend_color *state); 578void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 579void r600_set_max_scissor(struct r600_context *rctx); 580void r600_bind_rs_state(struct pipe_context *ctx, void *state); 581void r600_delete_rs_state(struct pipe_context *ctx, void *state); 582void r600_sampler_view_destroy(struct pipe_context *ctx, 583 struct pipe_sampler_view *state); 584void r600_delete_sampler(struct pipe_context *ctx, void *state); 585void r600_delete_state(struct pipe_context *ctx, void *state); 586void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 587void *r600_create_shader_state_ps(struct pipe_context *ctx, 588 const struct pipe_shader_state *state); 589void *r600_create_shader_state_vs(struct pipe_context *ctx, 590 const struct pipe_shader_state *state); 591void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 592void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 593void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 594void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 595void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 596void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 597 struct pipe_constant_buffer *cb); 598struct pipe_stream_output_target * 599r600_create_so_target(struct pipe_context *ctx, 600 struct pipe_resource *buffer, 601 unsigned buffer_offset, 602 unsigned buffer_size); 603void r600_so_target_destroy(struct pipe_context *ctx, 604 struct pipe_stream_output_target *target); 605void r600_set_so_targets(struct pipe_context *ctx, 606 unsigned num_targets, 607 struct pipe_stream_output_target **targets, 608 unsigned append_bitmask); 609void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask); 610void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 611 const struct pipe_stencil_ref *state); 612void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 613uint32_t r600_translate_stencil_op(int s_op); 614uint32_t r600_translate_fill(uint32_t func); 615unsigned r600_tex_wrap(unsigned wrap); 616unsigned r600_tex_filter(unsigned filter); 617unsigned r600_tex_mipfilter(unsigned filter); 618unsigned r600_tex_compare(unsigned compare); 619 620/* 621 * Helpers for building command buffers 622 */ 623 624#define PKT3_SET_CONFIG_REG 0x68 625#define PKT3_SET_CONTEXT_REG 0x69 626#define PKT3_SET_CTL_CONST 0x6F 627#define PKT3_SET_LOOP_CONST 0x6C 628 629#define R600_CONFIG_REG_OFFSET 0x08000 630#define R600_CONTEXT_REG_OFFSET 0x28000 631#define R600_CTL_CONST_OFFSET 0x3CFF0 632#define R600_LOOP_CONST_OFFSET 0X0003E200 633#define EG_LOOP_CONST_OFFSET 0x0003A200 634 635#define PKT_TYPE_S(x) (((x) & 0x3) << 30) 636#define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 637#define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 638#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 639#define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 640 641#define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 642 643/*Evergreen Compute packet3*/ 644#define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE) 645 646static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 647{ 648 cb->buf[cb->atom.num_dw++] = value; 649} 650 651static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 652{ 653 assert(reg < R600_CONTEXT_REG_OFFSET); 654 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 655 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 656 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 657} 658 659/** 660 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 661 * shaders. 662 */ 663static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 664{ 665 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 666 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 667 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 668 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 669} 670 671/** 672 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 673 * shaders. 674 */ 675static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 676{ 677 assert(reg >= R600_CTL_CONST_OFFSET); 678 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 679 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 680 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 681} 682 683static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 684{ 685 assert(reg >= R600_LOOP_CONST_OFFSET); 686 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 687 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 688 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 689} 690 691/** 692 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 693 * shaders. 694 */ 695static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 696{ 697 assert(reg >= EG_LOOP_CONST_OFFSET); 698 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 699 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 700 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 701} 702 703static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 704{ 705 r600_store_config_reg_seq(cb, reg, 1); 706 r600_store_value(cb, value); 707} 708 709static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 710{ 711 r600_store_context_reg_seq(cb, reg, 1); 712 r600_store_value(cb, value); 713} 714 715static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 716{ 717 r600_store_ctl_const_seq(cb, reg, 1); 718 r600_store_value(cb, value); 719} 720 721static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 722{ 723 r600_store_loop_const_seq(cb, reg, 1); 724 r600_store_value(cb, value); 725} 726 727static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 728{ 729 eg_store_loop_const_seq(cb, reg, 1); 730 r600_store_value(cb, value); 731} 732 733void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 734void r600_release_command_buffer(struct r600_command_buffer *cb); 735 736/* 737 * Helpers for emitting state into a command stream directly. 738 */ 739 740static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 741 enum radeon_bo_usage usage) 742{ 743 assert(usage); 744 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 745} 746 747static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 748{ 749 cs->buf[cs->cdw++] = value; 750} 751 752static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr) 753{ 754 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS); 755 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0])); 756 cs->cdw += num; 757} 758 759static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 760{ 761 assert(reg < R600_CONTEXT_REG_OFFSET); 762 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 763 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 764 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 765} 766 767static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 768{ 769 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 770 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 771 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 772 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 773} 774 775static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 776{ 777 r600_write_context_reg_seq(cs, reg, num); 778 /* Set the compute bit on the packet header */ 779 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; 780} 781 782static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 783{ 784 assert(reg >= R600_CTL_CONST_OFFSET); 785 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 786 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 787 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 788} 789 790static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 791{ 792 r600_write_config_reg_seq(cs, reg, 1); 793 r600_write_value(cs, value); 794} 795 796static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 797{ 798 r600_write_context_reg_seq(cs, reg, 1); 799 r600_write_value(cs, value); 800} 801 802static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 803{ 804 r600_write_compute_context_reg_seq(cs, reg, 1); 805 r600_write_value(cs, value); 806} 807 808static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 809{ 810 r600_write_ctl_const_seq(cs, reg, 1); 811 r600_write_value(cs, value); 812} 813 814/* 815 * common helpers 816 */ 817static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 818{ 819 return value * (1 << frac_bits); 820} 821#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 822 823static inline unsigned r600_tex_aniso_filter(unsigned filter) 824{ 825 if (filter <= 1) return 0; 826 if (filter <= 2) return 1; 827 if (filter <= 4) return 2; 828 if (filter <= 8) return 3; 829 /* else */ return 4; 830} 831 832/* 12.4 fixed-point */ 833static INLINE unsigned r600_pack_float_12p4(float x) 834{ 835 return x <= 0 ? 0 : 836 x >= 4096 ? 0xffff : x * 16; 837} 838 839static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 840{ 841 struct r600_screen *rscreen = (struct r600_screen*)screen; 842 struct r600_resource *rresource = (struct r600_resource*)resource; 843 844 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 845} 846 847#endif 848