r600_state.c revision 2df399c34bb39122a45bdd5b430b48346542e1cb 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "r600d.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31
32static uint32_t r600_translate_blend_function(int blend_func)
33{
34	switch (blend_func) {
35	case PIPE_BLEND_ADD:
36		return V_028804_COMB_DST_PLUS_SRC;
37	case PIPE_BLEND_SUBTRACT:
38		return V_028804_COMB_SRC_MINUS_DST;
39	case PIPE_BLEND_REVERSE_SUBTRACT:
40		return V_028804_COMB_DST_MINUS_SRC;
41	case PIPE_BLEND_MIN:
42		return V_028804_COMB_MIN_DST_SRC;
43	case PIPE_BLEND_MAX:
44		return V_028804_COMB_MAX_DST_SRC;
45	default:
46		R600_ERR("Unknown blend function %d\n", blend_func);
47		assert(0);
48		break;
49	}
50	return 0;
51}
52
53static uint32_t r600_translate_blend_factor(int blend_fact)
54{
55	switch (blend_fact) {
56	case PIPE_BLENDFACTOR_ONE:
57		return V_028804_BLEND_ONE;
58	case PIPE_BLENDFACTOR_SRC_COLOR:
59		return V_028804_BLEND_SRC_COLOR;
60	case PIPE_BLENDFACTOR_SRC_ALPHA:
61		return V_028804_BLEND_SRC_ALPHA;
62	case PIPE_BLENDFACTOR_DST_ALPHA:
63		return V_028804_BLEND_DST_ALPHA;
64	case PIPE_BLENDFACTOR_DST_COLOR:
65		return V_028804_BLEND_DST_COLOR;
66	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67		return V_028804_BLEND_SRC_ALPHA_SATURATE;
68	case PIPE_BLENDFACTOR_CONST_COLOR:
69		return V_028804_BLEND_CONST_COLOR;
70	case PIPE_BLENDFACTOR_CONST_ALPHA:
71		return V_028804_BLEND_CONST_ALPHA;
72	case PIPE_BLENDFACTOR_ZERO:
73		return V_028804_BLEND_ZERO;
74	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75		return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77		return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79		return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80	case PIPE_BLENDFACTOR_INV_DST_COLOR:
81		return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83		return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85		return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86	case PIPE_BLENDFACTOR_SRC1_COLOR:
87		return V_028804_BLEND_SRC1_COLOR;
88	case PIPE_BLENDFACTOR_SRC1_ALPHA:
89		return V_028804_BLEND_SRC1_ALPHA;
90	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91		return V_028804_BLEND_INV_SRC1_COLOR;
92	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93		return V_028804_BLEND_INV_SRC1_ALPHA;
94	default:
95		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96		assert(0);
97		break;
98	}
99	return 0;
100}
101
102static unsigned r600_tex_dim(unsigned dim)
103{
104	switch (dim) {
105	default:
106	case PIPE_TEXTURE_1D:
107		return V_038000_SQ_TEX_DIM_1D;
108	case PIPE_TEXTURE_1D_ARRAY:
109		return V_038000_SQ_TEX_DIM_1D_ARRAY;
110	case PIPE_TEXTURE_2D:
111	case PIPE_TEXTURE_RECT:
112		return V_038000_SQ_TEX_DIM_2D;
113	case PIPE_TEXTURE_2D_ARRAY:
114		return V_038000_SQ_TEX_DIM_2D_ARRAY;
115	case PIPE_TEXTURE_3D:
116		return V_038000_SQ_TEX_DIM_3D;
117	case PIPE_TEXTURE_CUBE:
118		return V_038000_SQ_TEX_DIM_CUBEMAP;
119	}
120}
121
122static uint32_t r600_translate_dbformat(enum pipe_format format)
123{
124	switch (format) {
125	case PIPE_FORMAT_Z16_UNORM:
126		return V_028010_DEPTH_16;
127	case PIPE_FORMAT_Z24X8_UNORM:
128		return V_028010_DEPTH_X8_24;
129	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
130		return V_028010_DEPTH_8_24;
131	case PIPE_FORMAT_Z32_FLOAT:
132		return V_028010_DEPTH_32_FLOAT;
133	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
134		return V_028010_DEPTH_X24_8_32_FLOAT;
135	default:
136		return ~0U;
137	}
138}
139
140static uint32_t r600_translate_colorswap(enum pipe_format format)
141{
142	switch (format) {
143	/* 8-bit buffers. */
144	case PIPE_FORMAT_A8_UNORM:
145	case PIPE_FORMAT_A8_SNORM:
146	case PIPE_FORMAT_A8_UINT:
147	case PIPE_FORMAT_A8_SINT:
148	case PIPE_FORMAT_A16_UNORM:
149	case PIPE_FORMAT_A16_SNORM:
150	case PIPE_FORMAT_A16_UINT:
151	case PIPE_FORMAT_A16_SINT:
152	case PIPE_FORMAT_A16_FLOAT:
153	case PIPE_FORMAT_A32_UINT:
154	case PIPE_FORMAT_A32_SINT:
155	case PIPE_FORMAT_A32_FLOAT:
156	case PIPE_FORMAT_R4A4_UNORM:
157		return V_0280A0_SWAP_ALT_REV;
158	case PIPE_FORMAT_I8_UNORM:
159	case PIPE_FORMAT_I8_SNORM:
160	case PIPE_FORMAT_I8_UINT:
161	case PIPE_FORMAT_I8_SINT:
162	case PIPE_FORMAT_L8_UNORM:
163	case PIPE_FORMAT_L8_SNORM:
164	case PIPE_FORMAT_L8_UINT:
165	case PIPE_FORMAT_L8_SINT:
166	case PIPE_FORMAT_L8_SRGB:
167	case PIPE_FORMAT_L16_UNORM:
168	case PIPE_FORMAT_L16_SNORM:
169	case PIPE_FORMAT_L16_UINT:
170	case PIPE_FORMAT_L16_SINT:
171	case PIPE_FORMAT_L16_FLOAT:
172	case PIPE_FORMAT_L32_UINT:
173	case PIPE_FORMAT_L32_SINT:
174	case PIPE_FORMAT_L32_FLOAT:
175	case PIPE_FORMAT_I16_UNORM:
176	case PIPE_FORMAT_I16_SNORM:
177	case PIPE_FORMAT_I16_UINT:
178	case PIPE_FORMAT_I16_SINT:
179	case PIPE_FORMAT_I16_FLOAT:
180	case PIPE_FORMAT_I32_UINT:
181	case PIPE_FORMAT_I32_SINT:
182	case PIPE_FORMAT_I32_FLOAT:
183	case PIPE_FORMAT_R8_UNORM:
184	case PIPE_FORMAT_R8_SNORM:
185	case PIPE_FORMAT_R8_UINT:
186	case PIPE_FORMAT_R8_SINT:
187		return V_0280A0_SWAP_STD;
188
189	case PIPE_FORMAT_L4A4_UNORM:
190	case PIPE_FORMAT_A4R4_UNORM:
191		return V_0280A0_SWAP_ALT;
192
193	/* 16-bit buffers. */
194	case PIPE_FORMAT_B5G6R5_UNORM:
195		return V_0280A0_SWAP_STD_REV;
196
197	case PIPE_FORMAT_B5G5R5A1_UNORM:
198	case PIPE_FORMAT_B5G5R5X1_UNORM:
199		return V_0280A0_SWAP_ALT;
200
201	case PIPE_FORMAT_B4G4R4A4_UNORM:
202	case PIPE_FORMAT_B4G4R4X4_UNORM:
203		return V_0280A0_SWAP_ALT;
204
205	case PIPE_FORMAT_Z16_UNORM:
206		return V_0280A0_SWAP_STD;
207
208	case PIPE_FORMAT_L8A8_UNORM:
209	case PIPE_FORMAT_L8A8_SNORM:
210	case PIPE_FORMAT_L8A8_UINT:
211	case PIPE_FORMAT_L8A8_SINT:
212	case PIPE_FORMAT_L8A8_SRGB:
213	case PIPE_FORMAT_L16A16_UNORM:
214	case PIPE_FORMAT_L16A16_SNORM:
215	case PIPE_FORMAT_L16A16_UINT:
216	case PIPE_FORMAT_L16A16_SINT:
217	case PIPE_FORMAT_L16A16_FLOAT:
218	case PIPE_FORMAT_L32A32_UINT:
219	case PIPE_FORMAT_L32A32_SINT:
220	case PIPE_FORMAT_L32A32_FLOAT:
221		return V_0280A0_SWAP_ALT;
222	case PIPE_FORMAT_R8G8_UNORM:
223	case PIPE_FORMAT_R8G8_SNORM:
224	case PIPE_FORMAT_R8G8_UINT:
225	case PIPE_FORMAT_R8G8_SINT:
226		return V_0280A0_SWAP_STD;
227
228	case PIPE_FORMAT_R16_UNORM:
229	case PIPE_FORMAT_R16_SNORM:
230	case PIPE_FORMAT_R16_UINT:
231	case PIPE_FORMAT_R16_SINT:
232	case PIPE_FORMAT_R16_FLOAT:
233		return V_0280A0_SWAP_STD;
234
235	/* 32-bit buffers. */
236
237	case PIPE_FORMAT_A8B8G8R8_SRGB:
238		return V_0280A0_SWAP_STD_REV;
239	case PIPE_FORMAT_B8G8R8A8_SRGB:
240		return V_0280A0_SWAP_ALT;
241
242	case PIPE_FORMAT_B8G8R8A8_UNORM:
243	case PIPE_FORMAT_B8G8R8X8_UNORM:
244		return V_0280A0_SWAP_ALT;
245
246	case PIPE_FORMAT_A8R8G8B8_UNORM:
247	case PIPE_FORMAT_X8R8G8B8_UNORM:
248		return V_0280A0_SWAP_ALT_REV;
249	case PIPE_FORMAT_R8G8B8A8_SNORM:
250	case PIPE_FORMAT_R8G8B8A8_UNORM:
251	case PIPE_FORMAT_R8G8B8X8_UNORM:
252	case PIPE_FORMAT_R8G8B8A8_SINT:
253	case PIPE_FORMAT_R8G8B8A8_UINT:
254		return V_0280A0_SWAP_STD;
255
256	case PIPE_FORMAT_A8B8G8R8_UNORM:
257	case PIPE_FORMAT_X8B8G8R8_UNORM:
258	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
259		return V_0280A0_SWAP_STD_REV;
260
261	case PIPE_FORMAT_Z24X8_UNORM:
262	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
263		return V_0280A0_SWAP_STD;
264
265	case PIPE_FORMAT_X8Z24_UNORM:
266	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
267		return V_0280A0_SWAP_STD;
268
269	case PIPE_FORMAT_R10G10B10A2_UNORM:
270	case PIPE_FORMAT_R10G10B10X2_SNORM:
271	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
272		return V_0280A0_SWAP_STD;
273
274	case PIPE_FORMAT_B10G10R10A2_UNORM:
275	case PIPE_FORMAT_B10G10R10A2_UINT:
276		return V_0280A0_SWAP_ALT;
277
278	case PIPE_FORMAT_R11G11B10_FLOAT:
279	case PIPE_FORMAT_R16G16_UNORM:
280	case PIPE_FORMAT_R16G16_SNORM:
281	case PIPE_FORMAT_R16G16_FLOAT:
282	case PIPE_FORMAT_R16G16_UINT:
283	case PIPE_FORMAT_R16G16_SINT:
284	case PIPE_FORMAT_R16G16B16_FLOAT:
285	case PIPE_FORMAT_R32G32B32_FLOAT:
286	case PIPE_FORMAT_R32_UINT:
287	case PIPE_FORMAT_R32_SINT:
288	case PIPE_FORMAT_R32_FLOAT:
289	case PIPE_FORMAT_Z32_FLOAT:
290		return V_0280A0_SWAP_STD;
291
292	/* 64-bit buffers. */
293	case PIPE_FORMAT_R32G32_FLOAT:
294	case PIPE_FORMAT_R32G32_UINT:
295	case PIPE_FORMAT_R32G32_SINT:
296	case PIPE_FORMAT_R16G16B16A16_UNORM:
297	case PIPE_FORMAT_R16G16B16A16_SNORM:
298	case PIPE_FORMAT_R16G16B16A16_UINT:
299	case PIPE_FORMAT_R16G16B16A16_SINT:
300	case PIPE_FORMAT_R16G16B16A16_FLOAT:
301	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303	/* 128-bit buffers. */
304	case PIPE_FORMAT_R32G32B32A32_FLOAT:
305	case PIPE_FORMAT_R32G32B32A32_SNORM:
306	case PIPE_FORMAT_R32G32B32A32_UNORM:
307	case PIPE_FORMAT_R32G32B32A32_SINT:
308	case PIPE_FORMAT_R32G32B32A32_UINT:
309		return V_0280A0_SWAP_STD;
310	default:
311		R600_ERR("unsupported colorswap format %d\n", format);
312		return ~0U;
313	}
314	return ~0U;
315}
316
317static uint32_t r600_translate_colorformat(enum pipe_format format)
318{
319	switch (format) {
320	case PIPE_FORMAT_L4A4_UNORM:
321	case PIPE_FORMAT_R4A4_UNORM:
322	case PIPE_FORMAT_A4R4_UNORM:
323		return V_0280A0_COLOR_4_4;
324
325	/* 8-bit buffers. */
326	case PIPE_FORMAT_A8_UNORM:
327	case PIPE_FORMAT_A8_SNORM:
328	case PIPE_FORMAT_A8_UINT:
329	case PIPE_FORMAT_A8_SINT:
330	case PIPE_FORMAT_I8_UNORM:
331	case PIPE_FORMAT_I8_SNORM:
332	case PIPE_FORMAT_I8_UINT:
333	case PIPE_FORMAT_I8_SINT:
334	case PIPE_FORMAT_L8_UNORM:
335	case PIPE_FORMAT_L8_SNORM:
336	case PIPE_FORMAT_L8_UINT:
337	case PIPE_FORMAT_L8_SINT:
338	case PIPE_FORMAT_L8_SRGB:
339	case PIPE_FORMAT_R8_UNORM:
340	case PIPE_FORMAT_R8_SNORM:
341	case PIPE_FORMAT_R8_UINT:
342	case PIPE_FORMAT_R8_SINT:
343		return V_0280A0_COLOR_8;
344
345	/* 16-bit buffers. */
346	case PIPE_FORMAT_B5G6R5_UNORM:
347		return V_0280A0_COLOR_5_6_5;
348
349	case PIPE_FORMAT_B5G5R5A1_UNORM:
350	case PIPE_FORMAT_B5G5R5X1_UNORM:
351		return V_0280A0_COLOR_1_5_5_5;
352
353	case PIPE_FORMAT_B4G4R4A4_UNORM:
354	case PIPE_FORMAT_B4G4R4X4_UNORM:
355		return V_0280A0_COLOR_4_4_4_4;
356
357	case PIPE_FORMAT_Z16_UNORM:
358		return V_0280A0_COLOR_16;
359
360	case PIPE_FORMAT_L8A8_UNORM:
361	case PIPE_FORMAT_L8A8_SNORM:
362	case PIPE_FORMAT_L8A8_UINT:
363	case PIPE_FORMAT_L8A8_SINT:
364	case PIPE_FORMAT_L8A8_SRGB:
365	case PIPE_FORMAT_R8G8_UNORM:
366	case PIPE_FORMAT_R8G8_SNORM:
367	case PIPE_FORMAT_R8G8_UINT:
368	case PIPE_FORMAT_R8G8_SINT:
369		return V_0280A0_COLOR_8_8;
370
371	case PIPE_FORMAT_R16_UNORM:
372	case PIPE_FORMAT_R16_SNORM:
373	case PIPE_FORMAT_R16_UINT:
374	case PIPE_FORMAT_R16_SINT:
375	case PIPE_FORMAT_A16_UNORM:
376	case PIPE_FORMAT_A16_SNORM:
377	case PIPE_FORMAT_A16_UINT:
378	case PIPE_FORMAT_A16_SINT:
379	case PIPE_FORMAT_L16_UNORM:
380	case PIPE_FORMAT_L16_SNORM:
381	case PIPE_FORMAT_L16_UINT:
382	case PIPE_FORMAT_L16_SINT:
383	case PIPE_FORMAT_I16_UNORM:
384	case PIPE_FORMAT_I16_SNORM:
385	case PIPE_FORMAT_I16_UINT:
386	case PIPE_FORMAT_I16_SINT:
387		return V_0280A0_COLOR_16;
388
389	case PIPE_FORMAT_R16_FLOAT:
390	case PIPE_FORMAT_A16_FLOAT:
391	case PIPE_FORMAT_L16_FLOAT:
392	case PIPE_FORMAT_I16_FLOAT:
393		return V_0280A0_COLOR_16_FLOAT;
394
395	/* 32-bit buffers. */
396	case PIPE_FORMAT_A8B8G8R8_SRGB:
397	case PIPE_FORMAT_A8B8G8R8_UNORM:
398	case PIPE_FORMAT_A8R8G8B8_UNORM:
399	case PIPE_FORMAT_B8G8R8A8_SRGB:
400	case PIPE_FORMAT_B8G8R8A8_UNORM:
401	case PIPE_FORMAT_B8G8R8X8_UNORM:
402	case PIPE_FORMAT_R8G8B8A8_SNORM:
403	case PIPE_FORMAT_R8G8B8A8_UNORM:
404	case PIPE_FORMAT_R8G8B8X8_UNORM:
405	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406	case PIPE_FORMAT_X8B8G8R8_UNORM:
407	case PIPE_FORMAT_X8R8G8B8_UNORM:
408	case PIPE_FORMAT_R8G8B8_UNORM:
409	case PIPE_FORMAT_R8G8B8A8_SINT:
410	case PIPE_FORMAT_R8G8B8A8_UINT:
411		return V_0280A0_COLOR_8_8_8_8;
412
413	case PIPE_FORMAT_R10G10B10A2_UNORM:
414	case PIPE_FORMAT_R10G10B10X2_SNORM:
415	case PIPE_FORMAT_B10G10R10A2_UNORM:
416	case PIPE_FORMAT_B10G10R10A2_UINT:
417	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
418		return V_0280A0_COLOR_2_10_10_10;
419
420	case PIPE_FORMAT_Z24X8_UNORM:
421	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
422		return V_0280A0_COLOR_8_24;
423
424	case PIPE_FORMAT_X8Z24_UNORM:
425	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
426		return V_0280A0_COLOR_24_8;
427
428	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
429		return V_0280A0_COLOR_X24_8_32_FLOAT;
430
431	case PIPE_FORMAT_R32_UINT:
432	case PIPE_FORMAT_R32_SINT:
433	case PIPE_FORMAT_A32_UINT:
434	case PIPE_FORMAT_A32_SINT:
435	case PIPE_FORMAT_L32_UINT:
436	case PIPE_FORMAT_L32_SINT:
437	case PIPE_FORMAT_I32_UINT:
438	case PIPE_FORMAT_I32_SINT:
439		return V_0280A0_COLOR_32;
440
441	case PIPE_FORMAT_R32_FLOAT:
442	case PIPE_FORMAT_A32_FLOAT:
443	case PIPE_FORMAT_L32_FLOAT:
444	case PIPE_FORMAT_I32_FLOAT:
445	case PIPE_FORMAT_Z32_FLOAT:
446		return V_0280A0_COLOR_32_FLOAT;
447
448	case PIPE_FORMAT_R16G16_FLOAT:
449	case PIPE_FORMAT_L16A16_FLOAT:
450		return V_0280A0_COLOR_16_16_FLOAT;
451
452	case PIPE_FORMAT_R16G16_UNORM:
453	case PIPE_FORMAT_R16G16_SNORM:
454	case PIPE_FORMAT_R16G16_UINT:
455	case PIPE_FORMAT_R16G16_SINT:
456	case PIPE_FORMAT_L16A16_UNORM:
457	case PIPE_FORMAT_L16A16_SNORM:
458	case PIPE_FORMAT_L16A16_UINT:
459	case PIPE_FORMAT_L16A16_SINT:
460		return V_0280A0_COLOR_16_16;
461
462	case PIPE_FORMAT_R11G11B10_FLOAT:
463		return V_0280A0_COLOR_10_11_11_FLOAT;
464
465	/* 64-bit buffers. */
466	case PIPE_FORMAT_R16G16B16A16_UINT:
467	case PIPE_FORMAT_R16G16B16A16_SINT:
468	case PIPE_FORMAT_R16G16B16A16_UNORM:
469	case PIPE_FORMAT_R16G16B16A16_SNORM:
470		return V_0280A0_COLOR_16_16_16_16;
471
472	case PIPE_FORMAT_R16G16B16_FLOAT:
473	case PIPE_FORMAT_R16G16B16A16_FLOAT:
474		return V_0280A0_COLOR_16_16_16_16_FLOAT;
475
476	case PIPE_FORMAT_R32G32_FLOAT:
477	case PIPE_FORMAT_L32A32_FLOAT:
478		return V_0280A0_COLOR_32_32_FLOAT;
479
480	case PIPE_FORMAT_R32G32_SINT:
481	case PIPE_FORMAT_R32G32_UINT:
482	case PIPE_FORMAT_L32A32_UINT:
483	case PIPE_FORMAT_L32A32_SINT:
484		return V_0280A0_COLOR_32_32;
485
486	/* 96-bit buffers. */
487	case PIPE_FORMAT_R32G32B32_FLOAT:
488		return V_0280A0_COLOR_32_32_32_FLOAT;
489
490	/* 128-bit buffers. */
491	case PIPE_FORMAT_R32G32B32A32_FLOAT:
492		return V_0280A0_COLOR_32_32_32_32_FLOAT;
493	case PIPE_FORMAT_R32G32B32A32_SNORM:
494	case PIPE_FORMAT_R32G32B32A32_UNORM:
495	case PIPE_FORMAT_R32G32B32A32_SINT:
496	case PIPE_FORMAT_R32G32B32A32_UINT:
497		return V_0280A0_COLOR_32_32_32_32;
498
499	/* YUV buffers. */
500	case PIPE_FORMAT_UYVY:
501	case PIPE_FORMAT_YUYV:
502	default:
503		return ~0U; /* Unsupported. */
504	}
505}
506
507static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
508{
509	if (R600_BIG_ENDIAN) {
510		switch(colorformat) {
511		case V_0280A0_COLOR_4_4:
512			return ENDIAN_NONE;
513
514		/* 8-bit buffers. */
515		case V_0280A0_COLOR_8:
516			return ENDIAN_NONE;
517
518		/* 16-bit buffers. */
519		case V_0280A0_COLOR_5_6_5:
520		case V_0280A0_COLOR_1_5_5_5:
521		case V_0280A0_COLOR_4_4_4_4:
522		case V_0280A0_COLOR_16:
523		case V_0280A0_COLOR_8_8:
524			return ENDIAN_8IN16;
525
526		/* 32-bit buffers. */
527		case V_0280A0_COLOR_8_8_8_8:
528		case V_0280A0_COLOR_2_10_10_10:
529		case V_0280A0_COLOR_8_24:
530		case V_0280A0_COLOR_24_8:
531		case V_0280A0_COLOR_32_FLOAT:
532		case V_0280A0_COLOR_16_16_FLOAT:
533		case V_0280A0_COLOR_16_16:
534			return ENDIAN_8IN32;
535
536		/* 64-bit buffers. */
537		case V_0280A0_COLOR_16_16_16_16:
538		case V_0280A0_COLOR_16_16_16_16_FLOAT:
539			return ENDIAN_8IN16;
540
541		case V_0280A0_COLOR_32_32_FLOAT:
542		case V_0280A0_COLOR_32_32:
543		case V_0280A0_COLOR_X24_8_32_FLOAT:
544			return ENDIAN_8IN32;
545
546		/* 128-bit buffers. */
547		case V_0280A0_COLOR_32_32_32_FLOAT:
548		case V_0280A0_COLOR_32_32_32_32_FLOAT:
549		case V_0280A0_COLOR_32_32_32_32:
550			return ENDIAN_8IN32;
551		default:
552			return ENDIAN_NONE; /* Unsupported. */
553		}
554	} else {
555		return ENDIAN_NONE;
556	}
557}
558
559static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
560{
561	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
562}
563
564static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
565{
566	return r600_translate_colorformat(format) != ~0U &&
567	       r600_translate_colorswap(format) != ~0U;
568}
569
570static bool r600_is_zs_format_supported(enum pipe_format format)
571{
572	return r600_translate_dbformat(format) != ~0U;
573}
574
575boolean r600_is_format_supported(struct pipe_screen *screen,
576				 enum pipe_format format,
577				 enum pipe_texture_target target,
578				 unsigned sample_count,
579				 unsigned usage)
580{
581	unsigned retval = 0;
582
583	if (target >= PIPE_MAX_TEXTURE_TYPES) {
584		R600_ERR("r600: unsupported texture type %d\n", target);
585		return FALSE;
586	}
587
588	if (!util_format_is_supported(format, usage))
589		return FALSE;
590
591	/* Multisample */
592	if (sample_count > 1)
593		return FALSE;
594
595	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
596	    r600_is_sampler_format_supported(screen, format)) {
597		retval |= PIPE_BIND_SAMPLER_VIEW;
598	}
599
600	if ((usage & (PIPE_BIND_RENDER_TARGET |
601		      PIPE_BIND_DISPLAY_TARGET |
602		      PIPE_BIND_SCANOUT |
603		      PIPE_BIND_SHARED)) &&
604	    r600_is_colorbuffer_format_supported(format)) {
605		retval |= usage &
606			  (PIPE_BIND_RENDER_TARGET |
607			   PIPE_BIND_DISPLAY_TARGET |
608			   PIPE_BIND_SCANOUT |
609			   PIPE_BIND_SHARED);
610	}
611
612	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
613	    r600_is_zs_format_supported(format)) {
614		retval |= PIPE_BIND_DEPTH_STENCIL;
615	}
616
617	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
618	    r600_is_vertex_format_supported(format)) {
619		retval |= PIPE_BIND_VERTEX_BUFFER;
620	}
621
622	if (usage & PIPE_BIND_TRANSFER_READ)
623		retval |= PIPE_BIND_TRANSFER_READ;
624	if (usage & PIPE_BIND_TRANSFER_WRITE)
625		retval |= PIPE_BIND_TRANSFER_WRITE;
626
627	return retval == usage;
628}
629
630void r600_polygon_offset_update(struct r600_context *rctx)
631{
632	struct r600_pipe_state state;
633
634	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
635	state.nregs = 0;
636	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
637		float offset_units = rctx->rasterizer->offset_units;
638		unsigned offset_db_fmt_cntl = 0, depth;
639
640		switch (rctx->framebuffer.zsbuf->format) {
641		case PIPE_FORMAT_Z24X8_UNORM:
642		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
643			depth = -24;
644			offset_units *= 2.0f;
645			break;
646		case PIPE_FORMAT_Z32_FLOAT:
647		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
648			depth = -23;
649			offset_units *= 1.0f;
650			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
651			break;
652		case PIPE_FORMAT_Z16_UNORM:
653			depth = -16;
654			offset_units *= 4.0f;
655			break;
656		default:
657			return;
658		}
659		/* XXX some of those reg can be computed with cso */
660		offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
661		r600_pipe_state_add_reg(&state,
662				R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
663				fui(rctx->rasterizer->offset_scale));
664		r600_pipe_state_add_reg(&state,
665				R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
666				fui(offset_units));
667		r600_pipe_state_add_reg(&state,
668				R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
669				fui(rctx->rasterizer->offset_scale));
670		r600_pipe_state_add_reg(&state,
671				R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
672				fui(offset_units));
673		r600_pipe_state_add_reg(&state,
674				R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
675				offset_db_fmt_cntl);
676		r600_context_pipe_state_set(rctx, &state);
677	}
678}
679
680static void *r600_create_blend_state(struct pipe_context *ctx,
681					const struct pipe_blend_state *state)
682{
683	struct r600_context *rctx = (struct r600_context *)ctx;
684	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
685	struct r600_pipe_state *rstate;
686	uint32_t color_control = 0, target_mask;
687
688	if (blend == NULL) {
689		return NULL;
690	}
691	rstate = &blend->rstate;
692
693	rstate->id = R600_PIPE_STATE_BLEND;
694
695	target_mask = 0;
696
697	/* R600 does not support per-MRT blends */
698	if (rctx->family > CHIP_R600)
699		color_control |= S_028808_PER_MRT_BLEND(1);
700	if (state->logicop_enable) {
701		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
702	} else {
703		color_control |= (0xcc << 16);
704	}
705	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
706	if (state->independent_blend_enable) {
707		for (int i = 0; i < 8; i++) {
708			if (state->rt[i].blend_enable) {
709				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
710			}
711			target_mask |= (state->rt[i].colormask << (4 * i));
712		}
713	} else {
714		for (int i = 0; i < 8; i++) {
715			if (state->rt[0].blend_enable) {
716				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
717			}
718			target_mask |= (state->rt[0].colormask << (4 * i));
719		}
720	}
721
722	if (target_mask)
723		color_control |= S_028808_SPECIAL_OP(V_028808_NORMAL);
724	else
725		color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
726
727	blend->cb_target_mask = target_mask;
728	blend->cb_color_control = color_control;
729	/* only MRT0 has dual src blend */
730	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
731	for (int i = 0; i < 8; i++) {
732		/* state->rt entries > 0 only written if independent blending */
733		const int j = state->independent_blend_enable ? i : 0;
734
735		unsigned eqRGB = state->rt[j].rgb_func;
736		unsigned srcRGB = state->rt[j].rgb_src_factor;
737		unsigned dstRGB = state->rt[j].rgb_dst_factor;
738
739		unsigned eqA = state->rt[j].alpha_func;
740		unsigned srcA = state->rt[j].alpha_src_factor;
741		unsigned dstA = state->rt[j].alpha_dst_factor;
742		uint32_t bc = 0;
743
744		if (!state->rt[j].blend_enable)
745			continue;
746
747		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
748		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
749		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
750
751		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
752			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
753			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
754			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
755			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
756		}
757
758		/* R600 does not support per-MRT blends */
759		if (rctx->family > CHIP_R600)
760			r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
761		if (i == 0)
762			r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
763	}
764	return rstate;
765}
766
767static void *r600_create_dsa_state(struct pipe_context *ctx,
768				   const struct pipe_depth_stencil_alpha_state *state)
769{
770	struct r600_context *rctx = (struct r600_context *)ctx;
771	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
772	unsigned db_depth_control, alpha_test_control, alpha_ref;
773	struct r600_pipe_state *rstate;
774
775	if (dsa == NULL) {
776		return NULL;
777	}
778
779	dsa->valuemask[0] = state->stencil[0].valuemask;
780	dsa->valuemask[1] = state->stencil[1].valuemask;
781	dsa->writemask[0] = state->stencil[0].writemask;
782	dsa->writemask[1] = state->stencil[1].writemask;
783
784	rstate = &dsa->rstate;
785
786	rstate->id = R600_PIPE_STATE_DSA;
787	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
788		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
789		S_028800_ZFUNC(state->depth.func);
790
791	/* stencil */
792	if (state->stencil[0].enabled) {
793		db_depth_control |= S_028800_STENCIL_ENABLE(1);
794		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
795		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
796		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
797		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
798
799		if (state->stencil[1].enabled) {
800			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
801			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
802			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
803			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
804			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
805		}
806	}
807
808	/* alpha */
809	alpha_test_control = 0;
810	alpha_ref = 0;
811	if (state->alpha.enabled) {
812		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
813		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
814		alpha_ref = fui(state->alpha.ref_value);
815	}
816	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
817	dsa->alpha_ref = alpha_ref;
818
819	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
820	return rstate;
821}
822
823static void *r600_create_rs_state(struct pipe_context *ctx,
824				  const struct pipe_rasterizer_state *state)
825{
826	struct r600_context *rctx = (struct r600_context *)ctx;
827	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
828	struct r600_pipe_state *rstate;
829	unsigned tmp;
830	unsigned prov_vtx = 1, polygon_dual_mode;
831	unsigned sc_mode_cntl;
832	float psize_min, psize_max;
833
834	if (rs == NULL) {
835		return NULL;
836	}
837
838	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
839				state->fill_back != PIPE_POLYGON_MODE_FILL);
840
841	if (state->flatshade_first)
842		prov_vtx = 0;
843
844	rstate = &rs->rstate;
845	rs->flatshade = state->flatshade;
846	rs->sprite_coord_enable = state->sprite_coord_enable;
847	rs->two_side = state->light_twoside;
848	rs->clip_plane_enable = state->clip_plane_enable;
849	rs->pa_sc_line_stipple = state->line_stipple_enable ?
850				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
851				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
852	rs->pa_cl_clip_cntl =
853		S_028810_PS_UCP_MODE(3) |
854		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
855		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
856		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
857
858	/* offset */
859	rs->offset_units = state->offset_units;
860	rs->offset_scale = state->offset_scale * 12.0f;
861
862	rstate->id = R600_PIPE_STATE_RASTERIZER;
863	tmp = S_0286D4_FLAT_SHADE_ENA(1);
864	if (state->sprite_coord_enable) {
865		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
866			S_0286D4_PNT_SPRITE_OVRD_X(2) |
867			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
868			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
869			S_0286D4_PNT_SPRITE_OVRD_W(1);
870		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
871			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
872		}
873	}
874	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
875
876	/* point size 12.4 fixed point */
877	tmp = r600_pack_float_12p4(state->point_size/2);
878	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
879
880	if (state->point_size_per_vertex) {
881		psize_min = util_get_min_point_size(state);
882		psize_max = 8192;
883	} else {
884		/* Force the point size to be as if the vertex output was disabled. */
885		psize_min = state->point_size;
886		psize_max = state->point_size;
887	}
888	/* Divide by two, because 0.5 = 1 pixel. */
889	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
890				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
891				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
892
893	tmp = r600_pack_float_12p4(state->line_width/2);
894	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
895
896	if (rctx->chip_class >= R700) {
897		sc_mode_cntl =
898			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
899			S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
900			S_028A4C_R700_ZMM_LINE_OFFSET(1) |
901			S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
902	} else {
903		sc_mode_cntl =
904			S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
905			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
906		rs->scissor_enable = state->scissor;
907	}
908	sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
909
910	r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
911
912	r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
913				S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
914
915	r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
916	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
917				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
918				S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
919				S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
920				S_028814_FACE(!state->front_ccw) |
921				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
922				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
923				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
924				S_028814_POLY_MODE(polygon_dual_mode) |
925				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
926				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
927	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
928	return rstate;
929}
930
931static void *r600_create_sampler_state(struct pipe_context *ctx,
932					const struct pipe_sampler_state *state)
933{
934	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
935	union util_color uc;
936	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
937
938	if (ss == NULL) {
939		return NULL;
940	}
941
942	ss->seamless_cube_map = state->seamless_cube_map;
943	ss->border_color_use = false;
944	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
945	/* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
946	ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
947				S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
948				S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
949				S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
950				S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
951				S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
952				S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
953				S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
954				S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
955	/* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
956	ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
957				S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
958				S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
959	/* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
960	ss->tex_sampler_words[2] = S_03C008_TYPE(1);
961	if (uc.ui) {
962		ss->border_color_use = true;
963		/* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
964		ss->border_color[0] = fui(state->border_color.f[0]);
965		/* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
966		ss->border_color[1] = fui(state->border_color.f[1]);
967		/* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
968		ss->border_color[2] = fui(state->border_color.f[2]);
969		/* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
970		ss->border_color[3] = fui(state->border_color.f[3]);
971	}
972	return ss;
973}
974
975static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
976							struct pipe_resource *texture,
977							const struct pipe_sampler_view *state)
978{
979	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
980	struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
981	unsigned format, endian;
982	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
983	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
984	unsigned width, height, depth, offset_level, last_level;
985
986	if (view == NULL)
987		return NULL;
988
989	/* initialize base object */
990	view->base = *state;
991	view->base.texture = NULL;
992	pipe_reference(NULL, &texture->reference);
993	view->base.texture = texture;
994	view->base.reference.count = 1;
995	view->base.context = ctx;
996
997	swizzle[0] = state->swizzle_r;
998	swizzle[1] = state->swizzle_g;
999	swizzle[2] = state->swizzle_b;
1000	swizzle[3] = state->swizzle_a;
1001
1002	format = r600_translate_texformat(ctx->screen, state->format,
1003					  swizzle,
1004					  &word4, &yuv_format);
1005	assert(format != ~0);
1006	if (format == ~0) {
1007		FREE(view);
1008		return NULL;
1009	}
1010
1011	if (tmp->is_depth && !tmp->is_flushing_texture) {
1012		if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1013			FREE(view);
1014			return NULL;
1015		}
1016		tmp = tmp->flushed_depth_texture;
1017	}
1018
1019	endian = r600_colorformat_endian_swap(format);
1020
1021	offset_level = state->u.tex.first_level;
1022	last_level = state->u.tex.last_level - offset_level;
1023	width = tmp->surface.level[offset_level].npix_x;
1024	height = tmp->surface.level[offset_level].npix_y;
1025	depth = tmp->surface.level[offset_level].npix_z;
1026	pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1027	tile_type = tmp->tile_type;
1028
1029	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1030		height = 1;
1031		depth = texture->array_size;
1032	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1033		depth = texture->array_size;
1034	}
1035	switch (tmp->surface.level[offset_level].mode) {
1036	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1037		array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1038		break;
1039	case RADEON_SURF_MODE_1D:
1040		array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1041		break;
1042	case RADEON_SURF_MODE_2D:
1043		array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1044		break;
1045	case RADEON_SURF_MODE_LINEAR:
1046	default:
1047		array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1048		break;
1049	}
1050
1051	view->tex_resource = &tmp->resource;
1052	view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1053				       S_038000_TILE_MODE(array_mode) |
1054				       S_038000_TILE_TYPE(tile_type) |
1055				       S_038000_PITCH((pitch / 8) - 1) |
1056				       S_038000_TEX_WIDTH(width - 1));
1057	view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1058				       S_038004_TEX_DEPTH(depth - 1) |
1059				       S_038004_DATA_FORMAT(format));
1060	view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1061	if (offset_level >= tmp->surface.last_level) {
1062		view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1063	} else {
1064		view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1065	}
1066	view->tex_resource_words[4] = (word4 |
1067				       S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1068				       S_038010_REQUEST_SIZE(1) |
1069				       S_038010_ENDIAN_SWAP(endian) |
1070				       S_038010_BASE_LEVEL(0));
1071	view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
1072				       S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1073				       S_038014_LAST_ARRAY(state->u.tex.last_layer));
1074	view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1075				       S_038018_MAX_ANISO(4 /* max 16 samples */));
1076	return &view->base;
1077}
1078
1079static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1080				      struct pipe_sampler_view **views)
1081{
1082	struct r600_context *rctx = (struct r600_context *)ctx;
1083	r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views);
1084}
1085
1086static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1087				      struct pipe_sampler_view **views)
1088{
1089	struct r600_context *rctx = (struct r600_context *)ctx;
1090	r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views);
1091}
1092
1093static void r600_set_clip_state(struct pipe_context *ctx,
1094				const struct pipe_clip_state *state)
1095{
1096	struct r600_context *rctx = (struct r600_context *)ctx;
1097	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1098	struct pipe_constant_buffer cb;
1099
1100	if (rstate == NULL)
1101		return;
1102
1103	rctx->clip = *state;
1104	rstate->id = R600_PIPE_STATE_CLIP;
1105	for (int i = 0; i < 6; i++) {
1106		r600_pipe_state_add_reg(rstate,
1107					R_028E20_PA_CL_UCP0_X + i * 16,
1108					fui(state->ucp[i][0]));
1109		r600_pipe_state_add_reg(rstate,
1110					R_028E24_PA_CL_UCP0_Y + i * 16,
1111					fui(state->ucp[i][1]) );
1112		r600_pipe_state_add_reg(rstate,
1113					R_028E28_PA_CL_UCP0_Z + i * 16,
1114					fui(state->ucp[i][2]));
1115		r600_pipe_state_add_reg(rstate,
1116					R_028E2C_PA_CL_UCP0_W + i * 16,
1117					fui(state->ucp[i][3]));
1118	}
1119
1120	free(rctx->states[R600_PIPE_STATE_CLIP]);
1121	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1122	r600_context_pipe_state_set(rctx, rstate);
1123
1124	cb.buffer = NULL;
1125	cb.user_buffer = state->ucp;
1126	cb.buffer_offset = 0;
1127	cb.buffer_size = 4*4*8;
1128	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1129	pipe_resource_reference(&cb.buffer, NULL);
1130}
1131
1132static void r600_set_polygon_stipple(struct pipe_context *ctx,
1133					 const struct pipe_poly_stipple *state)
1134{
1135}
1136
1137static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1138{
1139}
1140
1141void r600_set_scissor_state(struct r600_context *rctx,
1142			    const struct pipe_scissor_state *state)
1143{
1144	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1145	uint32_t tl, br;
1146
1147	if (rstate == NULL)
1148		return;
1149
1150	rstate->id = R600_PIPE_STATE_SCISSOR;
1151	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1152	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1153	r600_pipe_state_add_reg(rstate,
1154				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1155	r600_pipe_state_add_reg(rstate,
1156				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1157
1158	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1159	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1160	r600_context_pipe_state_set(rctx, rstate);
1161}
1162
1163static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1164					const struct pipe_scissor_state *state)
1165{
1166	struct r600_context *rctx = (struct r600_context *)ctx;
1167
1168	if (rctx->chip_class == R600) {
1169		rctx->scissor_state = *state;
1170
1171		if (!rctx->scissor_enable)
1172			return;
1173	}
1174
1175	r600_set_scissor_state(rctx, state);
1176}
1177
1178static void r600_set_viewport_state(struct pipe_context *ctx,
1179					const struct pipe_viewport_state *state)
1180{
1181	struct r600_context *rctx = (struct r600_context *)ctx;
1182	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1183
1184	if (rstate == NULL)
1185		return;
1186
1187	rctx->viewport = *state;
1188	rstate->id = R600_PIPE_STATE_VIEWPORT;
1189	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1190	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1191	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1192	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1193	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1194	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1195
1196	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1197	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1198	r600_context_pipe_state_set(rctx, rstate);
1199}
1200
1201static void r600_init_color_surface(struct r600_context *rctx,
1202				    struct r600_surface *surf)
1203{
1204	struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1205	unsigned level = surf->base.u.tex.level;
1206	unsigned pitch, slice;
1207	unsigned color_info;
1208	unsigned format, swap, ntype, endian;
1209	unsigned offset;
1210	const struct util_format_description *desc;
1211	int i;
1212	bool blend_bypass = 0, blend_clamp = 1;
1213
1214	if (rtex->is_depth && !rtex->is_flushing_texture) {
1215		r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1216		rtex = rtex->flushed_depth_texture;
1217		assert(rtex);
1218	}
1219
1220	offset = rtex->surface.level[level].offset;
1221	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1222		offset += rtex->surface.level[level].slice_size *
1223			  surf->base.u.tex.first_layer;
1224	}
1225	pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1226	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1227	if (slice) {
1228		slice = slice - 1;
1229	}
1230	color_info = 0;
1231	switch (rtex->surface.level[level].mode) {
1232	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1233		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1234		break;
1235	case RADEON_SURF_MODE_1D:
1236		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1237		break;
1238	case RADEON_SURF_MODE_2D:
1239		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1240		break;
1241	case RADEON_SURF_MODE_LINEAR:
1242	default:
1243		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1244		break;
1245	}
1246
1247	desc = util_format_description(surf->base.format);
1248
1249	for (i = 0; i < 4; i++) {
1250		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1251			break;
1252		}
1253	}
1254
1255	ntype = V_0280A0_NUMBER_UNORM;
1256	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1257		ntype = V_0280A0_NUMBER_SRGB;
1258	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1259		if (desc->channel[i].normalized)
1260			ntype = V_0280A0_NUMBER_SNORM;
1261		else if (desc->channel[i].pure_integer)
1262			ntype = V_0280A0_NUMBER_SINT;
1263	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1264		if (desc->channel[i].normalized)
1265			ntype = V_0280A0_NUMBER_UNORM;
1266		else if (desc->channel[i].pure_integer)
1267			ntype = V_0280A0_NUMBER_UINT;
1268	}
1269
1270	format = r600_translate_colorformat(surf->base.format);
1271	assert(format != ~0);
1272
1273	swap = r600_translate_colorswap(surf->base.format);
1274	assert(swap != ~0);
1275
1276	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1277		endian = ENDIAN_NONE;
1278	} else {
1279		endian = r600_colorformat_endian_swap(format);
1280	}
1281
1282	/* set blend bypass according to docs if SINT/UINT or
1283	   8/24 COLOR variants */
1284	if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1285	    format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1286	    format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1287		blend_clamp = 0;
1288		blend_bypass = 1;
1289	}
1290
1291	surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1292
1293	color_info |= S_0280A0_FORMAT(format) |
1294		S_0280A0_COMP_SWAP(swap) |
1295		S_0280A0_BLEND_BYPASS(blend_bypass) |
1296		S_0280A0_BLEND_CLAMP(blend_clamp) |
1297		S_0280A0_NUMBER_TYPE(ntype) |
1298		S_0280A0_ENDIAN(endian);
1299
1300	/* EXPORT_NORM is an optimzation that can be enabled for better
1301	 * performance in certain cases
1302	 */
1303	if (rctx->chip_class == R600) {
1304		/* EXPORT_NORM can be enabled if:
1305		 * - 11-bit or smaller UNORM/SNORM/SRGB
1306		 * - BLEND_CLAMP is enabled
1307		 * - BLEND_FLOAT32 is disabled
1308		 */
1309		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1310		    (desc->channel[i].size < 12 &&
1311		     desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1312		     ntype != V_0280A0_NUMBER_UINT &&
1313		     ntype != V_0280A0_NUMBER_SINT) &&
1314		    G_0280A0_BLEND_CLAMP(color_info) &&
1315		    !G_0280A0_BLEND_FLOAT32(color_info)) {
1316			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1317			surf->export_16bpc = true;
1318		}
1319	} else {
1320		/* EXPORT_NORM can be enabled if:
1321		 * - 11-bit or smaller UNORM/SNORM/SRGB
1322		 * - 16-bit or smaller FLOAT
1323		 */
1324		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1325		    ((desc->channel[i].size < 12 &&
1326		      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1327		      ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1328		    (desc->channel[i].size < 17 &&
1329		     desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1330			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1331			surf->export_16bpc = true;
1332		}
1333	}
1334
1335	surf->cb_color_base = offset >> 8;
1336	surf->cb_color_info = color_info;
1337	surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1338			      S_028060_SLICE_TILE_MAX(slice);
1339	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1340		surf->cb_color_view = 0;
1341	} else {
1342		surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1343				      S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1344	}
1345
1346	surf->color_initialized = true;
1347}
1348
1349static void r600_init_depth_surface(struct r600_context *rctx,
1350				    struct r600_surface *surf)
1351{
1352	struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture;
1353	unsigned level, pitch, slice, format, offset, array_mode;
1354
1355	level = surf->base.u.tex.level;
1356	offset = rtex->surface.level[level].offset;
1357	pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1358	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1359	if (slice) {
1360		slice = slice - 1;
1361	}
1362	switch (rtex->surface.level[level].mode) {
1363	case RADEON_SURF_MODE_2D:
1364		array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1365		break;
1366	case RADEON_SURF_MODE_1D:
1367	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1368	case RADEON_SURF_MODE_LINEAR:
1369	default:
1370		array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1371		break;
1372	}
1373
1374	format = r600_translate_dbformat(surf->base.format);
1375	assert(format != ~0);
1376
1377	surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1378	surf->db_depth_base = offset >> 8;
1379	surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1380			      S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1381	surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1382	surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1383
1384	surf->depth_initialized = true;
1385}
1386
1387static void r600_set_framebuffer_state(struct pipe_context *ctx,
1388					const struct pipe_framebuffer_state *state)
1389{
1390	struct r600_context *rctx = (struct r600_context *)ctx;
1391	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1392	struct r600_surface *surf;
1393	struct r600_resource *res;
1394	uint32_t tl, br, i;
1395
1396	if (rstate == NULL)
1397		return;
1398
1399	r600_flush_framebuffer(rctx, false);
1400
1401	/* unreference old buffer and reference new one */
1402	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1403
1404	util_copy_framebuffer_state(&rctx->framebuffer, state);
1405
1406	/* build states */
1407	rctx->export_16bpc = true;
1408	rctx->nr_cbufs = state->nr_cbufs;
1409
1410	for (i = 0; i < state->nr_cbufs; i++) {
1411		surf = (struct r600_surface*)state->cbufs[i];
1412		res = (struct r600_resource*)surf->base.texture;
1413
1414		if (!surf->color_initialized) {
1415			r600_init_color_surface(rctx, surf);
1416		}
1417
1418		if (!surf->export_16bpc) {
1419			rctx->export_16bpc = false;
1420		}
1421
1422		r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
1423					   surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1424		r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
1425					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1426		r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
1427					surf->cb_color_size);
1428		r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
1429					surf->cb_color_view);
1430		r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
1431					   surf->cb_color_frag, res, RADEON_USAGE_READWRITE);
1432		r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
1433					   surf->cb_color_tile, res, RADEON_USAGE_READWRITE);
1434	}
1435	/* set CB_COLOR1_INFO for possible dual-src blending */
1436	if (i == 1) {
1437		r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
1438					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1439		i++;
1440	}
1441
1442	/* Update alpha-test state dependencies.
1443	 * Alpha-test is done on the first colorbuffer only. */
1444	if (state->nr_cbufs) {
1445		surf = (struct r600_surface*)state->cbufs[0];
1446		if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1447			rctx->alphatest_state.bypass = surf->alphatest_bypass;
1448			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1449		}
1450	}
1451
1452	if (state->zsbuf) {
1453		surf = (struct r600_surface*)state->zsbuf;
1454		res = (struct r600_resource*)surf->base.texture;
1455
1456		if (!surf->depth_initialized) {
1457			r600_init_depth_surface(rctx, surf);
1458		}
1459
1460		r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
1461					   res, RADEON_USAGE_READWRITE);
1462		r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
1463		r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
1464		r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
1465					   res, RADEON_USAGE_READWRITE);
1466		r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1467	}
1468
1469	tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1470	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1471
1472	r600_pipe_state_add_reg(rstate,
1473				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1474	r600_pipe_state_add_reg(rstate,
1475				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1476
1477	/* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1478	 * will assure that the alpha-test will work even if there is
1479	 * no colorbuffer bound. */
1480	r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1481				(1ull << MAX2(state->nr_cbufs, 1)) - 1);
1482
1483	if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1484		rctx->alphatest_state.bypass = false;
1485		r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1486	}
1487
1488	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1489	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1490	r600_context_pipe_state_set(rctx, rstate);
1491
1492	if (state->zsbuf) {
1493		r600_polygon_offset_update(rctx);
1494	}
1495
1496	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1497		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1498		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1499	}
1500}
1501
1502static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1503{
1504	struct radeon_winsys_cs *cs = rctx->cs;
1505	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1506	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1507	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1508	unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1509
1510	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1511	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1512	r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1513	r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1514			       a->cb_color_control |
1515			       S_028808_MULTIWRITE_ENABLE(multiwrite));
1516}
1517
1518static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1519{
1520	struct radeon_winsys_cs *cs = rctx->cs;
1521	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1522	unsigned db_render_control = 0;
1523	unsigned db_render_override =
1524		S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1525		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1526		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1527
1528	if (a->occlusion_query_enabled) {
1529		if (rctx->chip_class >= R700) {
1530			db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1531		}
1532		db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1533	}
1534	if (a->flush_depthstencil_through_cb) {
1535		assert(a->copy_depth || a->copy_stencil);
1536
1537		db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1538				     S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1539				     S_028D0C_COPY_CENTROID(1);
1540	}
1541
1542	r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1543	r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1544	r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1545}
1546
1547static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1548{
1549	struct radeon_winsys_cs *cs = rctx->cs;
1550	uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1551
1552	while (dirty_mask) {
1553		struct pipe_vertex_buffer *vb;
1554		struct r600_resource *rbuffer;
1555		unsigned offset;
1556		unsigned buffer_index = u_bit_scan(&dirty_mask);
1557
1558		vb = &rctx->vertex_buffer_state.vb[buffer_index];
1559		rbuffer = (struct r600_resource*)vb->buffer;
1560		assert(rbuffer);
1561
1562		offset = vb->buffer_offset;
1563
1564		/* fetch resources start at index 320 */
1565		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1566		r600_write_value(cs, (320 + buffer_index) * 7);
1567		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1568		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1569		r600_write_value(cs, /* RESOURCEi_WORD2 */
1570				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1571				 S_038008_STRIDE(vb->stride));
1572		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1573		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1574		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1575		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1576
1577		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1578		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1579	}
1580}
1581
1582static void r600_emit_constant_buffers(struct r600_context *rctx,
1583				       struct r600_constbuf_state *state,
1584				       unsigned buffer_id_base,
1585				       unsigned reg_alu_constbuf_size,
1586				       unsigned reg_alu_const_cache)
1587{
1588	struct radeon_winsys_cs *cs = rctx->cs;
1589	uint32_t dirty_mask = state->dirty_mask;
1590
1591	while (dirty_mask) {
1592		struct pipe_constant_buffer *cb;
1593		struct r600_resource *rbuffer;
1594		unsigned offset;
1595		unsigned buffer_index = ffs(dirty_mask) - 1;
1596
1597		cb = &state->cb[buffer_index];
1598		rbuffer = (struct r600_resource*)cb->buffer;
1599		assert(rbuffer);
1600
1601		offset = cb->buffer_offset;
1602
1603		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1604				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1605		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1606
1607		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1608		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1609
1610		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1611		r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1612		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1613		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1614		r600_write_value(cs, /* RESOURCEi_WORD2 */
1615				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1616				 S_038008_STRIDE(16));
1617		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1618		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1619		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1620		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1621
1622		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1623		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1624
1625		dirty_mask &= ~(1 << buffer_index);
1626	}
1627	state->dirty_mask = 0;
1628}
1629
1630static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1631{
1632	r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1633				   R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1634				   R_028980_ALU_CONST_CACHE_VS_0);
1635}
1636
1637static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1638{
1639	r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1640				   R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1641				   R_028940_ALU_CONST_CACHE_PS_0);
1642}
1643
1644static void r600_emit_sampler_views(struct r600_context *rctx,
1645				    struct r600_samplerview_state *state,
1646				    unsigned resource_id_base)
1647{
1648	struct radeon_winsys_cs *cs = rctx->cs;
1649	uint32_t dirty_mask = state->dirty_mask;
1650
1651	while (dirty_mask) {
1652		struct r600_pipe_sampler_view *rview;
1653		unsigned resource_index = u_bit_scan(&dirty_mask);
1654		unsigned reloc;
1655
1656		rview = state->views[resource_index];
1657		assert(rview);
1658
1659		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1660		r600_write_value(cs, (resource_id_base + resource_index) * 7);
1661		r600_write_array(cs, 7, rview->tex_resource_words);
1662
1663		/* XXX The kernel needs two relocations. This is stupid. */
1664		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1665					      RADEON_USAGE_READ);
1666		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1667		r600_write_value(cs, reloc);
1668		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1669		r600_write_value(cs, reloc);
1670	}
1671	state->dirty_mask = 0;
1672}
1673
1674static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1675{
1676	r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS);
1677}
1678
1679static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1680{
1681	r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1682}
1683
1684static void r600_emit_sampler(struct r600_context *rctx,
1685				struct r600_textures_info *texinfo,
1686				unsigned resource_id_base,
1687				unsigned border_color_reg)
1688{
1689	struct radeon_winsys_cs *cs = rctx->cs;
1690	unsigned i;
1691
1692	for (i = 0; i < texinfo->n_samplers; i++) {
1693
1694		if (texinfo->samplers[i] == NULL) {
1695			continue;
1696		}
1697
1698		/* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1699		 * filtering between layers.
1700		 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1701		 */
1702		if (texinfo->views.views[i]) {
1703			if (texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1704			    texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1705				texinfo->samplers[i]->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1706				texinfo->is_array_sampler[i] = true;
1707			} else {
1708				texinfo->samplers[i]->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1709				texinfo->is_array_sampler[i] = false;
1710			}
1711		}
1712
1713		r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1714		r600_write_value(cs, (resource_id_base + i) * 3);
1715		r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1716
1717		if (texinfo->samplers[i]->border_color_use) {
1718			unsigned offset;
1719
1720			offset = border_color_reg;
1721			offset += i * 16;
1722			r600_write_config_reg_seq(cs, offset, 4);
1723			r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
1724		}
1725	}
1726}
1727
1728static void r600_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
1729{
1730	r600_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1731}
1732
1733static void r600_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
1734{
1735	r600_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1736}
1737
1738static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1739{
1740	struct radeon_winsys_cs *cs = rctx->cs;
1741	unsigned tmp;
1742
1743	tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1744		S_009508_SYNC_GRADIENT(1) |
1745		S_009508_SYNC_WALKER(1) |
1746		S_009508_SYNC_ALIGNER(1);
1747	if (!rctx->seamless_cube_map.enabled) {
1748		tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1749	}
1750	r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1751}
1752
1753void r600_init_state_functions(struct r600_context *rctx)
1754{
1755	r600_init_atom(&rctx->seamless_cube_map.atom, r600_emit_seamless_cube_map, 3, 0);
1756	r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
1757	r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
1758	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1759	r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
1760	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1761	r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0);
1762	r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0);
1763	r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0);
1764	r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0);
1765	r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0);
1766	/* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
1767	 * does not take effect
1768	 */
1769	r600_init_atom(&rctx->vs_samplers.atom_sampler, r600_emit_vs_sampler, 0, EMIT_EARLY);
1770	r600_init_atom(&rctx->ps_samplers.atom_sampler, r600_emit_ps_sampler, 0, EMIT_EARLY);
1771
1772	rctx->context.create_blend_state = r600_create_blend_state;
1773	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1774	rctx->context.create_fs_state = r600_create_shader_state_ps;
1775	rctx->context.create_rasterizer_state = r600_create_rs_state;
1776	rctx->context.create_sampler_state = r600_create_sampler_state;
1777	rctx->context.create_sampler_view = r600_create_sampler_view;
1778	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1779	rctx->context.create_vs_state = r600_create_shader_state_vs;
1780	rctx->context.bind_blend_state = r600_bind_blend_state;
1781	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1782	rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1783	rctx->context.bind_fs_state = r600_bind_ps_shader;
1784	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1785	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1786	rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1787	rctx->context.bind_vs_state = r600_bind_vs_shader;
1788	rctx->context.delete_blend_state = r600_delete_state;
1789	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1790	rctx->context.delete_fs_state = r600_delete_ps_shader;
1791	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1792	rctx->context.delete_sampler_state = r600_delete_sampler;
1793	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1794	rctx->context.delete_vs_state = r600_delete_vs_shader;
1795	rctx->context.set_blend_color = r600_set_blend_color;
1796	rctx->context.set_clip_state = r600_set_clip_state;
1797	rctx->context.set_constant_buffer = r600_set_constant_buffer;
1798	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1799	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1800	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1801	rctx->context.set_sample_mask = r600_set_sample_mask;
1802	rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
1803	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1804	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1805	rctx->context.set_index_buffer = r600_set_index_buffer;
1806	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1807	rctx->context.set_viewport_state = r600_set_viewport_state;
1808	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1809	rctx->context.texture_barrier = r600_texture_barrier;
1810	rctx->context.create_stream_output_target = r600_create_so_target;
1811	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1812	rctx->context.set_stream_output_targets = r600_set_so_targets;
1813}
1814
1815/* Adjust GPR allocation on R6xx/R7xx */
1816void r600_adjust_gprs(struct r600_context *rctx)
1817{
1818	struct r600_pipe_state rstate;
1819	unsigned num_ps_gprs = rctx->default_ps_gprs;
1820	unsigned num_vs_gprs = rctx->default_vs_gprs;
1821	unsigned tmp;
1822	int diff;
1823
1824	/* XXX: Following call moved from r600_bind_[ps|vs]_shader,
1825	 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
1826	 * adjusting the GPR allocation?
1827	 * Do we need this if we aren't really changing config below? */
1828	r600_inval_shader_cache(rctx);
1829
1830	if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
1831	{
1832		diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
1833		num_vs_gprs -= diff;
1834		num_ps_gprs += diff;
1835	}
1836
1837	if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
1838	{
1839		diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
1840		num_ps_gprs -= diff;
1841		num_vs_gprs += diff;
1842	}
1843
1844	tmp = 0;
1845	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1846	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1847	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1848	rstate.nregs = 0;
1849	r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
1850
1851	r600_context_pipe_state_set(rctx, &rstate);
1852}
1853
1854void r600_init_atom_start_cs(struct r600_context *rctx)
1855{
1856	int ps_prio;
1857	int vs_prio;
1858	int gs_prio;
1859	int es_prio;
1860	int num_ps_gprs;
1861	int num_vs_gprs;
1862	int num_gs_gprs;
1863	int num_es_gprs;
1864	int num_temp_gprs;
1865	int num_ps_threads;
1866	int num_vs_threads;
1867	int num_gs_threads;
1868	int num_es_threads;
1869	int num_ps_stack_entries;
1870	int num_vs_stack_entries;
1871	int num_gs_stack_entries;
1872	int num_es_stack_entries;
1873	enum radeon_family family;
1874	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1875	uint32_t tmp;
1876	unsigned i;
1877
1878	r600_init_command_buffer(cb, 256, EMIT_EARLY);
1879
1880	/* R6xx requires this packet at the start of each command buffer */
1881	if (rctx->chip_class == R600) {
1882		r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
1883		r600_store_value(cb, 0);
1884	}
1885	/* All asics require this one */
1886	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1887	r600_store_value(cb, 0x80000000);
1888	r600_store_value(cb, 0x80000000);
1889
1890	family = rctx->family;
1891	ps_prio = 0;
1892	vs_prio = 1;
1893	gs_prio = 2;
1894	es_prio = 3;
1895	switch (family) {
1896	case CHIP_R600:
1897		num_ps_gprs = 192;
1898		num_vs_gprs = 56;
1899		num_temp_gprs = 4;
1900		num_gs_gprs = 0;
1901		num_es_gprs = 0;
1902		num_ps_threads = 136;
1903		num_vs_threads = 48;
1904		num_gs_threads = 4;
1905		num_es_threads = 4;
1906		num_ps_stack_entries = 128;
1907		num_vs_stack_entries = 128;
1908		num_gs_stack_entries = 0;
1909		num_es_stack_entries = 0;
1910		break;
1911	case CHIP_RV630:
1912	case CHIP_RV635:
1913		num_ps_gprs = 84;
1914		num_vs_gprs = 36;
1915		num_temp_gprs = 4;
1916		num_gs_gprs = 0;
1917		num_es_gprs = 0;
1918		num_ps_threads = 144;
1919		num_vs_threads = 40;
1920		num_gs_threads = 4;
1921		num_es_threads = 4;
1922		num_ps_stack_entries = 40;
1923		num_vs_stack_entries = 40;
1924		num_gs_stack_entries = 32;
1925		num_es_stack_entries = 16;
1926		break;
1927	case CHIP_RV610:
1928	case CHIP_RV620:
1929	case CHIP_RS780:
1930	case CHIP_RS880:
1931	default:
1932		num_ps_gprs = 84;
1933		num_vs_gprs = 36;
1934		num_temp_gprs = 4;
1935		num_gs_gprs = 0;
1936		num_es_gprs = 0;
1937		num_ps_threads = 136;
1938		num_vs_threads = 48;
1939		num_gs_threads = 4;
1940		num_es_threads = 4;
1941		num_ps_stack_entries = 40;
1942		num_vs_stack_entries = 40;
1943		num_gs_stack_entries = 32;
1944		num_es_stack_entries = 16;
1945		break;
1946	case CHIP_RV670:
1947		num_ps_gprs = 144;
1948		num_vs_gprs = 40;
1949		num_temp_gprs = 4;
1950		num_gs_gprs = 0;
1951		num_es_gprs = 0;
1952		num_ps_threads = 136;
1953		num_vs_threads = 48;
1954		num_gs_threads = 4;
1955		num_es_threads = 4;
1956		num_ps_stack_entries = 40;
1957		num_vs_stack_entries = 40;
1958		num_gs_stack_entries = 32;
1959		num_es_stack_entries = 16;
1960		break;
1961	case CHIP_RV770:
1962		num_ps_gprs = 192;
1963		num_vs_gprs = 56;
1964		num_temp_gprs = 4;
1965		num_gs_gprs = 0;
1966		num_es_gprs = 0;
1967		num_ps_threads = 188;
1968		num_vs_threads = 60;
1969		num_gs_threads = 0;
1970		num_es_threads = 0;
1971		num_ps_stack_entries = 256;
1972		num_vs_stack_entries = 256;
1973		num_gs_stack_entries = 0;
1974		num_es_stack_entries = 0;
1975		break;
1976	case CHIP_RV730:
1977	case CHIP_RV740:
1978		num_ps_gprs = 84;
1979		num_vs_gprs = 36;
1980		num_temp_gprs = 4;
1981		num_gs_gprs = 0;
1982		num_es_gprs = 0;
1983		num_ps_threads = 188;
1984		num_vs_threads = 60;
1985		num_gs_threads = 0;
1986		num_es_threads = 0;
1987		num_ps_stack_entries = 128;
1988		num_vs_stack_entries = 128;
1989		num_gs_stack_entries = 0;
1990		num_es_stack_entries = 0;
1991		break;
1992	case CHIP_RV710:
1993		num_ps_gprs = 192;
1994		num_vs_gprs = 56;
1995		num_temp_gprs = 4;
1996		num_gs_gprs = 0;
1997		num_es_gprs = 0;
1998		num_ps_threads = 144;
1999		num_vs_threads = 48;
2000		num_gs_threads = 0;
2001		num_es_threads = 0;
2002		num_ps_stack_entries = 128;
2003		num_vs_stack_entries = 128;
2004		num_gs_stack_entries = 0;
2005		num_es_stack_entries = 0;
2006		break;
2007	}
2008
2009	rctx->default_ps_gprs = num_ps_gprs;
2010	rctx->default_vs_gprs = num_vs_gprs;
2011	rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2012
2013	/* SQ_CONFIG */
2014	tmp = 0;
2015	switch (family) {
2016	case CHIP_RV610:
2017	case CHIP_RV620:
2018	case CHIP_RS780:
2019	case CHIP_RS880:
2020	case CHIP_RV710:
2021		break;
2022	default:
2023		tmp |= S_008C00_VC_ENABLE(1);
2024		break;
2025	}
2026	tmp |= S_008C00_DX9_CONSTS(0);
2027	tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2028	tmp |= S_008C00_PS_PRIO(ps_prio);
2029	tmp |= S_008C00_VS_PRIO(vs_prio);
2030	tmp |= S_008C00_GS_PRIO(gs_prio);
2031	tmp |= S_008C00_ES_PRIO(es_prio);
2032	r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2033
2034	/* SQ_GPR_RESOURCE_MGMT_2 */
2035	tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2036	tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2037	r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2038	r600_store_value(cb, tmp);
2039
2040	/* SQ_THREAD_RESOURCE_MGMT */
2041	tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2042	tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2043	tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2044	tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2045	r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2046
2047	/* SQ_STACK_RESOURCE_MGMT_1 */
2048	tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2049	tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2050	r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2051
2052	/* SQ_STACK_RESOURCE_MGMT_2 */
2053	tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2054	tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2055	r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2056
2057	r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2058
2059	if (rctx->chip_class >= R700) {
2060		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2061		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2062		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2063		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2064	} else {
2065		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2066		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2067		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2068		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2069	}
2070	r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2071	r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2072	r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2073	r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2074	r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2075	r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2076	r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2077	r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2078	r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2079	r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2080
2081	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2082	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2083	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2084	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2085	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2086	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2087	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2088	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2089	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2090	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2091	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2092	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2093	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2094	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2095
2096	r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2097	r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2098	r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2099
2100	r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2101	r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2102	r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2103	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2104
2105	r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2106
2107	r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2108	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2109	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2110
2111	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2112
2113	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2114	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2115	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2116
2117	r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2118	r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2119	r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2120	r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2121
2122	r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2123	r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2124	r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2125
2126	r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00);
2127
2128	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2129	r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2130
2131	r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2132	r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */
2133	r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2134
2135	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6);
2136	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2137	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2138	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2139	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2140	r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
2141	r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */
2142
2143	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2144	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2145	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2146
2147	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2148
2149	r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8);
2150	for (i = 0; i < 8; i++) {
2151		r600_store_value(cb, 0);
2152	}
2153
2154	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2155	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2156
2157	if (rctx->chip_class >= R700) {
2158		r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2159	}
2160
2161	r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2162	r600_store_value(cb, 0x1000000);  /* R_028C30_CB_CLRCMP_CONTROL */
2163	r600_store_value(cb, 0);          /* R_028C34_CB_CLRCMP_SRC */
2164	r600_store_value(cb, 0xFF);       /* R_028C38_CB_CLRCMP_DST */
2165	r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2166
2167	r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF);
2168
2169	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2170	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2171	r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2172
2173	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2174	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2175	r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2176
2177	r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2178	r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2179	r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2180
2181	r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2182	r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2183
2184	if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2185		r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2186	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2187	if (rctx->screen->has_streamout) {
2188		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2189	}
2190
2191	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2192	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2193}
2194
2195void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2196{
2197	struct r600_context *rctx = (struct r600_context *)ctx;
2198	struct r600_pipe_state *rstate = &shader->rstate;
2199	struct r600_shader *rshader = &shader->shader;
2200	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2201	int pos_index = -1, face_index = -1;
2202	unsigned tmp, sid, ufi = 0;
2203	int need_linear = 0;
2204	unsigned z_export = 0, stencil_export = 0;
2205
2206	rstate->nregs = 0;
2207
2208	for (i = 0; i < rshader->ninput; i++) {
2209		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2210			pos_index = i;
2211		if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2212			face_index = i;
2213
2214		sid = rshader->input[i].spi_sid;
2215
2216		tmp = S_028644_SEMANTIC(sid);
2217
2218		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2219			rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2220			(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2221				rctx->rasterizer && rctx->rasterizer->flatshade))
2222			tmp |= S_028644_FLAT_SHADE(1);
2223
2224		if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2225				rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2226			tmp |= S_028644_PT_SPRITE_TEX(1);
2227		}
2228
2229		if (rshader->input[i].centroid)
2230			tmp |= S_028644_SEL_CENTROID(1);
2231
2232		if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2233			need_linear = 1;
2234			tmp |= S_028644_SEL_LINEAR(1);
2235		}
2236
2237		r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2238				tmp);
2239	}
2240
2241	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2242	for (i = 0; i < rshader->noutput; i++) {
2243		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2244			z_export = 1;
2245		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2246			stencil_export = 1;
2247	}
2248	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2249	db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2250	if (rshader->uses_kill)
2251		db_shader_control |= S_02880C_KILL_ENABLE(1);
2252
2253	exports_ps = 0;
2254	for (i = 0; i < rshader->noutput; i++) {
2255		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2256		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2257			exports_ps |= 1;
2258		}
2259	}
2260	num_cout = rshader->nr_ps_color_exports;
2261	exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2262	if (!exports_ps) {
2263		/* always at least export 1 component per pixel */
2264		exports_ps = 2;
2265	}
2266
2267	shader->nr_ps_color_outputs = num_cout;
2268
2269	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2270				S_0286CC_PERSP_GRADIENT_ENA(1)|
2271				S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2272	spi_input_z = 0;
2273	if (pos_index != -1) {
2274		spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2275					S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2276					S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2277					S_0286CC_BARYC_SAMPLE_CNTL(1));
2278		spi_input_z |= 1;
2279	}
2280
2281	spi_ps_in_control_1 = 0;
2282	if (face_index != -1) {
2283		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2284			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2285	}
2286
2287	/* HW bug in original R600 */
2288	if (rctx->family == CHIP_R600)
2289		ufi = 1;
2290
2291	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2292	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2293	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2294	r600_pipe_state_add_reg_bo(rstate,
2295				   R_028840_SQ_PGM_START_PS,
2296				   0, shader->bo, RADEON_USAGE_READ);
2297	r600_pipe_state_add_reg(rstate,
2298				R_028850_SQ_PGM_RESOURCES_PS,
2299				S_028850_NUM_GPRS(rshader->bc.ngpr) |
2300				S_028850_STACK_SIZE(rshader->bc.nstack) |
2301				S_028850_UNCACHED_FIRST_INST(ufi));
2302	r600_pipe_state_add_reg(rstate,
2303				R_028854_SQ_PGM_EXPORTS_PS,
2304				exports_ps);
2305	/* only set some bits here, the other bits are set in the dsa state */
2306	shader->db_shader_control = db_shader_control;
2307	shader->ps_depth_export = z_export | stencil_export;
2308
2309	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2310	if (rctx->rasterizer)
2311		shader->flatshade = rctx->rasterizer->flatshade;
2312}
2313
2314void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2315{
2316	struct r600_context *rctx = (struct r600_context *)ctx;
2317	struct r600_pipe_state *rstate = &shader->rstate;
2318	struct r600_shader *rshader = &shader->shader;
2319	unsigned spi_vs_out_id[10] = {};
2320	unsigned i, tmp, nparams = 0;
2321
2322	/* clear previous register */
2323	rstate->nregs = 0;
2324
2325	for (i = 0; i < rshader->noutput; i++) {
2326		if (rshader->output[i].spi_sid) {
2327			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2328			spi_vs_out_id[nparams / 4] |= tmp;
2329			nparams++;
2330		}
2331	}
2332
2333	for (i = 0; i < 10; i++) {
2334		r600_pipe_state_add_reg(rstate,
2335					R_028614_SPI_VS_OUT_ID_0 + i * 4,
2336					spi_vs_out_id[i]);
2337	}
2338
2339	/* Certain attributes (position, psize, etc.) don't count as params.
2340	 * VS is required to export at least one param and r600_shader_from_tgsi()
2341	 * takes care of adding a dummy export.
2342	 */
2343	if (nparams < 1)
2344		nparams = 1;
2345
2346	r600_pipe_state_add_reg(rstate,
2347				R_0286C4_SPI_VS_OUT_CONFIG,
2348				S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2349	r600_pipe_state_add_reg(rstate,
2350				R_028868_SQ_PGM_RESOURCES_VS,
2351				S_028868_NUM_GPRS(rshader->bc.ngpr) |
2352				S_028868_STACK_SIZE(rshader->bc.nstack));
2353	r600_pipe_state_add_reg_bo(rstate,
2354			R_028858_SQ_PGM_START_VS,
2355			0, shader->bo, RADEON_USAGE_READ);
2356
2357	shader->pa_cl_vs_out_cntl =
2358		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2359		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2360		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2361		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2362}
2363
2364void r600_fetch_shader(struct pipe_context *ctx,
2365		       struct r600_vertex_element *ve)
2366{
2367	struct r600_pipe_state *rstate;
2368	struct r600_context *rctx = (struct r600_context *)ctx;
2369
2370	rstate = &ve->rstate;
2371	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2372	rstate->nregs = 0;
2373	r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2374				0,
2375				ve->fetch_shader, RADEON_USAGE_READ);
2376}
2377
2378void *r600_create_db_flush_dsa(struct r600_context *rctx)
2379{
2380	struct pipe_depth_stencil_alpha_state dsa;
2381	boolean quirk = false;
2382
2383	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2384		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2385		quirk = true;
2386
2387	memset(&dsa, 0, sizeof(dsa));
2388
2389	if (quirk) {
2390		dsa.depth.enabled = 1;
2391		dsa.depth.func = PIPE_FUNC_LEQUAL;
2392		dsa.stencil[0].enabled = 1;
2393		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2394		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2395		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2396		dsa.stencil[0].writemask = 0xff;
2397	}
2398
2399	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2400}
2401
2402void r600_update_dual_export_state(struct r600_context * rctx)
2403{
2404	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2405			       !rctx->ps_shader->current->ps_depth_export;
2406	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2407				     S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2408
2409	if (db_shader_control != rctx->db_shader_control) {
2410		struct r600_pipe_state rstate;
2411
2412		rctx->db_shader_control = db_shader_control;
2413		rstate.nregs = 0;
2414		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2415		r600_context_pipe_state_set(rctx, &rstate);
2416	}
2417}
2418