r600_state.c revision 4f215952760b2e5a92b25ddfa89469c1ec110160
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_formats.h" 24#include "r600d.h" 25 26#include "pipe/p_shader_tokens.h" 27#include "util/u_pack_color.h" 28#include "util/u_memory.h" 29#include "util/u_framebuffer.h" 30#include "util/u_dual_blend.h" 31 32static uint32_t r600_translate_blend_function(int blend_func) 33{ 34 switch (blend_func) { 35 case PIPE_BLEND_ADD: 36 return V_028804_COMB_DST_PLUS_SRC; 37 case PIPE_BLEND_SUBTRACT: 38 return V_028804_COMB_SRC_MINUS_DST; 39 case PIPE_BLEND_REVERSE_SUBTRACT: 40 return V_028804_COMB_DST_MINUS_SRC; 41 case PIPE_BLEND_MIN: 42 return V_028804_COMB_MIN_DST_SRC; 43 case PIPE_BLEND_MAX: 44 return V_028804_COMB_MAX_DST_SRC; 45 default: 46 R600_ERR("Unknown blend function %d\n", blend_func); 47 assert(0); 48 break; 49 } 50 return 0; 51} 52 53static uint32_t r600_translate_blend_factor(int blend_fact) 54{ 55 switch (blend_fact) { 56 case PIPE_BLENDFACTOR_ONE: 57 return V_028804_BLEND_ONE; 58 case PIPE_BLENDFACTOR_SRC_COLOR: 59 return V_028804_BLEND_SRC_COLOR; 60 case PIPE_BLENDFACTOR_SRC_ALPHA: 61 return V_028804_BLEND_SRC_ALPHA; 62 case PIPE_BLENDFACTOR_DST_ALPHA: 63 return V_028804_BLEND_DST_ALPHA; 64 case PIPE_BLENDFACTOR_DST_COLOR: 65 return V_028804_BLEND_DST_COLOR; 66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 67 return V_028804_BLEND_SRC_ALPHA_SATURATE; 68 case PIPE_BLENDFACTOR_CONST_COLOR: 69 return V_028804_BLEND_CONST_COLOR; 70 case PIPE_BLENDFACTOR_CONST_ALPHA: 71 return V_028804_BLEND_CONST_ALPHA; 72 case PIPE_BLENDFACTOR_ZERO: 73 return V_028804_BLEND_ZERO; 74 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR; 76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA; 78 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA; 80 case PIPE_BLENDFACTOR_INV_DST_COLOR: 81 return V_028804_BLEND_ONE_MINUS_DST_COLOR; 82 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR; 84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA; 86 case PIPE_BLENDFACTOR_SRC1_COLOR: 87 return V_028804_BLEND_SRC1_COLOR; 88 case PIPE_BLENDFACTOR_SRC1_ALPHA: 89 return V_028804_BLEND_SRC1_ALPHA; 90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 91 return V_028804_BLEND_INV_SRC1_COLOR; 92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 93 return V_028804_BLEND_INV_SRC1_ALPHA; 94 default: 95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 96 assert(0); 97 break; 98 } 99 return 0; 100} 101 102static unsigned r600_tex_dim(unsigned dim) 103{ 104 switch (dim) { 105 default: 106 case PIPE_TEXTURE_1D: 107 return V_038000_SQ_TEX_DIM_1D; 108 case PIPE_TEXTURE_1D_ARRAY: 109 return V_038000_SQ_TEX_DIM_1D_ARRAY; 110 case PIPE_TEXTURE_2D: 111 case PIPE_TEXTURE_RECT: 112 return V_038000_SQ_TEX_DIM_2D; 113 case PIPE_TEXTURE_2D_ARRAY: 114 return V_038000_SQ_TEX_DIM_2D_ARRAY; 115 case PIPE_TEXTURE_3D: 116 return V_038000_SQ_TEX_DIM_3D; 117 case PIPE_TEXTURE_CUBE: 118 return V_038000_SQ_TEX_DIM_CUBEMAP; 119 } 120} 121 122static uint32_t r600_translate_dbformat(enum pipe_format format) 123{ 124 switch (format) { 125 case PIPE_FORMAT_Z16_UNORM: 126 return V_028010_DEPTH_16; 127 case PIPE_FORMAT_Z24X8_UNORM: 128 return V_028010_DEPTH_X8_24; 129 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 130 return V_028010_DEPTH_8_24; 131 case PIPE_FORMAT_Z32_FLOAT: 132 return V_028010_DEPTH_32_FLOAT; 133 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 134 return V_028010_DEPTH_X24_8_32_FLOAT; 135 default: 136 return ~0U; 137 } 138} 139 140static uint32_t r600_translate_colorswap(enum pipe_format format) 141{ 142 switch (format) { 143 /* 8-bit buffers. */ 144 case PIPE_FORMAT_A8_UNORM: 145 case PIPE_FORMAT_A8_SNORM: 146 case PIPE_FORMAT_A8_UINT: 147 case PIPE_FORMAT_A8_SINT: 148 case PIPE_FORMAT_A16_UNORM: 149 case PIPE_FORMAT_A16_SNORM: 150 case PIPE_FORMAT_A16_UINT: 151 case PIPE_FORMAT_A16_SINT: 152 case PIPE_FORMAT_A16_FLOAT: 153 case PIPE_FORMAT_A32_UINT: 154 case PIPE_FORMAT_A32_SINT: 155 case PIPE_FORMAT_A32_FLOAT: 156 case PIPE_FORMAT_R4A4_UNORM: 157 return V_0280A0_SWAP_ALT_REV; 158 case PIPE_FORMAT_I8_UNORM: 159 case PIPE_FORMAT_I8_SNORM: 160 case PIPE_FORMAT_I8_UINT: 161 case PIPE_FORMAT_I8_SINT: 162 case PIPE_FORMAT_L8_UNORM: 163 case PIPE_FORMAT_L8_SNORM: 164 case PIPE_FORMAT_L8_UINT: 165 case PIPE_FORMAT_L8_SINT: 166 case PIPE_FORMAT_L8_SRGB: 167 case PIPE_FORMAT_L16_UNORM: 168 case PIPE_FORMAT_L16_SNORM: 169 case PIPE_FORMAT_L16_UINT: 170 case PIPE_FORMAT_L16_SINT: 171 case PIPE_FORMAT_L16_FLOAT: 172 case PIPE_FORMAT_L32_UINT: 173 case PIPE_FORMAT_L32_SINT: 174 case PIPE_FORMAT_L32_FLOAT: 175 case PIPE_FORMAT_I16_UNORM: 176 case PIPE_FORMAT_I16_SNORM: 177 case PIPE_FORMAT_I16_UINT: 178 case PIPE_FORMAT_I16_SINT: 179 case PIPE_FORMAT_I16_FLOAT: 180 case PIPE_FORMAT_I32_UINT: 181 case PIPE_FORMAT_I32_SINT: 182 case PIPE_FORMAT_I32_FLOAT: 183 case PIPE_FORMAT_R8_UNORM: 184 case PIPE_FORMAT_R8_SNORM: 185 case PIPE_FORMAT_R8_UINT: 186 case PIPE_FORMAT_R8_SINT: 187 return V_0280A0_SWAP_STD; 188 189 case PIPE_FORMAT_L4A4_UNORM: 190 case PIPE_FORMAT_A4R4_UNORM: 191 return V_0280A0_SWAP_ALT; 192 193 /* 16-bit buffers. */ 194 case PIPE_FORMAT_B5G6R5_UNORM: 195 return V_0280A0_SWAP_STD_REV; 196 197 case PIPE_FORMAT_B5G5R5A1_UNORM: 198 case PIPE_FORMAT_B5G5R5X1_UNORM: 199 return V_0280A0_SWAP_ALT; 200 201 case PIPE_FORMAT_B4G4R4A4_UNORM: 202 case PIPE_FORMAT_B4G4R4X4_UNORM: 203 return V_0280A0_SWAP_ALT; 204 205 case PIPE_FORMAT_Z16_UNORM: 206 return V_0280A0_SWAP_STD; 207 208 case PIPE_FORMAT_L8A8_UNORM: 209 case PIPE_FORMAT_L8A8_SNORM: 210 case PIPE_FORMAT_L8A8_UINT: 211 case PIPE_FORMAT_L8A8_SINT: 212 case PIPE_FORMAT_L8A8_SRGB: 213 case PIPE_FORMAT_L16A16_UNORM: 214 case PIPE_FORMAT_L16A16_SNORM: 215 case PIPE_FORMAT_L16A16_UINT: 216 case PIPE_FORMAT_L16A16_SINT: 217 case PIPE_FORMAT_L16A16_FLOAT: 218 case PIPE_FORMAT_L32A32_UINT: 219 case PIPE_FORMAT_L32A32_SINT: 220 case PIPE_FORMAT_L32A32_FLOAT: 221 return V_0280A0_SWAP_ALT; 222 case PIPE_FORMAT_R8G8_UNORM: 223 case PIPE_FORMAT_R8G8_SNORM: 224 case PIPE_FORMAT_R8G8_UINT: 225 case PIPE_FORMAT_R8G8_SINT: 226 return V_0280A0_SWAP_STD; 227 228 case PIPE_FORMAT_R16_UNORM: 229 case PIPE_FORMAT_R16_SNORM: 230 case PIPE_FORMAT_R16_UINT: 231 case PIPE_FORMAT_R16_SINT: 232 case PIPE_FORMAT_R16_FLOAT: 233 return V_0280A0_SWAP_STD; 234 235 /* 32-bit buffers. */ 236 237 case PIPE_FORMAT_A8B8G8R8_SRGB: 238 return V_0280A0_SWAP_STD_REV; 239 case PIPE_FORMAT_B8G8R8A8_SRGB: 240 return V_0280A0_SWAP_ALT; 241 242 case PIPE_FORMAT_B8G8R8A8_UNORM: 243 case PIPE_FORMAT_B8G8R8X8_UNORM: 244 return V_0280A0_SWAP_ALT; 245 246 case PIPE_FORMAT_A8R8G8B8_UNORM: 247 case PIPE_FORMAT_X8R8G8B8_UNORM: 248 return V_0280A0_SWAP_ALT_REV; 249 case PIPE_FORMAT_R8G8B8A8_SNORM: 250 case PIPE_FORMAT_R8G8B8A8_UNORM: 251 case PIPE_FORMAT_R8G8B8X8_UNORM: 252 case PIPE_FORMAT_R8G8B8A8_SINT: 253 case PIPE_FORMAT_R8G8B8A8_UINT: 254 return V_0280A0_SWAP_STD; 255 256 case PIPE_FORMAT_A8B8G8R8_UNORM: 257 case PIPE_FORMAT_X8B8G8R8_UNORM: 258 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ 259 return V_0280A0_SWAP_STD_REV; 260 261 case PIPE_FORMAT_Z24X8_UNORM: 262 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 263 return V_0280A0_SWAP_STD; 264 265 case PIPE_FORMAT_X8Z24_UNORM: 266 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 267 return V_0280A0_SWAP_STD; 268 269 case PIPE_FORMAT_R10G10B10A2_UNORM: 270 case PIPE_FORMAT_R10G10B10X2_SNORM: 271 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 272 return V_0280A0_SWAP_STD; 273 274 case PIPE_FORMAT_B10G10R10A2_UNORM: 275 case PIPE_FORMAT_B10G10R10A2_UINT: 276 return V_0280A0_SWAP_ALT; 277 278 case PIPE_FORMAT_R11G11B10_FLOAT: 279 case PIPE_FORMAT_R16G16_UNORM: 280 case PIPE_FORMAT_R16G16_SNORM: 281 case PIPE_FORMAT_R16G16_FLOAT: 282 case PIPE_FORMAT_R16G16_UINT: 283 case PIPE_FORMAT_R16G16_SINT: 284 case PIPE_FORMAT_R32_UINT: 285 case PIPE_FORMAT_R32_SINT: 286 case PIPE_FORMAT_R32_FLOAT: 287 case PIPE_FORMAT_Z32_FLOAT: 288 return V_0280A0_SWAP_STD; 289 290 /* 64-bit buffers. */ 291 case PIPE_FORMAT_R32G32_FLOAT: 292 case PIPE_FORMAT_R32G32_UINT: 293 case PIPE_FORMAT_R32G32_SINT: 294 case PIPE_FORMAT_R16G16B16A16_UNORM: 295 case PIPE_FORMAT_R16G16B16A16_SNORM: 296 case PIPE_FORMAT_R16G16B16A16_UINT: 297 case PIPE_FORMAT_R16G16B16A16_SINT: 298 case PIPE_FORMAT_R16G16B16A16_FLOAT: 299 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 300 301 /* 128-bit buffers. */ 302 case PIPE_FORMAT_R32G32B32A32_FLOAT: 303 case PIPE_FORMAT_R32G32B32A32_SNORM: 304 case PIPE_FORMAT_R32G32B32A32_UNORM: 305 case PIPE_FORMAT_R32G32B32A32_SINT: 306 case PIPE_FORMAT_R32G32B32A32_UINT: 307 return V_0280A0_SWAP_STD; 308 default: 309 R600_ERR("unsupported colorswap format %d\n", format); 310 return ~0U; 311 } 312 return ~0U; 313} 314 315static uint32_t r600_translate_colorformat(enum pipe_format format) 316{ 317 switch (format) { 318 case PIPE_FORMAT_L4A4_UNORM: 319 case PIPE_FORMAT_R4A4_UNORM: 320 case PIPE_FORMAT_A4R4_UNORM: 321 return V_0280A0_COLOR_4_4; 322 323 /* 8-bit buffers. */ 324 case PIPE_FORMAT_A8_UNORM: 325 case PIPE_FORMAT_A8_SNORM: 326 case PIPE_FORMAT_A8_UINT: 327 case PIPE_FORMAT_A8_SINT: 328 case PIPE_FORMAT_I8_UNORM: 329 case PIPE_FORMAT_I8_SNORM: 330 case PIPE_FORMAT_I8_UINT: 331 case PIPE_FORMAT_I8_SINT: 332 case PIPE_FORMAT_L8_UNORM: 333 case PIPE_FORMAT_L8_SNORM: 334 case PIPE_FORMAT_L8_UINT: 335 case PIPE_FORMAT_L8_SINT: 336 case PIPE_FORMAT_L8_SRGB: 337 case PIPE_FORMAT_R8_UNORM: 338 case PIPE_FORMAT_R8_SNORM: 339 case PIPE_FORMAT_R8_UINT: 340 case PIPE_FORMAT_R8_SINT: 341 return V_0280A0_COLOR_8; 342 343 /* 16-bit buffers. */ 344 case PIPE_FORMAT_B5G6R5_UNORM: 345 return V_0280A0_COLOR_5_6_5; 346 347 case PIPE_FORMAT_B5G5R5A1_UNORM: 348 case PIPE_FORMAT_B5G5R5X1_UNORM: 349 return V_0280A0_COLOR_1_5_5_5; 350 351 case PIPE_FORMAT_B4G4R4A4_UNORM: 352 case PIPE_FORMAT_B4G4R4X4_UNORM: 353 return V_0280A0_COLOR_4_4_4_4; 354 355 case PIPE_FORMAT_Z16_UNORM: 356 return V_0280A0_COLOR_16; 357 358 case PIPE_FORMAT_L8A8_UNORM: 359 case PIPE_FORMAT_L8A8_SNORM: 360 case PIPE_FORMAT_L8A8_UINT: 361 case PIPE_FORMAT_L8A8_SINT: 362 case PIPE_FORMAT_L8A8_SRGB: 363 case PIPE_FORMAT_R8G8_UNORM: 364 case PIPE_FORMAT_R8G8_SNORM: 365 case PIPE_FORMAT_R8G8_UINT: 366 case PIPE_FORMAT_R8G8_SINT: 367 return V_0280A0_COLOR_8_8; 368 369 case PIPE_FORMAT_R16_UNORM: 370 case PIPE_FORMAT_R16_SNORM: 371 case PIPE_FORMAT_R16_UINT: 372 case PIPE_FORMAT_R16_SINT: 373 case PIPE_FORMAT_A16_UNORM: 374 case PIPE_FORMAT_A16_SNORM: 375 case PIPE_FORMAT_A16_UINT: 376 case PIPE_FORMAT_A16_SINT: 377 case PIPE_FORMAT_L16_UNORM: 378 case PIPE_FORMAT_L16_SNORM: 379 case PIPE_FORMAT_L16_UINT: 380 case PIPE_FORMAT_L16_SINT: 381 case PIPE_FORMAT_I16_UNORM: 382 case PIPE_FORMAT_I16_SNORM: 383 case PIPE_FORMAT_I16_UINT: 384 case PIPE_FORMAT_I16_SINT: 385 return V_0280A0_COLOR_16; 386 387 case PIPE_FORMAT_R16_FLOAT: 388 case PIPE_FORMAT_A16_FLOAT: 389 case PIPE_FORMAT_L16_FLOAT: 390 case PIPE_FORMAT_I16_FLOAT: 391 return V_0280A0_COLOR_16_FLOAT; 392 393 /* 32-bit buffers. */ 394 case PIPE_FORMAT_A8B8G8R8_SRGB: 395 case PIPE_FORMAT_A8B8G8R8_UNORM: 396 case PIPE_FORMAT_A8R8G8B8_UNORM: 397 case PIPE_FORMAT_B8G8R8A8_SRGB: 398 case PIPE_FORMAT_B8G8R8A8_UNORM: 399 case PIPE_FORMAT_B8G8R8X8_UNORM: 400 case PIPE_FORMAT_R8G8B8A8_SNORM: 401 case PIPE_FORMAT_R8G8B8A8_UNORM: 402 case PIPE_FORMAT_R8G8B8X8_UNORM: 403 case PIPE_FORMAT_R8SG8SB8UX8U_NORM: 404 case PIPE_FORMAT_X8B8G8R8_UNORM: 405 case PIPE_FORMAT_X8R8G8B8_UNORM: 406 case PIPE_FORMAT_R8G8B8A8_SINT: 407 case PIPE_FORMAT_R8G8B8A8_UINT: 408 return V_0280A0_COLOR_8_8_8_8; 409 410 case PIPE_FORMAT_R10G10B10A2_UNORM: 411 case PIPE_FORMAT_R10G10B10X2_SNORM: 412 case PIPE_FORMAT_B10G10R10A2_UNORM: 413 case PIPE_FORMAT_B10G10R10A2_UINT: 414 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 415 return V_0280A0_COLOR_2_10_10_10; 416 417 case PIPE_FORMAT_Z24X8_UNORM: 418 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 419 return V_0280A0_COLOR_8_24; 420 421 case PIPE_FORMAT_X8Z24_UNORM: 422 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 423 return V_0280A0_COLOR_24_8; 424 425 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 426 return V_0280A0_COLOR_X24_8_32_FLOAT; 427 428 case PIPE_FORMAT_R32_UINT: 429 case PIPE_FORMAT_R32_SINT: 430 case PIPE_FORMAT_A32_UINT: 431 case PIPE_FORMAT_A32_SINT: 432 case PIPE_FORMAT_L32_UINT: 433 case PIPE_FORMAT_L32_SINT: 434 case PIPE_FORMAT_I32_UINT: 435 case PIPE_FORMAT_I32_SINT: 436 return V_0280A0_COLOR_32; 437 438 case PIPE_FORMAT_R32_FLOAT: 439 case PIPE_FORMAT_A32_FLOAT: 440 case PIPE_FORMAT_L32_FLOAT: 441 case PIPE_FORMAT_I32_FLOAT: 442 case PIPE_FORMAT_Z32_FLOAT: 443 return V_0280A0_COLOR_32_FLOAT; 444 445 case PIPE_FORMAT_R16G16_FLOAT: 446 case PIPE_FORMAT_L16A16_FLOAT: 447 return V_0280A0_COLOR_16_16_FLOAT; 448 449 case PIPE_FORMAT_R16G16_UNORM: 450 case PIPE_FORMAT_R16G16_SNORM: 451 case PIPE_FORMAT_R16G16_UINT: 452 case PIPE_FORMAT_R16G16_SINT: 453 case PIPE_FORMAT_L16A16_UNORM: 454 case PIPE_FORMAT_L16A16_SNORM: 455 case PIPE_FORMAT_L16A16_UINT: 456 case PIPE_FORMAT_L16A16_SINT: 457 return V_0280A0_COLOR_16_16; 458 459 case PIPE_FORMAT_R11G11B10_FLOAT: 460 return V_0280A0_COLOR_10_11_11_FLOAT; 461 462 /* 64-bit buffers. */ 463 case PIPE_FORMAT_R16G16B16A16_UINT: 464 case PIPE_FORMAT_R16G16B16A16_SINT: 465 case PIPE_FORMAT_R16G16B16A16_UNORM: 466 case PIPE_FORMAT_R16G16B16A16_SNORM: 467 return V_0280A0_COLOR_16_16_16_16; 468 469 case PIPE_FORMAT_R16G16B16A16_FLOAT: 470 return V_0280A0_COLOR_16_16_16_16_FLOAT; 471 472 case PIPE_FORMAT_R32G32_FLOAT: 473 case PIPE_FORMAT_L32A32_FLOAT: 474 return V_0280A0_COLOR_32_32_FLOAT; 475 476 case PIPE_FORMAT_R32G32_SINT: 477 case PIPE_FORMAT_R32G32_UINT: 478 case PIPE_FORMAT_L32A32_UINT: 479 case PIPE_FORMAT_L32A32_SINT: 480 return V_0280A0_COLOR_32_32; 481 482 /* 128-bit buffers. */ 483 case PIPE_FORMAT_R32G32B32A32_FLOAT: 484 return V_0280A0_COLOR_32_32_32_32_FLOAT; 485 case PIPE_FORMAT_R32G32B32A32_SNORM: 486 case PIPE_FORMAT_R32G32B32A32_UNORM: 487 case PIPE_FORMAT_R32G32B32A32_SINT: 488 case PIPE_FORMAT_R32G32B32A32_UINT: 489 return V_0280A0_COLOR_32_32_32_32; 490 491 /* YUV buffers. */ 492 case PIPE_FORMAT_UYVY: 493 case PIPE_FORMAT_YUYV: 494 default: 495 return ~0U; /* Unsupported. */ 496 } 497} 498 499static uint32_t r600_colorformat_endian_swap(uint32_t colorformat) 500{ 501 if (R600_BIG_ENDIAN) { 502 switch(colorformat) { 503 case V_0280A0_COLOR_4_4: 504 return ENDIAN_NONE; 505 506 /* 8-bit buffers. */ 507 case V_0280A0_COLOR_8: 508 return ENDIAN_NONE; 509 510 /* 16-bit buffers. */ 511 case V_0280A0_COLOR_5_6_5: 512 case V_0280A0_COLOR_1_5_5_5: 513 case V_0280A0_COLOR_4_4_4_4: 514 case V_0280A0_COLOR_16: 515 case V_0280A0_COLOR_8_8: 516 return ENDIAN_8IN16; 517 518 /* 32-bit buffers. */ 519 case V_0280A0_COLOR_8_8_8_8: 520 case V_0280A0_COLOR_2_10_10_10: 521 case V_0280A0_COLOR_8_24: 522 case V_0280A0_COLOR_24_8: 523 case V_0280A0_COLOR_32_FLOAT: 524 case V_0280A0_COLOR_16_16_FLOAT: 525 case V_0280A0_COLOR_16_16: 526 return ENDIAN_8IN32; 527 528 /* 64-bit buffers. */ 529 case V_0280A0_COLOR_16_16_16_16: 530 case V_0280A0_COLOR_16_16_16_16_FLOAT: 531 return ENDIAN_8IN16; 532 533 case V_0280A0_COLOR_32_32_FLOAT: 534 case V_0280A0_COLOR_32_32: 535 case V_0280A0_COLOR_X24_8_32_FLOAT: 536 return ENDIAN_8IN32; 537 538 /* 128-bit buffers. */ 539 case V_0280A0_COLOR_32_32_32_FLOAT: 540 case V_0280A0_COLOR_32_32_32_32_FLOAT: 541 case V_0280A0_COLOR_32_32_32_32: 542 return ENDIAN_8IN32; 543 default: 544 return ENDIAN_NONE; /* Unsupported. */ 545 } 546 } else { 547 return ENDIAN_NONE; 548 } 549} 550 551static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 552{ 553 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U; 554} 555 556static bool r600_is_colorbuffer_format_supported(enum pipe_format format) 557{ 558 return r600_translate_colorformat(format) != ~0U && 559 r600_translate_colorswap(format) != ~0U; 560} 561 562static bool r600_is_zs_format_supported(enum pipe_format format) 563{ 564 return r600_translate_dbformat(format) != ~0U; 565} 566 567boolean r600_is_format_supported(struct pipe_screen *screen, 568 enum pipe_format format, 569 enum pipe_texture_target target, 570 unsigned sample_count, 571 unsigned usage) 572{ 573 unsigned retval = 0; 574 575 if (target >= PIPE_MAX_TEXTURE_TYPES) { 576 R600_ERR("r600: unsupported texture type %d\n", target); 577 return FALSE; 578 } 579 580 if (!util_format_is_supported(format, usage)) 581 return FALSE; 582 583 /* Multisample */ 584 if (sample_count > 1) 585 return FALSE; 586 587 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 588 r600_is_sampler_format_supported(screen, format)) { 589 retval |= PIPE_BIND_SAMPLER_VIEW; 590 } 591 592 if ((usage & (PIPE_BIND_RENDER_TARGET | 593 PIPE_BIND_DISPLAY_TARGET | 594 PIPE_BIND_SCANOUT | 595 PIPE_BIND_SHARED)) && 596 r600_is_colorbuffer_format_supported(format)) { 597 retval |= usage & 598 (PIPE_BIND_RENDER_TARGET | 599 PIPE_BIND_DISPLAY_TARGET | 600 PIPE_BIND_SCANOUT | 601 PIPE_BIND_SHARED); 602 } 603 604 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 605 r600_is_zs_format_supported(format)) { 606 retval |= PIPE_BIND_DEPTH_STENCIL; 607 } 608 609 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 610 r600_is_vertex_format_supported(format)) { 611 retval |= PIPE_BIND_VERTEX_BUFFER; 612 } 613 614 if (usage & PIPE_BIND_TRANSFER_READ) 615 retval |= PIPE_BIND_TRANSFER_READ; 616 if (usage & PIPE_BIND_TRANSFER_WRITE) 617 retval |= PIPE_BIND_TRANSFER_WRITE; 618 619 return retval == usage; 620} 621 622void r600_polygon_offset_update(struct r600_context *rctx) 623{ 624 struct r600_pipe_state state; 625 626 state.id = R600_PIPE_STATE_POLYGON_OFFSET; 627 state.nregs = 0; 628 if (rctx->rasterizer && rctx->framebuffer.zsbuf) { 629 float offset_units = rctx->rasterizer->offset_units; 630 unsigned offset_db_fmt_cntl = 0, depth; 631 632 switch (rctx->framebuffer.zsbuf->format) { 633 case PIPE_FORMAT_Z24X8_UNORM: 634 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 635 depth = -24; 636 offset_units *= 2.0f; 637 break; 638 case PIPE_FORMAT_Z32_FLOAT: 639 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 640 depth = -23; 641 offset_units *= 1.0f; 642 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 643 break; 644 case PIPE_FORMAT_Z16_UNORM: 645 depth = -16; 646 offset_units *= 4.0f; 647 break; 648 default: 649 return; 650 } 651 /* XXX some of those reg can be computed with cso */ 652 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 653 r600_pipe_state_add_reg(&state, 654 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 655 fui(rctx->rasterizer->offset_scale)); 656 r600_pipe_state_add_reg(&state, 657 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 658 fui(offset_units)); 659 r600_pipe_state_add_reg(&state, 660 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 661 fui(rctx->rasterizer->offset_scale)); 662 r600_pipe_state_add_reg(&state, 663 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 664 fui(offset_units)); 665 r600_pipe_state_add_reg(&state, 666 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 667 offset_db_fmt_cntl); 668 r600_context_pipe_state_set(rctx, &state); 669 } 670} 671 672static void *r600_create_blend_state(struct pipe_context *ctx, 673 const struct pipe_blend_state *state) 674{ 675 struct r600_context *rctx = (struct r600_context *)ctx; 676 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); 677 struct r600_pipe_state *rstate; 678 uint32_t color_control = 0, target_mask; 679 680 if (blend == NULL) { 681 return NULL; 682 } 683 rstate = &blend->rstate; 684 685 rstate->id = R600_PIPE_STATE_BLEND; 686 687 target_mask = 0; 688 689 /* R600 does not support per-MRT blends */ 690 if (rctx->family > CHIP_R600) 691 color_control |= S_028808_PER_MRT_BLEND(1); 692 if (state->logicop_enable) { 693 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 694 } else { 695 color_control |= (0xcc << 16); 696 } 697 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 698 if (state->independent_blend_enable) { 699 for (int i = 0; i < 8; i++) { 700 if (state->rt[i].blend_enable) { 701 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 702 } 703 target_mask |= (state->rt[i].colormask << (4 * i)); 704 } 705 } else { 706 for (int i = 0; i < 8; i++) { 707 if (state->rt[0].blend_enable) { 708 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 709 } 710 target_mask |= (state->rt[0].colormask << (4 * i)); 711 } 712 } 713 714 if (target_mask) 715 color_control |= S_028808_SPECIAL_OP(V_028808_NORMAL); 716 else 717 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE); 718 719 blend->cb_target_mask = target_mask; 720 blend->cb_color_control = color_control; 721 /* only MRT0 has dual src blend */ 722 blend->dual_src_blend = util_blend_state_is_dual(state, 0); 723 for (int i = 0; i < 8; i++) { 724 /* state->rt entries > 0 only written if independent blending */ 725 const int j = state->independent_blend_enable ? i : 0; 726 727 unsigned eqRGB = state->rt[j].rgb_func; 728 unsigned srcRGB = state->rt[j].rgb_src_factor; 729 unsigned dstRGB = state->rt[j].rgb_dst_factor; 730 731 unsigned eqA = state->rt[j].alpha_func; 732 unsigned srcA = state->rt[j].alpha_src_factor; 733 unsigned dstA = state->rt[j].alpha_dst_factor; 734 uint32_t bc = 0; 735 736 if (!state->rt[j].blend_enable) 737 continue; 738 739 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 740 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 741 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 742 743 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 744 bc |= S_028804_SEPARATE_ALPHA_BLEND(1); 745 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 746 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 747 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 748 } 749 750 /* R600 does not support per-MRT blends */ 751 if (rctx->family > CHIP_R600) 752 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc); 753 if (i == 0) 754 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc); 755 } 756 return rstate; 757} 758 759static void *r600_create_dsa_state(struct pipe_context *ctx, 760 const struct pipe_depth_stencil_alpha_state *state) 761{ 762 struct r600_context *rctx = (struct r600_context *)ctx; 763 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa); 764 unsigned db_depth_control, alpha_test_control, alpha_ref; 765 struct r600_pipe_state *rstate; 766 767 if (dsa == NULL) { 768 return NULL; 769 } 770 771 dsa->valuemask[0] = state->stencil[0].valuemask; 772 dsa->valuemask[1] = state->stencil[1].valuemask; 773 dsa->writemask[0] = state->stencil[0].writemask; 774 dsa->writemask[1] = state->stencil[1].writemask; 775 776 rstate = &dsa->rstate; 777 778 rstate->id = R600_PIPE_STATE_DSA; 779 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 780 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 781 S_028800_ZFUNC(state->depth.func); 782 783 /* stencil */ 784 if (state->stencil[0].enabled) { 785 db_depth_control |= S_028800_STENCIL_ENABLE(1); 786 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ 787 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 788 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 789 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 790 791 if (state->stencil[1].enabled) { 792 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 793 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ 794 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 795 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 796 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 797 } 798 } 799 800 /* alpha */ 801 alpha_test_control = 0; 802 alpha_ref = 0; 803 if (state->alpha.enabled) { 804 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 805 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 806 alpha_ref = fui(state->alpha.ref_value); 807 } 808 dsa->sx_alpha_test_control = alpha_test_control & 0xff; 809 dsa->alpha_ref = alpha_ref; 810 811 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control); 812 return rstate; 813} 814 815static void *r600_create_rs_state(struct pipe_context *ctx, 816 const struct pipe_rasterizer_state *state) 817{ 818 struct r600_context *rctx = (struct r600_context *)ctx; 819 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); 820 struct r600_pipe_state *rstate; 821 unsigned tmp; 822 unsigned prov_vtx = 1, polygon_dual_mode; 823 unsigned sc_mode_cntl; 824 float psize_min, psize_max; 825 826 if (rs == NULL) { 827 return NULL; 828 } 829 830 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 831 state->fill_back != PIPE_POLYGON_MODE_FILL); 832 833 if (state->flatshade_first) 834 prov_vtx = 0; 835 836 rstate = &rs->rstate; 837 rs->flatshade = state->flatshade; 838 rs->sprite_coord_enable = state->sprite_coord_enable; 839 rs->two_side = state->light_twoside; 840 rs->clip_plane_enable = state->clip_plane_enable; 841 rs->pa_sc_line_stipple = state->line_stipple_enable ? 842 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 843 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 844 rs->pa_cl_clip_cntl = 845 S_028810_PS_UCP_MODE(3) | 846 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 847 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 848 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 849 850 /* offset */ 851 rs->offset_units = state->offset_units; 852 rs->offset_scale = state->offset_scale * 12.0f; 853 854 rstate->id = R600_PIPE_STATE_RASTERIZER; 855 tmp = S_0286D4_FLAT_SHADE_ENA(1); 856 if (state->sprite_coord_enable) { 857 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 858 S_0286D4_PNT_SPRITE_OVRD_X(2) | 859 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 860 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 861 S_0286D4_PNT_SPRITE_OVRD_W(1); 862 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 863 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 864 } 865 } 866 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp); 867 868 /* point size 12.4 fixed point */ 869 tmp = r600_pack_float_12p4(state->point_size/2); 870 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 871 872 if (state->point_size_per_vertex) { 873 psize_min = util_get_min_point_size(state); 874 psize_max = 8192; 875 } else { 876 /* Force the point size to be as if the vertex output was disabled. */ 877 psize_min = state->point_size; 878 psize_max = state->point_size; 879 } 880 /* Divide by two, because 0.5 = 1 pixel. */ 881 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 882 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 883 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); 884 885 tmp = r600_pack_float_12p4(state->line_width/2); 886 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 887 888 if (rctx->chip_class >= R700) { 889 sc_mode_cntl = 890 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | 891 S_028A4C_FORCE_EOV_REZ_ENABLE(1) | 892 S_028A4C_R700_ZMM_LINE_OFFSET(1) | 893 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor); 894 } else { 895 sc_mode_cntl = 896 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | 897 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1); 898 rs->scissor_enable = state->scissor; 899 } 900 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable); 901 902 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl); 903 904 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 905 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules)); 906 907 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 908 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL, 909 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 910 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) | 911 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) | 912 S_028814_FACE(!state->front_ccw) | 913 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 914 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 915 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 916 S_028814_POLY_MODE(polygon_dual_mode) | 917 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 918 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back))); 919 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard)); 920 return rstate; 921} 922 923static void *r600_create_sampler_state(struct pipe_context *ctx, 924 const struct pipe_sampler_state *state) 925{ 926 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); 927 union util_color uc; 928 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0; 929 930 if (ss == NULL) { 931 return NULL; 932 } 933 934 ss->seamless_cube_map = state->seamless_cube_map; 935 ss->border_color_use = false; 936 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 937 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */ 938 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 939 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 940 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 941 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) | 942 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) | 943 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 944 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) | 945 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 946 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0); 947 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */ 948 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | 949 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | 950 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)); 951 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */ 952 ss->tex_sampler_words[2] = S_03C008_TYPE(1); 953 if (uc.ui) { 954 ss->border_color_use = true; 955 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */ 956 ss->border_color[0] = fui(state->border_color.f[0]); 957 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */ 958 ss->border_color[1] = fui(state->border_color.f[1]); 959 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */ 960 ss->border_color[2] = fui(state->border_color.f[2]); 961 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */ 962 ss->border_color[3] = fui(state->border_color.f[3]); 963 } 964 return ss; 965} 966 967static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx, 968 struct pipe_resource *texture, 969 const struct pipe_sampler_view *state) 970{ 971 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); 972 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; 973 unsigned format, endian; 974 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 975 unsigned char swizzle[4], array_mode = 0, tile_type = 0; 976 unsigned width, height, depth, offset_level, last_level; 977 978 if (view == NULL) 979 return NULL; 980 981 /* initialize base object */ 982 view->base = *state; 983 view->base.texture = NULL; 984 pipe_reference(NULL, &texture->reference); 985 view->base.texture = texture; 986 view->base.reference.count = 1; 987 view->base.context = ctx; 988 989 swizzle[0] = state->swizzle_r; 990 swizzle[1] = state->swizzle_g; 991 swizzle[2] = state->swizzle_b; 992 swizzle[3] = state->swizzle_a; 993 994 format = r600_translate_texformat(ctx->screen, state->format, 995 swizzle, 996 &word4, &yuv_format); 997 assert(format != ~0); 998 if (format == ~0) { 999 FREE(view); 1000 return NULL; 1001 } 1002 1003 if (tmp->is_depth && !tmp->is_flushing_texture) { 1004 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) { 1005 FREE(view); 1006 return NULL; 1007 } 1008 tmp = tmp->flushed_depth_texture; 1009 } 1010 1011 endian = r600_colorformat_endian_swap(format); 1012 1013 offset_level = state->u.tex.first_level; 1014 last_level = state->u.tex.last_level - offset_level; 1015 width = tmp->surface.level[offset_level].npix_x; 1016 height = tmp->surface.level[offset_level].npix_y; 1017 depth = tmp->surface.level[offset_level].npix_z; 1018 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); 1019 tile_type = tmp->tile_type; 1020 1021 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 1022 height = 1; 1023 depth = texture->array_size; 1024 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 1025 depth = texture->array_size; 1026 } 1027 switch (tmp->surface.level[offset_level].mode) { 1028 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1029 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; 1030 break; 1031 case RADEON_SURF_MODE_1D: 1032 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 1033 break; 1034 case RADEON_SURF_MODE_2D: 1035 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 1036 break; 1037 case RADEON_SURF_MODE_LINEAR: 1038 default: 1039 array_mode = V_038000_ARRAY_LINEAR_GENERAL; 1040 break; 1041 } 1042 1043 view->tex_resource = &tmp->resource; 1044 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) | 1045 S_038000_TILE_MODE(array_mode) | 1046 S_038000_TILE_TYPE(tile_type) | 1047 S_038000_PITCH((pitch / 8) - 1) | 1048 S_038000_TEX_WIDTH(width - 1)); 1049 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) | 1050 S_038004_TEX_DEPTH(depth - 1) | 1051 S_038004_DATA_FORMAT(format)); 1052 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8; 1053 if (offset_level >= tmp->surface.last_level) { 1054 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8; 1055 } else { 1056 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8; 1057 } 1058 view->tex_resource_words[4] = (word4 | 1059 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) | 1060 S_038010_REQUEST_SIZE(1) | 1061 S_038010_ENDIAN_SWAP(endian) | 1062 S_038010_BASE_LEVEL(0)); 1063 view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) | 1064 S_038014_BASE_ARRAY(state->u.tex.first_layer) | 1065 S_038014_LAST_ARRAY(state->u.tex.last_layer)); 1066 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | 1067 S_038018_MAX_ANISO(4 /* max 16 samples */)); 1068 return &view->base; 1069} 1070 1071static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count, 1072 struct pipe_sampler_view **views) 1073{ 1074 struct r600_context *rctx = (struct r600_context *)ctx; 1075 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views); 1076} 1077 1078static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count, 1079 struct pipe_sampler_view **views) 1080{ 1081 struct r600_context *rctx = (struct r600_context *)ctx; 1082 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views); 1083} 1084 1085static void r600_set_clip_state(struct pipe_context *ctx, 1086 const struct pipe_clip_state *state) 1087{ 1088 struct r600_context *rctx = (struct r600_context *)ctx; 1089 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1090 struct pipe_constant_buffer cb; 1091 1092 if (rstate == NULL) 1093 return; 1094 1095 rctx->clip = *state; 1096 rstate->id = R600_PIPE_STATE_CLIP; 1097 for (int i = 0; i < 6; i++) { 1098 r600_pipe_state_add_reg(rstate, 1099 R_028E20_PA_CL_UCP0_X + i * 16, 1100 fui(state->ucp[i][0])); 1101 r600_pipe_state_add_reg(rstate, 1102 R_028E24_PA_CL_UCP0_Y + i * 16, 1103 fui(state->ucp[i][1]) ); 1104 r600_pipe_state_add_reg(rstate, 1105 R_028E28_PA_CL_UCP0_Z + i * 16, 1106 fui(state->ucp[i][2])); 1107 r600_pipe_state_add_reg(rstate, 1108 R_028E2C_PA_CL_UCP0_W + i * 16, 1109 fui(state->ucp[i][3])); 1110 } 1111 1112 free(rctx->states[R600_PIPE_STATE_CLIP]); 1113 rctx->states[R600_PIPE_STATE_CLIP] = rstate; 1114 r600_context_pipe_state_set(rctx, rstate); 1115 1116 cb.buffer = NULL; 1117 cb.user_buffer = state->ucp; 1118 cb.buffer_offset = 0; 1119 cb.buffer_size = 4*4*8; 1120 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb); 1121 pipe_resource_reference(&cb.buffer, NULL); 1122} 1123 1124static void r600_set_polygon_stipple(struct pipe_context *ctx, 1125 const struct pipe_poly_stipple *state) 1126{ 1127} 1128 1129static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 1130{ 1131} 1132 1133void r600_set_scissor_state(struct r600_context *rctx, 1134 const struct pipe_scissor_state *state) 1135{ 1136 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1137 uint32_t tl, br; 1138 1139 if (rstate == NULL) 1140 return; 1141 1142 rstate->id = R600_PIPE_STATE_SCISSOR; 1143 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); 1144 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 1145 r600_pipe_state_add_reg(rstate, 1146 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl); 1147 r600_pipe_state_add_reg(rstate, 1148 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br); 1149 1150 free(rctx->states[R600_PIPE_STATE_SCISSOR]); 1151 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate; 1152 r600_context_pipe_state_set(rctx, rstate); 1153} 1154 1155static void r600_pipe_set_scissor_state(struct pipe_context *ctx, 1156 const struct pipe_scissor_state *state) 1157{ 1158 struct r600_context *rctx = (struct r600_context *)ctx; 1159 1160 if (rctx->chip_class == R600) { 1161 rctx->scissor_state = *state; 1162 1163 if (!rctx->scissor_enable) 1164 return; 1165 } 1166 1167 r600_set_scissor_state(rctx, state); 1168} 1169 1170static void r600_set_viewport_state(struct pipe_context *ctx, 1171 const struct pipe_viewport_state *state) 1172{ 1173 struct r600_context *rctx = (struct r600_context *)ctx; 1174 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1175 1176 if (rstate == NULL) 1177 return; 1178 1179 rctx->viewport = *state; 1180 rstate->id = R600_PIPE_STATE_VIEWPORT; 1181 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); 1182 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); 1183 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); 1184 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); 1185 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); 1186 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); 1187 1188 free(rctx->states[R600_PIPE_STATE_VIEWPORT]); 1189 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate; 1190 r600_context_pipe_state_set(rctx, rstate); 1191} 1192 1193static void r600_init_color_surface(struct r600_context *rctx, 1194 struct r600_surface *surf) 1195{ 1196 struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture; 1197 unsigned level = surf->base.u.tex.level; 1198 unsigned pitch, slice; 1199 unsigned color_info; 1200 unsigned format, swap, ntype, endian; 1201 unsigned offset; 1202 const struct util_format_description *desc; 1203 int i; 1204 bool blend_bypass = 0, blend_clamp = 1; 1205 1206 if (rtex->is_depth && !rtex->is_flushing_texture) { 1207 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL); 1208 rtex = rtex->flushed_depth_texture; 1209 assert(rtex); 1210 } 1211 1212 offset = rtex->surface.level[level].offset; 1213 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1214 offset += rtex->surface.level[level].slice_size * 1215 surf->base.u.tex.first_layer; 1216 } 1217 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1218 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1219 if (slice) { 1220 slice = slice - 1; 1221 } 1222 color_info = 0; 1223 switch (rtex->surface.level[level].mode) { 1224 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1225 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED); 1226 break; 1227 case RADEON_SURF_MODE_1D: 1228 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1229 break; 1230 case RADEON_SURF_MODE_2D: 1231 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1232 break; 1233 case RADEON_SURF_MODE_LINEAR: 1234 default: 1235 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL); 1236 break; 1237 } 1238 1239 desc = util_format_description(surf->base.format); 1240 1241 for (i = 0; i < 4; i++) { 1242 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1243 break; 1244 } 1245 } 1246 1247 ntype = V_0280A0_NUMBER_UNORM; 1248 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1249 ntype = V_0280A0_NUMBER_SRGB; 1250 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1251 if (desc->channel[i].normalized) 1252 ntype = V_0280A0_NUMBER_SNORM; 1253 else if (desc->channel[i].pure_integer) 1254 ntype = V_0280A0_NUMBER_SINT; 1255 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1256 if (desc->channel[i].normalized) 1257 ntype = V_0280A0_NUMBER_UNORM; 1258 else if (desc->channel[i].pure_integer) 1259 ntype = V_0280A0_NUMBER_UINT; 1260 } 1261 1262 format = r600_translate_colorformat(surf->base.format); 1263 assert(format != ~0); 1264 1265 swap = r600_translate_colorswap(surf->base.format); 1266 assert(swap != ~0); 1267 1268 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { 1269 endian = ENDIAN_NONE; 1270 } else { 1271 endian = r600_colorformat_endian_swap(format); 1272 } 1273 1274 /* set blend bypass according to docs if SINT/UINT or 1275 8/24 COLOR variants */ 1276 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT || 1277 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 || 1278 format == V_0280A0_COLOR_X24_8_32_FLOAT) { 1279 blend_clamp = 0; 1280 blend_bypass = 1; 1281 } 1282 1283 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT; 1284 1285 color_info |= S_0280A0_FORMAT(format) | 1286 S_0280A0_COMP_SWAP(swap) | 1287 S_0280A0_BLEND_BYPASS(blend_bypass) | 1288 S_0280A0_BLEND_CLAMP(blend_clamp) | 1289 S_0280A0_NUMBER_TYPE(ntype) | 1290 S_0280A0_ENDIAN(endian); 1291 1292 /* EXPORT_NORM is an optimzation that can be enabled for better 1293 * performance in certain cases 1294 */ 1295 if (rctx->chip_class == R600) { 1296 /* EXPORT_NORM can be enabled if: 1297 * - 11-bit or smaller UNORM/SNORM/SRGB 1298 * - BLEND_CLAMP is enabled 1299 * - BLEND_FLOAT32 is disabled 1300 */ 1301 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1302 (desc->channel[i].size < 12 && 1303 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1304 ntype != V_0280A0_NUMBER_UINT && 1305 ntype != V_0280A0_NUMBER_SINT) && 1306 G_0280A0_BLEND_CLAMP(color_info) && 1307 !G_0280A0_BLEND_FLOAT32(color_info)) { 1308 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1309 surf->export_16bpc = true; 1310 } 1311 } else { 1312 /* EXPORT_NORM can be enabled if: 1313 * - 11-bit or smaller UNORM/SNORM/SRGB 1314 * - 16-bit or smaller FLOAT 1315 */ 1316 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1317 ((desc->channel[i].size < 12 && 1318 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1319 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) || 1320 (desc->channel[i].size < 17 && 1321 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) { 1322 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1323 surf->export_16bpc = true; 1324 } 1325 } 1326 1327 surf->cb_color_base = offset >> 8; 1328 surf->cb_color_info = color_info; 1329 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) | 1330 S_028060_SLICE_TILE_MAX(slice); 1331 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1332 surf->cb_color_view = 0; 1333 } else { 1334 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | 1335 S_028080_SLICE_MAX(surf->base.u.tex.last_layer); 1336 } 1337 1338 surf->color_initialized = true; 1339} 1340 1341static void r600_init_depth_surface(struct r600_context *rctx, 1342 struct r600_surface *surf) 1343{ 1344 struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture; 1345 unsigned level, pitch, slice, format, offset, array_mode; 1346 1347 level = surf->base.u.tex.level; 1348 offset = rtex->surface.level[level].offset; 1349 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1350 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1351 if (slice) { 1352 slice = slice - 1; 1353 } 1354 switch (rtex->surface.level[level].mode) { 1355 case RADEON_SURF_MODE_2D: 1356 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 1357 break; 1358 case RADEON_SURF_MODE_1D: 1359 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1360 case RADEON_SURF_MODE_LINEAR: 1361 default: 1362 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 1363 break; 1364 } 1365 1366 format = r600_translate_dbformat(surf->base.format); 1367 assert(format != ~0); 1368 1369 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); 1370 surf->db_depth_base = offset >> 8; 1371 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) | 1372 S_028004_SLICE_MAX(surf->base.u.tex.last_layer); 1373 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice); 1374 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1; 1375 1376 surf->depth_initialized = true; 1377} 1378 1379static void r600_set_framebuffer_state(struct pipe_context *ctx, 1380 const struct pipe_framebuffer_state *state) 1381{ 1382 struct r600_context *rctx = (struct r600_context *)ctx; 1383 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1384 struct r600_surface *surf; 1385 struct r600_resource *res; 1386 uint32_t tl, br, i; 1387 1388 if (rstate == NULL) 1389 return; 1390 1391 r600_flush_framebuffer(rctx, false); 1392 1393 /* unreference old buffer and reference new one */ 1394 rstate->id = R600_PIPE_STATE_FRAMEBUFFER; 1395 1396 util_copy_framebuffer_state(&rctx->framebuffer, state); 1397 1398 /* build states */ 1399 rctx->export_16bpc = true; 1400 rctx->nr_cbufs = state->nr_cbufs; 1401 1402 for (i = 0; i < state->nr_cbufs; i++) { 1403 surf = (struct r600_surface*)state->cbufs[i]; 1404 res = (struct r600_resource*)surf->base.texture; 1405 1406 if (!surf->color_initialized) { 1407 r600_init_color_surface(rctx, surf); 1408 } 1409 1410 if (!surf->export_16bpc) { 1411 rctx->export_16bpc = false; 1412 } 1413 1414 r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4, 1415 surf->cb_color_base, res, RADEON_USAGE_READWRITE); 1416 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 1417 surf->cb_color_info, res, RADEON_USAGE_READWRITE); 1418 r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4, 1419 surf->cb_color_size); 1420 r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4, 1421 surf->cb_color_view); 1422 r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4, 1423 surf->cb_color_frag, res, RADEON_USAGE_READWRITE); 1424 r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4, 1425 surf->cb_color_tile, res, RADEON_USAGE_READWRITE); 1426 } 1427 /* set CB_COLOR1_INFO for possible dual-src blending */ 1428 if (i == 1) { 1429 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4, 1430 surf->cb_color_info, res, RADEON_USAGE_READWRITE); 1431 i++; 1432 } 1433 1434 /* Update alpha-test state dependencies. 1435 * Alpha-test is done on the first colorbuffer only. */ 1436 if (state->nr_cbufs) { 1437 surf = (struct r600_surface*)state->cbufs[0]; 1438 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) { 1439 rctx->alphatest_state.bypass = surf->alphatest_bypass; 1440 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 1441 } 1442 } 1443 1444 if (state->zsbuf) { 1445 surf = (struct r600_surface*)state->zsbuf; 1446 res = (struct r600_resource*)surf->base.texture; 1447 1448 if (!surf->depth_initialized) { 1449 r600_init_depth_surface(rctx, surf); 1450 } 1451 1452 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base, 1453 res, RADEON_USAGE_READWRITE); 1454 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size); 1455 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view); 1456 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info, 1457 res, RADEON_USAGE_READWRITE); 1458 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit); 1459 } 1460 1461 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1); 1462 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height); 1463 1464 r600_pipe_state_add_reg(rstate, 1465 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl); 1466 r600_pipe_state_add_reg(rstate, 1467 R_028208_PA_SC_WINDOW_SCISSOR_BR, br); 1468 1469 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This 1470 * will assure that the alpha-test will work even if there is 1471 * no colorbuffer bound. */ 1472 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1473 (1ull << MAX2(state->nr_cbufs, 1)) - 1); 1474 1475 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) { 1476 rctx->alphatest_state.bypass = false; 1477 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 1478 } 1479 1480 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); 1481 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; 1482 r600_context_pipe_state_set(rctx, rstate); 1483 1484 if (state->zsbuf) { 1485 r600_polygon_offset_update(rctx); 1486 } 1487 1488 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) { 1489 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs; 1490 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 1491 } 1492} 1493 1494static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) 1495{ 1496 struct radeon_winsys_cs *cs = rctx->cs; 1497 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; 1498 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1; 1499 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1; 1500 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1; 1501 1502 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); 1503 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */ 1504 r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */ 1505 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, 1506 a->cb_color_control | 1507 S_028808_MULTIWRITE_ENABLE(multiwrite)); 1508} 1509 1510static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) 1511{ 1512 struct radeon_winsys_cs *cs = rctx->cs; 1513 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; 1514 unsigned db_render_control = 0; 1515 unsigned db_render_override = 1516 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) | 1517 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | 1518 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); 1519 1520 if (a->occlusion_query_enabled) { 1521 if (rctx->chip_class >= R700) { 1522 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); 1523 } 1524 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); 1525 } 1526 if (a->flush_depthstencil_through_cb) { 1527 assert(a->copy_depth || a->copy_stencil); 1528 1529 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) | 1530 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) | 1531 S_028D0C_COPY_CENTROID(1); 1532 } 1533 1534 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2); 1535 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */ 1536 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */ 1537} 1538 1539static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom) 1540{ 1541 struct radeon_winsys_cs *cs = rctx->cs; 1542 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask; 1543 1544 while (dirty_mask) { 1545 struct pipe_vertex_buffer *vb; 1546 struct r600_resource *rbuffer; 1547 unsigned offset; 1548 unsigned buffer_index = u_bit_scan(&dirty_mask); 1549 1550 vb = &rctx->vertex_buffer_state.vb[buffer_index]; 1551 rbuffer = (struct r600_resource*)vb->buffer; 1552 assert(rbuffer); 1553 1554 offset = vb->buffer_offset; 1555 1556 /* fetch resources start at index 320 */ 1557 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1558 r600_write_value(cs, (320 + buffer_index) * 7); 1559 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */ 1560 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */ 1561 r600_write_value(cs, /* RESOURCEi_WORD2 */ 1562 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 1563 S_038008_STRIDE(vb->stride)); 1564 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */ 1565 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */ 1566 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */ 1567 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */ 1568 1569 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1570 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ)); 1571 } 1572} 1573 1574static void r600_emit_constant_buffers(struct r600_context *rctx, 1575 struct r600_constbuf_state *state, 1576 unsigned buffer_id_base, 1577 unsigned reg_alu_constbuf_size, 1578 unsigned reg_alu_const_cache) 1579{ 1580 struct radeon_winsys_cs *cs = rctx->cs; 1581 uint32_t dirty_mask = state->dirty_mask; 1582 1583 while (dirty_mask) { 1584 struct pipe_constant_buffer *cb; 1585 struct r600_resource *rbuffer; 1586 unsigned offset; 1587 unsigned buffer_index = ffs(dirty_mask) - 1; 1588 1589 cb = &state->cb[buffer_index]; 1590 rbuffer = (struct r600_resource*)cb->buffer; 1591 assert(rbuffer); 1592 1593 offset = cb->buffer_offset; 1594 1595 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4, 1596 ALIGN_DIVUP(cb->buffer_size >> 4, 16)); 1597 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8); 1598 1599 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1600 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ)); 1601 1602 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1603 r600_write_value(cs, (buffer_id_base + buffer_index) * 7); 1604 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */ 1605 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */ 1606 r600_write_value(cs, /* RESOURCEi_WORD2 */ 1607 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 1608 S_038008_STRIDE(16)); 1609 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */ 1610 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */ 1611 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */ 1612 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */ 1613 1614 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1615 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ)); 1616 1617 dirty_mask &= ~(1 << buffer_index); 1618 } 1619 state->dirty_mask = 0; 1620} 1621 1622static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 1623{ 1624 r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160, 1625 R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 1626 R_028980_ALU_CONST_CACHE_VS_0); 1627} 1628 1629static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 1630{ 1631 r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0, 1632 R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 1633 R_028940_ALU_CONST_CACHE_PS_0); 1634} 1635 1636static void r600_emit_sampler_views(struct r600_context *rctx, 1637 struct r600_samplerview_state *state, 1638 unsigned resource_id_base) 1639{ 1640 struct radeon_winsys_cs *cs = rctx->cs; 1641 uint32_t dirty_mask = state->dirty_mask; 1642 1643 while (dirty_mask) { 1644 struct r600_pipe_sampler_view *rview; 1645 unsigned resource_index = u_bit_scan(&dirty_mask); 1646 unsigned reloc; 1647 1648 rview = state->views[resource_index]; 1649 assert(rview); 1650 1651 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1652 r600_write_value(cs, (resource_id_base + resource_index) * 7); 1653 r600_write_array(cs, 7, rview->tex_resource_words); 1654 1655 /* XXX The kernel needs two relocations. This is stupid. */ 1656 reloc = r600_context_bo_reloc(rctx, rview->tex_resource, 1657 RADEON_USAGE_READ); 1658 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1659 r600_write_value(cs, reloc); 1660 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1661 r600_write_value(cs, reloc); 1662 } 1663 state->dirty_mask = 0; 1664} 1665 1666static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 1667{ 1668 r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS); 1669} 1670 1671static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 1672{ 1673 r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS); 1674} 1675 1676static void r600_emit_sampler(struct r600_context *rctx, 1677 struct r600_textures_info *texinfo, 1678 unsigned resource_id_base, 1679 unsigned border_color_reg) 1680{ 1681 struct radeon_winsys_cs *cs = rctx->cs; 1682 unsigned i; 1683 1684 for (i = 0; i < texinfo->n_samplers; i++) { 1685 1686 if (texinfo->samplers[i] == NULL) { 1687 continue; 1688 } 1689 1690 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable 1691 * filtering between layers. 1692 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. 1693 */ 1694 if (texinfo->views.views[i]) { 1695 if (texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 1696 texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) { 1697 texinfo->samplers[i]->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1); 1698 texinfo->is_array_sampler[i] = true; 1699 } else { 1700 texinfo->samplers[i]->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE; 1701 texinfo->is_array_sampler[i] = false; 1702 } 1703 } 1704 1705 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0)); 1706 r600_write_value(cs, (resource_id_base + i) * 3); 1707 r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words); 1708 1709 if (texinfo->samplers[i]->border_color_use) { 1710 unsigned offset; 1711 1712 offset = border_color_reg; 1713 offset += i * 16; 1714 r600_write_config_reg_seq(cs, offset, 4); 1715 r600_write_array(cs, 4, texinfo->samplers[i]->border_color); 1716 } 1717 } 1718} 1719 1720static void r600_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom) 1721{ 1722 r600_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED); 1723} 1724 1725static void r600_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom) 1726{ 1727 r600_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED); 1728} 1729 1730static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom) 1731{ 1732 struct radeon_winsys_cs *cs = rctx->cs; 1733 unsigned tmp; 1734 1735 tmp = S_009508_DISABLE_CUBE_ANISO(1) | 1736 S_009508_SYNC_GRADIENT(1) | 1737 S_009508_SYNC_WALKER(1) | 1738 S_009508_SYNC_ALIGNER(1); 1739 if (!rctx->seamless_cube_map.enabled) { 1740 tmp |= S_009508_DISABLE_CUBE_WRAP(1); 1741 } 1742 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp); 1743} 1744 1745void r600_init_state_functions(struct r600_context *rctx) 1746{ 1747 r600_init_atom(&rctx->seamless_cube_map.atom, r600_emit_seamless_cube_map, 3, 0); 1748 r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom); 1749 r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0); 1750 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 1751 r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0); 1752 r600_atom_dirty(rctx, &rctx->db_misc_state.atom); 1753 r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0); 1754 r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0); 1755 r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0); 1756 r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0); 1757 r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0); 1758 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change 1759 * does not take effect 1760 */ 1761 r600_init_atom(&rctx->vs_samplers.atom_sampler, r600_emit_vs_sampler, 0, EMIT_EARLY); 1762 r600_init_atom(&rctx->ps_samplers.atom_sampler, r600_emit_ps_sampler, 0, EMIT_EARLY); 1763 1764 rctx->context.create_blend_state = r600_create_blend_state; 1765 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; 1766 rctx->context.create_fs_state = r600_create_shader_state_ps; 1767 rctx->context.create_rasterizer_state = r600_create_rs_state; 1768 rctx->context.create_sampler_state = r600_create_sampler_state; 1769 rctx->context.create_sampler_view = r600_create_sampler_view; 1770 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 1771 rctx->context.create_vs_state = r600_create_shader_state_vs; 1772 rctx->context.bind_blend_state = r600_bind_blend_state; 1773 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; 1774 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers; 1775 rctx->context.bind_fs_state = r600_bind_ps_shader; 1776 rctx->context.bind_rasterizer_state = r600_bind_rs_state; 1777 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 1778 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers; 1779 rctx->context.bind_vs_state = r600_bind_vs_shader; 1780 rctx->context.delete_blend_state = r600_delete_state; 1781 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 1782 rctx->context.delete_fs_state = r600_delete_ps_shader; 1783 rctx->context.delete_rasterizer_state = r600_delete_rs_state; 1784 rctx->context.delete_sampler_state = r600_delete_sampler; 1785 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 1786 rctx->context.delete_vs_state = r600_delete_vs_shader; 1787 rctx->context.set_blend_color = r600_set_blend_color; 1788 rctx->context.set_clip_state = r600_set_clip_state; 1789 rctx->context.set_constant_buffer = r600_set_constant_buffer; 1790 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views; 1791 rctx->context.set_framebuffer_state = r600_set_framebuffer_state; 1792 rctx->context.set_polygon_stipple = r600_set_polygon_stipple; 1793 rctx->context.set_sample_mask = r600_set_sample_mask; 1794 rctx->context.set_scissor_state = r600_pipe_set_scissor_state; 1795 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref; 1796 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 1797 rctx->context.set_index_buffer = r600_set_index_buffer; 1798 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views; 1799 rctx->context.set_viewport_state = r600_set_viewport_state; 1800 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 1801 rctx->context.texture_barrier = r600_texture_barrier; 1802 rctx->context.create_stream_output_target = r600_create_so_target; 1803 rctx->context.stream_output_target_destroy = r600_so_target_destroy; 1804 rctx->context.set_stream_output_targets = r600_set_so_targets; 1805} 1806 1807/* Adjust GPR allocation on R6xx/R7xx */ 1808void r600_adjust_gprs(struct r600_context *rctx) 1809{ 1810 struct r600_pipe_state rstate; 1811 unsigned num_ps_gprs = rctx->default_ps_gprs; 1812 unsigned num_vs_gprs = rctx->default_vs_gprs; 1813 unsigned tmp; 1814 int diff; 1815 1816 /* XXX: Following call moved from r600_bind_[ps|vs]_shader, 1817 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for 1818 * adjusting the GPR allocation? 1819 * Do we need this if we aren't really changing config below? */ 1820 r600_inval_shader_cache(rctx); 1821 1822 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs) 1823 { 1824 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs; 1825 num_vs_gprs -= diff; 1826 num_ps_gprs += diff; 1827 } 1828 1829 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs) 1830 { 1831 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs; 1832 num_ps_gprs -= diff; 1833 num_vs_gprs += diff; 1834 } 1835 1836 tmp = 0; 1837 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs); 1838 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs); 1839 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs); 1840 rstate.nregs = 0; 1841 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp); 1842 1843 r600_context_pipe_state_set(rctx, &rstate); 1844} 1845 1846void r600_init_atom_start_cs(struct r600_context *rctx) 1847{ 1848 int ps_prio; 1849 int vs_prio; 1850 int gs_prio; 1851 int es_prio; 1852 int num_ps_gprs; 1853 int num_vs_gprs; 1854 int num_gs_gprs; 1855 int num_es_gprs; 1856 int num_temp_gprs; 1857 int num_ps_threads; 1858 int num_vs_threads; 1859 int num_gs_threads; 1860 int num_es_threads; 1861 int num_ps_stack_entries; 1862 int num_vs_stack_entries; 1863 int num_gs_stack_entries; 1864 int num_es_stack_entries; 1865 enum radeon_family family; 1866 struct r600_command_buffer *cb = &rctx->start_cs_cmd; 1867 uint32_t tmp; 1868 unsigned i; 1869 1870 r600_init_command_buffer(cb, 256, EMIT_EARLY); 1871 1872 /* R6xx requires this packet at the start of each command buffer */ 1873 if (rctx->chip_class == R600) { 1874 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0)); 1875 r600_store_value(cb, 0); 1876 } 1877 /* All asics require this one */ 1878 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); 1879 r600_store_value(cb, 0x80000000); 1880 r600_store_value(cb, 0x80000000); 1881 1882 family = rctx->family; 1883 ps_prio = 0; 1884 vs_prio = 1; 1885 gs_prio = 2; 1886 es_prio = 3; 1887 switch (family) { 1888 case CHIP_R600: 1889 num_ps_gprs = 192; 1890 num_vs_gprs = 56; 1891 num_temp_gprs = 4; 1892 num_gs_gprs = 0; 1893 num_es_gprs = 0; 1894 num_ps_threads = 136; 1895 num_vs_threads = 48; 1896 num_gs_threads = 4; 1897 num_es_threads = 4; 1898 num_ps_stack_entries = 128; 1899 num_vs_stack_entries = 128; 1900 num_gs_stack_entries = 0; 1901 num_es_stack_entries = 0; 1902 break; 1903 case CHIP_RV630: 1904 case CHIP_RV635: 1905 num_ps_gprs = 84; 1906 num_vs_gprs = 36; 1907 num_temp_gprs = 4; 1908 num_gs_gprs = 0; 1909 num_es_gprs = 0; 1910 num_ps_threads = 144; 1911 num_vs_threads = 40; 1912 num_gs_threads = 4; 1913 num_es_threads = 4; 1914 num_ps_stack_entries = 40; 1915 num_vs_stack_entries = 40; 1916 num_gs_stack_entries = 32; 1917 num_es_stack_entries = 16; 1918 break; 1919 case CHIP_RV610: 1920 case CHIP_RV620: 1921 case CHIP_RS780: 1922 case CHIP_RS880: 1923 default: 1924 num_ps_gprs = 84; 1925 num_vs_gprs = 36; 1926 num_temp_gprs = 4; 1927 num_gs_gprs = 0; 1928 num_es_gprs = 0; 1929 num_ps_threads = 136; 1930 num_vs_threads = 48; 1931 num_gs_threads = 4; 1932 num_es_threads = 4; 1933 num_ps_stack_entries = 40; 1934 num_vs_stack_entries = 40; 1935 num_gs_stack_entries = 32; 1936 num_es_stack_entries = 16; 1937 break; 1938 case CHIP_RV670: 1939 num_ps_gprs = 144; 1940 num_vs_gprs = 40; 1941 num_temp_gprs = 4; 1942 num_gs_gprs = 0; 1943 num_es_gprs = 0; 1944 num_ps_threads = 136; 1945 num_vs_threads = 48; 1946 num_gs_threads = 4; 1947 num_es_threads = 4; 1948 num_ps_stack_entries = 40; 1949 num_vs_stack_entries = 40; 1950 num_gs_stack_entries = 32; 1951 num_es_stack_entries = 16; 1952 break; 1953 case CHIP_RV770: 1954 num_ps_gprs = 192; 1955 num_vs_gprs = 56; 1956 num_temp_gprs = 4; 1957 num_gs_gprs = 0; 1958 num_es_gprs = 0; 1959 num_ps_threads = 188; 1960 num_vs_threads = 60; 1961 num_gs_threads = 0; 1962 num_es_threads = 0; 1963 num_ps_stack_entries = 256; 1964 num_vs_stack_entries = 256; 1965 num_gs_stack_entries = 0; 1966 num_es_stack_entries = 0; 1967 break; 1968 case CHIP_RV730: 1969 case CHIP_RV740: 1970 num_ps_gprs = 84; 1971 num_vs_gprs = 36; 1972 num_temp_gprs = 4; 1973 num_gs_gprs = 0; 1974 num_es_gprs = 0; 1975 num_ps_threads = 188; 1976 num_vs_threads = 60; 1977 num_gs_threads = 0; 1978 num_es_threads = 0; 1979 num_ps_stack_entries = 128; 1980 num_vs_stack_entries = 128; 1981 num_gs_stack_entries = 0; 1982 num_es_stack_entries = 0; 1983 break; 1984 case CHIP_RV710: 1985 num_ps_gprs = 192; 1986 num_vs_gprs = 56; 1987 num_temp_gprs = 4; 1988 num_gs_gprs = 0; 1989 num_es_gprs = 0; 1990 num_ps_threads = 144; 1991 num_vs_threads = 48; 1992 num_gs_threads = 0; 1993 num_es_threads = 0; 1994 num_ps_stack_entries = 128; 1995 num_vs_stack_entries = 128; 1996 num_gs_stack_entries = 0; 1997 num_es_stack_entries = 0; 1998 break; 1999 } 2000 2001 rctx->default_ps_gprs = num_ps_gprs; 2002 rctx->default_vs_gprs = num_vs_gprs; 2003 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs; 2004 2005 /* SQ_CONFIG */ 2006 tmp = 0; 2007 switch (family) { 2008 case CHIP_RV610: 2009 case CHIP_RV620: 2010 case CHIP_RS780: 2011 case CHIP_RS880: 2012 case CHIP_RV710: 2013 break; 2014 default: 2015 tmp |= S_008C00_VC_ENABLE(1); 2016 break; 2017 } 2018 tmp |= S_008C00_DX9_CONSTS(0); 2019 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); 2020 tmp |= S_008C00_PS_PRIO(ps_prio); 2021 tmp |= S_008C00_VS_PRIO(vs_prio); 2022 tmp |= S_008C00_GS_PRIO(gs_prio); 2023 tmp |= S_008C00_ES_PRIO(es_prio); 2024 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp); 2025 2026 /* SQ_GPR_RESOURCE_MGMT_2 */ 2027 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs); 2028 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); 2029 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4); 2030 r600_store_value(cb, tmp); 2031 2032 /* SQ_THREAD_RESOURCE_MGMT */ 2033 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads); 2034 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads); 2035 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads); 2036 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads); 2037 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */ 2038 2039 /* SQ_STACK_RESOURCE_MGMT_1 */ 2040 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 2041 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 2042 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */ 2043 2044 /* SQ_STACK_RESOURCE_MGMT_2 */ 2045 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 2046 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 2047 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */ 2048 2049 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0); 2050 2051 if (rctx->chip_class >= R700) { 2052 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000); 2053 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0); 2054 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204); 2055 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); 2056 } else { 2057 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2058 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000); 2059 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204); 2060 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1); 2061 } 2062 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9); 2063 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */ 2064 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */ 2065 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */ 2066 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */ 2067 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */ 2068 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */ 2069 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */ 2070 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */ 2071 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */ 2072 2073 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); 2074 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ 2075 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ 2076 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ 2077 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ 2078 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ 2079 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ 2080 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ 2081 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ 2082 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ 2083 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ 2084 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ 2085 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ 2086 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */ 2087 2088 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0); 2089 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0); 2090 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0); 2091 2092 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3); 2093 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */ 2094 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */ 2095 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ 2096 2097 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0); 2098 2099 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2); 2100 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */ 2101 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */ 2102 2103 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); 2104 2105 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2); 2106 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */ 2107 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */ 2108 2109 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3); 2110 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */ 2111 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */ 2112 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */ 2113 2114 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2); 2115 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */ 2116 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */ 2117 2118 r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00); 2119 2120 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); 2121 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0); 2122 2123 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2); 2124 r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */ 2125 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */ 2126 2127 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6); 2128 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */ 2129 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */ 2130 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */ 2131 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */ 2132 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ 2133 r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */ 2134 2135 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2); 2136 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */ 2137 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */ 2138 2139 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F); 2140 2141 r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8); 2142 for (i = 0; i < 8; i++) { 2143 r600_store_value(cb, 0); 2144 } 2145 2146 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); 2147 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 2148 2149 if (rctx->chip_class >= R700) { 2150 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 2151 } 2152 2153 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4); 2154 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */ 2155 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */ 2156 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */ 2157 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */ 2158 2159 r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF); 2160 2161 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); 2162 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ 2163 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ 2164 2165 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); 2166 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ 2167 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ 2168 2169 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2); 2170 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */ 2171 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */ 2172 2173 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0); 2174 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0); 2175 2176 if (rctx->chip_class == R700 && rctx->screen->has_streamout) 2177 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); 2178 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); 2179 if (rctx->screen->has_streamout) { 2180 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); 2181 } 2182 2183 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF); 2184 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF); 2185} 2186 2187void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2188{ 2189 struct r600_context *rctx = (struct r600_context *)ctx; 2190 struct r600_pipe_state *rstate = &shader->rstate; 2191 struct r600_shader *rshader = &shader->shader; 2192 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; 2193 int pos_index = -1, face_index = -1; 2194 unsigned tmp, sid, ufi = 0; 2195 int need_linear = 0; 2196 unsigned z_export = 0, stencil_export = 0; 2197 2198 rstate->nregs = 0; 2199 2200 for (i = 0; i < rshader->ninput; i++) { 2201 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) 2202 pos_index = i; 2203 if (rshader->input[i].name == TGSI_SEMANTIC_FACE) 2204 face_index = i; 2205 2206 sid = rshader->input[i].spi_sid; 2207 2208 tmp = S_028644_SEMANTIC(sid); 2209 2210 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || 2211 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 2212 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && 2213 rctx->rasterizer && rctx->rasterizer->flatshade)) 2214 tmp |= S_028644_FLAT_SHADE(1); 2215 2216 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC && 2217 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) { 2218 tmp |= S_028644_PT_SPRITE_TEX(1); 2219 } 2220 2221 if (rshader->input[i].centroid) 2222 tmp |= S_028644_SEL_CENTROID(1); 2223 2224 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) { 2225 need_linear = 1; 2226 tmp |= S_028644_SEL_LINEAR(1); 2227 } 2228 2229 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 2230 tmp); 2231 } 2232 2233 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 2234 for (i = 0; i < rshader->noutput; i++) { 2235 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) 2236 z_export = 1; 2237 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 2238 stencil_export = 1; 2239 } 2240 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export); 2241 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export); 2242 if (rshader->uses_kill) 2243 db_shader_control |= S_02880C_KILL_ENABLE(1); 2244 2245 exports_ps = 0; 2246 for (i = 0; i < rshader->noutput; i++) { 2247 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || 2248 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) { 2249 exports_ps |= 1; 2250 } 2251 } 2252 num_cout = rshader->nr_ps_color_exports; 2253 exports_ps |= S_028854_EXPORT_COLORS(num_cout); 2254 if (!exports_ps) { 2255 /* always at least export 1 component per pixel */ 2256 exports_ps = 2; 2257 } 2258 2259 shader->nr_ps_color_outputs = num_cout; 2260 2261 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) | 2262 S_0286CC_PERSP_GRADIENT_ENA(1)| 2263 S_0286CC_LINEAR_GRADIENT_ENA(need_linear); 2264 spi_input_z = 0; 2265 if (pos_index != -1) { 2266 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) | 2267 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) | 2268 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) | 2269 S_0286CC_BARYC_SAMPLE_CNTL(1)); 2270 spi_input_z |= 1; 2271 } 2272 2273 spi_ps_in_control_1 = 0; 2274 if (face_index != -1) { 2275 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | 2276 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); 2277 } 2278 2279 /* HW bug in original R600 */ 2280 if (rctx->family == CHIP_R600) 2281 ufi = 1; 2282 2283 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0); 2284 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1); 2285 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z); 2286 r600_pipe_state_add_reg_bo(rstate, 2287 R_028840_SQ_PGM_START_PS, 2288 0, shader->bo, RADEON_USAGE_READ); 2289 r600_pipe_state_add_reg(rstate, 2290 R_028850_SQ_PGM_RESOURCES_PS, 2291 S_028850_NUM_GPRS(rshader->bc.ngpr) | 2292 S_028850_STACK_SIZE(rshader->bc.nstack) | 2293 S_028850_UNCACHED_FIRST_INST(ufi)); 2294 r600_pipe_state_add_reg(rstate, 2295 R_028854_SQ_PGM_EXPORTS_PS, 2296 exports_ps); 2297 /* only set some bits here, the other bits are set in the dsa state */ 2298 shader->db_shader_control = db_shader_control; 2299 shader->ps_depth_export = z_export | stencil_export; 2300 2301 shader->sprite_coord_enable = rctx->sprite_coord_enable; 2302 if (rctx->rasterizer) 2303 shader->flatshade = rctx->rasterizer->flatshade; 2304} 2305 2306void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2307{ 2308 struct r600_context *rctx = (struct r600_context *)ctx; 2309 struct r600_pipe_state *rstate = &shader->rstate; 2310 struct r600_shader *rshader = &shader->shader; 2311 unsigned spi_vs_out_id[10] = {}; 2312 unsigned i, tmp, nparams = 0; 2313 2314 /* clear previous register */ 2315 rstate->nregs = 0; 2316 2317 for (i = 0; i < rshader->noutput; i++) { 2318 if (rshader->output[i].spi_sid) { 2319 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); 2320 spi_vs_out_id[nparams / 4] |= tmp; 2321 nparams++; 2322 } 2323 } 2324 2325 for (i = 0; i < 10; i++) { 2326 r600_pipe_state_add_reg(rstate, 2327 R_028614_SPI_VS_OUT_ID_0 + i * 4, 2328 spi_vs_out_id[i]); 2329 } 2330 2331 /* Certain attributes (position, psize, etc.) don't count as params. 2332 * VS is required to export at least one param and r600_shader_from_tgsi() 2333 * takes care of adding a dummy export. 2334 */ 2335 if (nparams < 1) 2336 nparams = 1; 2337 2338 r600_pipe_state_add_reg(rstate, 2339 R_0286C4_SPI_VS_OUT_CONFIG, 2340 S_0286C4_VS_EXPORT_COUNT(nparams - 1)); 2341 r600_pipe_state_add_reg(rstate, 2342 R_028868_SQ_PGM_RESOURCES_VS, 2343 S_028868_NUM_GPRS(rshader->bc.ngpr) | 2344 S_028868_STACK_SIZE(rshader->bc.nstack)); 2345 r600_pipe_state_add_reg_bo(rstate, 2346 R_028858_SQ_PGM_START_VS, 2347 0, shader->bo, RADEON_USAGE_READ); 2348 2349 shader->pa_cl_vs_out_cntl = 2350 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) | 2351 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) | 2352 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) | 2353 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size); 2354} 2355 2356void r600_fetch_shader(struct pipe_context *ctx, 2357 struct r600_vertex_element *ve) 2358{ 2359 struct r600_pipe_state *rstate; 2360 struct r600_context *rctx = (struct r600_context *)ctx; 2361 2362 rstate = &ve->rstate; 2363 rstate->id = R600_PIPE_STATE_FETCH_SHADER; 2364 rstate->nregs = 0; 2365 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS, 2366 0, 2367 ve->fetch_shader, RADEON_USAGE_READ); 2368} 2369 2370void *r600_create_db_flush_dsa(struct r600_context *rctx) 2371{ 2372 struct pipe_depth_stencil_alpha_state dsa; 2373 boolean quirk = false; 2374 2375 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 || 2376 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635) 2377 quirk = true; 2378 2379 memset(&dsa, 0, sizeof(dsa)); 2380 2381 if (quirk) { 2382 dsa.depth.enabled = 1; 2383 dsa.depth.func = PIPE_FUNC_LEQUAL; 2384 dsa.stencil[0].enabled = 1; 2385 dsa.stencil[0].func = PIPE_FUNC_ALWAYS; 2386 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP; 2387 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR; 2388 dsa.stencil[0].writemask = 0xff; 2389 } 2390 2391 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 2392} 2393 2394void r600_update_dual_export_state(struct r600_context * rctx) 2395{ 2396 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs && 2397 !rctx->ps_shader->current->ps_depth_export; 2398 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control | 2399 S_02880C_DUAL_EXPORT_ENABLE(dual_export); 2400 2401 if (db_shader_control != rctx->db_shader_control) { 2402 struct r600_pipe_state rstate; 2403 2404 rctx->db_shader_control = db_shader_control; 2405 rstate.nregs = 0; 2406 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control); 2407 r600_context_pipe_state_set(rctx, &rstate); 2408 } 2409} 2410