r600_state.c revision 78354011f99c4103345f8f32e10b0b4b884ebdaf 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "r600d.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31
32static uint32_t r600_translate_blend_function(int blend_func)
33{
34	switch (blend_func) {
35	case PIPE_BLEND_ADD:
36		return V_028804_COMB_DST_PLUS_SRC;
37	case PIPE_BLEND_SUBTRACT:
38		return V_028804_COMB_SRC_MINUS_DST;
39	case PIPE_BLEND_REVERSE_SUBTRACT:
40		return V_028804_COMB_DST_MINUS_SRC;
41	case PIPE_BLEND_MIN:
42		return V_028804_COMB_MIN_DST_SRC;
43	case PIPE_BLEND_MAX:
44		return V_028804_COMB_MAX_DST_SRC;
45	default:
46		R600_ERR("Unknown blend function %d\n", blend_func);
47		assert(0);
48		break;
49	}
50	return 0;
51}
52
53static uint32_t r600_translate_blend_factor(int blend_fact)
54{
55	switch (blend_fact) {
56	case PIPE_BLENDFACTOR_ONE:
57		return V_028804_BLEND_ONE;
58	case PIPE_BLENDFACTOR_SRC_COLOR:
59		return V_028804_BLEND_SRC_COLOR;
60	case PIPE_BLENDFACTOR_SRC_ALPHA:
61		return V_028804_BLEND_SRC_ALPHA;
62	case PIPE_BLENDFACTOR_DST_ALPHA:
63		return V_028804_BLEND_DST_ALPHA;
64	case PIPE_BLENDFACTOR_DST_COLOR:
65		return V_028804_BLEND_DST_COLOR;
66	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67		return V_028804_BLEND_SRC_ALPHA_SATURATE;
68	case PIPE_BLENDFACTOR_CONST_COLOR:
69		return V_028804_BLEND_CONST_COLOR;
70	case PIPE_BLENDFACTOR_CONST_ALPHA:
71		return V_028804_BLEND_CONST_ALPHA;
72	case PIPE_BLENDFACTOR_ZERO:
73		return V_028804_BLEND_ZERO;
74	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75		return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77		return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79		return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80	case PIPE_BLENDFACTOR_INV_DST_COLOR:
81		return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83		return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85		return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86	case PIPE_BLENDFACTOR_SRC1_COLOR:
87		return V_028804_BLEND_SRC1_COLOR;
88	case PIPE_BLENDFACTOR_SRC1_ALPHA:
89		return V_028804_BLEND_SRC1_ALPHA;
90	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91		return V_028804_BLEND_INV_SRC1_COLOR;
92	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93		return V_028804_BLEND_INV_SRC1_ALPHA;
94	default:
95		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96		assert(0);
97		break;
98	}
99	return 0;
100}
101
102static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
103{
104	switch (dim) {
105	default:
106	case PIPE_TEXTURE_1D:
107		return V_038000_SQ_TEX_DIM_1D;
108	case PIPE_TEXTURE_1D_ARRAY:
109		return V_038000_SQ_TEX_DIM_1D_ARRAY;
110	case PIPE_TEXTURE_2D:
111	case PIPE_TEXTURE_RECT:
112		return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
113					V_038000_SQ_TEX_DIM_2D;
114	case PIPE_TEXTURE_2D_ARRAY:
115		return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
116					V_038000_SQ_TEX_DIM_2D_ARRAY;
117	case PIPE_TEXTURE_3D:
118		return V_038000_SQ_TEX_DIM_3D;
119	case PIPE_TEXTURE_CUBE:
120		return V_038000_SQ_TEX_DIM_CUBEMAP;
121	}
122}
123
124static uint32_t r600_translate_dbformat(enum pipe_format format)
125{
126	switch (format) {
127	case PIPE_FORMAT_Z16_UNORM:
128		return V_028010_DEPTH_16;
129	case PIPE_FORMAT_Z24X8_UNORM:
130		return V_028010_DEPTH_X8_24;
131	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
132		return V_028010_DEPTH_8_24;
133	case PIPE_FORMAT_Z32_FLOAT:
134		return V_028010_DEPTH_32_FLOAT;
135	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
136		return V_028010_DEPTH_X24_8_32_FLOAT;
137	default:
138		return ~0U;
139	}
140}
141
142static uint32_t r600_translate_colorswap(enum pipe_format format)
143{
144	switch (format) {
145	/* 8-bit buffers. */
146	case PIPE_FORMAT_A8_UNORM:
147	case PIPE_FORMAT_A8_SNORM:
148	case PIPE_FORMAT_A8_UINT:
149	case PIPE_FORMAT_A8_SINT:
150	case PIPE_FORMAT_A16_UNORM:
151	case PIPE_FORMAT_A16_SNORM:
152	case PIPE_FORMAT_A16_UINT:
153	case PIPE_FORMAT_A16_SINT:
154	case PIPE_FORMAT_A16_FLOAT:
155	case PIPE_FORMAT_A32_UINT:
156	case PIPE_FORMAT_A32_SINT:
157	case PIPE_FORMAT_A32_FLOAT:
158	case PIPE_FORMAT_R4A4_UNORM:
159		return V_0280A0_SWAP_ALT_REV;
160	case PIPE_FORMAT_I8_UNORM:
161	case PIPE_FORMAT_I8_SNORM:
162	case PIPE_FORMAT_I8_UINT:
163	case PIPE_FORMAT_I8_SINT:
164	case PIPE_FORMAT_L8_UNORM:
165	case PIPE_FORMAT_L8_SNORM:
166	case PIPE_FORMAT_L8_UINT:
167	case PIPE_FORMAT_L8_SINT:
168	case PIPE_FORMAT_L8_SRGB:
169	case PIPE_FORMAT_L16_UNORM:
170	case PIPE_FORMAT_L16_SNORM:
171	case PIPE_FORMAT_L16_UINT:
172	case PIPE_FORMAT_L16_SINT:
173	case PIPE_FORMAT_L16_FLOAT:
174	case PIPE_FORMAT_L32_UINT:
175	case PIPE_FORMAT_L32_SINT:
176	case PIPE_FORMAT_L32_FLOAT:
177	case PIPE_FORMAT_I16_UNORM:
178	case PIPE_FORMAT_I16_SNORM:
179	case PIPE_FORMAT_I16_UINT:
180	case PIPE_FORMAT_I16_SINT:
181	case PIPE_FORMAT_I16_FLOAT:
182	case PIPE_FORMAT_I32_UINT:
183	case PIPE_FORMAT_I32_SINT:
184	case PIPE_FORMAT_I32_FLOAT:
185	case PIPE_FORMAT_R8_UNORM:
186	case PIPE_FORMAT_R8_SNORM:
187	case PIPE_FORMAT_R8_UINT:
188	case PIPE_FORMAT_R8_SINT:
189		return V_0280A0_SWAP_STD;
190
191	case PIPE_FORMAT_L4A4_UNORM:
192	case PIPE_FORMAT_A4R4_UNORM:
193		return V_0280A0_SWAP_ALT;
194
195	/* 16-bit buffers. */
196	case PIPE_FORMAT_B5G6R5_UNORM:
197		return V_0280A0_SWAP_STD_REV;
198
199	case PIPE_FORMAT_B5G5R5A1_UNORM:
200	case PIPE_FORMAT_B5G5R5X1_UNORM:
201		return V_0280A0_SWAP_ALT;
202
203	case PIPE_FORMAT_B4G4R4A4_UNORM:
204	case PIPE_FORMAT_B4G4R4X4_UNORM:
205		return V_0280A0_SWAP_ALT;
206
207	case PIPE_FORMAT_Z16_UNORM:
208		return V_0280A0_SWAP_STD;
209
210	case PIPE_FORMAT_L8A8_UNORM:
211	case PIPE_FORMAT_L8A8_SNORM:
212	case PIPE_FORMAT_L8A8_UINT:
213	case PIPE_FORMAT_L8A8_SINT:
214	case PIPE_FORMAT_L8A8_SRGB:
215	case PIPE_FORMAT_L16A16_UNORM:
216	case PIPE_FORMAT_L16A16_SNORM:
217	case PIPE_FORMAT_L16A16_UINT:
218	case PIPE_FORMAT_L16A16_SINT:
219	case PIPE_FORMAT_L16A16_FLOAT:
220	case PIPE_FORMAT_L32A32_UINT:
221	case PIPE_FORMAT_L32A32_SINT:
222	case PIPE_FORMAT_L32A32_FLOAT:
223		return V_0280A0_SWAP_ALT;
224	case PIPE_FORMAT_R8G8_UNORM:
225	case PIPE_FORMAT_R8G8_SNORM:
226	case PIPE_FORMAT_R8G8_UINT:
227	case PIPE_FORMAT_R8G8_SINT:
228		return V_0280A0_SWAP_STD;
229
230	case PIPE_FORMAT_R16_UNORM:
231	case PIPE_FORMAT_R16_SNORM:
232	case PIPE_FORMAT_R16_UINT:
233	case PIPE_FORMAT_R16_SINT:
234	case PIPE_FORMAT_R16_FLOAT:
235		return V_0280A0_SWAP_STD;
236
237	/* 32-bit buffers. */
238
239	case PIPE_FORMAT_A8B8G8R8_SRGB:
240		return V_0280A0_SWAP_STD_REV;
241	case PIPE_FORMAT_B8G8R8A8_SRGB:
242		return V_0280A0_SWAP_ALT;
243
244	case PIPE_FORMAT_B8G8R8A8_UNORM:
245	case PIPE_FORMAT_B8G8R8X8_UNORM:
246		return V_0280A0_SWAP_ALT;
247
248	case PIPE_FORMAT_A8R8G8B8_UNORM:
249	case PIPE_FORMAT_X8R8G8B8_UNORM:
250		return V_0280A0_SWAP_ALT_REV;
251	case PIPE_FORMAT_R8G8B8A8_SNORM:
252	case PIPE_FORMAT_R8G8B8A8_UNORM:
253	case PIPE_FORMAT_R8G8B8X8_UNORM:
254	case PIPE_FORMAT_R8G8B8A8_SINT:
255	case PIPE_FORMAT_R8G8B8A8_UINT:
256		return V_0280A0_SWAP_STD;
257
258	case PIPE_FORMAT_A8B8G8R8_UNORM:
259	case PIPE_FORMAT_X8B8G8R8_UNORM:
260	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261		return V_0280A0_SWAP_STD_REV;
262
263	case PIPE_FORMAT_Z24X8_UNORM:
264	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265		return V_0280A0_SWAP_STD;
266
267	case PIPE_FORMAT_X8Z24_UNORM:
268	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
269		return V_0280A0_SWAP_STD;
270
271	case PIPE_FORMAT_R10G10B10A2_UNORM:
272	case PIPE_FORMAT_R10G10B10X2_SNORM:
273	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
274		return V_0280A0_SWAP_STD;
275
276	case PIPE_FORMAT_B10G10R10A2_UNORM:
277	case PIPE_FORMAT_B10G10R10A2_UINT:
278		return V_0280A0_SWAP_ALT;
279
280	case PIPE_FORMAT_R11G11B10_FLOAT:
281	case PIPE_FORMAT_R16G16_UNORM:
282	case PIPE_FORMAT_R16G16_SNORM:
283	case PIPE_FORMAT_R16G16_FLOAT:
284	case PIPE_FORMAT_R16G16_UINT:
285	case PIPE_FORMAT_R16G16_SINT:
286	case PIPE_FORMAT_R32_UINT:
287	case PIPE_FORMAT_R32_SINT:
288	case PIPE_FORMAT_R32_FLOAT:
289	case PIPE_FORMAT_Z32_FLOAT:
290		return V_0280A0_SWAP_STD;
291
292	/* 64-bit buffers. */
293	case PIPE_FORMAT_R32G32_FLOAT:
294	case PIPE_FORMAT_R32G32_UINT:
295	case PIPE_FORMAT_R32G32_SINT:
296	case PIPE_FORMAT_R16G16B16A16_UNORM:
297	case PIPE_FORMAT_R16G16B16A16_SNORM:
298	case PIPE_FORMAT_R16G16B16A16_UINT:
299	case PIPE_FORMAT_R16G16B16A16_SINT:
300	case PIPE_FORMAT_R16G16B16A16_FLOAT:
301	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303	/* 128-bit buffers. */
304	case PIPE_FORMAT_R32G32B32A32_FLOAT:
305	case PIPE_FORMAT_R32G32B32A32_SNORM:
306	case PIPE_FORMAT_R32G32B32A32_UNORM:
307	case PIPE_FORMAT_R32G32B32A32_SINT:
308	case PIPE_FORMAT_R32G32B32A32_UINT:
309		return V_0280A0_SWAP_STD;
310	default:
311		R600_ERR("unsupported colorswap format %d\n", format);
312		return ~0U;
313	}
314	return ~0U;
315}
316
317static uint32_t r600_translate_colorformat(enum pipe_format format)
318{
319	switch (format) {
320	case PIPE_FORMAT_L4A4_UNORM:
321	case PIPE_FORMAT_R4A4_UNORM:
322	case PIPE_FORMAT_A4R4_UNORM:
323		return V_0280A0_COLOR_4_4;
324
325	/* 8-bit buffers. */
326	case PIPE_FORMAT_A8_UNORM:
327	case PIPE_FORMAT_A8_SNORM:
328	case PIPE_FORMAT_A8_UINT:
329	case PIPE_FORMAT_A8_SINT:
330	case PIPE_FORMAT_I8_UNORM:
331	case PIPE_FORMAT_I8_SNORM:
332	case PIPE_FORMAT_I8_UINT:
333	case PIPE_FORMAT_I8_SINT:
334	case PIPE_FORMAT_L8_UNORM:
335	case PIPE_FORMAT_L8_SNORM:
336	case PIPE_FORMAT_L8_UINT:
337	case PIPE_FORMAT_L8_SINT:
338	case PIPE_FORMAT_L8_SRGB:
339	case PIPE_FORMAT_R8_UNORM:
340	case PIPE_FORMAT_R8_SNORM:
341	case PIPE_FORMAT_R8_UINT:
342	case PIPE_FORMAT_R8_SINT:
343		return V_0280A0_COLOR_8;
344
345	/* 16-bit buffers. */
346	case PIPE_FORMAT_B5G6R5_UNORM:
347		return V_0280A0_COLOR_5_6_5;
348
349	case PIPE_FORMAT_B5G5R5A1_UNORM:
350	case PIPE_FORMAT_B5G5R5X1_UNORM:
351		return V_0280A0_COLOR_1_5_5_5;
352
353	case PIPE_FORMAT_B4G4R4A4_UNORM:
354	case PIPE_FORMAT_B4G4R4X4_UNORM:
355		return V_0280A0_COLOR_4_4_4_4;
356
357	case PIPE_FORMAT_Z16_UNORM:
358		return V_0280A0_COLOR_16;
359
360	case PIPE_FORMAT_L8A8_UNORM:
361	case PIPE_FORMAT_L8A8_SNORM:
362	case PIPE_FORMAT_L8A8_UINT:
363	case PIPE_FORMAT_L8A8_SINT:
364	case PIPE_FORMAT_L8A8_SRGB:
365	case PIPE_FORMAT_R8G8_UNORM:
366	case PIPE_FORMAT_R8G8_SNORM:
367	case PIPE_FORMAT_R8G8_UINT:
368	case PIPE_FORMAT_R8G8_SINT:
369		return V_0280A0_COLOR_8_8;
370
371	case PIPE_FORMAT_R16_UNORM:
372	case PIPE_FORMAT_R16_SNORM:
373	case PIPE_FORMAT_R16_UINT:
374	case PIPE_FORMAT_R16_SINT:
375	case PIPE_FORMAT_A16_UNORM:
376	case PIPE_FORMAT_A16_SNORM:
377	case PIPE_FORMAT_A16_UINT:
378	case PIPE_FORMAT_A16_SINT:
379	case PIPE_FORMAT_L16_UNORM:
380	case PIPE_FORMAT_L16_SNORM:
381	case PIPE_FORMAT_L16_UINT:
382	case PIPE_FORMAT_L16_SINT:
383	case PIPE_FORMAT_I16_UNORM:
384	case PIPE_FORMAT_I16_SNORM:
385	case PIPE_FORMAT_I16_UINT:
386	case PIPE_FORMAT_I16_SINT:
387		return V_0280A0_COLOR_16;
388
389	case PIPE_FORMAT_R16_FLOAT:
390	case PIPE_FORMAT_A16_FLOAT:
391	case PIPE_FORMAT_L16_FLOAT:
392	case PIPE_FORMAT_I16_FLOAT:
393		return V_0280A0_COLOR_16_FLOAT;
394
395	/* 32-bit buffers. */
396	case PIPE_FORMAT_A8B8G8R8_SRGB:
397	case PIPE_FORMAT_A8B8G8R8_UNORM:
398	case PIPE_FORMAT_A8R8G8B8_UNORM:
399	case PIPE_FORMAT_B8G8R8A8_SRGB:
400	case PIPE_FORMAT_B8G8R8A8_UNORM:
401	case PIPE_FORMAT_B8G8R8X8_UNORM:
402	case PIPE_FORMAT_R8G8B8A8_SNORM:
403	case PIPE_FORMAT_R8G8B8A8_UNORM:
404	case PIPE_FORMAT_R8G8B8X8_UNORM:
405	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406	case PIPE_FORMAT_X8B8G8R8_UNORM:
407	case PIPE_FORMAT_X8R8G8B8_UNORM:
408	case PIPE_FORMAT_R8G8B8A8_SINT:
409	case PIPE_FORMAT_R8G8B8A8_UINT:
410		return V_0280A0_COLOR_8_8_8_8;
411
412	case PIPE_FORMAT_R10G10B10A2_UNORM:
413	case PIPE_FORMAT_R10G10B10X2_SNORM:
414	case PIPE_FORMAT_B10G10R10A2_UNORM:
415	case PIPE_FORMAT_B10G10R10A2_UINT:
416	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
417		return V_0280A0_COLOR_2_10_10_10;
418
419	case PIPE_FORMAT_Z24X8_UNORM:
420	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
421		return V_0280A0_COLOR_8_24;
422
423	case PIPE_FORMAT_X8Z24_UNORM:
424	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
425		return V_0280A0_COLOR_24_8;
426
427	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
428		return V_0280A0_COLOR_X24_8_32_FLOAT;
429
430	case PIPE_FORMAT_R32_UINT:
431	case PIPE_FORMAT_R32_SINT:
432	case PIPE_FORMAT_A32_UINT:
433	case PIPE_FORMAT_A32_SINT:
434	case PIPE_FORMAT_L32_UINT:
435	case PIPE_FORMAT_L32_SINT:
436	case PIPE_FORMAT_I32_UINT:
437	case PIPE_FORMAT_I32_SINT:
438		return V_0280A0_COLOR_32;
439
440	case PIPE_FORMAT_R32_FLOAT:
441	case PIPE_FORMAT_A32_FLOAT:
442	case PIPE_FORMAT_L32_FLOAT:
443	case PIPE_FORMAT_I32_FLOAT:
444	case PIPE_FORMAT_Z32_FLOAT:
445		return V_0280A0_COLOR_32_FLOAT;
446
447	case PIPE_FORMAT_R16G16_FLOAT:
448	case PIPE_FORMAT_L16A16_FLOAT:
449		return V_0280A0_COLOR_16_16_FLOAT;
450
451	case PIPE_FORMAT_R16G16_UNORM:
452	case PIPE_FORMAT_R16G16_SNORM:
453	case PIPE_FORMAT_R16G16_UINT:
454	case PIPE_FORMAT_R16G16_SINT:
455	case PIPE_FORMAT_L16A16_UNORM:
456	case PIPE_FORMAT_L16A16_SNORM:
457	case PIPE_FORMAT_L16A16_UINT:
458	case PIPE_FORMAT_L16A16_SINT:
459		return V_0280A0_COLOR_16_16;
460
461	case PIPE_FORMAT_R11G11B10_FLOAT:
462		return V_0280A0_COLOR_10_11_11_FLOAT;
463
464	/* 64-bit buffers. */
465	case PIPE_FORMAT_R16G16B16A16_UINT:
466	case PIPE_FORMAT_R16G16B16A16_SINT:
467	case PIPE_FORMAT_R16G16B16A16_UNORM:
468	case PIPE_FORMAT_R16G16B16A16_SNORM:
469		return V_0280A0_COLOR_16_16_16_16;
470
471	case PIPE_FORMAT_R16G16B16A16_FLOAT:
472		return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474	case PIPE_FORMAT_R32G32_FLOAT:
475	case PIPE_FORMAT_L32A32_FLOAT:
476		return V_0280A0_COLOR_32_32_FLOAT;
477
478	case PIPE_FORMAT_R32G32_SINT:
479	case PIPE_FORMAT_R32G32_UINT:
480	case PIPE_FORMAT_L32A32_UINT:
481	case PIPE_FORMAT_L32A32_SINT:
482		return V_0280A0_COLOR_32_32;
483
484	/* 128-bit buffers. */
485	case PIPE_FORMAT_R32G32B32A32_FLOAT:
486		return V_0280A0_COLOR_32_32_32_32_FLOAT;
487	case PIPE_FORMAT_R32G32B32A32_SNORM:
488	case PIPE_FORMAT_R32G32B32A32_UNORM:
489	case PIPE_FORMAT_R32G32B32A32_SINT:
490	case PIPE_FORMAT_R32G32B32A32_UINT:
491		return V_0280A0_COLOR_32_32_32_32;
492
493	/* YUV buffers. */
494	case PIPE_FORMAT_UYVY:
495	case PIPE_FORMAT_YUYV:
496	default:
497		return ~0U; /* Unsupported. */
498	}
499}
500
501static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
502{
503	if (R600_BIG_ENDIAN) {
504		switch(colorformat) {
505		case V_0280A0_COLOR_4_4:
506			return ENDIAN_NONE;
507
508		/* 8-bit buffers. */
509		case V_0280A0_COLOR_8:
510			return ENDIAN_NONE;
511
512		/* 16-bit buffers. */
513		case V_0280A0_COLOR_5_6_5:
514		case V_0280A0_COLOR_1_5_5_5:
515		case V_0280A0_COLOR_4_4_4_4:
516		case V_0280A0_COLOR_16:
517		case V_0280A0_COLOR_8_8:
518			return ENDIAN_8IN16;
519
520		/* 32-bit buffers. */
521		case V_0280A0_COLOR_8_8_8_8:
522		case V_0280A0_COLOR_2_10_10_10:
523		case V_0280A0_COLOR_8_24:
524		case V_0280A0_COLOR_24_8:
525		case V_0280A0_COLOR_32_FLOAT:
526		case V_0280A0_COLOR_16_16_FLOAT:
527		case V_0280A0_COLOR_16_16:
528			return ENDIAN_8IN32;
529
530		/* 64-bit buffers. */
531		case V_0280A0_COLOR_16_16_16_16:
532		case V_0280A0_COLOR_16_16_16_16_FLOAT:
533			return ENDIAN_8IN16;
534
535		case V_0280A0_COLOR_32_32_FLOAT:
536		case V_0280A0_COLOR_32_32:
537		case V_0280A0_COLOR_X24_8_32_FLOAT:
538			return ENDIAN_8IN32;
539
540		/* 128-bit buffers. */
541		case V_0280A0_COLOR_32_32_32_FLOAT:
542		case V_0280A0_COLOR_32_32_32_32_FLOAT:
543		case V_0280A0_COLOR_32_32_32_32:
544			return ENDIAN_8IN32;
545		default:
546			return ENDIAN_NONE; /* Unsupported. */
547		}
548	} else {
549		return ENDIAN_NONE;
550	}
551}
552
553static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
554{
555	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
556}
557
558static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
559{
560	return r600_translate_colorformat(format) != ~0U &&
561	       r600_translate_colorswap(format) != ~0U;
562}
563
564static bool r600_is_zs_format_supported(enum pipe_format format)
565{
566	return r600_translate_dbformat(format) != ~0U;
567}
568
569boolean r600_is_format_supported(struct pipe_screen *screen,
570				 enum pipe_format format,
571				 enum pipe_texture_target target,
572				 unsigned sample_count,
573				 unsigned usage)
574{
575	struct r600_screen *rscreen = (struct r600_screen*)screen;
576	unsigned retval = 0;
577
578	if (target >= PIPE_MAX_TEXTURE_TYPES) {
579		R600_ERR("r600: unsupported texture type %d\n", target);
580		return FALSE;
581	}
582
583	if (!util_format_is_supported(format, usage))
584		return FALSE;
585
586	if (sample_count > 1) {
587		if (rscreen->info.drm_minor < 21)
588			return FALSE;
589		if (rscreen->chip_class != R700)
590			return FALSE;
591
592		switch (sample_count) {
593		case 2:
594		case 4:
595		case 8:
596			break;
597		default:
598			return FALSE;
599		}
600
601		/* require render-target support for multisample resources */
602		if (util_format_is_depth_or_stencil(format)) {
603			usage |= PIPE_BIND_DEPTH_STENCIL;
604		} else if (util_format_is_pure_integer(format)) {
605			return FALSE;
606		} else {
607			usage |= PIPE_BIND_RENDER_TARGET;
608		}
609	}
610
611	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
612	    r600_is_sampler_format_supported(screen, format)) {
613		retval |= PIPE_BIND_SAMPLER_VIEW;
614	}
615
616	if ((usage & (PIPE_BIND_RENDER_TARGET |
617		      PIPE_BIND_DISPLAY_TARGET |
618		      PIPE_BIND_SCANOUT |
619		      PIPE_BIND_SHARED)) &&
620	    r600_is_colorbuffer_format_supported(format)) {
621		retval |= usage &
622			  (PIPE_BIND_RENDER_TARGET |
623			   PIPE_BIND_DISPLAY_TARGET |
624			   PIPE_BIND_SCANOUT |
625			   PIPE_BIND_SHARED);
626	}
627
628	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
629	    r600_is_zs_format_supported(format)) {
630		retval |= PIPE_BIND_DEPTH_STENCIL;
631	}
632
633	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
634	    r600_is_vertex_format_supported(format)) {
635		retval |= PIPE_BIND_VERTEX_BUFFER;
636	}
637
638	if (usage & PIPE_BIND_TRANSFER_READ)
639		retval |= PIPE_BIND_TRANSFER_READ;
640	if (usage & PIPE_BIND_TRANSFER_WRITE)
641		retval |= PIPE_BIND_TRANSFER_WRITE;
642
643	return retval == usage;
644}
645
646void r600_polygon_offset_update(struct r600_context *rctx)
647{
648	struct r600_pipe_state state;
649
650	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
651	state.nregs = 0;
652	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
653		float offset_units = rctx->rasterizer->offset_units;
654		unsigned offset_db_fmt_cntl = 0, depth;
655
656		switch (rctx->framebuffer.zsbuf->format) {
657		case PIPE_FORMAT_Z24X8_UNORM:
658		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
659			depth = -24;
660			offset_units *= 2.0f;
661			break;
662		case PIPE_FORMAT_Z32_FLOAT:
663		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
664			depth = -23;
665			offset_units *= 1.0f;
666			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
667			break;
668		case PIPE_FORMAT_Z16_UNORM:
669			depth = -16;
670			offset_units *= 4.0f;
671			break;
672		default:
673			return;
674		}
675		/* XXX some of those reg can be computed with cso */
676		offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
677		r600_pipe_state_add_reg(&state,
678				R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
679				fui(rctx->rasterizer->offset_scale));
680		r600_pipe_state_add_reg(&state,
681				R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
682				fui(offset_units));
683		r600_pipe_state_add_reg(&state,
684				R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
685				fui(rctx->rasterizer->offset_scale));
686		r600_pipe_state_add_reg(&state,
687				R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
688				fui(offset_units));
689		r600_pipe_state_add_reg(&state,
690				R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
691				offset_db_fmt_cntl);
692		r600_context_pipe_state_set(rctx, &state);
693	}
694}
695
696static void *r600_create_blend_state_mode(struct pipe_context *ctx,
697					  const struct pipe_blend_state *state,
698					  int mode)
699{
700	struct r600_context *rctx = (struct r600_context *)ctx;
701	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
702	struct r600_pipe_state *rstate;
703	uint32_t color_control = 0, target_mask = 0;
704
705	if (blend == NULL) {
706		return NULL;
707	}
708	rstate = &blend->rstate;
709
710	rstate->id = R600_PIPE_STATE_BLEND;
711
712	/* R600 does not support per-MRT blends */
713	if (rctx->family > CHIP_R600)
714		color_control |= S_028808_PER_MRT_BLEND(1);
715
716	if (state->logicop_enable) {
717		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
718	} else {
719		color_control |= (0xcc << 16);
720	}
721	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
722	if (state->independent_blend_enable) {
723		for (int i = 0; i < 8; i++) {
724			if (state->rt[i].blend_enable) {
725				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
726			}
727			target_mask |= (state->rt[i].colormask << (4 * i));
728		}
729	} else {
730		for (int i = 0; i < 8; i++) {
731			if (state->rt[0].blend_enable) {
732				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
733			}
734			target_mask |= (state->rt[0].colormask << (4 * i));
735		}
736	}
737
738	if (target_mask)
739		color_control |= S_028808_SPECIAL_OP(mode);
740	else
741		color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
742
743	blend->cb_target_mask = target_mask;
744	blend->cb_color_control = color_control;
745	/* only MRT0 has dual src blend */
746	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
747	for (int i = 0; i < 8; i++) {
748		/* state->rt entries > 0 only written if independent blending */
749		const int j = state->independent_blend_enable ? i : 0;
750
751		unsigned eqRGB = state->rt[j].rgb_func;
752		unsigned srcRGB = state->rt[j].rgb_src_factor;
753		unsigned dstRGB = state->rt[j].rgb_dst_factor;
754
755		unsigned eqA = state->rt[j].alpha_func;
756		unsigned srcA = state->rt[j].alpha_src_factor;
757		unsigned dstA = state->rt[j].alpha_dst_factor;
758		uint32_t bc = 0;
759
760		if (!state->rt[j].blend_enable)
761			continue;
762
763		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
764		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
765		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
766
767		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
768			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
769			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
770			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
771			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
772		}
773
774		/* R600 does not support per-MRT blends */
775		if (rctx->family > CHIP_R600)
776			r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
777		if (i == 0)
778			r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
779	}
780
781	r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
782				S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
783				S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
784				S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
785				S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
786				S_028D44_ALPHA_TO_MASK_OFFSET3(2));
787
788	blend->alpha_to_one = state->alpha_to_one;
789	return rstate;
790}
791
792
793static void *r600_create_blend_state(struct pipe_context *ctx,
794				     const struct pipe_blend_state *state)
795{
796	return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
797}
798
799static void *r600_create_dsa_state(struct pipe_context *ctx,
800				   const struct pipe_depth_stencil_alpha_state *state)
801{
802	struct r600_context *rctx = (struct r600_context *)ctx;
803	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
804	unsigned db_depth_control, alpha_test_control, alpha_ref;
805	struct r600_pipe_state *rstate;
806
807	if (dsa == NULL) {
808		return NULL;
809	}
810
811	dsa->valuemask[0] = state->stencil[0].valuemask;
812	dsa->valuemask[1] = state->stencil[1].valuemask;
813	dsa->writemask[0] = state->stencil[0].writemask;
814	dsa->writemask[1] = state->stencil[1].writemask;
815
816	rstate = &dsa->rstate;
817
818	rstate->id = R600_PIPE_STATE_DSA;
819	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
820		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
821		S_028800_ZFUNC(state->depth.func);
822
823	/* stencil */
824	if (state->stencil[0].enabled) {
825		db_depth_control |= S_028800_STENCIL_ENABLE(1);
826		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
827		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
828		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
829		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
830
831		if (state->stencil[1].enabled) {
832			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
833			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
834			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
835			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
836			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
837		}
838	}
839
840	/* alpha */
841	alpha_test_control = 0;
842	alpha_ref = 0;
843	if (state->alpha.enabled) {
844		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
845		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
846		alpha_ref = fui(state->alpha.ref_value);
847	}
848	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
849	dsa->alpha_ref = alpha_ref;
850
851	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
852	return rstate;
853}
854
855static void *r600_create_rs_state(struct pipe_context *ctx,
856				  const struct pipe_rasterizer_state *state)
857{
858	struct r600_context *rctx = (struct r600_context *)ctx;
859	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
860	struct r600_pipe_state *rstate;
861	unsigned tmp;
862	unsigned prov_vtx = 1, polygon_dual_mode;
863	unsigned sc_mode_cntl;
864	float psize_min, psize_max;
865
866	if (rs == NULL) {
867		return NULL;
868	}
869
870	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
871				state->fill_back != PIPE_POLYGON_MODE_FILL);
872
873	if (state->flatshade_first)
874		prov_vtx = 0;
875
876	rstate = &rs->rstate;
877	rs->flatshade = state->flatshade;
878	rs->sprite_coord_enable = state->sprite_coord_enable;
879	rs->two_side = state->light_twoside;
880	rs->clip_plane_enable = state->clip_plane_enable;
881	rs->pa_sc_line_stipple = state->line_stipple_enable ?
882				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
883				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
884	rs->pa_cl_clip_cntl =
885		S_028810_PS_UCP_MODE(3) |
886		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
887		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
888		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
889	rs->multisample_enable = state->multisample;
890
891	/* offset */
892	rs->offset_units = state->offset_units;
893	rs->offset_scale = state->offset_scale * 12.0f;
894
895	rstate->id = R600_PIPE_STATE_RASTERIZER;
896	tmp = S_0286D4_FLAT_SHADE_ENA(1);
897	if (state->sprite_coord_enable) {
898		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
899			S_0286D4_PNT_SPRITE_OVRD_X(2) |
900			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
901			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
902			S_0286D4_PNT_SPRITE_OVRD_W(1);
903		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
904			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
905		}
906	}
907	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
908
909	/* point size 12.4 fixed point */
910	tmp = r600_pack_float_12p4(state->point_size/2);
911	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
912
913	if (state->point_size_per_vertex) {
914		psize_min = util_get_min_point_size(state);
915		psize_max = 8192;
916	} else {
917		/* Force the point size to be as if the vertex output was disabled. */
918		psize_min = state->point_size;
919		psize_max = state->point_size;
920	}
921	/* Divide by two, because 0.5 = 1 pixel. */
922	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
923				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
924				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
925
926	tmp = r600_pack_float_12p4(state->line_width/2);
927	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
928
929	if (rctx->chip_class >= R700) {
930		sc_mode_cntl =
931			S_028A4C_MSAA_ENABLE(state->multisample) |
932			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
933			S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
934			S_028A4C_R700_ZMM_LINE_OFFSET(1) |
935			S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
936	} else {
937		sc_mode_cntl =
938			S_028A4C_MSAA_ENABLE(state->multisample) |
939			S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
940			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
941		rs->scissor_enable = state->scissor;
942	}
943	sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
944
945	r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
946
947	r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
948				S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
949
950	r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
951	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
952				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
953				S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
954				S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
955				S_028814_FACE(!state->front_ccw) |
956				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
957				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
958				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
959				S_028814_POLY_MODE(polygon_dual_mode) |
960				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
961				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
962	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
963	return rstate;
964}
965
966static void *r600_create_sampler_state(struct pipe_context *ctx,
967					const struct pipe_sampler_state *state)
968{
969	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
970	union util_color uc;
971	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
972
973	if (ss == NULL) {
974		return NULL;
975	}
976
977	ss->seamless_cube_map = state->seamless_cube_map;
978	ss->border_color_use = false;
979	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
980	/* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
981	ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
982				S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
983				S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
984				S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
985				S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
986				S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
987				S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
988				S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
989				S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
990	/* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
991	ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
992				S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
993				S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
994	/* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
995	ss->tex_sampler_words[2] = S_03C008_TYPE(1);
996	if (uc.ui) {
997		ss->border_color_use = true;
998		/* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
999		ss->border_color[0] = fui(state->border_color.f[0]);
1000		/* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
1001		ss->border_color[1] = fui(state->border_color.f[1]);
1002		/* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
1003		ss->border_color[2] = fui(state->border_color.f[2]);
1004		/* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
1005		ss->border_color[3] = fui(state->border_color.f[3]);
1006	}
1007	return ss;
1008}
1009
1010static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1011							struct pipe_resource *texture,
1012							const struct pipe_sampler_view *state)
1013{
1014	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1015	struct r600_texture *tmp = (struct r600_texture*)texture;
1016	unsigned format, endian;
1017	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1018	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1019	unsigned width, height, depth, offset_level, last_level;
1020
1021	if (view == NULL)
1022		return NULL;
1023
1024	/* initialize base object */
1025	view->base = *state;
1026	view->base.texture = NULL;
1027	pipe_reference(NULL, &texture->reference);
1028	view->base.texture = texture;
1029	view->base.reference.count = 1;
1030	view->base.context = ctx;
1031
1032	swizzle[0] = state->swizzle_r;
1033	swizzle[1] = state->swizzle_g;
1034	swizzle[2] = state->swizzle_b;
1035	swizzle[3] = state->swizzle_a;
1036
1037	format = r600_translate_texformat(ctx->screen, state->format,
1038					  swizzle,
1039					  &word4, &yuv_format);
1040	assert(format != ~0);
1041	if (format == ~0) {
1042		FREE(view);
1043		return NULL;
1044	}
1045
1046	if (tmp->is_depth && !tmp->is_flushing_texture) {
1047		if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1048			FREE(view);
1049			return NULL;
1050		}
1051		tmp = tmp->flushed_depth_texture;
1052	}
1053
1054	endian = r600_colorformat_endian_swap(format);
1055
1056	offset_level = state->u.tex.first_level;
1057	last_level = state->u.tex.last_level - offset_level;
1058	width = tmp->surface.level[offset_level].npix_x;
1059	height = tmp->surface.level[offset_level].npix_y;
1060	depth = tmp->surface.level[offset_level].npix_z;
1061	pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1062	tile_type = tmp->tile_type;
1063
1064	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1065		height = 1;
1066		depth = texture->array_size;
1067	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1068		depth = texture->array_size;
1069	}
1070	switch (tmp->surface.level[offset_level].mode) {
1071	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1072		array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1073		break;
1074	case RADEON_SURF_MODE_1D:
1075		array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1076		break;
1077	case RADEON_SURF_MODE_2D:
1078		array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1079		break;
1080	case RADEON_SURF_MODE_LINEAR:
1081	default:
1082		array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1083		break;
1084	}
1085
1086	view->tex_resource = &tmp->resource;
1087	view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1088				       S_038000_TILE_MODE(array_mode) |
1089				       S_038000_TILE_TYPE(tile_type) |
1090				       S_038000_PITCH((pitch / 8) - 1) |
1091				       S_038000_TEX_WIDTH(width - 1));
1092	view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1093				       S_038004_TEX_DEPTH(depth - 1) |
1094				       S_038004_DATA_FORMAT(format));
1095	view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1096	if (offset_level >= tmp->surface.last_level) {
1097		view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1098	} else {
1099		view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1100	}
1101	view->tex_resource_words[4] = (word4 |
1102				       S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1103				       S_038010_REQUEST_SIZE(1) |
1104				       S_038010_ENDIAN_SWAP(endian) |
1105				       S_038010_BASE_LEVEL(0));
1106	view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1107				       S_038014_LAST_ARRAY(state->u.tex.last_layer));
1108	if (texture->nr_samples > 1) {
1109		/* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1110		view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1111	} else {
1112		view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1113	}
1114	view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1115				       S_038018_MAX_ANISO(4 /* max 16 samples */));
1116	return &view->base;
1117}
1118
1119static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1120				      struct pipe_sampler_view **views)
1121{
1122	r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
1123}
1124
1125static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1126				      struct pipe_sampler_view **views)
1127{
1128	r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
1129}
1130
1131static void r600_set_clip_state(struct pipe_context *ctx,
1132				const struct pipe_clip_state *state)
1133{
1134	struct r600_context *rctx = (struct r600_context *)ctx;
1135	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1136	struct pipe_constant_buffer cb;
1137
1138	if (rstate == NULL)
1139		return;
1140
1141	rctx->clip = *state;
1142	rstate->id = R600_PIPE_STATE_CLIP;
1143	for (int i = 0; i < 6; i++) {
1144		r600_pipe_state_add_reg(rstate,
1145					R_028E20_PA_CL_UCP0_X + i * 16,
1146					fui(state->ucp[i][0]));
1147		r600_pipe_state_add_reg(rstate,
1148					R_028E24_PA_CL_UCP0_Y + i * 16,
1149					fui(state->ucp[i][1]) );
1150		r600_pipe_state_add_reg(rstate,
1151					R_028E28_PA_CL_UCP0_Z + i * 16,
1152					fui(state->ucp[i][2]));
1153		r600_pipe_state_add_reg(rstate,
1154					R_028E2C_PA_CL_UCP0_W + i * 16,
1155					fui(state->ucp[i][3]));
1156	}
1157
1158	free(rctx->states[R600_PIPE_STATE_CLIP]);
1159	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1160	r600_context_pipe_state_set(rctx, rstate);
1161
1162	cb.buffer = NULL;
1163	cb.user_buffer = state->ucp;
1164	cb.buffer_offset = 0;
1165	cb.buffer_size = 4*4*8;
1166	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1167	pipe_resource_reference(&cb.buffer, NULL);
1168}
1169
1170static void r600_set_polygon_stipple(struct pipe_context *ctx,
1171					 const struct pipe_poly_stipple *state)
1172{
1173}
1174
1175void r600_set_scissor_state(struct r600_context *rctx,
1176			    const struct pipe_scissor_state *state)
1177{
1178	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1179	uint32_t tl, br;
1180
1181	if (rstate == NULL)
1182		return;
1183
1184	rstate->id = R600_PIPE_STATE_SCISSOR;
1185	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1186	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1187	r600_pipe_state_add_reg(rstate,
1188				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1189	r600_pipe_state_add_reg(rstate,
1190				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1191
1192	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1193	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1194	r600_context_pipe_state_set(rctx, rstate);
1195}
1196
1197static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1198					const struct pipe_scissor_state *state)
1199{
1200	struct r600_context *rctx = (struct r600_context *)ctx;
1201
1202	if (rctx->chip_class == R600) {
1203		rctx->scissor_state = *state;
1204
1205		if (!rctx->scissor_enable)
1206			return;
1207	}
1208
1209	r600_set_scissor_state(rctx, state);
1210}
1211
1212static void r600_set_viewport_state(struct pipe_context *ctx,
1213					const struct pipe_viewport_state *state)
1214{
1215	struct r600_context *rctx = (struct r600_context *)ctx;
1216	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1217
1218	if (rstate == NULL)
1219		return;
1220
1221	rctx->viewport = *state;
1222	rstate->id = R600_PIPE_STATE_VIEWPORT;
1223	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1224	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1225	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1226	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1227	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1228	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1229
1230	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1231	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1232	r600_context_pipe_state_set(rctx, rstate);
1233}
1234
1235static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1236						       unsigned size, unsigned alignment)
1237{
1238	struct pipe_resource buffer;
1239
1240	memset(&buffer, 0, sizeof buffer);
1241	buffer.target = PIPE_BUFFER;
1242	buffer.format = PIPE_FORMAT_R8_UNORM;
1243	buffer.bind = PIPE_BIND_CUSTOM;
1244	buffer.usage = PIPE_USAGE_STATIC;
1245	buffer.flags = 0;
1246	buffer.width0 = size;
1247	buffer.height0 = 1;
1248	buffer.depth0 = 1;
1249	buffer.array_size = 1;
1250
1251	return (struct r600_resource*)
1252		r600_buffer_create(&rscreen->screen, &buffer, alignment);
1253}
1254
1255static void r600_init_color_surface(struct r600_context *rctx,
1256				    struct r600_surface *surf,
1257				    bool force_cmask_fmask)
1258{
1259	struct r600_screen *rscreen = rctx->screen;
1260	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1261	unsigned level = surf->base.u.tex.level;
1262	unsigned pitch, slice;
1263	unsigned color_info;
1264	unsigned format, swap, ntype, endian;
1265	unsigned offset;
1266	const struct util_format_description *desc;
1267	int i;
1268	bool blend_bypass = 0, blend_clamp = 1;
1269
1270	if (rtex->is_depth && !rtex->is_flushing_texture) {
1271		r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1272		rtex = rtex->flushed_depth_texture;
1273		assert(rtex);
1274	}
1275
1276	offset = rtex->surface.level[level].offset;
1277	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1278		offset += rtex->surface.level[level].slice_size *
1279			  surf->base.u.tex.first_layer;
1280	}
1281	pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1282	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1283	if (slice) {
1284		slice = slice - 1;
1285	}
1286	color_info = 0;
1287	switch (rtex->surface.level[level].mode) {
1288	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1289		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1290		break;
1291	case RADEON_SURF_MODE_1D:
1292		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1293		break;
1294	case RADEON_SURF_MODE_2D:
1295		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1296		break;
1297	case RADEON_SURF_MODE_LINEAR:
1298	default:
1299		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1300		break;
1301	}
1302
1303	desc = util_format_description(surf->base.format);
1304
1305	for (i = 0; i < 4; i++) {
1306		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1307			break;
1308		}
1309	}
1310
1311	ntype = V_0280A0_NUMBER_UNORM;
1312	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1313		ntype = V_0280A0_NUMBER_SRGB;
1314	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1315		if (desc->channel[i].normalized)
1316			ntype = V_0280A0_NUMBER_SNORM;
1317		else if (desc->channel[i].pure_integer)
1318			ntype = V_0280A0_NUMBER_SINT;
1319	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1320		if (desc->channel[i].normalized)
1321			ntype = V_0280A0_NUMBER_UNORM;
1322		else if (desc->channel[i].pure_integer)
1323			ntype = V_0280A0_NUMBER_UINT;
1324	}
1325
1326	format = r600_translate_colorformat(surf->base.format);
1327	assert(format != ~0);
1328
1329	swap = r600_translate_colorswap(surf->base.format);
1330	assert(swap != ~0);
1331
1332	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1333		endian = ENDIAN_NONE;
1334	} else {
1335		endian = r600_colorformat_endian_swap(format);
1336	}
1337
1338	/* set blend bypass according to docs if SINT/UINT or
1339	   8/24 COLOR variants */
1340	if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1341	    format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1342	    format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1343		blend_clamp = 0;
1344		blend_bypass = 1;
1345	}
1346
1347	surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1348
1349	color_info |= S_0280A0_FORMAT(format) |
1350		S_0280A0_COMP_SWAP(swap) |
1351		S_0280A0_BLEND_BYPASS(blend_bypass) |
1352		S_0280A0_BLEND_CLAMP(blend_clamp) |
1353		S_0280A0_NUMBER_TYPE(ntype) |
1354		S_0280A0_ENDIAN(endian);
1355
1356	/* EXPORT_NORM is an optimzation that can be enabled for better
1357	 * performance in certain cases
1358	 */
1359	if (rctx->chip_class == R600) {
1360		/* EXPORT_NORM can be enabled if:
1361		 * - 11-bit or smaller UNORM/SNORM/SRGB
1362		 * - BLEND_CLAMP is enabled
1363		 * - BLEND_FLOAT32 is disabled
1364		 */
1365		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1366		    (desc->channel[i].size < 12 &&
1367		     desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1368		     ntype != V_0280A0_NUMBER_UINT &&
1369		     ntype != V_0280A0_NUMBER_SINT) &&
1370		    G_0280A0_BLEND_CLAMP(color_info) &&
1371		    !G_0280A0_BLEND_FLOAT32(color_info)) {
1372			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1373			surf->export_16bpc = true;
1374		}
1375	} else {
1376		/* EXPORT_NORM can be enabled if:
1377		 * - 11-bit or smaller UNORM/SNORM/SRGB
1378		 * - 16-bit or smaller FLOAT
1379		 */
1380		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1381		    ((desc->channel[i].size < 12 &&
1382		      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1383		      ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1384		    (desc->channel[i].size < 17 &&
1385		     desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1386			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1387			surf->export_16bpc = true;
1388		}
1389	}
1390
1391	/* These might not always be initialized to zero. */
1392	surf->cb_color_base = offset >> 8;
1393	surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1394			      S_028060_SLICE_TILE_MAX(slice);
1395	surf->cb_color_fmask = surf->cb_color_base;
1396	surf->cb_color_cmask = surf->cb_color_base;
1397	surf->cb_color_mask = 0;
1398
1399	pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1400				&rtex->resource.b.b);
1401	pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1402				&rtex->resource.b.b);
1403
1404	if (rtex->cmask_size) {
1405		surf->cb_color_cmask = rtex->cmask_offset >> 8;
1406		surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1407
1408		if (rtex->fmask_size) {
1409			color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1410			surf->cb_color_fmask = rtex->fmask_offset >> 8;
1411			surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1412		} else { /* cmask only */
1413			color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1414		}
1415	} else if (force_cmask_fmask) {
1416		/* Allocate dummy FMASK and CMASK if they aren't allocated already.
1417		 *
1418		 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1419		 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1420		 * because it's not an MSAA buffer.
1421		 */
1422		struct r600_cmask_info cmask;
1423		struct r600_fmask_info fmask;
1424
1425		r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1426		r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1427
1428		/* CMASK. */
1429		if (!rctx->dummy_cmask ||
1430		    rctx->dummy_cmask->buf->size < cmask.size ||
1431		    rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1432			struct pipe_transfer *transfer;
1433			void *ptr;
1434
1435			pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1436			rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1437
1438			/* Set the contents to 0xCC. */
1439			ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1440			memset(ptr, 0xCC, cmask.size);
1441			pipe_buffer_unmap(&rctx->context, transfer);
1442		}
1443		pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1444					&rctx->dummy_cmask->b.b);
1445
1446		/* FMASK. */
1447		if (!rctx->dummy_fmask ||
1448		    rctx->dummy_fmask->buf->size < fmask.size ||
1449		    rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1450			pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1451			rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1452
1453		}
1454		pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1455					&rctx->dummy_fmask->b.b);
1456
1457		/* Init the registers. */
1458		color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1459		surf->cb_color_cmask = 0;
1460		surf->cb_color_fmask = 0;
1461		surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1462				      S_028100_FMASK_TILE_MAX(slice);
1463	}
1464
1465	surf->cb_color_info = color_info;
1466
1467	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1468		surf->cb_color_view = 0;
1469	} else {
1470		surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1471				      S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1472	}
1473
1474	surf->color_initialized = true;
1475}
1476
1477static void r600_init_depth_surface(struct r600_context *rctx,
1478				    struct r600_surface *surf)
1479{
1480	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1481	unsigned level, pitch, slice, format, offset, array_mode;
1482
1483	level = surf->base.u.tex.level;
1484	offset = rtex->surface.level[level].offset;
1485	pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1486	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1487	if (slice) {
1488		slice = slice - 1;
1489	}
1490	switch (rtex->surface.level[level].mode) {
1491	case RADEON_SURF_MODE_2D:
1492		array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1493		break;
1494	case RADEON_SURF_MODE_1D:
1495	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1496	case RADEON_SURF_MODE_LINEAR:
1497	default:
1498		array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1499		break;
1500	}
1501
1502	format = r600_translate_dbformat(surf->base.format);
1503	assert(format != ~0);
1504
1505	surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1506	surf->db_depth_base = offset >> 8;
1507	surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1508			      S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1509	surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1510	surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1511
1512	surf->depth_initialized = true;
1513}
1514
1515#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
1516	(((s0x) & 0xf) | (((s0y) & 0xf) << 4) |		   \
1517	(((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |	   \
1518	(((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |	   \
1519	 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1520
1521static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1522{
1523	static uint32_t sample_locs_2x[] = {
1524		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1525		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1526	};
1527	static unsigned max_dist_2x = 4;
1528	static uint32_t sample_locs_4x[] = {
1529		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1530		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1531	};
1532	static unsigned max_dist_4x = 6;
1533	static uint32_t sample_locs_8x[] = {
1534		FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1535		FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1536	};
1537	static unsigned max_dist_8x = 8;
1538	struct r600_context *rctx = (struct r600_context *)ctx;
1539
1540	if (rctx->family == CHIP_R600) {
1541		switch (nsample) {
1542		case 0:
1543		case 1:
1544			return 0;
1545		case 2:
1546			r600_pipe_state_add_reg(rstate, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1547			return max_dist_2x;
1548		case 4:
1549			r600_pipe_state_add_reg(rstate, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1550			return max_dist_4x;
1551		case 8:
1552			r600_pipe_state_add_reg(rstate, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, sample_locs_8x[0]);
1553			r600_pipe_state_add_reg(rstate, R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, sample_locs_8x[1]);
1554			return max_dist_8x;
1555		}
1556	} else {
1557		switch (nsample) {
1558		case 0:
1559		case 1:
1560			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0);
1561			r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, 0);
1562			return 0;
1563		case 2:
1564			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_2x[0]);
1565			r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_2x[1]);
1566			return max_dist_2x;
1567		case 4:
1568			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_4x[0]);
1569			r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_4x[1]);
1570			return max_dist_4x;
1571		case 8:
1572			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_8x[0]);
1573			r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_8x[1]);
1574			return max_dist_8x;
1575		}
1576	}
1577	R600_ERR("Invalid nr_samples %i\n", nsample);
1578	return 0;
1579}
1580
1581static void r600_set_framebuffer_state(struct pipe_context *ctx,
1582					const struct pipe_framebuffer_state *state)
1583{
1584	struct r600_context *rctx = (struct r600_context *)ctx;
1585	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1586	struct r600_surface *surf;
1587	struct r600_resource *res;
1588	struct r600_texture *rtex;
1589	uint32_t tl, br, i, nr_samples, max_dist;
1590	bool is_resolve = state->nr_cbufs == 2 &&
1591			  state->cbufs[0]->texture->nr_samples > 1 &&
1592		          state->cbufs[1]->texture->nr_samples <= 1;
1593	/* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1594	bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve;
1595
1596	if (rstate == NULL)
1597		return;
1598
1599	r600_flush_framebuffer(rctx, false);
1600
1601	/* unreference old buffer and reference new one */
1602	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1603
1604	util_copy_framebuffer_state(&rctx->framebuffer, state);
1605
1606	/* Colorbuffers. */
1607	rctx->export_16bpc = true;
1608	rctx->nr_cbufs = state->nr_cbufs;
1609	rctx->cb0_is_integer = state->nr_cbufs &&
1610			       util_format_is_pure_integer(state->cbufs[0]->format);
1611	rctx->compressed_cb_mask = 0;
1612
1613	for (i = 0; i < state->nr_cbufs; i++) {
1614		bool force_cmask_fmask = cb1_force_cmask_fmask && i == 1;
1615		surf = (struct r600_surface*)state->cbufs[i];
1616		res = (struct r600_resource*)surf->base.texture;
1617		rtex = (struct r600_texture*)res;
1618
1619		if (!surf->color_initialized || force_cmask_fmask) {
1620			r600_init_color_surface(rctx, surf, force_cmask_fmask);
1621			if (force_cmask_fmask) {
1622				/* re-initialize later without compression */
1623				surf->color_initialized = false;
1624			}
1625		}
1626
1627		if (!surf->export_16bpc) {
1628			rctx->export_16bpc = false;
1629		}
1630
1631		r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
1632					   surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1633		r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
1634					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1635		r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
1636					surf->cb_color_size);
1637		r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
1638					surf->cb_color_view);
1639		r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
1640					   surf->cb_color_fmask, surf->cb_buffer_fmask,
1641					   RADEON_USAGE_READWRITE);
1642		r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
1643					   surf->cb_color_cmask, surf->cb_buffer_cmask,
1644					   RADEON_USAGE_READWRITE);
1645		r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4,
1646					surf->cb_color_mask);
1647
1648		if (rtex->fmask_size && rtex->cmask_size) {
1649			rctx->compressed_cb_mask |= 1 << i;
1650		}
1651	}
1652	/* set CB_COLOR1_INFO for possible dual-src blending */
1653	if (i == 1) {
1654		r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
1655					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1656		i++;
1657	}
1658	for (; i < 8 ; i++) {
1659		r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0);
1660	}
1661
1662	/* Update alpha-test state dependencies.
1663	 * Alpha-test is done on the first colorbuffer only. */
1664	if (state->nr_cbufs) {
1665		surf = (struct r600_surface*)state->cbufs[0];
1666		if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1667			rctx->alphatest_state.bypass = surf->alphatest_bypass;
1668			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1669		}
1670	}
1671
1672	/* ZS buffer. */
1673	if (state->zsbuf) {
1674		surf = (struct r600_surface*)state->zsbuf;
1675		res = (struct r600_resource*)surf->base.texture;
1676
1677		if (!surf->depth_initialized) {
1678			r600_init_depth_surface(rctx, surf);
1679		}
1680
1681		r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
1682					   res, RADEON_USAGE_READWRITE);
1683		r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
1684		r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
1685		r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
1686					   res, RADEON_USAGE_READWRITE);
1687		r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1688	}
1689
1690	/* Framebuffer dimensions. */
1691	tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1692	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1693
1694	r600_pipe_state_add_reg(rstate,
1695				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1696	r600_pipe_state_add_reg(rstate,
1697				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1698
1699	/* If we're doing MSAA resolve... */
1700	if (is_resolve) {
1701		r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1);
1702	} else {
1703		/* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1704		 * will assure that the alpha-test will work even if there is
1705		 * no colorbuffer bound. */
1706		r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1707					(1ull << MAX2(state->nr_cbufs, 1)) - 1);
1708	}
1709
1710	/* Multisampling */
1711	if (state->nr_cbufs)
1712		nr_samples = state->cbufs[0]->texture->nr_samples;
1713	else if (state->zsbuf)
1714		nr_samples = state->zsbuf->texture->nr_samples;
1715	else
1716		nr_samples = 0;
1717
1718	max_dist = r600_set_ms_pos(ctx, rstate, nr_samples);
1719
1720	if (nr_samples > 1) {
1721		unsigned log_samples = util_logbase2(nr_samples);
1722
1723		r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL,
1724					S_028C00_LAST_PIXEL(1) |
1725					S_028C00_EXPAND_LINE_WIDTH(1));
1726		r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1727					S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1728					S_028C04_MAX_SAMPLE_DIST(max_dist));
1729	} else {
1730		r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1731		r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1732	}
1733
1734	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1735	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1736	r600_context_pipe_state_set(rctx, rstate);
1737
1738	if (state->zsbuf) {
1739		r600_polygon_offset_update(rctx);
1740	}
1741
1742	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1743		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1744		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1745	}
1746
1747	if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1748		rctx->alphatest_state.bypass = false;
1749		r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1750	}
1751}
1752
1753static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1754{
1755	struct radeon_winsys_cs *cs = rctx->cs;
1756	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1757
1758	if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1759		r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1760		if (rctx->chip_class == R600) {
1761			r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1762			r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1763		} else {
1764			r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1765			r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1766		}
1767		r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1768	} else {
1769		unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1770		unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1771		unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1772
1773		r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1774		r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1775		/* Always enable the first color output to make sure alpha-test works even without one. */
1776		r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1777		r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1778				       a->cb_color_control |
1779				       S_028808_MULTIWRITE_ENABLE(multiwrite));
1780	}
1781}
1782
1783static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1784{
1785	struct radeon_winsys_cs *cs = rctx->cs;
1786	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1787	unsigned db_render_control = 0;
1788	unsigned db_render_override =
1789		S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1790		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1791		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1792
1793	if (a->occlusion_query_enabled) {
1794		if (rctx->chip_class >= R700) {
1795			db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1796		}
1797		db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1798	}
1799	if (a->flush_depthstencil_through_cb) {
1800		assert(a->copy_depth || a->copy_stencil);
1801
1802		db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1803				     S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1804				     S_028D0C_COPY_CENTROID(1) |
1805				     S_028D0C_COPY_SAMPLE(a->copy_sample);
1806	}
1807
1808	r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1809	r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1810	r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1811}
1812
1813static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1814{
1815	struct radeon_winsys_cs *cs = rctx->cs;
1816	uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1817
1818	while (dirty_mask) {
1819		struct pipe_vertex_buffer *vb;
1820		struct r600_resource *rbuffer;
1821		unsigned offset;
1822		unsigned buffer_index = u_bit_scan(&dirty_mask);
1823
1824		vb = &rctx->vertex_buffer_state.vb[buffer_index];
1825		rbuffer = (struct r600_resource*)vb->buffer;
1826		assert(rbuffer);
1827
1828		offset = vb->buffer_offset;
1829
1830		/* fetch resources start at index 320 */
1831		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1832		r600_write_value(cs, (320 + buffer_index) * 7);
1833		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1834		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1835		r600_write_value(cs, /* RESOURCEi_WORD2 */
1836				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1837				 S_038008_STRIDE(vb->stride));
1838		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1839		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1840		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1841		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1842
1843		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1844		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1845	}
1846}
1847
1848static void r600_emit_constant_buffers(struct r600_context *rctx,
1849				       struct r600_constbuf_state *state,
1850				       unsigned buffer_id_base,
1851				       unsigned reg_alu_constbuf_size,
1852				       unsigned reg_alu_const_cache)
1853{
1854	struct radeon_winsys_cs *cs = rctx->cs;
1855	uint32_t dirty_mask = state->dirty_mask;
1856
1857	while (dirty_mask) {
1858		struct pipe_constant_buffer *cb;
1859		struct r600_resource *rbuffer;
1860		unsigned offset;
1861		unsigned buffer_index = ffs(dirty_mask) - 1;
1862
1863		cb = &state->cb[buffer_index];
1864		rbuffer = (struct r600_resource*)cb->buffer;
1865		assert(rbuffer);
1866
1867		offset = cb->buffer_offset;
1868
1869		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1870				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1871		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1872
1873		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1874		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1875
1876		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1877		r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1878		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1879		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1880		r600_write_value(cs, /* RESOURCEi_WORD2 */
1881				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1882				 S_038008_STRIDE(16));
1883		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1884		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1885		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1886		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1887
1888		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1889		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1890
1891		dirty_mask &= ~(1 << buffer_index);
1892	}
1893	state->dirty_mask = 0;
1894}
1895
1896static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1897{
1898	r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1899				   R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1900				   R_028980_ALU_CONST_CACHE_VS_0);
1901}
1902
1903static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1904{
1905	r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1906				   R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1907				   R_028940_ALU_CONST_CACHE_PS_0);
1908}
1909
1910static void r600_emit_sampler_views(struct r600_context *rctx,
1911				    struct r600_samplerview_state *state,
1912				    unsigned resource_id_base)
1913{
1914	struct radeon_winsys_cs *cs = rctx->cs;
1915	uint32_t dirty_mask = state->dirty_mask;
1916
1917	while (dirty_mask) {
1918		struct r600_pipe_sampler_view *rview;
1919		unsigned resource_index = u_bit_scan(&dirty_mask);
1920		unsigned reloc;
1921
1922		rview = state->views[resource_index];
1923		assert(rview);
1924
1925		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1926		r600_write_value(cs, (resource_id_base + resource_index) * 7);
1927		r600_write_array(cs, 7, rview->tex_resource_words);
1928
1929		/* XXX The kernel needs two relocations. This is stupid. */
1930		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1931					      RADEON_USAGE_READ);
1932		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1933		r600_write_value(cs, reloc);
1934		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1935		r600_write_value(cs, reloc);
1936	}
1937	state->dirty_mask = 0;
1938}
1939
1940static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1941{
1942	r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS);
1943}
1944
1945static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1946{
1947	r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1948}
1949
1950static void r600_emit_sampler(struct r600_context *rctx,
1951				struct r600_textures_info *texinfo,
1952				unsigned resource_id_base,
1953				unsigned border_color_reg)
1954{
1955	struct radeon_winsys_cs *cs = rctx->cs;
1956	unsigned i;
1957
1958	for (i = 0; i < texinfo->n_samplers; i++) {
1959
1960		if (texinfo->samplers[i] == NULL) {
1961			continue;
1962		}
1963
1964		/* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1965		 * filtering between layers.
1966		 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1967		 */
1968		if (texinfo->views.views[i]) {
1969			if (texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1970			    texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1971				texinfo->samplers[i]->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1972				texinfo->is_array_sampler[i] = true;
1973			} else {
1974				texinfo->samplers[i]->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1975				texinfo->is_array_sampler[i] = false;
1976			}
1977		}
1978
1979		r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1980		r600_write_value(cs, (resource_id_base + i) * 3);
1981		r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1982
1983		if (texinfo->samplers[i]->border_color_use) {
1984			unsigned offset;
1985
1986			offset = border_color_reg;
1987			offset += i * 16;
1988			r600_write_config_reg_seq(cs, offset, 4);
1989			r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
1990		}
1991	}
1992}
1993
1994static void r600_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
1995{
1996	r600_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1997}
1998
1999static void r600_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
2000{
2001	r600_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2002}
2003
2004static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2005{
2006	struct radeon_winsys_cs *cs = rctx->cs;
2007	unsigned tmp;
2008
2009	tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2010		S_009508_SYNC_GRADIENT(1) |
2011		S_009508_SYNC_WALKER(1) |
2012		S_009508_SYNC_ALIGNER(1);
2013	if (!rctx->seamless_cube_map.enabled) {
2014		tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2015	}
2016	r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2017}
2018
2019static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2020{
2021	struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2022	uint8_t mask = s->sample_mask;
2023
2024	r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2025			       mask | (mask << 8) | (mask << 16) | (mask << 24));
2026}
2027
2028void r600_init_state_functions(struct r600_context *rctx)
2029{
2030	r600_init_atom(&rctx->seamless_cube_map.atom, r600_emit_seamless_cube_map, 3, 0);
2031	r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
2032	r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
2033	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2034	r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
2035	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
2036	r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0);
2037	r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0);
2038	r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0);
2039	r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0);
2040	r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0);
2041	/* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2042	 * does not take effect
2043	 */
2044	r600_init_atom(&rctx->vs_samplers.atom_sampler, r600_emit_vs_sampler, 0, EMIT_EARLY);
2045	r600_init_atom(&rctx->ps_samplers.atom_sampler, r600_emit_ps_sampler, 0, EMIT_EARLY);
2046
2047	r600_init_atom(&rctx->sample_mask.atom, r600_emit_sample_mask, 3, 0);
2048	rctx->sample_mask.sample_mask = ~0;
2049	r600_atom_dirty(rctx, &rctx->sample_mask.atom);
2050
2051	rctx->context.create_blend_state = r600_create_blend_state;
2052	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2053	rctx->context.create_fs_state = r600_create_shader_state_ps;
2054	rctx->context.create_rasterizer_state = r600_create_rs_state;
2055	rctx->context.create_sampler_state = r600_create_sampler_state;
2056	rctx->context.create_sampler_view = r600_create_sampler_view;
2057	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
2058	rctx->context.create_vs_state = r600_create_shader_state_vs;
2059	rctx->context.bind_blend_state = r600_bind_blend_state;
2060	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2061	rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
2062	rctx->context.bind_fs_state = r600_bind_ps_shader;
2063	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
2064	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
2065	rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
2066	rctx->context.bind_vs_state = r600_bind_vs_shader;
2067	rctx->context.delete_blend_state = r600_delete_state;
2068	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
2069	rctx->context.delete_fs_state = r600_delete_ps_shader;
2070	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
2071	rctx->context.delete_sampler_state = r600_delete_sampler;
2072	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
2073	rctx->context.delete_vs_state = r600_delete_vs_shader;
2074	rctx->context.set_blend_color = r600_set_blend_color;
2075	rctx->context.set_clip_state = r600_set_clip_state;
2076	rctx->context.set_constant_buffer = r600_set_constant_buffer;
2077	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
2078	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2079	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2080	rctx->context.set_sample_mask = r600_set_sample_mask;
2081	rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
2082	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
2083	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
2084	rctx->context.set_index_buffer = r600_set_index_buffer;
2085	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
2086	rctx->context.set_viewport_state = r600_set_viewport_state;
2087	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
2088	rctx->context.texture_barrier = r600_texture_barrier;
2089	rctx->context.create_stream_output_target = r600_create_so_target;
2090	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
2091	rctx->context.set_stream_output_targets = r600_set_so_targets;
2092}
2093
2094/* Adjust GPR allocation on R6xx/R7xx */
2095void r600_adjust_gprs(struct r600_context *rctx)
2096{
2097	struct r600_pipe_state rstate;
2098	unsigned num_ps_gprs = rctx->default_ps_gprs;
2099	unsigned num_vs_gprs = rctx->default_vs_gprs;
2100	unsigned tmp;
2101	int diff;
2102
2103	/* XXX: Following call moved from r600_bind_[ps|vs]_shader,
2104	 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
2105	 * adjusting the GPR allocation?
2106	 * Do we need this if we aren't really changing config below? */
2107	r600_inval_shader_cache(rctx);
2108
2109	if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
2110	{
2111		diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2112		num_vs_gprs -= diff;
2113		num_ps_gprs += diff;
2114	}
2115
2116	if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2117	{
2118		diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2119		num_ps_gprs -= diff;
2120		num_vs_gprs += diff;
2121	}
2122
2123	tmp = 0;
2124	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2125	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2126	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2127	rstate.nregs = 0;
2128	r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2129
2130	r600_context_pipe_state_set(rctx, &rstate);
2131}
2132
2133void r600_init_atom_start_cs(struct r600_context *rctx)
2134{
2135	int ps_prio;
2136	int vs_prio;
2137	int gs_prio;
2138	int es_prio;
2139	int num_ps_gprs;
2140	int num_vs_gprs;
2141	int num_gs_gprs;
2142	int num_es_gprs;
2143	int num_temp_gprs;
2144	int num_ps_threads;
2145	int num_vs_threads;
2146	int num_gs_threads;
2147	int num_es_threads;
2148	int num_ps_stack_entries;
2149	int num_vs_stack_entries;
2150	int num_gs_stack_entries;
2151	int num_es_stack_entries;
2152	enum radeon_family family;
2153	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2154	uint32_t tmp;
2155
2156	r600_init_command_buffer(cb, 256, EMIT_EARLY);
2157
2158	/* R6xx requires this packet at the start of each command buffer */
2159	if (rctx->chip_class == R600) {
2160		r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2161		r600_store_value(cb, 0);
2162	}
2163	/* All asics require this one */
2164	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2165	r600_store_value(cb, 0x80000000);
2166	r600_store_value(cb, 0x80000000);
2167
2168	family = rctx->family;
2169	ps_prio = 0;
2170	vs_prio = 1;
2171	gs_prio = 2;
2172	es_prio = 3;
2173	switch (family) {
2174	case CHIP_R600:
2175		num_ps_gprs = 192;
2176		num_vs_gprs = 56;
2177		num_temp_gprs = 4;
2178		num_gs_gprs = 0;
2179		num_es_gprs = 0;
2180		num_ps_threads = 136;
2181		num_vs_threads = 48;
2182		num_gs_threads = 4;
2183		num_es_threads = 4;
2184		num_ps_stack_entries = 128;
2185		num_vs_stack_entries = 128;
2186		num_gs_stack_entries = 0;
2187		num_es_stack_entries = 0;
2188		break;
2189	case CHIP_RV630:
2190	case CHIP_RV635:
2191		num_ps_gprs = 84;
2192		num_vs_gprs = 36;
2193		num_temp_gprs = 4;
2194		num_gs_gprs = 0;
2195		num_es_gprs = 0;
2196		num_ps_threads = 144;
2197		num_vs_threads = 40;
2198		num_gs_threads = 4;
2199		num_es_threads = 4;
2200		num_ps_stack_entries = 40;
2201		num_vs_stack_entries = 40;
2202		num_gs_stack_entries = 32;
2203		num_es_stack_entries = 16;
2204		break;
2205	case CHIP_RV610:
2206	case CHIP_RV620:
2207	case CHIP_RS780:
2208	case CHIP_RS880:
2209	default:
2210		num_ps_gprs = 84;
2211		num_vs_gprs = 36;
2212		num_temp_gprs = 4;
2213		num_gs_gprs = 0;
2214		num_es_gprs = 0;
2215		num_ps_threads = 136;
2216		num_vs_threads = 48;
2217		num_gs_threads = 4;
2218		num_es_threads = 4;
2219		num_ps_stack_entries = 40;
2220		num_vs_stack_entries = 40;
2221		num_gs_stack_entries = 32;
2222		num_es_stack_entries = 16;
2223		break;
2224	case CHIP_RV670:
2225		num_ps_gprs = 144;
2226		num_vs_gprs = 40;
2227		num_temp_gprs = 4;
2228		num_gs_gprs = 0;
2229		num_es_gprs = 0;
2230		num_ps_threads = 136;
2231		num_vs_threads = 48;
2232		num_gs_threads = 4;
2233		num_es_threads = 4;
2234		num_ps_stack_entries = 40;
2235		num_vs_stack_entries = 40;
2236		num_gs_stack_entries = 32;
2237		num_es_stack_entries = 16;
2238		break;
2239	case CHIP_RV770:
2240		num_ps_gprs = 192;
2241		num_vs_gprs = 56;
2242		num_temp_gprs = 4;
2243		num_gs_gprs = 0;
2244		num_es_gprs = 0;
2245		num_ps_threads = 188;
2246		num_vs_threads = 60;
2247		num_gs_threads = 0;
2248		num_es_threads = 0;
2249		num_ps_stack_entries = 256;
2250		num_vs_stack_entries = 256;
2251		num_gs_stack_entries = 0;
2252		num_es_stack_entries = 0;
2253		break;
2254	case CHIP_RV730:
2255	case CHIP_RV740:
2256		num_ps_gprs = 84;
2257		num_vs_gprs = 36;
2258		num_temp_gprs = 4;
2259		num_gs_gprs = 0;
2260		num_es_gprs = 0;
2261		num_ps_threads = 188;
2262		num_vs_threads = 60;
2263		num_gs_threads = 0;
2264		num_es_threads = 0;
2265		num_ps_stack_entries = 128;
2266		num_vs_stack_entries = 128;
2267		num_gs_stack_entries = 0;
2268		num_es_stack_entries = 0;
2269		break;
2270	case CHIP_RV710:
2271		num_ps_gprs = 192;
2272		num_vs_gprs = 56;
2273		num_temp_gprs = 4;
2274		num_gs_gprs = 0;
2275		num_es_gprs = 0;
2276		num_ps_threads = 144;
2277		num_vs_threads = 48;
2278		num_gs_threads = 0;
2279		num_es_threads = 0;
2280		num_ps_stack_entries = 128;
2281		num_vs_stack_entries = 128;
2282		num_gs_stack_entries = 0;
2283		num_es_stack_entries = 0;
2284		break;
2285	}
2286
2287	rctx->default_ps_gprs = num_ps_gprs;
2288	rctx->default_vs_gprs = num_vs_gprs;
2289	rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2290
2291	/* SQ_CONFIG */
2292	tmp = 0;
2293	switch (family) {
2294	case CHIP_RV610:
2295	case CHIP_RV620:
2296	case CHIP_RS780:
2297	case CHIP_RS880:
2298	case CHIP_RV710:
2299		break;
2300	default:
2301		tmp |= S_008C00_VC_ENABLE(1);
2302		break;
2303	}
2304	tmp |= S_008C00_DX9_CONSTS(0);
2305	tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2306	tmp |= S_008C00_PS_PRIO(ps_prio);
2307	tmp |= S_008C00_VS_PRIO(vs_prio);
2308	tmp |= S_008C00_GS_PRIO(gs_prio);
2309	tmp |= S_008C00_ES_PRIO(es_prio);
2310	r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2311
2312	/* SQ_GPR_RESOURCE_MGMT_2 */
2313	tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2314	tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2315	r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2316	r600_store_value(cb, tmp);
2317
2318	/* SQ_THREAD_RESOURCE_MGMT */
2319	tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2320	tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2321	tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2322	tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2323	r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2324
2325	/* SQ_STACK_RESOURCE_MGMT_1 */
2326	tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2327	tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2328	r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2329
2330	/* SQ_STACK_RESOURCE_MGMT_2 */
2331	tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2332	tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2333	r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2334
2335	r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2336
2337	if (rctx->chip_class >= R700) {
2338		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2339		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2340		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2341		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2342	} else {
2343		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2344		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2345		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2346		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2347	}
2348	r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2349	r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2350	r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2351	r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2352	r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2353	r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2354	r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2355	r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2356	r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2357	r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2358
2359	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2360	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2361	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2362	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2363	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2364	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2365	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2366	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2367	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2368	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2369	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2370	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2371	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2372	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2373
2374	r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2375	r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2376	r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2377
2378	r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2379	r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2380	r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2381	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2382
2383	r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2384
2385	r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2386	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2387	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2388
2389	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2390
2391	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2392	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2393	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2394
2395	r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2396	r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2397	r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2398	r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2399
2400	r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2401	r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2402	r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2403
2404	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2405	r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2406
2407	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2408	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2409	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2410	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2411	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2412
2413	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2414	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2415	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2416
2417	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2418
2419	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2420	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2421
2422	if (rctx->chip_class >= R700) {
2423		r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2424	}
2425
2426	r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2427	r600_store_value(cb, 0x1000000);  /* R_028C30_CB_CLRCMP_CONTROL */
2428	r600_store_value(cb, 0);          /* R_028C34_CB_CLRCMP_SRC */
2429	r600_store_value(cb, 0xFF);       /* R_028C38_CB_CLRCMP_DST */
2430	r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2431
2432	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2433	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2434	r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2435
2436	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2437	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2438	r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2439
2440	r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2441	r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2442	r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2443
2444	r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2445	r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2446
2447	if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2448		r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2449	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2450	if (rctx->screen->has_streamout) {
2451		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2452	}
2453
2454	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2455	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2456}
2457
2458void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2459{
2460	struct r600_context *rctx = (struct r600_context *)ctx;
2461	struct r600_pipe_state *rstate = &shader->rstate;
2462	struct r600_shader *rshader = &shader->shader;
2463	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2464	int pos_index = -1, face_index = -1;
2465	unsigned tmp, sid, ufi = 0;
2466	int need_linear = 0;
2467	unsigned z_export = 0, stencil_export = 0;
2468
2469	rstate->nregs = 0;
2470
2471	for (i = 0; i < rshader->ninput; i++) {
2472		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2473			pos_index = i;
2474		if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2475			face_index = i;
2476
2477		sid = rshader->input[i].spi_sid;
2478
2479		tmp = S_028644_SEMANTIC(sid);
2480
2481		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2482			rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2483			(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2484				rctx->rasterizer && rctx->rasterizer->flatshade))
2485			tmp |= S_028644_FLAT_SHADE(1);
2486
2487		if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2488				rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2489			tmp |= S_028644_PT_SPRITE_TEX(1);
2490		}
2491
2492		if (rshader->input[i].centroid)
2493			tmp |= S_028644_SEL_CENTROID(1);
2494
2495		if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2496			need_linear = 1;
2497			tmp |= S_028644_SEL_LINEAR(1);
2498		}
2499
2500		r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2501				tmp);
2502	}
2503
2504	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2505	for (i = 0; i < rshader->noutput; i++) {
2506		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2507			z_export = 1;
2508		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2509			stencil_export = 1;
2510	}
2511	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2512	db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2513	if (rshader->uses_kill)
2514		db_shader_control |= S_02880C_KILL_ENABLE(1);
2515
2516	exports_ps = 0;
2517	for (i = 0; i < rshader->noutput; i++) {
2518		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2519		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2520			exports_ps |= 1;
2521		}
2522	}
2523	num_cout = rshader->nr_ps_color_exports;
2524	exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2525	if (!exports_ps) {
2526		/* always at least export 1 component per pixel */
2527		exports_ps = 2;
2528	}
2529
2530	shader->nr_ps_color_outputs = num_cout;
2531
2532	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2533				S_0286CC_PERSP_GRADIENT_ENA(1)|
2534				S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2535	spi_input_z = 0;
2536	if (pos_index != -1) {
2537		spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2538					S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2539					S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2540					S_0286CC_BARYC_SAMPLE_CNTL(1));
2541		spi_input_z |= 1;
2542	}
2543
2544	spi_ps_in_control_1 = 0;
2545	if (face_index != -1) {
2546		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2547			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2548	}
2549
2550	/* HW bug in original R600 */
2551	if (rctx->family == CHIP_R600)
2552		ufi = 1;
2553
2554	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2555	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2556	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2557	r600_pipe_state_add_reg_bo(rstate,
2558				   R_028840_SQ_PGM_START_PS,
2559				   0, shader->bo, RADEON_USAGE_READ);
2560	r600_pipe_state_add_reg(rstate,
2561				R_028850_SQ_PGM_RESOURCES_PS,
2562				S_028850_NUM_GPRS(rshader->bc.ngpr) |
2563				S_028850_STACK_SIZE(rshader->bc.nstack) |
2564				S_028850_UNCACHED_FIRST_INST(ufi));
2565	r600_pipe_state_add_reg(rstate,
2566				R_028854_SQ_PGM_EXPORTS_PS,
2567				exports_ps);
2568	/* only set some bits here, the other bits are set in the dsa state */
2569	shader->db_shader_control = db_shader_control;
2570	shader->ps_depth_export = z_export | stencil_export;
2571
2572	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2573	if (rctx->rasterizer)
2574		shader->flatshade = rctx->rasterizer->flatshade;
2575}
2576
2577void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2578{
2579	struct r600_context *rctx = (struct r600_context *)ctx;
2580	struct r600_pipe_state *rstate = &shader->rstate;
2581	struct r600_shader *rshader = &shader->shader;
2582	unsigned spi_vs_out_id[10] = {};
2583	unsigned i, tmp, nparams = 0;
2584
2585	/* clear previous register */
2586	rstate->nregs = 0;
2587
2588	for (i = 0; i < rshader->noutput; i++) {
2589		if (rshader->output[i].spi_sid) {
2590			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2591			spi_vs_out_id[nparams / 4] |= tmp;
2592			nparams++;
2593		}
2594	}
2595
2596	for (i = 0; i < 10; i++) {
2597		r600_pipe_state_add_reg(rstate,
2598					R_028614_SPI_VS_OUT_ID_0 + i * 4,
2599					spi_vs_out_id[i]);
2600	}
2601
2602	/* Certain attributes (position, psize, etc.) don't count as params.
2603	 * VS is required to export at least one param and r600_shader_from_tgsi()
2604	 * takes care of adding a dummy export.
2605	 */
2606	if (nparams < 1)
2607		nparams = 1;
2608
2609	r600_pipe_state_add_reg(rstate,
2610				R_0286C4_SPI_VS_OUT_CONFIG,
2611				S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2612	r600_pipe_state_add_reg(rstate,
2613				R_028868_SQ_PGM_RESOURCES_VS,
2614				S_028868_NUM_GPRS(rshader->bc.ngpr) |
2615				S_028868_STACK_SIZE(rshader->bc.nstack));
2616	r600_pipe_state_add_reg_bo(rstate,
2617			R_028858_SQ_PGM_START_VS,
2618			0, shader->bo, RADEON_USAGE_READ);
2619
2620	shader->pa_cl_vs_out_cntl =
2621		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2622		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2623		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2624		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2625}
2626
2627void r600_fetch_shader(struct pipe_context *ctx,
2628		       struct r600_vertex_element *ve)
2629{
2630	struct r600_pipe_state *rstate;
2631	struct r600_context *rctx = (struct r600_context *)ctx;
2632
2633	rstate = &ve->rstate;
2634	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2635	rstate->nregs = 0;
2636	r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2637				0,
2638				ve->fetch_shader, RADEON_USAGE_READ);
2639}
2640
2641void *r600_create_resolve_blend(struct r600_context *rctx)
2642{
2643	struct pipe_blend_state blend;
2644	struct r600_pipe_state *rstate;
2645	unsigned i;
2646
2647	memset(&blend, 0, sizeof(blend));
2648	blend.independent_blend_enable = true;
2649	for (i = 0; i < 2; i++) {
2650		blend.rt[i].colormask = 0xf;
2651		blend.rt[i].blend_enable = 1;
2652		blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2653		blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2654		blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2655		blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2656		blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2657		blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2658	}
2659	rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2660	return rstate;
2661}
2662
2663void *r700_create_resolve_blend(struct r600_context *rctx)
2664{
2665	struct pipe_blend_state blend;
2666	struct r600_pipe_state *rstate;
2667
2668	memset(&blend, 0, sizeof(blend));
2669	blend.independent_blend_enable = true;
2670	blend.rt[0].colormask = 0xf;
2671	rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2672	return rstate;
2673}
2674
2675void *r600_create_decompress_blend(struct r600_context *rctx)
2676{
2677	struct pipe_blend_state blend;
2678	struct r600_pipe_state *rstate;
2679
2680	memset(&blend, 0, sizeof(blend));
2681	blend.independent_blend_enable = true;
2682	blend.rt[0].colormask = 0xf;
2683	rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2684	return rstate;
2685}
2686
2687void *r600_create_db_flush_dsa(struct r600_context *rctx)
2688{
2689	struct pipe_depth_stencil_alpha_state dsa;
2690	boolean quirk = false;
2691
2692	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2693		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2694		quirk = true;
2695
2696	memset(&dsa, 0, sizeof(dsa));
2697
2698	if (quirk) {
2699		dsa.depth.enabled = 1;
2700		dsa.depth.func = PIPE_FUNC_LEQUAL;
2701		dsa.stencil[0].enabled = 1;
2702		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2703		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2704		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2705		dsa.stencil[0].writemask = 0xff;
2706	}
2707
2708	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2709}
2710
2711void r600_update_dual_export_state(struct r600_context * rctx)
2712{
2713	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2714			       !rctx->ps_shader->current->ps_depth_export;
2715	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2716				     S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2717
2718	if (db_shader_control != rctx->db_shader_control) {
2719		struct r600_pipe_state rstate;
2720
2721		rctx->db_shader_control = db_shader_control;
2722		rstate.nregs = 0;
2723		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2724		r600_context_pipe_state_set(rctx, &rstate);
2725	}
2726}
2727