r600_state.c revision 951ac46a6a0a901b53a518c8dcde734578cbf228 
1/*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23#include "r600_formats.h"
24#include "r600d.h"
25
26#include "pipe/p_shader_tokens.h"
27#include "util/u_pack_color.h"
28#include "util/u_memory.h"
29#include "util/u_framebuffer.h"
30#include "util/u_dual_blend.h"
31
32static uint32_t r600_translate_blend_function(int blend_func)
33{
34	switch (blend_func) {
35	case PIPE_BLEND_ADD:
36		return V_028804_COMB_DST_PLUS_SRC;
37	case PIPE_BLEND_SUBTRACT:
38		return V_028804_COMB_SRC_MINUS_DST;
39	case PIPE_BLEND_REVERSE_SUBTRACT:
40		return V_028804_COMB_DST_MINUS_SRC;
41	case PIPE_BLEND_MIN:
42		return V_028804_COMB_MIN_DST_SRC;
43	case PIPE_BLEND_MAX:
44		return V_028804_COMB_MAX_DST_SRC;
45	default:
46		R600_ERR("Unknown blend function %d\n", blend_func);
47		assert(0);
48		break;
49	}
50	return 0;
51}
52
53static uint32_t r600_translate_blend_factor(int blend_fact)
54{
55	switch (blend_fact) {
56	case PIPE_BLENDFACTOR_ONE:
57		return V_028804_BLEND_ONE;
58	case PIPE_BLENDFACTOR_SRC_COLOR:
59		return V_028804_BLEND_SRC_COLOR;
60	case PIPE_BLENDFACTOR_SRC_ALPHA:
61		return V_028804_BLEND_SRC_ALPHA;
62	case PIPE_BLENDFACTOR_DST_ALPHA:
63		return V_028804_BLEND_DST_ALPHA;
64	case PIPE_BLENDFACTOR_DST_COLOR:
65		return V_028804_BLEND_DST_COLOR;
66	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67		return V_028804_BLEND_SRC_ALPHA_SATURATE;
68	case PIPE_BLENDFACTOR_CONST_COLOR:
69		return V_028804_BLEND_CONST_COLOR;
70	case PIPE_BLENDFACTOR_CONST_ALPHA:
71		return V_028804_BLEND_CONST_ALPHA;
72	case PIPE_BLENDFACTOR_ZERO:
73		return V_028804_BLEND_ZERO;
74	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75		return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77		return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79		return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80	case PIPE_BLENDFACTOR_INV_DST_COLOR:
81		return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83		return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85		return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86	case PIPE_BLENDFACTOR_SRC1_COLOR:
87		return V_028804_BLEND_SRC1_COLOR;
88	case PIPE_BLENDFACTOR_SRC1_ALPHA:
89		return V_028804_BLEND_SRC1_ALPHA;
90	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91		return V_028804_BLEND_INV_SRC1_COLOR;
92	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93		return V_028804_BLEND_INV_SRC1_ALPHA;
94	default:
95		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96		assert(0);
97		break;
98	}
99	return 0;
100}
101
102static unsigned r600_tex_dim(unsigned dim)
103{
104	switch (dim) {
105	default:
106	case PIPE_TEXTURE_1D:
107		return V_038000_SQ_TEX_DIM_1D;
108	case PIPE_TEXTURE_1D_ARRAY:
109		return V_038000_SQ_TEX_DIM_1D_ARRAY;
110	case PIPE_TEXTURE_2D:
111	case PIPE_TEXTURE_RECT:
112		return V_038000_SQ_TEX_DIM_2D;
113	case PIPE_TEXTURE_2D_ARRAY:
114		return V_038000_SQ_TEX_DIM_2D_ARRAY;
115	case PIPE_TEXTURE_3D:
116		return V_038000_SQ_TEX_DIM_3D;
117	case PIPE_TEXTURE_CUBE:
118		return V_038000_SQ_TEX_DIM_CUBEMAP;
119	}
120}
121
122static uint32_t r600_translate_dbformat(enum pipe_format format)
123{
124	switch (format) {
125	case PIPE_FORMAT_Z16_UNORM:
126		return V_028010_DEPTH_16;
127	case PIPE_FORMAT_Z24X8_UNORM:
128		return V_028010_DEPTH_X8_24;
129	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
130		return V_028010_DEPTH_8_24;
131	case PIPE_FORMAT_Z32_FLOAT:
132		return V_028010_DEPTH_32_FLOAT;
133	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
134		return V_028010_DEPTH_X24_8_32_FLOAT;
135	default:
136		return ~0U;
137	}
138}
139
140static uint32_t r600_translate_colorswap(enum pipe_format format)
141{
142	switch (format) {
143	/* 8-bit buffers. */
144	case PIPE_FORMAT_A8_UNORM:
145	case PIPE_FORMAT_A8_SNORM:
146	case PIPE_FORMAT_A8_UINT:
147	case PIPE_FORMAT_A8_SINT:
148	case PIPE_FORMAT_A16_UNORM:
149	case PIPE_FORMAT_A16_SNORM:
150	case PIPE_FORMAT_A16_UINT:
151	case PIPE_FORMAT_A16_SINT:
152	case PIPE_FORMAT_A16_FLOAT:
153	case PIPE_FORMAT_A32_UINT:
154	case PIPE_FORMAT_A32_SINT:
155	case PIPE_FORMAT_A32_FLOAT:
156	case PIPE_FORMAT_R4A4_UNORM:
157		return V_0280A0_SWAP_ALT_REV;
158	case PIPE_FORMAT_I8_UNORM:
159	case PIPE_FORMAT_I8_SNORM:
160	case PIPE_FORMAT_I8_UINT:
161	case PIPE_FORMAT_I8_SINT:
162	case PIPE_FORMAT_L8_UNORM:
163	case PIPE_FORMAT_L8_SNORM:
164	case PIPE_FORMAT_L8_UINT:
165	case PIPE_FORMAT_L8_SINT:
166	case PIPE_FORMAT_L8_SRGB:
167	case PIPE_FORMAT_L16_UNORM:
168	case PIPE_FORMAT_L16_SNORM:
169	case PIPE_FORMAT_L16_UINT:
170	case PIPE_FORMAT_L16_SINT:
171	case PIPE_FORMAT_L16_FLOAT:
172	case PIPE_FORMAT_L32_UINT:
173	case PIPE_FORMAT_L32_SINT:
174	case PIPE_FORMAT_L32_FLOAT:
175	case PIPE_FORMAT_I16_UNORM:
176	case PIPE_FORMAT_I16_SNORM:
177	case PIPE_FORMAT_I16_UINT:
178	case PIPE_FORMAT_I16_SINT:
179	case PIPE_FORMAT_I16_FLOAT:
180	case PIPE_FORMAT_I32_UINT:
181	case PIPE_FORMAT_I32_SINT:
182	case PIPE_FORMAT_I32_FLOAT:
183	case PIPE_FORMAT_R8_UNORM:
184	case PIPE_FORMAT_R8_SNORM:
185	case PIPE_FORMAT_R8_UINT:
186	case PIPE_FORMAT_R8_SINT:
187		return V_0280A0_SWAP_STD;
188
189	case PIPE_FORMAT_L4A4_UNORM:
190	case PIPE_FORMAT_A4R4_UNORM:
191		return V_0280A0_SWAP_ALT;
192
193	/* 16-bit buffers. */
194	case PIPE_FORMAT_B5G6R5_UNORM:
195		return V_0280A0_SWAP_STD_REV;
196
197	case PIPE_FORMAT_B5G5R5A1_UNORM:
198	case PIPE_FORMAT_B5G5R5X1_UNORM:
199		return V_0280A0_SWAP_ALT;
200
201	case PIPE_FORMAT_B4G4R4A4_UNORM:
202	case PIPE_FORMAT_B4G4R4X4_UNORM:
203		return V_0280A0_SWAP_ALT;
204
205	case PIPE_FORMAT_Z16_UNORM:
206		return V_0280A0_SWAP_STD;
207
208	case PIPE_FORMAT_L8A8_UNORM:
209	case PIPE_FORMAT_L8A8_SNORM:
210	case PIPE_FORMAT_L8A8_UINT:
211	case PIPE_FORMAT_L8A8_SINT:
212	case PIPE_FORMAT_L8A8_SRGB:
213	case PIPE_FORMAT_L16A16_UNORM:
214	case PIPE_FORMAT_L16A16_SNORM:
215	case PIPE_FORMAT_L16A16_UINT:
216	case PIPE_FORMAT_L16A16_SINT:
217	case PIPE_FORMAT_L16A16_FLOAT:
218	case PIPE_FORMAT_L32A32_UINT:
219	case PIPE_FORMAT_L32A32_SINT:
220	case PIPE_FORMAT_L32A32_FLOAT:
221		return V_0280A0_SWAP_ALT;
222	case PIPE_FORMAT_R8G8_UNORM:
223	case PIPE_FORMAT_R8G8_SNORM:
224	case PIPE_FORMAT_R8G8_UINT:
225	case PIPE_FORMAT_R8G8_SINT:
226		return V_0280A0_SWAP_STD;
227
228	case PIPE_FORMAT_R16_UNORM:
229	case PIPE_FORMAT_R16_SNORM:
230	case PIPE_FORMAT_R16_UINT:
231	case PIPE_FORMAT_R16_SINT:
232	case PIPE_FORMAT_R16_FLOAT:
233		return V_0280A0_SWAP_STD;
234
235	/* 32-bit buffers. */
236
237	case PIPE_FORMAT_A8B8G8R8_SRGB:
238		return V_0280A0_SWAP_STD_REV;
239	case PIPE_FORMAT_B8G8R8A8_SRGB:
240		return V_0280A0_SWAP_ALT;
241
242	case PIPE_FORMAT_B8G8R8A8_UNORM:
243	case PIPE_FORMAT_B8G8R8X8_UNORM:
244		return V_0280A0_SWAP_ALT;
245
246	case PIPE_FORMAT_A8R8G8B8_UNORM:
247	case PIPE_FORMAT_X8R8G8B8_UNORM:
248		return V_0280A0_SWAP_ALT_REV;
249	case PIPE_FORMAT_R8G8B8A8_SNORM:
250	case PIPE_FORMAT_R8G8B8A8_UNORM:
251	case PIPE_FORMAT_R8G8B8X8_UNORM:
252	case PIPE_FORMAT_R8G8B8A8_SINT:
253	case PIPE_FORMAT_R8G8B8A8_UINT:
254		return V_0280A0_SWAP_STD;
255
256	case PIPE_FORMAT_A8B8G8R8_UNORM:
257	case PIPE_FORMAT_X8B8G8R8_UNORM:
258	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
259		return V_0280A0_SWAP_STD_REV;
260
261	case PIPE_FORMAT_Z24X8_UNORM:
262	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
263		return V_0280A0_SWAP_STD;
264
265	case PIPE_FORMAT_X8Z24_UNORM:
266	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
267		return V_0280A0_SWAP_STD;
268
269	case PIPE_FORMAT_R10G10B10A2_UNORM:
270	case PIPE_FORMAT_R10G10B10X2_SNORM:
271	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
272		return V_0280A0_SWAP_STD;
273
274	case PIPE_FORMAT_B10G10R10A2_UNORM:
275	case PIPE_FORMAT_B10G10R10A2_UINT:
276		return V_0280A0_SWAP_ALT;
277
278	case PIPE_FORMAT_R11G11B10_FLOAT:
279	case PIPE_FORMAT_R16G16_UNORM:
280	case PIPE_FORMAT_R16G16_SNORM:
281	case PIPE_FORMAT_R16G16_FLOAT:
282	case PIPE_FORMAT_R16G16_UINT:
283	case PIPE_FORMAT_R16G16_SINT:
284	case PIPE_FORMAT_R32_UINT:
285	case PIPE_FORMAT_R32_SINT:
286	case PIPE_FORMAT_R32_FLOAT:
287	case PIPE_FORMAT_Z32_FLOAT:
288		return V_0280A0_SWAP_STD;
289
290	/* 64-bit buffers. */
291	case PIPE_FORMAT_R32G32_FLOAT:
292	case PIPE_FORMAT_R32G32_UINT:
293	case PIPE_FORMAT_R32G32_SINT:
294	case PIPE_FORMAT_R16G16B16A16_UNORM:
295	case PIPE_FORMAT_R16G16B16A16_SNORM:
296	case PIPE_FORMAT_R16G16B16A16_UINT:
297	case PIPE_FORMAT_R16G16B16A16_SINT:
298	case PIPE_FORMAT_R16G16B16A16_FLOAT:
299	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
300
301	/* 128-bit buffers. */
302	case PIPE_FORMAT_R32G32B32A32_FLOAT:
303	case PIPE_FORMAT_R32G32B32A32_SNORM:
304	case PIPE_FORMAT_R32G32B32A32_UNORM:
305	case PIPE_FORMAT_R32G32B32A32_SINT:
306	case PIPE_FORMAT_R32G32B32A32_UINT:
307		return V_0280A0_SWAP_STD;
308	default:
309		R600_ERR("unsupported colorswap format %d\n", format);
310		return ~0U;
311	}
312	return ~0U;
313}
314
315static uint32_t r600_translate_colorformat(enum pipe_format format)
316{
317	switch (format) {
318	case PIPE_FORMAT_L4A4_UNORM:
319	case PIPE_FORMAT_R4A4_UNORM:
320	case PIPE_FORMAT_A4R4_UNORM:
321		return V_0280A0_COLOR_4_4;
322
323	/* 8-bit buffers. */
324	case PIPE_FORMAT_A8_UNORM:
325	case PIPE_FORMAT_A8_SNORM:
326	case PIPE_FORMAT_A8_UINT:
327	case PIPE_FORMAT_A8_SINT:
328	case PIPE_FORMAT_I8_UNORM:
329	case PIPE_FORMAT_I8_SNORM:
330	case PIPE_FORMAT_I8_UINT:
331	case PIPE_FORMAT_I8_SINT:
332	case PIPE_FORMAT_L8_UNORM:
333	case PIPE_FORMAT_L8_SNORM:
334	case PIPE_FORMAT_L8_UINT:
335	case PIPE_FORMAT_L8_SINT:
336	case PIPE_FORMAT_L8_SRGB:
337	case PIPE_FORMAT_R8_UNORM:
338	case PIPE_FORMAT_R8_SNORM:
339	case PIPE_FORMAT_R8_UINT:
340	case PIPE_FORMAT_R8_SINT:
341		return V_0280A0_COLOR_8;
342
343	/* 16-bit buffers. */
344	case PIPE_FORMAT_B5G6R5_UNORM:
345		return V_0280A0_COLOR_5_6_5;
346
347	case PIPE_FORMAT_B5G5R5A1_UNORM:
348	case PIPE_FORMAT_B5G5R5X1_UNORM:
349		return V_0280A0_COLOR_1_5_5_5;
350
351	case PIPE_FORMAT_B4G4R4A4_UNORM:
352	case PIPE_FORMAT_B4G4R4X4_UNORM:
353		return V_0280A0_COLOR_4_4_4_4;
354
355	case PIPE_FORMAT_Z16_UNORM:
356		return V_0280A0_COLOR_16;
357
358	case PIPE_FORMAT_L8A8_UNORM:
359	case PIPE_FORMAT_L8A8_SNORM:
360	case PIPE_FORMAT_L8A8_UINT:
361	case PIPE_FORMAT_L8A8_SINT:
362	case PIPE_FORMAT_L8A8_SRGB:
363	case PIPE_FORMAT_R8G8_UNORM:
364	case PIPE_FORMAT_R8G8_SNORM:
365	case PIPE_FORMAT_R8G8_UINT:
366	case PIPE_FORMAT_R8G8_SINT:
367		return V_0280A0_COLOR_8_8;
368
369	case PIPE_FORMAT_R16_UNORM:
370	case PIPE_FORMAT_R16_SNORM:
371	case PIPE_FORMAT_R16_UINT:
372	case PIPE_FORMAT_R16_SINT:
373	case PIPE_FORMAT_A16_UNORM:
374	case PIPE_FORMAT_A16_SNORM:
375	case PIPE_FORMAT_A16_UINT:
376	case PIPE_FORMAT_A16_SINT:
377	case PIPE_FORMAT_L16_UNORM:
378	case PIPE_FORMAT_L16_SNORM:
379	case PIPE_FORMAT_L16_UINT:
380	case PIPE_FORMAT_L16_SINT:
381	case PIPE_FORMAT_I16_UNORM:
382	case PIPE_FORMAT_I16_SNORM:
383	case PIPE_FORMAT_I16_UINT:
384	case PIPE_FORMAT_I16_SINT:
385		return V_0280A0_COLOR_16;
386
387	case PIPE_FORMAT_R16_FLOAT:
388	case PIPE_FORMAT_A16_FLOAT:
389	case PIPE_FORMAT_L16_FLOAT:
390	case PIPE_FORMAT_I16_FLOAT:
391		return V_0280A0_COLOR_16_FLOAT;
392
393	/* 32-bit buffers. */
394	case PIPE_FORMAT_A8B8G8R8_SRGB:
395	case PIPE_FORMAT_A8B8G8R8_UNORM:
396	case PIPE_FORMAT_A8R8G8B8_UNORM:
397	case PIPE_FORMAT_B8G8R8A8_SRGB:
398	case PIPE_FORMAT_B8G8R8A8_UNORM:
399	case PIPE_FORMAT_B8G8R8X8_UNORM:
400	case PIPE_FORMAT_R8G8B8A8_SNORM:
401	case PIPE_FORMAT_R8G8B8A8_UNORM:
402	case PIPE_FORMAT_R8G8B8X8_UNORM:
403	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
404	case PIPE_FORMAT_X8B8G8R8_UNORM:
405	case PIPE_FORMAT_X8R8G8B8_UNORM:
406	case PIPE_FORMAT_R8G8B8A8_SINT:
407	case PIPE_FORMAT_R8G8B8A8_UINT:
408		return V_0280A0_COLOR_8_8_8_8;
409
410	case PIPE_FORMAT_R10G10B10A2_UNORM:
411	case PIPE_FORMAT_R10G10B10X2_SNORM:
412	case PIPE_FORMAT_B10G10R10A2_UNORM:
413	case PIPE_FORMAT_B10G10R10A2_UINT:
414	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
415		return V_0280A0_COLOR_2_10_10_10;
416
417	case PIPE_FORMAT_Z24X8_UNORM:
418	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
419		return V_0280A0_COLOR_8_24;
420
421	case PIPE_FORMAT_X8Z24_UNORM:
422	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
423		return V_0280A0_COLOR_24_8;
424
425	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
426		return V_0280A0_COLOR_X24_8_32_FLOAT;
427
428	case PIPE_FORMAT_R32_UINT:
429	case PIPE_FORMAT_R32_SINT:
430	case PIPE_FORMAT_A32_UINT:
431	case PIPE_FORMAT_A32_SINT:
432	case PIPE_FORMAT_L32_UINT:
433	case PIPE_FORMAT_L32_SINT:
434	case PIPE_FORMAT_I32_UINT:
435	case PIPE_FORMAT_I32_SINT:
436		return V_0280A0_COLOR_32;
437
438	case PIPE_FORMAT_R32_FLOAT:
439	case PIPE_FORMAT_A32_FLOAT:
440	case PIPE_FORMAT_L32_FLOAT:
441	case PIPE_FORMAT_I32_FLOAT:
442	case PIPE_FORMAT_Z32_FLOAT:
443		return V_0280A0_COLOR_32_FLOAT;
444
445	case PIPE_FORMAT_R16G16_FLOAT:
446	case PIPE_FORMAT_L16A16_FLOAT:
447		return V_0280A0_COLOR_16_16_FLOAT;
448
449	case PIPE_FORMAT_R16G16_UNORM:
450	case PIPE_FORMAT_R16G16_SNORM:
451	case PIPE_FORMAT_R16G16_UINT:
452	case PIPE_FORMAT_R16G16_SINT:
453	case PIPE_FORMAT_L16A16_UNORM:
454	case PIPE_FORMAT_L16A16_SNORM:
455	case PIPE_FORMAT_L16A16_UINT:
456	case PIPE_FORMAT_L16A16_SINT:
457		return V_0280A0_COLOR_16_16;
458
459	case PIPE_FORMAT_R11G11B10_FLOAT:
460		return V_0280A0_COLOR_10_11_11_FLOAT;
461
462	/* 64-bit buffers. */
463	case PIPE_FORMAT_R16G16B16A16_UINT:
464	case PIPE_FORMAT_R16G16B16A16_SINT:
465	case PIPE_FORMAT_R16G16B16A16_UNORM:
466	case PIPE_FORMAT_R16G16B16A16_SNORM:
467		return V_0280A0_COLOR_16_16_16_16;
468
469	case PIPE_FORMAT_R16G16B16A16_FLOAT:
470		return V_0280A0_COLOR_16_16_16_16_FLOAT;
471
472	case PIPE_FORMAT_R32G32_FLOAT:
473	case PIPE_FORMAT_L32A32_FLOAT:
474		return V_0280A0_COLOR_32_32_FLOAT;
475
476	case PIPE_FORMAT_R32G32_SINT:
477	case PIPE_FORMAT_R32G32_UINT:
478	case PIPE_FORMAT_L32A32_UINT:
479	case PIPE_FORMAT_L32A32_SINT:
480		return V_0280A0_COLOR_32_32;
481
482	/* 128-bit buffers. */
483	case PIPE_FORMAT_R32G32B32A32_FLOAT:
484		return V_0280A0_COLOR_32_32_32_32_FLOAT;
485	case PIPE_FORMAT_R32G32B32A32_SNORM:
486	case PIPE_FORMAT_R32G32B32A32_UNORM:
487	case PIPE_FORMAT_R32G32B32A32_SINT:
488	case PIPE_FORMAT_R32G32B32A32_UINT:
489		return V_0280A0_COLOR_32_32_32_32;
490
491	/* YUV buffers. */
492	case PIPE_FORMAT_UYVY:
493	case PIPE_FORMAT_YUYV:
494	default:
495		return ~0U; /* Unsupported. */
496	}
497}
498
499static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
500{
501	if (R600_BIG_ENDIAN) {
502		switch(colorformat) {
503		case V_0280A0_COLOR_4_4:
504			return ENDIAN_NONE;
505
506		/* 8-bit buffers. */
507		case V_0280A0_COLOR_8:
508			return ENDIAN_NONE;
509
510		/* 16-bit buffers. */
511		case V_0280A0_COLOR_5_6_5:
512		case V_0280A0_COLOR_1_5_5_5:
513		case V_0280A0_COLOR_4_4_4_4:
514		case V_0280A0_COLOR_16:
515		case V_0280A0_COLOR_8_8:
516			return ENDIAN_8IN16;
517
518		/* 32-bit buffers. */
519		case V_0280A0_COLOR_8_8_8_8:
520		case V_0280A0_COLOR_2_10_10_10:
521		case V_0280A0_COLOR_8_24:
522		case V_0280A0_COLOR_24_8:
523		case V_0280A0_COLOR_32_FLOAT:
524		case V_0280A0_COLOR_16_16_FLOAT:
525		case V_0280A0_COLOR_16_16:
526			return ENDIAN_8IN32;
527
528		/* 64-bit buffers. */
529		case V_0280A0_COLOR_16_16_16_16:
530		case V_0280A0_COLOR_16_16_16_16_FLOAT:
531			return ENDIAN_8IN16;
532
533		case V_0280A0_COLOR_32_32_FLOAT:
534		case V_0280A0_COLOR_32_32:
535		case V_0280A0_COLOR_X24_8_32_FLOAT:
536			return ENDIAN_8IN32;
537
538		/* 128-bit buffers. */
539		case V_0280A0_COLOR_32_32_32_FLOAT:
540		case V_0280A0_COLOR_32_32_32_32_FLOAT:
541		case V_0280A0_COLOR_32_32_32_32:
542			return ENDIAN_8IN32;
543		default:
544			return ENDIAN_NONE; /* Unsupported. */
545		}
546	} else {
547		return ENDIAN_NONE;
548	}
549}
550
551static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
552{
553	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
554}
555
556static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
557{
558	return r600_translate_colorformat(format) != ~0U &&
559	       r600_translate_colorswap(format) != ~0U;
560}
561
562static bool r600_is_zs_format_supported(enum pipe_format format)
563{
564	return r600_translate_dbformat(format) != ~0U;
565}
566
567boolean r600_is_format_supported(struct pipe_screen *screen,
568				 enum pipe_format format,
569				 enum pipe_texture_target target,
570				 unsigned sample_count,
571				 unsigned usage)
572{
573	unsigned retval = 0;
574
575	if (target >= PIPE_MAX_TEXTURE_TYPES) {
576		R600_ERR("r600: unsupported texture type %d\n", target);
577		return FALSE;
578	}
579
580	if (!util_format_is_supported(format, usage))
581		return FALSE;
582
583	/* Multisample */
584	if (sample_count > 1)
585		return FALSE;
586
587	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
588	    r600_is_sampler_format_supported(screen, format)) {
589		retval |= PIPE_BIND_SAMPLER_VIEW;
590	}
591
592	if ((usage & (PIPE_BIND_RENDER_TARGET |
593		      PIPE_BIND_DISPLAY_TARGET |
594		      PIPE_BIND_SCANOUT |
595		      PIPE_BIND_SHARED)) &&
596	    r600_is_colorbuffer_format_supported(format)) {
597		retval |= usage &
598			  (PIPE_BIND_RENDER_TARGET |
599			   PIPE_BIND_DISPLAY_TARGET |
600			   PIPE_BIND_SCANOUT |
601			   PIPE_BIND_SHARED);
602	}
603
604	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
605	    r600_is_zs_format_supported(format)) {
606		retval |= PIPE_BIND_DEPTH_STENCIL;
607	}
608
609	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
610	    r600_is_vertex_format_supported(format)) {
611		retval |= PIPE_BIND_VERTEX_BUFFER;
612	}
613
614	if (usage & PIPE_BIND_TRANSFER_READ)
615		retval |= PIPE_BIND_TRANSFER_READ;
616	if (usage & PIPE_BIND_TRANSFER_WRITE)
617		retval |= PIPE_BIND_TRANSFER_WRITE;
618
619	return retval == usage;
620}
621
622void r600_polygon_offset_update(struct r600_context *rctx)
623{
624	struct r600_pipe_state state;
625
626	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
627	state.nregs = 0;
628	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
629		float offset_units = rctx->rasterizer->offset_units;
630		unsigned offset_db_fmt_cntl = 0, depth;
631
632		switch (rctx->framebuffer.zsbuf->format) {
633		case PIPE_FORMAT_Z24X8_UNORM:
634		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
635			depth = -24;
636			offset_units *= 2.0f;
637			break;
638		case PIPE_FORMAT_Z32_FLOAT:
639		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
640			depth = -23;
641			offset_units *= 1.0f;
642			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
643			break;
644		case PIPE_FORMAT_Z16_UNORM:
645			depth = -16;
646			offset_units *= 4.0f;
647			break;
648		default:
649			return;
650		}
651		/* XXX some of those reg can be computed with cso */
652		offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
653		r600_pipe_state_add_reg(&state,
654				R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
655				fui(rctx->rasterizer->offset_scale));
656		r600_pipe_state_add_reg(&state,
657				R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
658				fui(offset_units));
659		r600_pipe_state_add_reg(&state,
660				R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
661				fui(rctx->rasterizer->offset_scale));
662		r600_pipe_state_add_reg(&state,
663				R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
664				fui(offset_units));
665		r600_pipe_state_add_reg(&state,
666				R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
667				offset_db_fmt_cntl);
668		r600_context_pipe_state_set(rctx, &state);
669	}
670}
671
672static void *r600_create_blend_state(struct pipe_context *ctx,
673					const struct pipe_blend_state *state)
674{
675	struct r600_context *rctx = (struct r600_context *)ctx;
676	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
677	struct r600_pipe_state *rstate;
678	uint32_t color_control = 0, target_mask;
679
680	if (blend == NULL) {
681		return NULL;
682	}
683	rstate = &blend->rstate;
684
685	rstate->id = R600_PIPE_STATE_BLEND;
686
687	target_mask = 0;
688
689	/* R600 does not support per-MRT blends */
690	if (rctx->family > CHIP_R600)
691		color_control |= S_028808_PER_MRT_BLEND(1);
692	if (state->logicop_enable) {
693		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
694	} else {
695		color_control |= (0xcc << 16);
696	}
697	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
698	if (state->independent_blend_enable) {
699		for (int i = 0; i < 8; i++) {
700			if (state->rt[i].blend_enable) {
701				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
702			}
703			target_mask |= (state->rt[i].colormask << (4 * i));
704		}
705	} else {
706		for (int i = 0; i < 8; i++) {
707			if (state->rt[0].blend_enable) {
708				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
709			}
710			target_mask |= (state->rt[0].colormask << (4 * i));
711		}
712	}
713
714	if (target_mask)
715		color_control |= S_028808_SPECIAL_OP(V_028808_NORMAL);
716	else
717		color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
718
719	blend->cb_target_mask = target_mask;
720	blend->cb_color_control = color_control;
721	/* only MRT0 has dual src blend */
722	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
723	for (int i = 0; i < 8; i++) {
724		/* state->rt entries > 0 only written if independent blending */
725		const int j = state->independent_blend_enable ? i : 0;
726
727		unsigned eqRGB = state->rt[j].rgb_func;
728		unsigned srcRGB = state->rt[j].rgb_src_factor;
729		unsigned dstRGB = state->rt[j].rgb_dst_factor;
730
731		unsigned eqA = state->rt[j].alpha_func;
732		unsigned srcA = state->rt[j].alpha_src_factor;
733		unsigned dstA = state->rt[j].alpha_dst_factor;
734		uint32_t bc = 0;
735
736		if (!state->rt[j].blend_enable)
737			continue;
738
739		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
740		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
741		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
742
743		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
744			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
745			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
746			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
747			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
748		}
749
750		/* R600 does not support per-MRT blends */
751		if (rctx->family > CHIP_R600)
752			r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
753		if (i == 0)
754			r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
755	}
756
757	r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
758				S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
759				S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
760				S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
761				S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
762				S_028D44_ALPHA_TO_MASK_OFFSET3(2));
763
764	blend->alpha_to_one = state->alpha_to_one;
765	return rstate;
766}
767
768static void *r600_create_dsa_state(struct pipe_context *ctx,
769				   const struct pipe_depth_stencil_alpha_state *state)
770{
771	struct r600_context *rctx = (struct r600_context *)ctx;
772	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
773	unsigned db_depth_control, alpha_test_control, alpha_ref;
774	struct r600_pipe_state *rstate;
775
776	if (dsa == NULL) {
777		return NULL;
778	}
779
780	dsa->valuemask[0] = state->stencil[0].valuemask;
781	dsa->valuemask[1] = state->stencil[1].valuemask;
782	dsa->writemask[0] = state->stencil[0].writemask;
783	dsa->writemask[1] = state->stencil[1].writemask;
784
785	rstate = &dsa->rstate;
786
787	rstate->id = R600_PIPE_STATE_DSA;
788	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
789		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
790		S_028800_ZFUNC(state->depth.func);
791
792	/* stencil */
793	if (state->stencil[0].enabled) {
794		db_depth_control |= S_028800_STENCIL_ENABLE(1);
795		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
796		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
797		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
798		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
799
800		if (state->stencil[1].enabled) {
801			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
802			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
803			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
804			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
805			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
806		}
807	}
808
809	/* alpha */
810	alpha_test_control = 0;
811	alpha_ref = 0;
812	if (state->alpha.enabled) {
813		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
814		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
815		alpha_ref = fui(state->alpha.ref_value);
816	}
817	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
818	dsa->alpha_ref = alpha_ref;
819
820	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
821	return rstate;
822}
823
824static void *r600_create_rs_state(struct pipe_context *ctx,
825				  const struct pipe_rasterizer_state *state)
826{
827	struct r600_context *rctx = (struct r600_context *)ctx;
828	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
829	struct r600_pipe_state *rstate;
830	unsigned tmp;
831	unsigned prov_vtx = 1, polygon_dual_mode;
832	unsigned sc_mode_cntl;
833	float psize_min, psize_max;
834
835	if (rs == NULL) {
836		return NULL;
837	}
838
839	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
840				state->fill_back != PIPE_POLYGON_MODE_FILL);
841
842	if (state->flatshade_first)
843		prov_vtx = 0;
844
845	rstate = &rs->rstate;
846	rs->flatshade = state->flatshade;
847	rs->sprite_coord_enable = state->sprite_coord_enable;
848	rs->two_side = state->light_twoside;
849	rs->clip_plane_enable = state->clip_plane_enable;
850	rs->pa_sc_line_stipple = state->line_stipple_enable ?
851				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
852				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
853	rs->pa_cl_clip_cntl =
854		S_028810_PS_UCP_MODE(3) |
855		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
856		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
857		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
858	rs->multisample_enable = state->multisample;
859
860	/* offset */
861	rs->offset_units = state->offset_units;
862	rs->offset_scale = state->offset_scale * 12.0f;
863
864	rstate->id = R600_PIPE_STATE_RASTERIZER;
865	tmp = S_0286D4_FLAT_SHADE_ENA(1);
866	if (state->sprite_coord_enable) {
867		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
868			S_0286D4_PNT_SPRITE_OVRD_X(2) |
869			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
870			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
871			S_0286D4_PNT_SPRITE_OVRD_W(1);
872		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
873			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
874		}
875	}
876	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
877
878	/* point size 12.4 fixed point */
879	tmp = r600_pack_float_12p4(state->point_size/2);
880	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
881
882	if (state->point_size_per_vertex) {
883		psize_min = util_get_min_point_size(state);
884		psize_max = 8192;
885	} else {
886		/* Force the point size to be as if the vertex output was disabled. */
887		psize_min = state->point_size;
888		psize_max = state->point_size;
889	}
890	/* Divide by two, because 0.5 = 1 pixel. */
891	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
892				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
893				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
894
895	tmp = r600_pack_float_12p4(state->line_width/2);
896	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
897
898	if (rctx->chip_class >= R700) {
899		sc_mode_cntl =
900			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
901			S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
902			S_028A4C_R700_ZMM_LINE_OFFSET(1) |
903			S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
904	} else {
905		sc_mode_cntl =
906			S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
907			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
908		rs->scissor_enable = state->scissor;
909	}
910	sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
911
912	r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
913
914	r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
915				S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
916
917	r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
918	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
919				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
920				S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
921				S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
922				S_028814_FACE(!state->front_ccw) |
923				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
924				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
925				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
926				S_028814_POLY_MODE(polygon_dual_mode) |
927				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
928				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
929	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
930	return rstate;
931}
932
933static void *r600_create_sampler_state(struct pipe_context *ctx,
934					const struct pipe_sampler_state *state)
935{
936	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
937	union util_color uc;
938	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
939
940	if (ss == NULL) {
941		return NULL;
942	}
943
944	ss->seamless_cube_map = state->seamless_cube_map;
945	ss->border_color_use = false;
946	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
947	/* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
948	ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
949				S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
950				S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
951				S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
952				S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
953				S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
954				S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
955				S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
956				S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
957	/* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
958	ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
959				S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
960				S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
961	/* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
962	ss->tex_sampler_words[2] = S_03C008_TYPE(1);
963	if (uc.ui) {
964		ss->border_color_use = true;
965		/* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
966		ss->border_color[0] = fui(state->border_color.f[0]);
967		/* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
968		ss->border_color[1] = fui(state->border_color.f[1]);
969		/* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
970		ss->border_color[2] = fui(state->border_color.f[2]);
971		/* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
972		ss->border_color[3] = fui(state->border_color.f[3]);
973	}
974	return ss;
975}
976
977static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
978							struct pipe_resource *texture,
979							const struct pipe_sampler_view *state)
980{
981	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
982	struct r600_texture *tmp = (struct r600_texture*)texture;
983	unsigned format, endian;
984	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
985	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
986	unsigned width, height, depth, offset_level, last_level;
987
988	if (view == NULL)
989		return NULL;
990
991	/* initialize base object */
992	view->base = *state;
993	view->base.texture = NULL;
994	pipe_reference(NULL, &texture->reference);
995	view->base.texture = texture;
996	view->base.reference.count = 1;
997	view->base.context = ctx;
998
999	swizzle[0] = state->swizzle_r;
1000	swizzle[1] = state->swizzle_g;
1001	swizzle[2] = state->swizzle_b;
1002	swizzle[3] = state->swizzle_a;
1003
1004	format = r600_translate_texformat(ctx->screen, state->format,
1005					  swizzle,
1006					  &word4, &yuv_format);
1007	assert(format != ~0);
1008	if (format == ~0) {
1009		FREE(view);
1010		return NULL;
1011	}
1012
1013	if (tmp->is_depth && !tmp->is_flushing_texture) {
1014		if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1015			FREE(view);
1016			return NULL;
1017		}
1018		tmp = tmp->flushed_depth_texture;
1019	}
1020
1021	endian = r600_colorformat_endian_swap(format);
1022
1023	offset_level = state->u.tex.first_level;
1024	last_level = state->u.tex.last_level - offset_level;
1025	width = tmp->surface.level[offset_level].npix_x;
1026	height = tmp->surface.level[offset_level].npix_y;
1027	depth = tmp->surface.level[offset_level].npix_z;
1028	pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1029	tile_type = tmp->tile_type;
1030
1031	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1032		height = 1;
1033		depth = texture->array_size;
1034	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1035		depth = texture->array_size;
1036	}
1037	switch (tmp->surface.level[offset_level].mode) {
1038	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1039		array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1040		break;
1041	case RADEON_SURF_MODE_1D:
1042		array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1043		break;
1044	case RADEON_SURF_MODE_2D:
1045		array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1046		break;
1047	case RADEON_SURF_MODE_LINEAR:
1048	default:
1049		array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1050		break;
1051	}
1052
1053	view->tex_resource = &tmp->resource;
1054	view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1055				       S_038000_TILE_MODE(array_mode) |
1056				       S_038000_TILE_TYPE(tile_type) |
1057				       S_038000_PITCH((pitch / 8) - 1) |
1058				       S_038000_TEX_WIDTH(width - 1));
1059	view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1060				       S_038004_TEX_DEPTH(depth - 1) |
1061				       S_038004_DATA_FORMAT(format));
1062	view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1063	if (offset_level >= tmp->surface.last_level) {
1064		view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1065	} else {
1066		view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1067	}
1068	view->tex_resource_words[4] = (word4 |
1069				       S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1070				       S_038010_REQUEST_SIZE(1) |
1071				       S_038010_ENDIAN_SWAP(endian) |
1072				       S_038010_BASE_LEVEL(0));
1073	view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) |
1074				       S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1075				       S_038014_LAST_ARRAY(state->u.tex.last_layer));
1076	view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1077				       S_038018_MAX_ANISO(4 /* max 16 samples */));
1078	return &view->base;
1079}
1080
1081static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1082				      struct pipe_sampler_view **views)
1083{
1084	r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
1085}
1086
1087static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1088				      struct pipe_sampler_view **views)
1089{
1090	r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
1091}
1092
1093static void r600_set_clip_state(struct pipe_context *ctx,
1094				const struct pipe_clip_state *state)
1095{
1096	struct r600_context *rctx = (struct r600_context *)ctx;
1097	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1098	struct pipe_constant_buffer cb;
1099
1100	if (rstate == NULL)
1101		return;
1102
1103	rctx->clip = *state;
1104	rstate->id = R600_PIPE_STATE_CLIP;
1105	for (int i = 0; i < 6; i++) {
1106		r600_pipe_state_add_reg(rstate,
1107					R_028E20_PA_CL_UCP0_X + i * 16,
1108					fui(state->ucp[i][0]));
1109		r600_pipe_state_add_reg(rstate,
1110					R_028E24_PA_CL_UCP0_Y + i * 16,
1111					fui(state->ucp[i][1]) );
1112		r600_pipe_state_add_reg(rstate,
1113					R_028E28_PA_CL_UCP0_Z + i * 16,
1114					fui(state->ucp[i][2]));
1115		r600_pipe_state_add_reg(rstate,
1116					R_028E2C_PA_CL_UCP0_W + i * 16,
1117					fui(state->ucp[i][3]));
1118	}
1119
1120	free(rctx->states[R600_PIPE_STATE_CLIP]);
1121	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1122	r600_context_pipe_state_set(rctx, rstate);
1123
1124	cb.buffer = NULL;
1125	cb.user_buffer = state->ucp;
1126	cb.buffer_offset = 0;
1127	cb.buffer_size = 4*4*8;
1128	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1129	pipe_resource_reference(&cb.buffer, NULL);
1130}
1131
1132static void r600_set_polygon_stipple(struct pipe_context *ctx,
1133					 const struct pipe_poly_stipple *state)
1134{
1135}
1136
1137void r600_set_scissor_state(struct r600_context *rctx,
1138			    const struct pipe_scissor_state *state)
1139{
1140	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1141	uint32_t tl, br;
1142
1143	if (rstate == NULL)
1144		return;
1145
1146	rstate->id = R600_PIPE_STATE_SCISSOR;
1147	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1148	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1149	r600_pipe_state_add_reg(rstate,
1150				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1151	r600_pipe_state_add_reg(rstate,
1152				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1153
1154	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1155	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1156	r600_context_pipe_state_set(rctx, rstate);
1157}
1158
1159static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1160					const struct pipe_scissor_state *state)
1161{
1162	struct r600_context *rctx = (struct r600_context *)ctx;
1163
1164	if (rctx->chip_class == R600) {
1165		rctx->scissor_state = *state;
1166
1167		if (!rctx->scissor_enable)
1168			return;
1169	}
1170
1171	r600_set_scissor_state(rctx, state);
1172}
1173
1174static void r600_set_viewport_state(struct pipe_context *ctx,
1175					const struct pipe_viewport_state *state)
1176{
1177	struct r600_context *rctx = (struct r600_context *)ctx;
1178	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1179
1180	if (rstate == NULL)
1181		return;
1182
1183	rctx->viewport = *state;
1184	rstate->id = R600_PIPE_STATE_VIEWPORT;
1185	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1186	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1187	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1188	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1189	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1190	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1191
1192	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1193	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1194	r600_context_pipe_state_set(rctx, rstate);
1195}
1196
1197static void r600_init_color_surface(struct r600_context *rctx,
1198				    struct r600_surface *surf)
1199{
1200	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1201	unsigned level = surf->base.u.tex.level;
1202	unsigned pitch, slice;
1203	unsigned color_info;
1204	unsigned format, swap, ntype, endian;
1205	unsigned offset;
1206	const struct util_format_description *desc;
1207	int i;
1208	bool blend_bypass = 0, blend_clamp = 1;
1209
1210	if (rtex->is_depth && !rtex->is_flushing_texture) {
1211		r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1212		rtex = rtex->flushed_depth_texture;
1213		assert(rtex);
1214	}
1215
1216	offset = rtex->surface.level[level].offset;
1217	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1218		offset += rtex->surface.level[level].slice_size *
1219			  surf->base.u.tex.first_layer;
1220	}
1221	pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1222	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1223	if (slice) {
1224		slice = slice - 1;
1225	}
1226	color_info = 0;
1227	switch (rtex->surface.level[level].mode) {
1228	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1229		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1230		break;
1231	case RADEON_SURF_MODE_1D:
1232		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1233		break;
1234	case RADEON_SURF_MODE_2D:
1235		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1236		break;
1237	case RADEON_SURF_MODE_LINEAR:
1238	default:
1239		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1240		break;
1241	}
1242
1243	desc = util_format_description(surf->base.format);
1244
1245	for (i = 0; i < 4; i++) {
1246		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1247			break;
1248		}
1249	}
1250
1251	ntype = V_0280A0_NUMBER_UNORM;
1252	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1253		ntype = V_0280A0_NUMBER_SRGB;
1254	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1255		if (desc->channel[i].normalized)
1256			ntype = V_0280A0_NUMBER_SNORM;
1257		else if (desc->channel[i].pure_integer)
1258			ntype = V_0280A0_NUMBER_SINT;
1259	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1260		if (desc->channel[i].normalized)
1261			ntype = V_0280A0_NUMBER_UNORM;
1262		else if (desc->channel[i].pure_integer)
1263			ntype = V_0280A0_NUMBER_UINT;
1264	}
1265
1266	format = r600_translate_colorformat(surf->base.format);
1267	assert(format != ~0);
1268
1269	swap = r600_translate_colorswap(surf->base.format);
1270	assert(swap != ~0);
1271
1272	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1273		endian = ENDIAN_NONE;
1274	} else {
1275		endian = r600_colorformat_endian_swap(format);
1276	}
1277
1278	/* set blend bypass according to docs if SINT/UINT or
1279	   8/24 COLOR variants */
1280	if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1281	    format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1282	    format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1283		blend_clamp = 0;
1284		blend_bypass = 1;
1285	}
1286
1287	surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1288
1289	color_info |= S_0280A0_FORMAT(format) |
1290		S_0280A0_COMP_SWAP(swap) |
1291		S_0280A0_BLEND_BYPASS(blend_bypass) |
1292		S_0280A0_BLEND_CLAMP(blend_clamp) |
1293		S_0280A0_NUMBER_TYPE(ntype) |
1294		S_0280A0_ENDIAN(endian);
1295
1296	/* EXPORT_NORM is an optimzation that can be enabled for better
1297	 * performance in certain cases
1298	 */
1299	if (rctx->chip_class == R600) {
1300		/* EXPORT_NORM can be enabled if:
1301		 * - 11-bit or smaller UNORM/SNORM/SRGB
1302		 * - BLEND_CLAMP is enabled
1303		 * - BLEND_FLOAT32 is disabled
1304		 */
1305		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1306		    (desc->channel[i].size < 12 &&
1307		     desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1308		     ntype != V_0280A0_NUMBER_UINT &&
1309		     ntype != V_0280A0_NUMBER_SINT) &&
1310		    G_0280A0_BLEND_CLAMP(color_info) &&
1311		    !G_0280A0_BLEND_FLOAT32(color_info)) {
1312			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1313			surf->export_16bpc = true;
1314		}
1315	} else {
1316		/* EXPORT_NORM can be enabled if:
1317		 * - 11-bit or smaller UNORM/SNORM/SRGB
1318		 * - 16-bit or smaller FLOAT
1319		 */
1320		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1321		    ((desc->channel[i].size < 12 &&
1322		      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1323		      ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1324		    (desc->channel[i].size < 17 &&
1325		     desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1326			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1327			surf->export_16bpc = true;
1328		}
1329	}
1330
1331	surf->cb_color_base = offset >> 8;
1332	surf->cb_color_info = color_info;
1333	surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1334			      S_028060_SLICE_TILE_MAX(slice);
1335	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1336		surf->cb_color_view = 0;
1337	} else {
1338		surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1339				      S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1340	}
1341
1342	surf->color_initialized = true;
1343}
1344
1345static void r600_init_depth_surface(struct r600_context *rctx,
1346				    struct r600_surface *surf)
1347{
1348	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1349	unsigned level, pitch, slice, format, offset, array_mode;
1350
1351	level = surf->base.u.tex.level;
1352	offset = rtex->surface.level[level].offset;
1353	pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1354	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1355	if (slice) {
1356		slice = slice - 1;
1357	}
1358	switch (rtex->surface.level[level].mode) {
1359	case RADEON_SURF_MODE_2D:
1360		array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1361		break;
1362	case RADEON_SURF_MODE_1D:
1363	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1364	case RADEON_SURF_MODE_LINEAR:
1365	default:
1366		array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1367		break;
1368	}
1369
1370	format = r600_translate_dbformat(surf->base.format);
1371	assert(format != ~0);
1372
1373	surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1374	surf->db_depth_base = offset >> 8;
1375	surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1376			      S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1377	surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1378	surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1379
1380	surf->depth_initialized = true;
1381}
1382
1383static void r600_set_framebuffer_state(struct pipe_context *ctx,
1384					const struct pipe_framebuffer_state *state)
1385{
1386	struct r600_context *rctx = (struct r600_context *)ctx;
1387	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1388	struct r600_surface *surf;
1389	struct r600_resource *res;
1390	uint32_t tl, br, i;
1391
1392	if (rstate == NULL)
1393		return;
1394
1395	r600_flush_framebuffer(rctx, false);
1396
1397	/* unreference old buffer and reference new one */
1398	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1399
1400	util_copy_framebuffer_state(&rctx->framebuffer, state);
1401
1402	/* build states */
1403	rctx->export_16bpc = true;
1404	rctx->nr_cbufs = state->nr_cbufs;
1405	rctx->cb0_is_integer = state->nr_cbufs &&
1406			       util_format_is_pure_integer(state->cbufs[0]->format);
1407
1408	for (i = 0; i < state->nr_cbufs; i++) {
1409		surf = (struct r600_surface*)state->cbufs[i];
1410		res = (struct r600_resource*)surf->base.texture;
1411
1412		if (!surf->color_initialized) {
1413			r600_init_color_surface(rctx, surf);
1414		}
1415
1416		if (!surf->export_16bpc) {
1417			rctx->export_16bpc = false;
1418		}
1419
1420		r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
1421					   surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1422		r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
1423					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1424		r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
1425					surf->cb_color_size);
1426		r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
1427					surf->cb_color_view);
1428		r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
1429					   surf->cb_color_frag, res, RADEON_USAGE_READWRITE);
1430		r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
1431					   surf->cb_color_tile, res, RADEON_USAGE_READWRITE);
1432	}
1433	/* set CB_COLOR1_INFO for possible dual-src blending */
1434	if (i == 1) {
1435		r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
1436					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1437		i++;
1438	}
1439
1440	/* Update alpha-test state dependencies.
1441	 * Alpha-test is done on the first colorbuffer only. */
1442	if (state->nr_cbufs) {
1443		surf = (struct r600_surface*)state->cbufs[0];
1444		if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1445			rctx->alphatest_state.bypass = surf->alphatest_bypass;
1446			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1447		}
1448	}
1449
1450	if (state->zsbuf) {
1451		surf = (struct r600_surface*)state->zsbuf;
1452		res = (struct r600_resource*)surf->base.texture;
1453
1454		if (!surf->depth_initialized) {
1455			r600_init_depth_surface(rctx, surf);
1456		}
1457
1458		r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
1459					   res, RADEON_USAGE_READWRITE);
1460		r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
1461		r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
1462		r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
1463					   res, RADEON_USAGE_READWRITE);
1464		r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1465	}
1466
1467	tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1468	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1469
1470	r600_pipe_state_add_reg(rstate,
1471				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1472	r600_pipe_state_add_reg(rstate,
1473				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1474
1475	/* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1476	 * will assure that the alpha-test will work even if there is
1477	 * no colorbuffer bound. */
1478	r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1479				(1ull << MAX2(state->nr_cbufs, 1)) - 1);
1480
1481	if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1482		rctx->alphatest_state.bypass = false;
1483		r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1484	}
1485
1486	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1487	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1488	r600_context_pipe_state_set(rctx, rstate);
1489
1490	if (state->zsbuf) {
1491		r600_polygon_offset_update(rctx);
1492	}
1493
1494	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1495		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1496		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1497	}
1498}
1499
1500static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1501{
1502	struct radeon_winsys_cs *cs = rctx->cs;
1503	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1504	unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1505	unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1506	unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1507
1508	r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1509	r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1510	r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */
1511	r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1512			       a->cb_color_control |
1513			       S_028808_MULTIWRITE_ENABLE(multiwrite));
1514}
1515
1516static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1517{
1518	struct radeon_winsys_cs *cs = rctx->cs;
1519	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1520	unsigned db_render_control = 0;
1521	unsigned db_render_override =
1522		S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1523		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1524		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1525
1526	if (a->occlusion_query_enabled) {
1527		if (rctx->chip_class >= R700) {
1528			db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1529		}
1530		db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1531	}
1532	if (a->flush_depthstencil_through_cb) {
1533		assert(a->copy_depth || a->copy_stencil);
1534
1535		db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1536				     S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1537				     S_028D0C_COPY_CENTROID(1);
1538	}
1539
1540	r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1541	r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1542	r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1543}
1544
1545static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1546{
1547	struct radeon_winsys_cs *cs = rctx->cs;
1548	uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1549
1550	while (dirty_mask) {
1551		struct pipe_vertex_buffer *vb;
1552		struct r600_resource *rbuffer;
1553		unsigned offset;
1554		unsigned buffer_index = u_bit_scan(&dirty_mask);
1555
1556		vb = &rctx->vertex_buffer_state.vb[buffer_index];
1557		rbuffer = (struct r600_resource*)vb->buffer;
1558		assert(rbuffer);
1559
1560		offset = vb->buffer_offset;
1561
1562		/* fetch resources start at index 320 */
1563		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1564		r600_write_value(cs, (320 + buffer_index) * 7);
1565		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1566		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1567		r600_write_value(cs, /* RESOURCEi_WORD2 */
1568				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1569				 S_038008_STRIDE(vb->stride));
1570		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1571		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1572		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1573		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1574
1575		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1576		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1577	}
1578}
1579
1580static void r600_emit_constant_buffers(struct r600_context *rctx,
1581				       struct r600_constbuf_state *state,
1582				       unsigned buffer_id_base,
1583				       unsigned reg_alu_constbuf_size,
1584				       unsigned reg_alu_const_cache)
1585{
1586	struct radeon_winsys_cs *cs = rctx->cs;
1587	uint32_t dirty_mask = state->dirty_mask;
1588
1589	while (dirty_mask) {
1590		struct pipe_constant_buffer *cb;
1591		struct r600_resource *rbuffer;
1592		unsigned offset;
1593		unsigned buffer_index = ffs(dirty_mask) - 1;
1594
1595		cb = &state->cb[buffer_index];
1596		rbuffer = (struct r600_resource*)cb->buffer;
1597		assert(rbuffer);
1598
1599		offset = cb->buffer_offset;
1600
1601		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1602				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1603		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1604
1605		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1606		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1607
1608		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1609		r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1610		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1611		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1612		r600_write_value(cs, /* RESOURCEi_WORD2 */
1613				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1614				 S_038008_STRIDE(16));
1615		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1616		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1617		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1618		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1619
1620		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1621		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1622
1623		dirty_mask &= ~(1 << buffer_index);
1624	}
1625	state->dirty_mask = 0;
1626}
1627
1628static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1629{
1630	r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1631				   R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1632				   R_028980_ALU_CONST_CACHE_VS_0);
1633}
1634
1635static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1636{
1637	r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1638				   R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1639				   R_028940_ALU_CONST_CACHE_PS_0);
1640}
1641
1642static void r600_emit_sampler_views(struct r600_context *rctx,
1643				    struct r600_samplerview_state *state,
1644				    unsigned resource_id_base)
1645{
1646	struct radeon_winsys_cs *cs = rctx->cs;
1647	uint32_t dirty_mask = state->dirty_mask;
1648
1649	while (dirty_mask) {
1650		struct r600_pipe_sampler_view *rview;
1651		unsigned resource_index = u_bit_scan(&dirty_mask);
1652		unsigned reloc;
1653
1654		rview = state->views[resource_index];
1655		assert(rview);
1656
1657		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1658		r600_write_value(cs, (resource_id_base + resource_index) * 7);
1659		r600_write_array(cs, 7, rview->tex_resource_words);
1660
1661		/* XXX The kernel needs two relocations. This is stupid. */
1662		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1663					      RADEON_USAGE_READ);
1664		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1665		r600_write_value(cs, reloc);
1666		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1667		r600_write_value(cs, reloc);
1668	}
1669	state->dirty_mask = 0;
1670}
1671
1672static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1673{
1674	r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS);
1675}
1676
1677static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1678{
1679	r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1680}
1681
1682static void r600_emit_sampler(struct r600_context *rctx,
1683				struct r600_textures_info *texinfo,
1684				unsigned resource_id_base,
1685				unsigned border_color_reg)
1686{
1687	struct radeon_winsys_cs *cs = rctx->cs;
1688	unsigned i;
1689
1690	for (i = 0; i < texinfo->n_samplers; i++) {
1691
1692		if (texinfo->samplers[i] == NULL) {
1693			continue;
1694		}
1695
1696		/* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1697		 * filtering between layers.
1698		 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1699		 */
1700		if (texinfo->views.views[i]) {
1701			if (texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1702			    texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1703				texinfo->samplers[i]->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1704				texinfo->is_array_sampler[i] = true;
1705			} else {
1706				texinfo->samplers[i]->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1707				texinfo->is_array_sampler[i] = false;
1708			}
1709		}
1710
1711		r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1712		r600_write_value(cs, (resource_id_base + i) * 3);
1713		r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1714
1715		if (texinfo->samplers[i]->border_color_use) {
1716			unsigned offset;
1717
1718			offset = border_color_reg;
1719			offset += i * 16;
1720			r600_write_config_reg_seq(cs, offset, 4);
1721			r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
1722		}
1723	}
1724}
1725
1726static void r600_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
1727{
1728	r600_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
1729}
1730
1731static void r600_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
1732{
1733	r600_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
1734}
1735
1736static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
1737{
1738	struct radeon_winsys_cs *cs = rctx->cs;
1739	unsigned tmp;
1740
1741	tmp = S_009508_DISABLE_CUBE_ANISO(1) |
1742		S_009508_SYNC_GRADIENT(1) |
1743		S_009508_SYNC_WALKER(1) |
1744		S_009508_SYNC_ALIGNER(1);
1745	if (!rctx->seamless_cube_map.enabled) {
1746		tmp |= S_009508_DISABLE_CUBE_WRAP(1);
1747	}
1748	r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
1749}
1750
1751static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
1752{
1753	struct r600_sample_mask *s = (struct r600_sample_mask*)a;
1754	uint8_t mask = s->sample_mask;
1755
1756	r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
1757			       mask | (mask << 8) | (mask << 16) | (mask << 24));
1758}
1759
1760void r600_init_state_functions(struct r600_context *rctx)
1761{
1762	r600_init_atom(&rctx->seamless_cube_map.atom, r600_emit_seamless_cube_map, 3, 0);
1763	r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
1764	r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
1765	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1766	r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
1767	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1768	r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0);
1769	r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0);
1770	r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0);
1771	r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0);
1772	r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0);
1773	/* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
1774	 * does not take effect
1775	 */
1776	r600_init_atom(&rctx->vs_samplers.atom_sampler, r600_emit_vs_sampler, 0, EMIT_EARLY);
1777	r600_init_atom(&rctx->ps_samplers.atom_sampler, r600_emit_ps_sampler, 0, EMIT_EARLY);
1778
1779	r600_init_atom(&rctx->sample_mask.atom, r600_emit_sample_mask, 3, 0);
1780	rctx->sample_mask.sample_mask = ~0;
1781	r600_atom_dirty(rctx, &rctx->sample_mask.atom);
1782
1783	rctx->context.create_blend_state = r600_create_blend_state;
1784	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1785	rctx->context.create_fs_state = r600_create_shader_state_ps;
1786	rctx->context.create_rasterizer_state = r600_create_rs_state;
1787	rctx->context.create_sampler_state = r600_create_sampler_state;
1788	rctx->context.create_sampler_view = r600_create_sampler_view;
1789	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1790	rctx->context.create_vs_state = r600_create_shader_state_vs;
1791	rctx->context.bind_blend_state = r600_bind_blend_state;
1792	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1793	rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1794	rctx->context.bind_fs_state = r600_bind_ps_shader;
1795	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1796	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1797	rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1798	rctx->context.bind_vs_state = r600_bind_vs_shader;
1799	rctx->context.delete_blend_state = r600_delete_state;
1800	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1801	rctx->context.delete_fs_state = r600_delete_ps_shader;
1802	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1803	rctx->context.delete_sampler_state = r600_delete_sampler;
1804	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1805	rctx->context.delete_vs_state = r600_delete_vs_shader;
1806	rctx->context.set_blend_color = r600_set_blend_color;
1807	rctx->context.set_clip_state = r600_set_clip_state;
1808	rctx->context.set_constant_buffer = r600_set_constant_buffer;
1809	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1810	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1811	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1812	rctx->context.set_sample_mask = r600_set_sample_mask;
1813	rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
1814	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1815	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1816	rctx->context.set_index_buffer = r600_set_index_buffer;
1817	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1818	rctx->context.set_viewport_state = r600_set_viewport_state;
1819	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1820	rctx->context.texture_barrier = r600_texture_barrier;
1821	rctx->context.create_stream_output_target = r600_create_so_target;
1822	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1823	rctx->context.set_stream_output_targets = r600_set_so_targets;
1824}
1825
1826/* Adjust GPR allocation on R6xx/R7xx */
1827void r600_adjust_gprs(struct r600_context *rctx)
1828{
1829	struct r600_pipe_state rstate;
1830	unsigned num_ps_gprs = rctx->default_ps_gprs;
1831	unsigned num_vs_gprs = rctx->default_vs_gprs;
1832	unsigned tmp;
1833	int diff;
1834
1835	/* XXX: Following call moved from r600_bind_[ps|vs]_shader,
1836	 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
1837	 * adjusting the GPR allocation?
1838	 * Do we need this if we aren't really changing config below? */
1839	r600_inval_shader_cache(rctx);
1840
1841	if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
1842	{
1843		diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
1844		num_vs_gprs -= diff;
1845		num_ps_gprs += diff;
1846	}
1847
1848	if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
1849	{
1850		diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
1851		num_ps_gprs -= diff;
1852		num_vs_gprs += diff;
1853	}
1854
1855	tmp = 0;
1856	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1857	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1858	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1859	rstate.nregs = 0;
1860	r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
1861
1862	r600_context_pipe_state_set(rctx, &rstate);
1863}
1864
1865void r600_init_atom_start_cs(struct r600_context *rctx)
1866{
1867	int ps_prio;
1868	int vs_prio;
1869	int gs_prio;
1870	int es_prio;
1871	int num_ps_gprs;
1872	int num_vs_gprs;
1873	int num_gs_gprs;
1874	int num_es_gprs;
1875	int num_temp_gprs;
1876	int num_ps_threads;
1877	int num_vs_threads;
1878	int num_gs_threads;
1879	int num_es_threads;
1880	int num_ps_stack_entries;
1881	int num_vs_stack_entries;
1882	int num_gs_stack_entries;
1883	int num_es_stack_entries;
1884	enum radeon_family family;
1885	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1886	uint32_t tmp;
1887	unsigned i;
1888
1889	r600_init_command_buffer(cb, 256, EMIT_EARLY);
1890
1891	/* R6xx requires this packet at the start of each command buffer */
1892	if (rctx->chip_class == R600) {
1893		r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
1894		r600_store_value(cb, 0);
1895	}
1896	/* All asics require this one */
1897	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1898	r600_store_value(cb, 0x80000000);
1899	r600_store_value(cb, 0x80000000);
1900
1901	family = rctx->family;
1902	ps_prio = 0;
1903	vs_prio = 1;
1904	gs_prio = 2;
1905	es_prio = 3;
1906	switch (family) {
1907	case CHIP_R600:
1908		num_ps_gprs = 192;
1909		num_vs_gprs = 56;
1910		num_temp_gprs = 4;
1911		num_gs_gprs = 0;
1912		num_es_gprs = 0;
1913		num_ps_threads = 136;
1914		num_vs_threads = 48;
1915		num_gs_threads = 4;
1916		num_es_threads = 4;
1917		num_ps_stack_entries = 128;
1918		num_vs_stack_entries = 128;
1919		num_gs_stack_entries = 0;
1920		num_es_stack_entries = 0;
1921		break;
1922	case CHIP_RV630:
1923	case CHIP_RV635:
1924		num_ps_gprs = 84;
1925		num_vs_gprs = 36;
1926		num_temp_gprs = 4;
1927		num_gs_gprs = 0;
1928		num_es_gprs = 0;
1929		num_ps_threads = 144;
1930		num_vs_threads = 40;
1931		num_gs_threads = 4;
1932		num_es_threads = 4;
1933		num_ps_stack_entries = 40;
1934		num_vs_stack_entries = 40;
1935		num_gs_stack_entries = 32;
1936		num_es_stack_entries = 16;
1937		break;
1938	case CHIP_RV610:
1939	case CHIP_RV620:
1940	case CHIP_RS780:
1941	case CHIP_RS880:
1942	default:
1943		num_ps_gprs = 84;
1944		num_vs_gprs = 36;
1945		num_temp_gprs = 4;
1946		num_gs_gprs = 0;
1947		num_es_gprs = 0;
1948		num_ps_threads = 136;
1949		num_vs_threads = 48;
1950		num_gs_threads = 4;
1951		num_es_threads = 4;
1952		num_ps_stack_entries = 40;
1953		num_vs_stack_entries = 40;
1954		num_gs_stack_entries = 32;
1955		num_es_stack_entries = 16;
1956		break;
1957	case CHIP_RV670:
1958		num_ps_gprs = 144;
1959		num_vs_gprs = 40;
1960		num_temp_gprs = 4;
1961		num_gs_gprs = 0;
1962		num_es_gprs = 0;
1963		num_ps_threads = 136;
1964		num_vs_threads = 48;
1965		num_gs_threads = 4;
1966		num_es_threads = 4;
1967		num_ps_stack_entries = 40;
1968		num_vs_stack_entries = 40;
1969		num_gs_stack_entries = 32;
1970		num_es_stack_entries = 16;
1971		break;
1972	case CHIP_RV770:
1973		num_ps_gprs = 192;
1974		num_vs_gprs = 56;
1975		num_temp_gprs = 4;
1976		num_gs_gprs = 0;
1977		num_es_gprs = 0;
1978		num_ps_threads = 188;
1979		num_vs_threads = 60;
1980		num_gs_threads = 0;
1981		num_es_threads = 0;
1982		num_ps_stack_entries = 256;
1983		num_vs_stack_entries = 256;
1984		num_gs_stack_entries = 0;
1985		num_es_stack_entries = 0;
1986		break;
1987	case CHIP_RV730:
1988	case CHIP_RV740:
1989		num_ps_gprs = 84;
1990		num_vs_gprs = 36;
1991		num_temp_gprs = 4;
1992		num_gs_gprs = 0;
1993		num_es_gprs = 0;
1994		num_ps_threads = 188;
1995		num_vs_threads = 60;
1996		num_gs_threads = 0;
1997		num_es_threads = 0;
1998		num_ps_stack_entries = 128;
1999		num_vs_stack_entries = 128;
2000		num_gs_stack_entries = 0;
2001		num_es_stack_entries = 0;
2002		break;
2003	case CHIP_RV710:
2004		num_ps_gprs = 192;
2005		num_vs_gprs = 56;
2006		num_temp_gprs = 4;
2007		num_gs_gprs = 0;
2008		num_es_gprs = 0;
2009		num_ps_threads = 144;
2010		num_vs_threads = 48;
2011		num_gs_threads = 0;
2012		num_es_threads = 0;
2013		num_ps_stack_entries = 128;
2014		num_vs_stack_entries = 128;
2015		num_gs_stack_entries = 0;
2016		num_es_stack_entries = 0;
2017		break;
2018	}
2019
2020	rctx->default_ps_gprs = num_ps_gprs;
2021	rctx->default_vs_gprs = num_vs_gprs;
2022	rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2023
2024	/* SQ_CONFIG */
2025	tmp = 0;
2026	switch (family) {
2027	case CHIP_RV610:
2028	case CHIP_RV620:
2029	case CHIP_RS780:
2030	case CHIP_RS880:
2031	case CHIP_RV710:
2032		break;
2033	default:
2034		tmp |= S_008C00_VC_ENABLE(1);
2035		break;
2036	}
2037	tmp |= S_008C00_DX9_CONSTS(0);
2038	tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2039	tmp |= S_008C00_PS_PRIO(ps_prio);
2040	tmp |= S_008C00_VS_PRIO(vs_prio);
2041	tmp |= S_008C00_GS_PRIO(gs_prio);
2042	tmp |= S_008C00_ES_PRIO(es_prio);
2043	r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2044
2045	/* SQ_GPR_RESOURCE_MGMT_2 */
2046	tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2047	tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2048	r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2049	r600_store_value(cb, tmp);
2050
2051	/* SQ_THREAD_RESOURCE_MGMT */
2052	tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2053	tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2054	tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2055	tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2056	r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2057
2058	/* SQ_STACK_RESOURCE_MGMT_1 */
2059	tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2060	tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2061	r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2062
2063	/* SQ_STACK_RESOURCE_MGMT_2 */
2064	tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2065	tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2066	r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2067
2068	r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2069
2070	if (rctx->chip_class >= R700) {
2071		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2072		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2073		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2074		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2075	} else {
2076		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2077		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2078		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2079		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2080	}
2081	r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2082	r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2083	r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2084	r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2085	r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2086	r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2087	r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2088	r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2089	r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2090	r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2091
2092	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2093	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2094	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2095	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2096	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2097	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2098	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2099	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2100	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2101	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2102	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2103	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2104	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2105	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2106
2107	r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2108	r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2109	r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2110
2111	r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2112	r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2113	r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2114	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2115
2116	r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2117
2118	r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2119	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2120	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2121
2122	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2123
2124	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2125	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2126	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2127
2128	r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2129	r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2130	r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2131	r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2132
2133	r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2134	r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2135	r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2136
2137	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2138	r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2139
2140	r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2141	r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */
2142	r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2143
2144	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6);
2145	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2146	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2147	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2148	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2149	r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
2150	r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */
2151
2152	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2153	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2154	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2155
2156	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2157
2158	r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8);
2159	for (i = 0; i < 8; i++) {
2160		r600_store_value(cb, 0);
2161	}
2162
2163	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2164	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2165
2166	if (rctx->chip_class >= R700) {
2167		r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2168	}
2169
2170	r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2171	r600_store_value(cb, 0x1000000);  /* R_028C30_CB_CLRCMP_CONTROL */
2172	r600_store_value(cb, 0);          /* R_028C34_CB_CLRCMP_SRC */
2173	r600_store_value(cb, 0xFF);       /* R_028C38_CB_CLRCMP_DST */
2174	r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2175
2176	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2177	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2178	r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2179
2180	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2181	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2182	r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2183
2184	r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2185	r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2186	r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2187
2188	r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2189	r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2190
2191	if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2192		r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2193	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2194	if (rctx->screen->has_streamout) {
2195		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2196	}
2197
2198	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2199	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2200}
2201
2202void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2203{
2204	struct r600_context *rctx = (struct r600_context *)ctx;
2205	struct r600_pipe_state *rstate = &shader->rstate;
2206	struct r600_shader *rshader = &shader->shader;
2207	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2208	int pos_index = -1, face_index = -1;
2209	unsigned tmp, sid, ufi = 0;
2210	int need_linear = 0;
2211	unsigned z_export = 0, stencil_export = 0;
2212
2213	rstate->nregs = 0;
2214
2215	for (i = 0; i < rshader->ninput; i++) {
2216		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2217			pos_index = i;
2218		if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2219			face_index = i;
2220
2221		sid = rshader->input[i].spi_sid;
2222
2223		tmp = S_028644_SEMANTIC(sid);
2224
2225		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2226			rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2227			(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2228				rctx->rasterizer && rctx->rasterizer->flatshade))
2229			tmp |= S_028644_FLAT_SHADE(1);
2230
2231		if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2232				rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2233			tmp |= S_028644_PT_SPRITE_TEX(1);
2234		}
2235
2236		if (rshader->input[i].centroid)
2237			tmp |= S_028644_SEL_CENTROID(1);
2238
2239		if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2240			need_linear = 1;
2241			tmp |= S_028644_SEL_LINEAR(1);
2242		}
2243
2244		r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2245				tmp);
2246	}
2247
2248	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2249	for (i = 0; i < rshader->noutput; i++) {
2250		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2251			z_export = 1;
2252		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2253			stencil_export = 1;
2254	}
2255	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2256	db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2257	if (rshader->uses_kill)
2258		db_shader_control |= S_02880C_KILL_ENABLE(1);
2259
2260	exports_ps = 0;
2261	for (i = 0; i < rshader->noutput; i++) {
2262		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2263		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2264			exports_ps |= 1;
2265		}
2266	}
2267	num_cout = rshader->nr_ps_color_exports;
2268	exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2269	if (!exports_ps) {
2270		/* always at least export 1 component per pixel */
2271		exports_ps = 2;
2272	}
2273
2274	shader->nr_ps_color_outputs = num_cout;
2275
2276	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2277				S_0286CC_PERSP_GRADIENT_ENA(1)|
2278				S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2279	spi_input_z = 0;
2280	if (pos_index != -1) {
2281		spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2282					S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2283					S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2284					S_0286CC_BARYC_SAMPLE_CNTL(1));
2285		spi_input_z |= 1;
2286	}
2287
2288	spi_ps_in_control_1 = 0;
2289	if (face_index != -1) {
2290		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2291			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2292	}
2293
2294	/* HW bug in original R600 */
2295	if (rctx->family == CHIP_R600)
2296		ufi = 1;
2297
2298	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2299	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2300	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2301	r600_pipe_state_add_reg_bo(rstate,
2302				   R_028840_SQ_PGM_START_PS,
2303				   0, shader->bo, RADEON_USAGE_READ);
2304	r600_pipe_state_add_reg(rstate,
2305				R_028850_SQ_PGM_RESOURCES_PS,
2306				S_028850_NUM_GPRS(rshader->bc.ngpr) |
2307				S_028850_STACK_SIZE(rshader->bc.nstack) |
2308				S_028850_UNCACHED_FIRST_INST(ufi));
2309	r600_pipe_state_add_reg(rstate,
2310				R_028854_SQ_PGM_EXPORTS_PS,
2311				exports_ps);
2312	/* only set some bits here, the other bits are set in the dsa state */
2313	shader->db_shader_control = db_shader_control;
2314	shader->ps_depth_export = z_export | stencil_export;
2315
2316	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2317	if (rctx->rasterizer)
2318		shader->flatshade = rctx->rasterizer->flatshade;
2319}
2320
2321void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2322{
2323	struct r600_context *rctx = (struct r600_context *)ctx;
2324	struct r600_pipe_state *rstate = &shader->rstate;
2325	struct r600_shader *rshader = &shader->shader;
2326	unsigned spi_vs_out_id[10] = {};
2327	unsigned i, tmp, nparams = 0;
2328
2329	/* clear previous register */
2330	rstate->nregs = 0;
2331
2332	for (i = 0; i < rshader->noutput; i++) {
2333		if (rshader->output[i].spi_sid) {
2334			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2335			spi_vs_out_id[nparams / 4] |= tmp;
2336			nparams++;
2337		}
2338	}
2339
2340	for (i = 0; i < 10; i++) {
2341		r600_pipe_state_add_reg(rstate,
2342					R_028614_SPI_VS_OUT_ID_0 + i * 4,
2343					spi_vs_out_id[i]);
2344	}
2345
2346	/* Certain attributes (position, psize, etc.) don't count as params.
2347	 * VS is required to export at least one param and r600_shader_from_tgsi()
2348	 * takes care of adding a dummy export.
2349	 */
2350	if (nparams < 1)
2351		nparams = 1;
2352
2353	r600_pipe_state_add_reg(rstate,
2354				R_0286C4_SPI_VS_OUT_CONFIG,
2355				S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2356	r600_pipe_state_add_reg(rstate,
2357				R_028868_SQ_PGM_RESOURCES_VS,
2358				S_028868_NUM_GPRS(rshader->bc.ngpr) |
2359				S_028868_STACK_SIZE(rshader->bc.nstack));
2360	r600_pipe_state_add_reg_bo(rstate,
2361			R_028858_SQ_PGM_START_VS,
2362			0, shader->bo, RADEON_USAGE_READ);
2363
2364	shader->pa_cl_vs_out_cntl =
2365		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2366		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2367		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2368		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2369}
2370
2371void r600_fetch_shader(struct pipe_context *ctx,
2372		       struct r600_vertex_element *ve)
2373{
2374	struct r600_pipe_state *rstate;
2375	struct r600_context *rctx = (struct r600_context *)ctx;
2376
2377	rstate = &ve->rstate;
2378	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2379	rstate->nregs = 0;
2380	r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2381				0,
2382				ve->fetch_shader, RADEON_USAGE_READ);
2383}
2384
2385void *r600_create_db_flush_dsa(struct r600_context *rctx)
2386{
2387	struct pipe_depth_stencil_alpha_state dsa;
2388	boolean quirk = false;
2389
2390	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2391		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2392		quirk = true;
2393
2394	memset(&dsa, 0, sizeof(dsa));
2395
2396	if (quirk) {
2397		dsa.depth.enabled = 1;
2398		dsa.depth.func = PIPE_FUNC_LEQUAL;
2399		dsa.stencil[0].enabled = 1;
2400		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2401		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2402		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2403		dsa.stencil[0].writemask = 0xff;
2404	}
2405
2406	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2407}
2408
2409void r600_update_dual_export_state(struct r600_context * rctx)
2410{
2411	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2412			       !rctx->ps_shader->current->ps_depth_export;
2413	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2414				     S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2415
2416	if (db_shader_control != rctx->db_shader_control) {
2417		struct r600_pipe_state rstate;
2418
2419		rctx->db_shader_control = db_shader_control;
2420		rstate.nregs = 0;
2421		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2422		r600_context_pipe_state_set(rctx, &rstate);
2423	}
2424}
2425