r600_state.c revision c2e9dd0276464ed61d48d3d80b9be8228767dfe2
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_formats.h" 24#include "r600d.h" 25 26#include "pipe/p_shader_tokens.h" 27#include "util/u_pack_color.h" 28#include "util/u_memory.h" 29#include "util/u_framebuffer.h" 30#include "util/u_dual_blend.h" 31 32static uint32_t r600_translate_blend_function(int blend_func) 33{ 34 switch (blend_func) { 35 case PIPE_BLEND_ADD: 36 return V_028804_COMB_DST_PLUS_SRC; 37 case PIPE_BLEND_SUBTRACT: 38 return V_028804_COMB_SRC_MINUS_DST; 39 case PIPE_BLEND_REVERSE_SUBTRACT: 40 return V_028804_COMB_DST_MINUS_SRC; 41 case PIPE_BLEND_MIN: 42 return V_028804_COMB_MIN_DST_SRC; 43 case PIPE_BLEND_MAX: 44 return V_028804_COMB_MAX_DST_SRC; 45 default: 46 R600_ERR("Unknown blend function %d\n", blend_func); 47 assert(0); 48 break; 49 } 50 return 0; 51} 52 53static uint32_t r600_translate_blend_factor(int blend_fact) 54{ 55 switch (blend_fact) { 56 case PIPE_BLENDFACTOR_ONE: 57 return V_028804_BLEND_ONE; 58 case PIPE_BLENDFACTOR_SRC_COLOR: 59 return V_028804_BLEND_SRC_COLOR; 60 case PIPE_BLENDFACTOR_SRC_ALPHA: 61 return V_028804_BLEND_SRC_ALPHA; 62 case PIPE_BLENDFACTOR_DST_ALPHA: 63 return V_028804_BLEND_DST_ALPHA; 64 case PIPE_BLENDFACTOR_DST_COLOR: 65 return V_028804_BLEND_DST_COLOR; 66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 67 return V_028804_BLEND_SRC_ALPHA_SATURATE; 68 case PIPE_BLENDFACTOR_CONST_COLOR: 69 return V_028804_BLEND_CONST_COLOR; 70 case PIPE_BLENDFACTOR_CONST_ALPHA: 71 return V_028804_BLEND_CONST_ALPHA; 72 case PIPE_BLENDFACTOR_ZERO: 73 return V_028804_BLEND_ZERO; 74 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR; 76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA; 78 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA; 80 case PIPE_BLENDFACTOR_INV_DST_COLOR: 81 return V_028804_BLEND_ONE_MINUS_DST_COLOR; 82 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR; 84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA; 86 case PIPE_BLENDFACTOR_SRC1_COLOR: 87 return V_028804_BLEND_SRC1_COLOR; 88 case PIPE_BLENDFACTOR_SRC1_ALPHA: 89 return V_028804_BLEND_SRC1_ALPHA; 90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 91 return V_028804_BLEND_INV_SRC1_COLOR; 92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 93 return V_028804_BLEND_INV_SRC1_ALPHA; 94 default: 95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 96 assert(0); 97 break; 98 } 99 return 0; 100} 101 102static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples) 103{ 104 switch (dim) { 105 default: 106 case PIPE_TEXTURE_1D: 107 return V_038000_SQ_TEX_DIM_1D; 108 case PIPE_TEXTURE_1D_ARRAY: 109 return V_038000_SQ_TEX_DIM_1D_ARRAY; 110 case PIPE_TEXTURE_2D: 111 case PIPE_TEXTURE_RECT: 112 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA : 113 V_038000_SQ_TEX_DIM_2D; 114 case PIPE_TEXTURE_2D_ARRAY: 115 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA : 116 V_038000_SQ_TEX_DIM_2D_ARRAY; 117 case PIPE_TEXTURE_3D: 118 return V_038000_SQ_TEX_DIM_3D; 119 case PIPE_TEXTURE_CUBE: 120 return V_038000_SQ_TEX_DIM_CUBEMAP; 121 } 122} 123 124static uint32_t r600_translate_dbformat(enum pipe_format format) 125{ 126 switch (format) { 127 case PIPE_FORMAT_Z16_UNORM: 128 return V_028010_DEPTH_16; 129 case PIPE_FORMAT_Z24X8_UNORM: 130 return V_028010_DEPTH_X8_24; 131 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 132 return V_028010_DEPTH_8_24; 133 case PIPE_FORMAT_Z32_FLOAT: 134 return V_028010_DEPTH_32_FLOAT; 135 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 136 return V_028010_DEPTH_X24_8_32_FLOAT; 137 default: 138 return ~0U; 139 } 140} 141 142static uint32_t r600_translate_colorswap(enum pipe_format format) 143{ 144 switch (format) { 145 /* 8-bit buffers. */ 146 case PIPE_FORMAT_A8_UNORM: 147 case PIPE_FORMAT_A8_SNORM: 148 case PIPE_FORMAT_A8_UINT: 149 case PIPE_FORMAT_A8_SINT: 150 case PIPE_FORMAT_A16_UNORM: 151 case PIPE_FORMAT_A16_SNORM: 152 case PIPE_FORMAT_A16_UINT: 153 case PIPE_FORMAT_A16_SINT: 154 case PIPE_FORMAT_A16_FLOAT: 155 case PIPE_FORMAT_A32_UINT: 156 case PIPE_FORMAT_A32_SINT: 157 case PIPE_FORMAT_A32_FLOAT: 158 case PIPE_FORMAT_R4A4_UNORM: 159 return V_0280A0_SWAP_ALT_REV; 160 case PIPE_FORMAT_I8_UNORM: 161 case PIPE_FORMAT_I8_SNORM: 162 case PIPE_FORMAT_I8_UINT: 163 case PIPE_FORMAT_I8_SINT: 164 case PIPE_FORMAT_L8_UNORM: 165 case PIPE_FORMAT_L8_SNORM: 166 case PIPE_FORMAT_L8_UINT: 167 case PIPE_FORMAT_L8_SINT: 168 case PIPE_FORMAT_L8_SRGB: 169 case PIPE_FORMAT_L16_UNORM: 170 case PIPE_FORMAT_L16_SNORM: 171 case PIPE_FORMAT_L16_UINT: 172 case PIPE_FORMAT_L16_SINT: 173 case PIPE_FORMAT_L16_FLOAT: 174 case PIPE_FORMAT_L32_UINT: 175 case PIPE_FORMAT_L32_SINT: 176 case PIPE_FORMAT_L32_FLOAT: 177 case PIPE_FORMAT_I16_UNORM: 178 case PIPE_FORMAT_I16_SNORM: 179 case PIPE_FORMAT_I16_UINT: 180 case PIPE_FORMAT_I16_SINT: 181 case PIPE_FORMAT_I16_FLOAT: 182 case PIPE_FORMAT_I32_UINT: 183 case PIPE_FORMAT_I32_SINT: 184 case PIPE_FORMAT_I32_FLOAT: 185 case PIPE_FORMAT_R8_UNORM: 186 case PIPE_FORMAT_R8_SNORM: 187 case PIPE_FORMAT_R8_UINT: 188 case PIPE_FORMAT_R8_SINT: 189 return V_0280A0_SWAP_STD; 190 191 case PIPE_FORMAT_L4A4_UNORM: 192 case PIPE_FORMAT_A4R4_UNORM: 193 return V_0280A0_SWAP_ALT; 194 195 /* 16-bit buffers. */ 196 case PIPE_FORMAT_B5G6R5_UNORM: 197 return V_0280A0_SWAP_STD_REV; 198 199 case PIPE_FORMAT_B5G5R5A1_UNORM: 200 case PIPE_FORMAT_B5G5R5X1_UNORM: 201 return V_0280A0_SWAP_ALT; 202 203 case PIPE_FORMAT_B4G4R4A4_UNORM: 204 case PIPE_FORMAT_B4G4R4X4_UNORM: 205 return V_0280A0_SWAP_ALT; 206 207 case PIPE_FORMAT_Z16_UNORM: 208 return V_0280A0_SWAP_STD; 209 210 case PIPE_FORMAT_L8A8_UNORM: 211 case PIPE_FORMAT_L8A8_SNORM: 212 case PIPE_FORMAT_L8A8_UINT: 213 case PIPE_FORMAT_L8A8_SINT: 214 case PIPE_FORMAT_L8A8_SRGB: 215 case PIPE_FORMAT_L16A16_UNORM: 216 case PIPE_FORMAT_L16A16_SNORM: 217 case PIPE_FORMAT_L16A16_UINT: 218 case PIPE_FORMAT_L16A16_SINT: 219 case PIPE_FORMAT_L16A16_FLOAT: 220 case PIPE_FORMAT_L32A32_UINT: 221 case PIPE_FORMAT_L32A32_SINT: 222 case PIPE_FORMAT_L32A32_FLOAT: 223 return V_0280A0_SWAP_ALT; 224 case PIPE_FORMAT_R8G8_UNORM: 225 case PIPE_FORMAT_R8G8_SNORM: 226 case PIPE_FORMAT_R8G8_UINT: 227 case PIPE_FORMAT_R8G8_SINT: 228 return V_0280A0_SWAP_STD; 229 230 case PIPE_FORMAT_R16_UNORM: 231 case PIPE_FORMAT_R16_SNORM: 232 case PIPE_FORMAT_R16_UINT: 233 case PIPE_FORMAT_R16_SINT: 234 case PIPE_FORMAT_R16_FLOAT: 235 return V_0280A0_SWAP_STD; 236 237 /* 32-bit buffers. */ 238 239 case PIPE_FORMAT_A8B8G8R8_SRGB: 240 return V_0280A0_SWAP_STD_REV; 241 case PIPE_FORMAT_B8G8R8A8_SRGB: 242 return V_0280A0_SWAP_ALT; 243 244 case PIPE_FORMAT_B8G8R8A8_UNORM: 245 case PIPE_FORMAT_B8G8R8X8_UNORM: 246 return V_0280A0_SWAP_ALT; 247 248 case PIPE_FORMAT_A8R8G8B8_UNORM: 249 case PIPE_FORMAT_X8R8G8B8_UNORM: 250 return V_0280A0_SWAP_ALT_REV; 251 case PIPE_FORMAT_R8G8B8A8_SNORM: 252 case PIPE_FORMAT_R8G8B8A8_UNORM: 253 case PIPE_FORMAT_R8G8B8X8_UNORM: 254 case PIPE_FORMAT_R8G8B8A8_SINT: 255 case PIPE_FORMAT_R8G8B8A8_UINT: 256 return V_0280A0_SWAP_STD; 257 258 case PIPE_FORMAT_A8B8G8R8_UNORM: 259 case PIPE_FORMAT_X8B8G8R8_UNORM: 260 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ 261 return V_0280A0_SWAP_STD_REV; 262 263 case PIPE_FORMAT_Z24X8_UNORM: 264 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 265 return V_0280A0_SWAP_STD; 266 267 case PIPE_FORMAT_X8Z24_UNORM: 268 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 269 return V_0280A0_SWAP_STD; 270 271 case PIPE_FORMAT_R10G10B10A2_UNORM: 272 case PIPE_FORMAT_R10G10B10X2_SNORM: 273 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 274 return V_0280A0_SWAP_STD; 275 276 case PIPE_FORMAT_B10G10R10A2_UNORM: 277 case PIPE_FORMAT_B10G10R10A2_UINT: 278 return V_0280A0_SWAP_ALT; 279 280 case PIPE_FORMAT_R11G11B10_FLOAT: 281 case PIPE_FORMAT_R16G16_UNORM: 282 case PIPE_FORMAT_R16G16_SNORM: 283 case PIPE_FORMAT_R16G16_FLOAT: 284 case PIPE_FORMAT_R16G16_UINT: 285 case PIPE_FORMAT_R16G16_SINT: 286 case PIPE_FORMAT_R32_UINT: 287 case PIPE_FORMAT_R32_SINT: 288 case PIPE_FORMAT_R32_FLOAT: 289 case PIPE_FORMAT_Z32_FLOAT: 290 return V_0280A0_SWAP_STD; 291 292 /* 64-bit buffers. */ 293 case PIPE_FORMAT_R32G32_FLOAT: 294 case PIPE_FORMAT_R32G32_UINT: 295 case PIPE_FORMAT_R32G32_SINT: 296 case PIPE_FORMAT_R16G16B16A16_UNORM: 297 case PIPE_FORMAT_R16G16B16A16_SNORM: 298 case PIPE_FORMAT_R16G16B16A16_UINT: 299 case PIPE_FORMAT_R16G16B16A16_SINT: 300 case PIPE_FORMAT_R16G16B16A16_FLOAT: 301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 302 303 /* 128-bit buffers. */ 304 case PIPE_FORMAT_R32G32B32A32_FLOAT: 305 case PIPE_FORMAT_R32G32B32A32_SNORM: 306 case PIPE_FORMAT_R32G32B32A32_UNORM: 307 case PIPE_FORMAT_R32G32B32A32_SINT: 308 case PIPE_FORMAT_R32G32B32A32_UINT: 309 return V_0280A0_SWAP_STD; 310 default: 311 R600_ERR("unsupported colorswap format %d\n", format); 312 return ~0U; 313 } 314 return ~0U; 315} 316 317static uint32_t r600_translate_colorformat(enum pipe_format format) 318{ 319 switch (format) { 320 case PIPE_FORMAT_L4A4_UNORM: 321 case PIPE_FORMAT_R4A4_UNORM: 322 case PIPE_FORMAT_A4R4_UNORM: 323 return V_0280A0_COLOR_4_4; 324 325 /* 8-bit buffers. */ 326 case PIPE_FORMAT_A8_UNORM: 327 case PIPE_FORMAT_A8_SNORM: 328 case PIPE_FORMAT_A8_UINT: 329 case PIPE_FORMAT_A8_SINT: 330 case PIPE_FORMAT_I8_UNORM: 331 case PIPE_FORMAT_I8_SNORM: 332 case PIPE_FORMAT_I8_UINT: 333 case PIPE_FORMAT_I8_SINT: 334 case PIPE_FORMAT_L8_UNORM: 335 case PIPE_FORMAT_L8_SNORM: 336 case PIPE_FORMAT_L8_UINT: 337 case PIPE_FORMAT_L8_SINT: 338 case PIPE_FORMAT_L8_SRGB: 339 case PIPE_FORMAT_R8_UNORM: 340 case PIPE_FORMAT_R8_SNORM: 341 case PIPE_FORMAT_R8_UINT: 342 case PIPE_FORMAT_R8_SINT: 343 return V_0280A0_COLOR_8; 344 345 /* 16-bit buffers. */ 346 case PIPE_FORMAT_B5G6R5_UNORM: 347 return V_0280A0_COLOR_5_6_5; 348 349 case PIPE_FORMAT_B5G5R5A1_UNORM: 350 case PIPE_FORMAT_B5G5R5X1_UNORM: 351 return V_0280A0_COLOR_1_5_5_5; 352 353 case PIPE_FORMAT_B4G4R4A4_UNORM: 354 case PIPE_FORMAT_B4G4R4X4_UNORM: 355 return V_0280A0_COLOR_4_4_4_4; 356 357 case PIPE_FORMAT_Z16_UNORM: 358 return V_0280A0_COLOR_16; 359 360 case PIPE_FORMAT_L8A8_UNORM: 361 case PIPE_FORMAT_L8A8_SNORM: 362 case PIPE_FORMAT_L8A8_UINT: 363 case PIPE_FORMAT_L8A8_SINT: 364 case PIPE_FORMAT_L8A8_SRGB: 365 case PIPE_FORMAT_R8G8_UNORM: 366 case PIPE_FORMAT_R8G8_SNORM: 367 case PIPE_FORMAT_R8G8_UINT: 368 case PIPE_FORMAT_R8G8_SINT: 369 return V_0280A0_COLOR_8_8; 370 371 case PIPE_FORMAT_R16_UNORM: 372 case PIPE_FORMAT_R16_SNORM: 373 case PIPE_FORMAT_R16_UINT: 374 case PIPE_FORMAT_R16_SINT: 375 case PIPE_FORMAT_A16_UNORM: 376 case PIPE_FORMAT_A16_SNORM: 377 case PIPE_FORMAT_A16_UINT: 378 case PIPE_FORMAT_A16_SINT: 379 case PIPE_FORMAT_L16_UNORM: 380 case PIPE_FORMAT_L16_SNORM: 381 case PIPE_FORMAT_L16_UINT: 382 case PIPE_FORMAT_L16_SINT: 383 case PIPE_FORMAT_I16_UNORM: 384 case PIPE_FORMAT_I16_SNORM: 385 case PIPE_FORMAT_I16_UINT: 386 case PIPE_FORMAT_I16_SINT: 387 return V_0280A0_COLOR_16; 388 389 case PIPE_FORMAT_R16_FLOAT: 390 case PIPE_FORMAT_A16_FLOAT: 391 case PIPE_FORMAT_L16_FLOAT: 392 case PIPE_FORMAT_I16_FLOAT: 393 return V_0280A0_COLOR_16_FLOAT; 394 395 /* 32-bit buffers. */ 396 case PIPE_FORMAT_A8B8G8R8_SRGB: 397 case PIPE_FORMAT_A8B8G8R8_UNORM: 398 case PIPE_FORMAT_A8R8G8B8_UNORM: 399 case PIPE_FORMAT_B8G8R8A8_SRGB: 400 case PIPE_FORMAT_B8G8R8A8_UNORM: 401 case PIPE_FORMAT_B8G8R8X8_UNORM: 402 case PIPE_FORMAT_R8G8B8A8_SNORM: 403 case PIPE_FORMAT_R8G8B8A8_UNORM: 404 case PIPE_FORMAT_R8G8B8X8_UNORM: 405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM: 406 case PIPE_FORMAT_X8B8G8R8_UNORM: 407 case PIPE_FORMAT_X8R8G8B8_UNORM: 408 case PIPE_FORMAT_R8G8B8A8_SINT: 409 case PIPE_FORMAT_R8G8B8A8_UINT: 410 return V_0280A0_COLOR_8_8_8_8; 411 412 case PIPE_FORMAT_R10G10B10A2_UNORM: 413 case PIPE_FORMAT_R10G10B10X2_SNORM: 414 case PIPE_FORMAT_B10G10R10A2_UNORM: 415 case PIPE_FORMAT_B10G10R10A2_UINT: 416 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 417 return V_0280A0_COLOR_2_10_10_10; 418 419 case PIPE_FORMAT_Z24X8_UNORM: 420 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 421 return V_0280A0_COLOR_8_24; 422 423 case PIPE_FORMAT_X8Z24_UNORM: 424 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 425 return V_0280A0_COLOR_24_8; 426 427 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 428 return V_0280A0_COLOR_X24_8_32_FLOAT; 429 430 case PIPE_FORMAT_R32_UINT: 431 case PIPE_FORMAT_R32_SINT: 432 case PIPE_FORMAT_A32_UINT: 433 case PIPE_FORMAT_A32_SINT: 434 case PIPE_FORMAT_L32_UINT: 435 case PIPE_FORMAT_L32_SINT: 436 case PIPE_FORMAT_I32_UINT: 437 case PIPE_FORMAT_I32_SINT: 438 return V_0280A0_COLOR_32; 439 440 case PIPE_FORMAT_R32_FLOAT: 441 case PIPE_FORMAT_A32_FLOAT: 442 case PIPE_FORMAT_L32_FLOAT: 443 case PIPE_FORMAT_I32_FLOAT: 444 case PIPE_FORMAT_Z32_FLOAT: 445 return V_0280A0_COLOR_32_FLOAT; 446 447 case PIPE_FORMAT_R16G16_FLOAT: 448 case PIPE_FORMAT_L16A16_FLOAT: 449 return V_0280A0_COLOR_16_16_FLOAT; 450 451 case PIPE_FORMAT_R16G16_UNORM: 452 case PIPE_FORMAT_R16G16_SNORM: 453 case PIPE_FORMAT_R16G16_UINT: 454 case PIPE_FORMAT_R16G16_SINT: 455 case PIPE_FORMAT_L16A16_UNORM: 456 case PIPE_FORMAT_L16A16_SNORM: 457 case PIPE_FORMAT_L16A16_UINT: 458 case PIPE_FORMAT_L16A16_SINT: 459 return V_0280A0_COLOR_16_16; 460 461 case PIPE_FORMAT_R11G11B10_FLOAT: 462 return V_0280A0_COLOR_10_11_11_FLOAT; 463 464 /* 64-bit buffers. */ 465 case PIPE_FORMAT_R16G16B16A16_UINT: 466 case PIPE_FORMAT_R16G16B16A16_SINT: 467 case PIPE_FORMAT_R16G16B16A16_UNORM: 468 case PIPE_FORMAT_R16G16B16A16_SNORM: 469 return V_0280A0_COLOR_16_16_16_16; 470 471 case PIPE_FORMAT_R16G16B16A16_FLOAT: 472 return V_0280A0_COLOR_16_16_16_16_FLOAT; 473 474 case PIPE_FORMAT_R32G32_FLOAT: 475 case PIPE_FORMAT_L32A32_FLOAT: 476 return V_0280A0_COLOR_32_32_FLOAT; 477 478 case PIPE_FORMAT_R32G32_SINT: 479 case PIPE_FORMAT_R32G32_UINT: 480 case PIPE_FORMAT_L32A32_UINT: 481 case PIPE_FORMAT_L32A32_SINT: 482 return V_0280A0_COLOR_32_32; 483 484 /* 128-bit buffers. */ 485 case PIPE_FORMAT_R32G32B32A32_FLOAT: 486 return V_0280A0_COLOR_32_32_32_32_FLOAT; 487 case PIPE_FORMAT_R32G32B32A32_SNORM: 488 case PIPE_FORMAT_R32G32B32A32_UNORM: 489 case PIPE_FORMAT_R32G32B32A32_SINT: 490 case PIPE_FORMAT_R32G32B32A32_UINT: 491 return V_0280A0_COLOR_32_32_32_32; 492 493 /* YUV buffers. */ 494 case PIPE_FORMAT_UYVY: 495 case PIPE_FORMAT_YUYV: 496 default: 497 return ~0U; /* Unsupported. */ 498 } 499} 500 501static uint32_t r600_colorformat_endian_swap(uint32_t colorformat) 502{ 503 if (R600_BIG_ENDIAN) { 504 switch(colorformat) { 505 case V_0280A0_COLOR_4_4: 506 return ENDIAN_NONE; 507 508 /* 8-bit buffers. */ 509 case V_0280A0_COLOR_8: 510 return ENDIAN_NONE; 511 512 /* 16-bit buffers. */ 513 case V_0280A0_COLOR_5_6_5: 514 case V_0280A0_COLOR_1_5_5_5: 515 case V_0280A0_COLOR_4_4_4_4: 516 case V_0280A0_COLOR_16: 517 case V_0280A0_COLOR_8_8: 518 return ENDIAN_8IN16; 519 520 /* 32-bit buffers. */ 521 case V_0280A0_COLOR_8_8_8_8: 522 case V_0280A0_COLOR_2_10_10_10: 523 case V_0280A0_COLOR_8_24: 524 case V_0280A0_COLOR_24_8: 525 case V_0280A0_COLOR_32_FLOAT: 526 case V_0280A0_COLOR_16_16_FLOAT: 527 case V_0280A0_COLOR_16_16: 528 return ENDIAN_8IN32; 529 530 /* 64-bit buffers. */ 531 case V_0280A0_COLOR_16_16_16_16: 532 case V_0280A0_COLOR_16_16_16_16_FLOAT: 533 return ENDIAN_8IN16; 534 535 case V_0280A0_COLOR_32_32_FLOAT: 536 case V_0280A0_COLOR_32_32: 537 case V_0280A0_COLOR_X24_8_32_FLOAT: 538 return ENDIAN_8IN32; 539 540 /* 128-bit buffers. */ 541 case V_0280A0_COLOR_32_32_32_FLOAT: 542 case V_0280A0_COLOR_32_32_32_32_FLOAT: 543 case V_0280A0_COLOR_32_32_32_32: 544 return ENDIAN_8IN32; 545 default: 546 return ENDIAN_NONE; /* Unsupported. */ 547 } 548 } else { 549 return ENDIAN_NONE; 550 } 551} 552 553static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 554{ 555 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U; 556} 557 558static bool r600_is_colorbuffer_format_supported(enum pipe_format format) 559{ 560 return r600_translate_colorformat(format) != ~0U && 561 r600_translate_colorswap(format) != ~0U; 562} 563 564static bool r600_is_zs_format_supported(enum pipe_format format) 565{ 566 return r600_translate_dbformat(format) != ~0U; 567} 568 569boolean r600_is_format_supported(struct pipe_screen *screen, 570 enum pipe_format format, 571 enum pipe_texture_target target, 572 unsigned sample_count, 573 unsigned usage) 574{ 575 struct r600_screen *rscreen = (struct r600_screen*)screen; 576 unsigned retval = 0; 577 578 if (target >= PIPE_MAX_TEXTURE_TYPES) { 579 R600_ERR("r600: unsupported texture type %d\n", target); 580 return FALSE; 581 } 582 583 if (!util_format_is_supported(format, usage)) 584 return FALSE; 585 586 if (sample_count > 1) { 587 if (rscreen->info.drm_minor < 22) 588 return FALSE; 589 590 /* R11G11B10 is broken on R6xx. */ 591 if (rscreen->chip_class == R600 && 592 format == PIPE_FORMAT_R11G11B10_FLOAT) 593 return FALSE; 594 595 switch (sample_count) { 596 case 2: 597 case 4: 598 case 8: 599 break; 600 default: 601 return FALSE; 602 } 603 604 /* require render-target support for multisample resources */ 605 if (util_format_is_depth_or_stencil(format)) { 606 usage |= PIPE_BIND_DEPTH_STENCIL; 607 } else if (util_format_is_pure_integer(format)) { 608 return FALSE; /* no integer textures */ 609 } else { 610 usage |= PIPE_BIND_RENDER_TARGET; 611 } 612 } 613 614 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 615 r600_is_sampler_format_supported(screen, format)) { 616 retval |= PIPE_BIND_SAMPLER_VIEW; 617 } 618 619 if ((usage & (PIPE_BIND_RENDER_TARGET | 620 PIPE_BIND_DISPLAY_TARGET | 621 PIPE_BIND_SCANOUT | 622 PIPE_BIND_SHARED)) && 623 r600_is_colorbuffer_format_supported(format)) { 624 retval |= usage & 625 (PIPE_BIND_RENDER_TARGET | 626 PIPE_BIND_DISPLAY_TARGET | 627 PIPE_BIND_SCANOUT | 628 PIPE_BIND_SHARED); 629 } 630 631 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 632 r600_is_zs_format_supported(format)) { 633 retval |= PIPE_BIND_DEPTH_STENCIL; 634 } 635 636 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 637 r600_is_vertex_format_supported(format)) { 638 retval |= PIPE_BIND_VERTEX_BUFFER; 639 } 640 641 if (usage & PIPE_BIND_TRANSFER_READ) 642 retval |= PIPE_BIND_TRANSFER_READ; 643 if (usage & PIPE_BIND_TRANSFER_WRITE) 644 retval |= PIPE_BIND_TRANSFER_WRITE; 645 646 return retval == usage; 647} 648 649void r600_polygon_offset_update(struct r600_context *rctx) 650{ 651 struct r600_pipe_state state; 652 653 state.id = R600_PIPE_STATE_POLYGON_OFFSET; 654 state.nregs = 0; 655 if (rctx->rasterizer && rctx->framebuffer.zsbuf) { 656 float offset_units = rctx->rasterizer->offset_units; 657 unsigned offset_db_fmt_cntl = 0, depth; 658 659 switch (rctx->framebuffer.zsbuf->format) { 660 case PIPE_FORMAT_Z24X8_UNORM: 661 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 662 depth = -24; 663 offset_units *= 2.0f; 664 break; 665 case PIPE_FORMAT_Z32_FLOAT: 666 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 667 depth = -23; 668 offset_units *= 1.0f; 669 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 670 break; 671 case PIPE_FORMAT_Z16_UNORM: 672 depth = -16; 673 offset_units *= 4.0f; 674 break; 675 default: 676 return; 677 } 678 /* XXX some of those reg can be computed with cso */ 679 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 680 r600_pipe_state_add_reg(&state, 681 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 682 fui(rctx->rasterizer->offset_scale)); 683 r600_pipe_state_add_reg(&state, 684 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 685 fui(offset_units)); 686 r600_pipe_state_add_reg(&state, 687 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 688 fui(rctx->rasterizer->offset_scale)); 689 r600_pipe_state_add_reg(&state, 690 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 691 fui(offset_units)); 692 r600_pipe_state_add_reg(&state, 693 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 694 offset_db_fmt_cntl); 695 r600_context_pipe_state_set(rctx, &state); 696 } 697} 698 699static void *r600_create_blend_state_mode(struct pipe_context *ctx, 700 const struct pipe_blend_state *state, 701 int mode) 702{ 703 struct r600_context *rctx = (struct r600_context *)ctx; 704 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); 705 struct r600_pipe_state *rstate; 706 uint32_t color_control = 0, target_mask = 0; 707 708 if (blend == NULL) { 709 return NULL; 710 } 711 rstate = &blend->rstate; 712 713 rstate->id = R600_PIPE_STATE_BLEND; 714 715 /* R600 does not support per-MRT blends */ 716 if (rctx->family > CHIP_R600) 717 color_control |= S_028808_PER_MRT_BLEND(1); 718 719 if (state->logicop_enable) { 720 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 721 } else { 722 color_control |= (0xcc << 16); 723 } 724 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 725 if (state->independent_blend_enable) { 726 for (int i = 0; i < 8; i++) { 727 if (state->rt[i].blend_enable) { 728 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 729 } 730 target_mask |= (state->rt[i].colormask << (4 * i)); 731 } 732 } else { 733 for (int i = 0; i < 8; i++) { 734 if (state->rt[0].blend_enable) { 735 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 736 } 737 target_mask |= (state->rt[0].colormask << (4 * i)); 738 } 739 } 740 741 if (target_mask) 742 color_control |= S_028808_SPECIAL_OP(mode); 743 else 744 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE); 745 746 blend->cb_target_mask = target_mask; 747 blend->cb_color_control = color_control; 748 /* only MRT0 has dual src blend */ 749 blend->dual_src_blend = util_blend_state_is_dual(state, 0); 750 for (int i = 0; i < 8; i++) { 751 /* state->rt entries > 0 only written if independent blending */ 752 const int j = state->independent_blend_enable ? i : 0; 753 754 unsigned eqRGB = state->rt[j].rgb_func; 755 unsigned srcRGB = state->rt[j].rgb_src_factor; 756 unsigned dstRGB = state->rt[j].rgb_dst_factor; 757 758 unsigned eqA = state->rt[j].alpha_func; 759 unsigned srcA = state->rt[j].alpha_src_factor; 760 unsigned dstA = state->rt[j].alpha_dst_factor; 761 uint32_t bc = 0; 762 763 if (!state->rt[j].blend_enable) 764 continue; 765 766 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 767 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 768 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 769 770 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 771 bc |= S_028804_SEPARATE_ALPHA_BLEND(1); 772 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 773 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 774 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 775 } 776 777 /* R600 does not support per-MRT blends */ 778 if (rctx->family > CHIP_R600) 779 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc); 780 if (i == 0) 781 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc); 782 } 783 784 r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 785 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) | 786 S_028D44_ALPHA_TO_MASK_OFFSET0(2) | 787 S_028D44_ALPHA_TO_MASK_OFFSET1(2) | 788 S_028D44_ALPHA_TO_MASK_OFFSET2(2) | 789 S_028D44_ALPHA_TO_MASK_OFFSET3(2)); 790 791 blend->alpha_to_one = state->alpha_to_one; 792 return rstate; 793} 794 795 796static void *r600_create_blend_state(struct pipe_context *ctx, 797 const struct pipe_blend_state *state) 798{ 799 return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL); 800} 801 802static void *r600_create_dsa_state(struct pipe_context *ctx, 803 const struct pipe_depth_stencil_alpha_state *state) 804{ 805 struct r600_context *rctx = (struct r600_context *)ctx; 806 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa); 807 unsigned db_depth_control, alpha_test_control, alpha_ref; 808 struct r600_pipe_state *rstate; 809 810 if (dsa == NULL) { 811 return NULL; 812 } 813 814 dsa->valuemask[0] = state->stencil[0].valuemask; 815 dsa->valuemask[1] = state->stencil[1].valuemask; 816 dsa->writemask[0] = state->stencil[0].writemask; 817 dsa->writemask[1] = state->stencil[1].writemask; 818 819 rstate = &dsa->rstate; 820 821 rstate->id = R600_PIPE_STATE_DSA; 822 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 823 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 824 S_028800_ZFUNC(state->depth.func); 825 826 /* stencil */ 827 if (state->stencil[0].enabled) { 828 db_depth_control |= S_028800_STENCIL_ENABLE(1); 829 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ 830 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 831 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 832 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 833 834 if (state->stencil[1].enabled) { 835 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 836 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ 837 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 838 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 839 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 840 } 841 } 842 843 /* alpha */ 844 alpha_test_control = 0; 845 alpha_ref = 0; 846 if (state->alpha.enabled) { 847 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 848 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 849 alpha_ref = fui(state->alpha.ref_value); 850 } 851 dsa->sx_alpha_test_control = alpha_test_control & 0xff; 852 dsa->alpha_ref = alpha_ref; 853 854 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control); 855 return rstate; 856} 857 858static void *r600_create_rs_state(struct pipe_context *ctx, 859 const struct pipe_rasterizer_state *state) 860{ 861 struct r600_context *rctx = (struct r600_context *)ctx; 862 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); 863 struct r600_pipe_state *rstate; 864 unsigned tmp; 865 unsigned prov_vtx = 1, polygon_dual_mode; 866 unsigned sc_mode_cntl; 867 float psize_min, psize_max; 868 869 if (rs == NULL) { 870 return NULL; 871 } 872 873 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 874 state->fill_back != PIPE_POLYGON_MODE_FILL); 875 876 if (state->flatshade_first) 877 prov_vtx = 0; 878 879 rstate = &rs->rstate; 880 rs->flatshade = state->flatshade; 881 rs->sprite_coord_enable = state->sprite_coord_enable; 882 rs->two_side = state->light_twoside; 883 rs->clip_plane_enable = state->clip_plane_enable; 884 rs->pa_sc_line_stipple = state->line_stipple_enable ? 885 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 886 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 887 rs->pa_cl_clip_cntl = 888 S_028810_PS_UCP_MODE(3) | 889 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 890 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 891 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 892 rs->multisample_enable = state->multisample; 893 894 /* offset */ 895 rs->offset_units = state->offset_units; 896 rs->offset_scale = state->offset_scale * 12.0f; 897 898 rstate->id = R600_PIPE_STATE_RASTERIZER; 899 tmp = S_0286D4_FLAT_SHADE_ENA(1); 900 if (state->sprite_coord_enable) { 901 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 902 S_0286D4_PNT_SPRITE_OVRD_X(2) | 903 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 904 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 905 S_0286D4_PNT_SPRITE_OVRD_W(1); 906 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 907 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 908 } 909 } 910 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp); 911 912 /* point size 12.4 fixed point */ 913 tmp = r600_pack_float_12p4(state->point_size/2); 914 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 915 916 if (state->point_size_per_vertex) { 917 psize_min = util_get_min_point_size(state); 918 psize_max = 8192; 919 } else { 920 /* Force the point size to be as if the vertex output was disabled. */ 921 psize_min = state->point_size; 922 psize_max = state->point_size; 923 } 924 /* Divide by two, because 0.5 = 1 pixel. */ 925 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 926 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 927 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); 928 929 tmp = r600_pack_float_12p4(state->line_width/2); 930 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 931 932 if (rctx->chip_class >= R700) { 933 sc_mode_cntl = 934 S_028A4C_MSAA_ENABLE(state->multisample) | 935 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | 936 S_028A4C_FORCE_EOV_REZ_ENABLE(1) | 937 S_028A4C_R700_ZMM_LINE_OFFSET(1) | 938 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor); 939 } else { 940 sc_mode_cntl = 941 S_028A4C_MSAA_ENABLE(state->multisample) | 942 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | 943 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1); 944 rs->scissor_enable = state->scissor; 945 } 946 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable); 947 948 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl); 949 950 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 951 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules)); 952 953 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 954 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL, 955 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 956 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) | 957 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) | 958 S_028814_FACE(!state->front_ccw) | 959 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 960 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 961 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 962 S_028814_POLY_MODE(polygon_dual_mode) | 963 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 964 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back))); 965 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard)); 966 return rstate; 967} 968 969static void *r600_create_sampler_state(struct pipe_context *ctx, 970 const struct pipe_sampler_state *state) 971{ 972 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); 973 union util_color uc; 974 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0; 975 976 if (ss == NULL) { 977 return NULL; 978 } 979 980 ss->seamless_cube_map = state->seamless_cube_map; 981 ss->border_color_use = false; 982 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 983 /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */ 984 ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 985 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 986 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 987 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) | 988 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) | 989 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 990 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) | 991 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 992 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0); 993 /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */ 994 ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | 995 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | 996 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)); 997 /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */ 998 ss->tex_sampler_words[2] = S_03C008_TYPE(1); 999 if (uc.ui) { 1000 ss->border_color_use = true; 1001 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */ 1002 ss->border_color[0] = fui(state->border_color.f[0]); 1003 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */ 1004 ss->border_color[1] = fui(state->border_color.f[1]); 1005 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */ 1006 ss->border_color[2] = fui(state->border_color.f[2]); 1007 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */ 1008 ss->border_color[3] = fui(state->border_color.f[3]); 1009 } 1010 return ss; 1011} 1012 1013static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx, 1014 struct pipe_resource *texture, 1015 const struct pipe_sampler_view *state) 1016{ 1017 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); 1018 struct r600_texture *tmp = (struct r600_texture*)texture; 1019 unsigned format, endian; 1020 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 1021 unsigned char swizzle[4], array_mode = 0, tile_type = 0; 1022 unsigned width, height, depth, offset_level, last_level; 1023 1024 if (view == NULL) 1025 return NULL; 1026 1027 /* initialize base object */ 1028 view->base = *state; 1029 view->base.texture = NULL; 1030 pipe_reference(NULL, &texture->reference); 1031 view->base.texture = texture; 1032 view->base.reference.count = 1; 1033 view->base.context = ctx; 1034 1035 swizzle[0] = state->swizzle_r; 1036 swizzle[1] = state->swizzle_g; 1037 swizzle[2] = state->swizzle_b; 1038 swizzle[3] = state->swizzle_a; 1039 1040 format = r600_translate_texformat(ctx->screen, state->format, 1041 swizzle, 1042 &word4, &yuv_format); 1043 assert(format != ~0); 1044 if (format == ~0) { 1045 FREE(view); 1046 return NULL; 1047 } 1048 1049 if (tmp->is_depth && !tmp->is_flushing_texture) { 1050 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) { 1051 FREE(view); 1052 return NULL; 1053 } 1054 tmp = tmp->flushed_depth_texture; 1055 } 1056 1057 endian = r600_colorformat_endian_swap(format); 1058 1059 offset_level = state->u.tex.first_level; 1060 last_level = state->u.tex.last_level - offset_level; 1061 width = tmp->surface.level[offset_level].npix_x; 1062 height = tmp->surface.level[offset_level].npix_y; 1063 depth = tmp->surface.level[offset_level].npix_z; 1064 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); 1065 tile_type = tmp->tile_type; 1066 1067 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 1068 height = 1; 1069 depth = texture->array_size; 1070 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 1071 depth = texture->array_size; 1072 } 1073 switch (tmp->surface.level[offset_level].mode) { 1074 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1075 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; 1076 break; 1077 case RADEON_SURF_MODE_1D: 1078 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 1079 break; 1080 case RADEON_SURF_MODE_2D: 1081 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 1082 break; 1083 case RADEON_SURF_MODE_LINEAR: 1084 default: 1085 array_mode = V_038000_ARRAY_LINEAR_GENERAL; 1086 break; 1087 } 1088 1089 view->tex_resource = &tmp->resource; 1090 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) | 1091 S_038000_TILE_MODE(array_mode) | 1092 S_038000_TILE_TYPE(tile_type) | 1093 S_038000_PITCH((pitch / 8) - 1) | 1094 S_038000_TEX_WIDTH(width - 1)); 1095 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) | 1096 S_038004_TEX_DEPTH(depth - 1) | 1097 S_038004_DATA_FORMAT(format)); 1098 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8; 1099 if (offset_level >= tmp->surface.last_level) { 1100 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8; 1101 } else { 1102 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8; 1103 } 1104 view->tex_resource_words[4] = (word4 | 1105 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) | 1106 S_038010_REQUEST_SIZE(1) | 1107 S_038010_ENDIAN_SWAP(endian) | 1108 S_038010_BASE_LEVEL(0)); 1109 view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) | 1110 S_038014_LAST_ARRAY(state->u.tex.last_layer)); 1111 if (texture->nr_samples > 1) { 1112 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */ 1113 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples)); 1114 } else { 1115 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level); 1116 } 1117 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | 1118 S_038018_MAX_ANISO(4 /* max 16 samples */)); 1119 return &view->base; 1120} 1121 1122static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count, 1123 struct pipe_sampler_view **views) 1124{ 1125 r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views); 1126} 1127 1128static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count, 1129 struct pipe_sampler_view **views) 1130{ 1131 r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views); 1132} 1133 1134static void r600_set_clip_state(struct pipe_context *ctx, 1135 const struct pipe_clip_state *state) 1136{ 1137 struct r600_context *rctx = (struct r600_context *)ctx; 1138 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1139 struct pipe_constant_buffer cb; 1140 1141 if (rstate == NULL) 1142 return; 1143 1144 rctx->clip = *state; 1145 rstate->id = R600_PIPE_STATE_CLIP; 1146 for (int i = 0; i < 6; i++) { 1147 r600_pipe_state_add_reg(rstate, 1148 R_028E20_PA_CL_UCP0_X + i * 16, 1149 fui(state->ucp[i][0])); 1150 r600_pipe_state_add_reg(rstate, 1151 R_028E24_PA_CL_UCP0_Y + i * 16, 1152 fui(state->ucp[i][1]) ); 1153 r600_pipe_state_add_reg(rstate, 1154 R_028E28_PA_CL_UCP0_Z + i * 16, 1155 fui(state->ucp[i][2])); 1156 r600_pipe_state_add_reg(rstate, 1157 R_028E2C_PA_CL_UCP0_W + i * 16, 1158 fui(state->ucp[i][3])); 1159 } 1160 1161 free(rctx->states[R600_PIPE_STATE_CLIP]); 1162 rctx->states[R600_PIPE_STATE_CLIP] = rstate; 1163 r600_context_pipe_state_set(rctx, rstate); 1164 1165 cb.buffer = NULL; 1166 cb.user_buffer = state->ucp; 1167 cb.buffer_offset = 0; 1168 cb.buffer_size = 4*4*8; 1169 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb); 1170 pipe_resource_reference(&cb.buffer, NULL); 1171} 1172 1173static void r600_set_polygon_stipple(struct pipe_context *ctx, 1174 const struct pipe_poly_stipple *state) 1175{ 1176} 1177 1178void r600_set_scissor_state(struct r600_context *rctx, 1179 const struct pipe_scissor_state *state) 1180{ 1181 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1182 uint32_t tl, br; 1183 1184 if (rstate == NULL) 1185 return; 1186 1187 rstate->id = R600_PIPE_STATE_SCISSOR; 1188 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); 1189 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 1190 r600_pipe_state_add_reg(rstate, 1191 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl); 1192 r600_pipe_state_add_reg(rstate, 1193 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br); 1194 1195 free(rctx->states[R600_PIPE_STATE_SCISSOR]); 1196 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate; 1197 r600_context_pipe_state_set(rctx, rstate); 1198} 1199 1200static void r600_pipe_set_scissor_state(struct pipe_context *ctx, 1201 const struct pipe_scissor_state *state) 1202{ 1203 struct r600_context *rctx = (struct r600_context *)ctx; 1204 1205 if (rctx->chip_class == R600) { 1206 rctx->scissor_state = *state; 1207 1208 if (!rctx->scissor_enable) 1209 return; 1210 } 1211 1212 r600_set_scissor_state(rctx, state); 1213} 1214 1215static void r600_set_viewport_state(struct pipe_context *ctx, 1216 const struct pipe_viewport_state *state) 1217{ 1218 struct r600_context *rctx = (struct r600_context *)ctx; 1219 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1220 1221 if (rstate == NULL) 1222 return; 1223 1224 rctx->viewport = *state; 1225 rstate->id = R600_PIPE_STATE_VIEWPORT; 1226 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); 1227 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); 1228 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); 1229 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); 1230 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); 1231 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); 1232 1233 free(rctx->states[R600_PIPE_STATE_VIEWPORT]); 1234 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate; 1235 r600_context_pipe_state_set(rctx, rstate); 1236} 1237 1238static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen, 1239 unsigned size, unsigned alignment) 1240{ 1241 struct pipe_resource buffer; 1242 1243 memset(&buffer, 0, sizeof buffer); 1244 buffer.target = PIPE_BUFFER; 1245 buffer.format = PIPE_FORMAT_R8_UNORM; 1246 buffer.bind = PIPE_BIND_CUSTOM; 1247 buffer.usage = PIPE_USAGE_STATIC; 1248 buffer.flags = 0; 1249 buffer.width0 = size; 1250 buffer.height0 = 1; 1251 buffer.depth0 = 1; 1252 buffer.array_size = 1; 1253 1254 return (struct r600_resource*) 1255 r600_buffer_create(&rscreen->screen, &buffer, alignment); 1256} 1257 1258static void r600_init_color_surface(struct r600_context *rctx, 1259 struct r600_surface *surf, 1260 bool force_cmask_fmask) 1261{ 1262 struct r600_screen *rscreen = rctx->screen; 1263 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 1264 unsigned level = surf->base.u.tex.level; 1265 unsigned pitch, slice; 1266 unsigned color_info; 1267 unsigned format, swap, ntype, endian; 1268 unsigned offset; 1269 const struct util_format_description *desc; 1270 int i; 1271 bool blend_bypass = 0, blend_clamp = 1; 1272 1273 if (rtex->is_depth && !rtex->is_flushing_texture) { 1274 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL); 1275 rtex = rtex->flushed_depth_texture; 1276 assert(rtex); 1277 } 1278 1279 offset = rtex->surface.level[level].offset; 1280 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1281 offset += rtex->surface.level[level].slice_size * 1282 surf->base.u.tex.first_layer; 1283 } 1284 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1285 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1286 if (slice) { 1287 slice = slice - 1; 1288 } 1289 color_info = 0; 1290 switch (rtex->surface.level[level].mode) { 1291 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1292 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED); 1293 break; 1294 case RADEON_SURF_MODE_1D: 1295 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1296 break; 1297 case RADEON_SURF_MODE_2D: 1298 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1299 break; 1300 case RADEON_SURF_MODE_LINEAR: 1301 default: 1302 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL); 1303 break; 1304 } 1305 1306 desc = util_format_description(surf->base.format); 1307 1308 for (i = 0; i < 4; i++) { 1309 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1310 break; 1311 } 1312 } 1313 1314 ntype = V_0280A0_NUMBER_UNORM; 1315 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1316 ntype = V_0280A0_NUMBER_SRGB; 1317 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1318 if (desc->channel[i].normalized) 1319 ntype = V_0280A0_NUMBER_SNORM; 1320 else if (desc->channel[i].pure_integer) 1321 ntype = V_0280A0_NUMBER_SINT; 1322 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1323 if (desc->channel[i].normalized) 1324 ntype = V_0280A0_NUMBER_UNORM; 1325 else if (desc->channel[i].pure_integer) 1326 ntype = V_0280A0_NUMBER_UINT; 1327 } 1328 1329 format = r600_translate_colorformat(surf->base.format); 1330 assert(format != ~0); 1331 1332 swap = r600_translate_colorswap(surf->base.format); 1333 assert(swap != ~0); 1334 1335 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { 1336 endian = ENDIAN_NONE; 1337 } else { 1338 endian = r600_colorformat_endian_swap(format); 1339 } 1340 1341 /* set blend bypass according to docs if SINT/UINT or 1342 8/24 COLOR variants */ 1343 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT || 1344 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 || 1345 format == V_0280A0_COLOR_X24_8_32_FLOAT) { 1346 blend_clamp = 0; 1347 blend_bypass = 1; 1348 } 1349 1350 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT; 1351 1352 color_info |= S_0280A0_FORMAT(format) | 1353 S_0280A0_COMP_SWAP(swap) | 1354 S_0280A0_BLEND_BYPASS(blend_bypass) | 1355 S_0280A0_BLEND_CLAMP(blend_clamp) | 1356 S_0280A0_NUMBER_TYPE(ntype) | 1357 S_0280A0_ENDIAN(endian); 1358 1359 /* EXPORT_NORM is an optimzation that can be enabled for better 1360 * performance in certain cases 1361 */ 1362 if (rctx->chip_class == R600) { 1363 /* EXPORT_NORM can be enabled if: 1364 * - 11-bit or smaller UNORM/SNORM/SRGB 1365 * - BLEND_CLAMP is enabled 1366 * - BLEND_FLOAT32 is disabled 1367 */ 1368 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1369 (desc->channel[i].size < 12 && 1370 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1371 ntype != V_0280A0_NUMBER_UINT && 1372 ntype != V_0280A0_NUMBER_SINT) && 1373 G_0280A0_BLEND_CLAMP(color_info) && 1374 !G_0280A0_BLEND_FLOAT32(color_info)) { 1375 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1376 surf->export_16bpc = true; 1377 } 1378 } else { 1379 /* EXPORT_NORM can be enabled if: 1380 * - 11-bit or smaller UNORM/SNORM/SRGB 1381 * - 16-bit or smaller FLOAT 1382 */ 1383 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1384 ((desc->channel[i].size < 12 && 1385 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1386 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) || 1387 (desc->channel[i].size < 17 && 1388 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) { 1389 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1390 surf->export_16bpc = true; 1391 } 1392 } 1393 1394 /* These might not always be initialized to zero. */ 1395 surf->cb_color_base = offset >> 8; 1396 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) | 1397 S_028060_SLICE_TILE_MAX(slice); 1398 surf->cb_color_fmask = surf->cb_color_base; 1399 surf->cb_color_cmask = surf->cb_color_base; 1400 surf->cb_color_mask = 0; 1401 1402 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, 1403 &rtex->resource.b.b); 1404 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, 1405 &rtex->resource.b.b); 1406 1407 if (rtex->cmask_size) { 1408 surf->cb_color_cmask = rtex->cmask_offset >> 8; 1409 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max); 1410 1411 if (rtex->fmask_size) { 1412 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE); 1413 surf->cb_color_fmask = rtex->fmask_offset >> 8; 1414 surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice); 1415 } else { /* cmask only */ 1416 color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE); 1417 } 1418 } else if (force_cmask_fmask) { 1419 /* Allocate dummy FMASK and CMASK if they aren't allocated already. 1420 * 1421 * R6xx needs FMASK and CMASK for the destination buffer of color resolve, 1422 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated, 1423 * because it's not an MSAA buffer. 1424 */ 1425 struct r600_cmask_info cmask; 1426 struct r600_fmask_info fmask; 1427 1428 r600_texture_get_cmask_info(rscreen, rtex, &cmask); 1429 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask); 1430 1431 /* CMASK. */ 1432 if (!rctx->dummy_cmask || 1433 rctx->dummy_cmask->buf->size < cmask.size || 1434 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) { 1435 struct pipe_transfer *transfer; 1436 void *ptr; 1437 1438 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL); 1439 rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment); 1440 1441 /* Set the contents to 0xCC. */ 1442 ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer); 1443 memset(ptr, 0xCC, cmask.size); 1444 pipe_buffer_unmap(&rctx->context, transfer); 1445 } 1446 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask, 1447 &rctx->dummy_cmask->b.b); 1448 1449 /* FMASK. */ 1450 if (!rctx->dummy_fmask || 1451 rctx->dummy_fmask->buf->size < fmask.size || 1452 rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) { 1453 pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL); 1454 rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment); 1455 1456 } 1457 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask, 1458 &rctx->dummy_fmask->b.b); 1459 1460 /* Init the registers. */ 1461 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE); 1462 surf->cb_color_cmask = 0; 1463 surf->cb_color_fmask = 0; 1464 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) | 1465 S_028100_FMASK_TILE_MAX(slice); 1466 } 1467 1468 surf->cb_color_info = color_info; 1469 1470 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1471 surf->cb_color_view = 0; 1472 } else { 1473 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | 1474 S_028080_SLICE_MAX(surf->base.u.tex.last_layer); 1475 } 1476 1477 surf->color_initialized = true; 1478} 1479 1480static void r600_init_depth_surface(struct r600_context *rctx, 1481 struct r600_surface *surf) 1482{ 1483 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture; 1484 unsigned level, pitch, slice, format, offset, array_mode; 1485 1486 level = surf->base.u.tex.level; 1487 offset = rtex->surface.level[level].offset; 1488 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1489 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1490 if (slice) { 1491 slice = slice - 1; 1492 } 1493 switch (rtex->surface.level[level].mode) { 1494 case RADEON_SURF_MODE_2D: 1495 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 1496 break; 1497 case RADEON_SURF_MODE_1D: 1498 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1499 case RADEON_SURF_MODE_LINEAR: 1500 default: 1501 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 1502 break; 1503 } 1504 1505 format = r600_translate_dbformat(surf->base.format); 1506 assert(format != ~0); 1507 1508 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); 1509 surf->db_depth_base = offset >> 8; 1510 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) | 1511 S_028004_SLICE_MAX(surf->base.u.tex.last_layer); 1512 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice); 1513 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1; 1514 1515 surf->depth_initialized = true; 1516} 1517 1518#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \ 1519 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \ 1520 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \ 1521 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \ 1522 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28)) 1523 1524static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample) 1525{ 1526 static uint32_t sample_locs_2x[] = { 1527 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), 1528 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4), 1529 }; 1530 static unsigned max_dist_2x = 4; 1531 static uint32_t sample_locs_4x[] = { 1532 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), 1533 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6), 1534 }; 1535 static unsigned max_dist_4x = 6; 1536 static uint32_t sample_locs_8x[] = { 1537 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2), 1538 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4), 1539 }; 1540 static unsigned max_dist_8x = 8; 1541 struct r600_context *rctx = (struct r600_context *)ctx; 1542 1543 if (rctx->family == CHIP_R600) { 1544 switch (nsample) { 1545 case 0: 1546 case 1: 1547 return 0; 1548 case 2: 1549 r600_pipe_state_add_reg(rstate, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]); 1550 return max_dist_2x; 1551 case 4: 1552 r600_pipe_state_add_reg(rstate, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]); 1553 return max_dist_4x; 1554 case 8: 1555 r600_pipe_state_add_reg(rstate, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, sample_locs_8x[0]); 1556 r600_pipe_state_add_reg(rstate, R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, sample_locs_8x[1]); 1557 return max_dist_8x; 1558 } 1559 } else { 1560 switch (nsample) { 1561 case 0: 1562 case 1: 1563 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0); 1564 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, 0); 1565 return 0; 1566 case 2: 1567 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_2x[0]); 1568 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_2x[1]); 1569 return max_dist_2x; 1570 case 4: 1571 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_4x[0]); 1572 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_4x[1]); 1573 return max_dist_4x; 1574 case 8: 1575 r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_8x[0]); 1576 r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_8x[1]); 1577 return max_dist_8x; 1578 } 1579 } 1580 R600_ERR("Invalid nr_samples %i\n", nsample); 1581 return 0; 1582} 1583 1584static void r600_set_framebuffer_state(struct pipe_context *ctx, 1585 const struct pipe_framebuffer_state *state) 1586{ 1587 struct r600_context *rctx = (struct r600_context *)ctx; 1588 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1589 struct r600_surface *surf; 1590 struct r600_resource *res; 1591 struct r600_texture *rtex; 1592 uint32_t tl, br, i, nr_samples, max_dist; 1593 bool is_resolve = state->nr_cbufs == 2 && 1594 state->cbufs[0]->texture->nr_samples > 1 && 1595 state->cbufs[1]->texture->nr_samples <= 1; 1596 /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */ 1597 bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve; 1598 1599 if (rstate == NULL) 1600 return; 1601 1602 r600_flush_framebuffer(rctx, false); 1603 1604 /* unreference old buffer and reference new one */ 1605 rstate->id = R600_PIPE_STATE_FRAMEBUFFER; 1606 1607 util_copy_framebuffer_state(&rctx->framebuffer, state); 1608 1609 /* Colorbuffers. */ 1610 rctx->export_16bpc = true; 1611 rctx->nr_cbufs = state->nr_cbufs; 1612 rctx->cb0_is_integer = state->nr_cbufs && 1613 util_format_is_pure_integer(state->cbufs[0]->format); 1614 rctx->compressed_cb_mask = 0; 1615 1616 for (i = 0; i < state->nr_cbufs; i++) { 1617 bool force_cmask_fmask = cb1_force_cmask_fmask && i == 1; 1618 surf = (struct r600_surface*)state->cbufs[i]; 1619 res = (struct r600_resource*)surf->base.texture; 1620 rtex = (struct r600_texture*)res; 1621 1622 if (!surf->color_initialized || force_cmask_fmask) { 1623 r600_init_color_surface(rctx, surf, force_cmask_fmask); 1624 if (force_cmask_fmask) { 1625 /* re-initialize later without compression */ 1626 surf->color_initialized = false; 1627 } 1628 } 1629 1630 if (!surf->export_16bpc) { 1631 rctx->export_16bpc = false; 1632 } 1633 1634 r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4, 1635 surf->cb_color_base, res, RADEON_USAGE_READWRITE); 1636 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 1637 surf->cb_color_info, res, RADEON_USAGE_READWRITE); 1638 r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4, 1639 surf->cb_color_size); 1640 r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4, 1641 surf->cb_color_view); 1642 r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4, 1643 surf->cb_color_fmask, surf->cb_buffer_fmask, 1644 RADEON_USAGE_READWRITE); 1645 r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4, 1646 surf->cb_color_cmask, surf->cb_buffer_cmask, 1647 RADEON_USAGE_READWRITE); 1648 r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4, 1649 surf->cb_color_mask); 1650 1651 if (rtex->fmask_size && rtex->cmask_size) { 1652 rctx->compressed_cb_mask |= 1 << i; 1653 } 1654 } 1655 /* set CB_COLOR1_INFO for possible dual-src blending */ 1656 if (i == 1) { 1657 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4, 1658 surf->cb_color_info, res, RADEON_USAGE_READWRITE); 1659 i++; 1660 } 1661 for (; i < 8 ; i++) { 1662 r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0); 1663 } 1664 1665 /* Update alpha-test state dependencies. 1666 * Alpha-test is done on the first colorbuffer only. */ 1667 if (state->nr_cbufs) { 1668 surf = (struct r600_surface*)state->cbufs[0]; 1669 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) { 1670 rctx->alphatest_state.bypass = surf->alphatest_bypass; 1671 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 1672 } 1673 } 1674 1675 /* ZS buffer. */ 1676 if (state->zsbuf) { 1677 surf = (struct r600_surface*)state->zsbuf; 1678 res = (struct r600_resource*)surf->base.texture; 1679 1680 if (!surf->depth_initialized) { 1681 r600_init_depth_surface(rctx, surf); 1682 } 1683 1684 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base, 1685 res, RADEON_USAGE_READWRITE); 1686 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size); 1687 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view); 1688 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info, 1689 res, RADEON_USAGE_READWRITE); 1690 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit); 1691 } 1692 1693 /* Framebuffer dimensions. */ 1694 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1); 1695 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height); 1696 1697 r600_pipe_state_add_reg(rstate, 1698 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl); 1699 r600_pipe_state_add_reg(rstate, 1700 R_028208_PA_SC_WINDOW_SCISSOR_BR, br); 1701 1702 /* If we're doing MSAA resolve... */ 1703 if (is_resolve) { 1704 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1); 1705 } else { 1706 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This 1707 * will assure that the alpha-test will work even if there is 1708 * no colorbuffer bound. */ 1709 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1710 (1ull << MAX2(state->nr_cbufs, 1)) - 1); 1711 } 1712 1713 /* Multisampling */ 1714 if (state->nr_cbufs) 1715 nr_samples = state->cbufs[0]->texture->nr_samples; 1716 else if (state->zsbuf) 1717 nr_samples = state->zsbuf->texture->nr_samples; 1718 else 1719 nr_samples = 0; 1720 1721 max_dist = r600_set_ms_pos(ctx, rstate, nr_samples); 1722 1723 if (nr_samples > 1) { 1724 unsigned log_samples = util_logbase2(nr_samples); 1725 1726 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 1727 S_028C00_LAST_PIXEL(1) | 1728 S_028C00_EXPAND_LINE_WIDTH(1)); 1729 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 1730 S_028C04_MSAA_NUM_SAMPLES(log_samples) | 1731 S_028C04_MAX_SAMPLE_DIST(max_dist)); 1732 } else { 1733 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1)); 1734 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0); 1735 } 1736 1737 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); 1738 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; 1739 r600_context_pipe_state_set(rctx, rstate); 1740 1741 if (state->zsbuf) { 1742 r600_polygon_offset_update(rctx); 1743 } 1744 1745 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) { 1746 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs; 1747 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 1748 } 1749 1750 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) { 1751 rctx->alphatest_state.bypass = false; 1752 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 1753 } 1754} 1755 1756static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) 1757{ 1758 struct radeon_winsys_cs *cs = rctx->cs; 1759 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; 1760 1761 if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) { 1762 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); 1763 if (rctx->chip_class == R600) { 1764 r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */ 1765 r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */ 1766 } else { 1767 r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */ 1768 r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */ 1769 } 1770 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control); 1771 } else { 1772 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1; 1773 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1; 1774 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1; 1775 1776 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); 1777 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */ 1778 /* Always enable the first color output to make sure alpha-test works even without one. */ 1779 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */ 1780 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, 1781 a->cb_color_control | 1782 S_028808_MULTIWRITE_ENABLE(multiwrite)); 1783 } 1784} 1785 1786static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) 1787{ 1788 struct radeon_winsys_cs *cs = rctx->cs; 1789 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; 1790 unsigned db_render_control = 0; 1791 unsigned db_render_override = 1792 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) | 1793 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | 1794 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); 1795 1796 if (a->occlusion_query_enabled) { 1797 if (rctx->chip_class >= R700) { 1798 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); 1799 } 1800 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); 1801 } 1802 if (a->flush_depthstencil_through_cb) { 1803 assert(a->copy_depth || a->copy_stencil); 1804 1805 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) | 1806 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) | 1807 S_028D0C_COPY_CENTROID(1) | 1808 S_028D0C_COPY_SAMPLE(a->copy_sample); 1809 } 1810 1811 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2); 1812 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */ 1813 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */ 1814} 1815 1816static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom) 1817{ 1818 struct radeon_winsys_cs *cs = rctx->cs; 1819 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask; 1820 1821 while (dirty_mask) { 1822 struct pipe_vertex_buffer *vb; 1823 struct r600_resource *rbuffer; 1824 unsigned offset; 1825 unsigned buffer_index = u_bit_scan(&dirty_mask); 1826 1827 vb = &rctx->vertex_buffer_state.vb[buffer_index]; 1828 rbuffer = (struct r600_resource*)vb->buffer; 1829 assert(rbuffer); 1830 1831 offset = vb->buffer_offset; 1832 1833 /* fetch resources start at index 320 */ 1834 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1835 r600_write_value(cs, (320 + buffer_index) * 7); 1836 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */ 1837 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */ 1838 r600_write_value(cs, /* RESOURCEi_WORD2 */ 1839 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 1840 S_038008_STRIDE(vb->stride)); 1841 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */ 1842 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */ 1843 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */ 1844 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */ 1845 1846 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1847 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ)); 1848 } 1849} 1850 1851static void r600_emit_constant_buffers(struct r600_context *rctx, 1852 struct r600_constbuf_state *state, 1853 unsigned buffer_id_base, 1854 unsigned reg_alu_constbuf_size, 1855 unsigned reg_alu_const_cache) 1856{ 1857 struct radeon_winsys_cs *cs = rctx->cs; 1858 uint32_t dirty_mask = state->dirty_mask; 1859 1860 while (dirty_mask) { 1861 struct pipe_constant_buffer *cb; 1862 struct r600_resource *rbuffer; 1863 unsigned offset; 1864 unsigned buffer_index = ffs(dirty_mask) - 1; 1865 1866 cb = &state->cb[buffer_index]; 1867 rbuffer = (struct r600_resource*)cb->buffer; 1868 assert(rbuffer); 1869 1870 offset = cb->buffer_offset; 1871 1872 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4, 1873 ALIGN_DIVUP(cb->buffer_size >> 4, 16)); 1874 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8); 1875 1876 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1877 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ)); 1878 1879 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1880 r600_write_value(cs, (buffer_id_base + buffer_index) * 7); 1881 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */ 1882 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */ 1883 r600_write_value(cs, /* RESOURCEi_WORD2 */ 1884 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 1885 S_038008_STRIDE(16)); 1886 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */ 1887 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */ 1888 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */ 1889 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */ 1890 1891 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1892 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ)); 1893 1894 dirty_mask &= ~(1 << buffer_index); 1895 } 1896 state->dirty_mask = 0; 1897} 1898 1899static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 1900{ 1901 r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160, 1902 R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 1903 R_028980_ALU_CONST_CACHE_VS_0); 1904} 1905 1906static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 1907{ 1908 r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0, 1909 R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 1910 R_028940_ALU_CONST_CACHE_PS_0); 1911} 1912 1913static void r600_emit_sampler_views(struct r600_context *rctx, 1914 struct r600_samplerview_state *state, 1915 unsigned resource_id_base) 1916{ 1917 struct radeon_winsys_cs *cs = rctx->cs; 1918 uint32_t dirty_mask = state->dirty_mask; 1919 1920 while (dirty_mask) { 1921 struct r600_pipe_sampler_view *rview; 1922 unsigned resource_index = u_bit_scan(&dirty_mask); 1923 unsigned reloc; 1924 1925 rview = state->views[resource_index]; 1926 assert(rview); 1927 1928 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1929 r600_write_value(cs, (resource_id_base + resource_index) * 7); 1930 r600_write_array(cs, 7, rview->tex_resource_words); 1931 1932 /* XXX The kernel needs two relocations. This is stupid. */ 1933 reloc = r600_context_bo_reloc(rctx, rview->tex_resource, 1934 RADEON_USAGE_READ); 1935 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1936 r600_write_value(cs, reloc); 1937 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1938 r600_write_value(cs, reloc); 1939 } 1940 state->dirty_mask = 0; 1941} 1942 1943static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 1944{ 1945 r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS); 1946} 1947 1948static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 1949{ 1950 r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS); 1951} 1952 1953static void r600_emit_sampler(struct r600_context *rctx, 1954 struct r600_textures_info *texinfo, 1955 unsigned resource_id_base, 1956 unsigned border_color_reg) 1957{ 1958 struct radeon_winsys_cs *cs = rctx->cs; 1959 unsigned i; 1960 1961 for (i = 0; i < texinfo->n_samplers; i++) { 1962 1963 if (texinfo->samplers[i] == NULL) { 1964 continue; 1965 } 1966 1967 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable 1968 * filtering between layers. 1969 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. 1970 */ 1971 if (texinfo->views.views[i]) { 1972 if (texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 1973 texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) { 1974 texinfo->samplers[i]->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1); 1975 texinfo->is_array_sampler[i] = true; 1976 } else { 1977 texinfo->samplers[i]->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE; 1978 texinfo->is_array_sampler[i] = false; 1979 } 1980 } 1981 1982 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0)); 1983 r600_write_value(cs, (resource_id_base + i) * 3); 1984 r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words); 1985 1986 if (texinfo->samplers[i]->border_color_use) { 1987 unsigned offset; 1988 1989 offset = border_color_reg; 1990 offset += i * 16; 1991 r600_write_config_reg_seq(cs, offset, 4); 1992 r600_write_array(cs, 4, texinfo->samplers[i]->border_color); 1993 } 1994 } 1995} 1996 1997static void r600_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom) 1998{ 1999 r600_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED); 2000} 2001 2002static void r600_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom) 2003{ 2004 r600_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED); 2005} 2006 2007static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom) 2008{ 2009 struct radeon_winsys_cs *cs = rctx->cs; 2010 unsigned tmp; 2011 2012 tmp = S_009508_DISABLE_CUBE_ANISO(1) | 2013 S_009508_SYNC_GRADIENT(1) | 2014 S_009508_SYNC_WALKER(1) | 2015 S_009508_SYNC_ALIGNER(1); 2016 if (!rctx->seamless_cube_map.enabled) { 2017 tmp |= S_009508_DISABLE_CUBE_WRAP(1); 2018 } 2019 r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp); 2020} 2021 2022static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a) 2023{ 2024 struct r600_sample_mask *s = (struct r600_sample_mask*)a; 2025 uint8_t mask = s->sample_mask; 2026 2027 r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK, 2028 mask | (mask << 8) | (mask << 16) | (mask << 24)); 2029} 2030 2031void r600_init_state_functions(struct r600_context *rctx) 2032{ 2033 r600_init_atom(&rctx->seamless_cube_map.atom, r600_emit_seamless_cube_map, 3, 0); 2034 r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom); 2035 r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0); 2036 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 2037 r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0); 2038 r600_atom_dirty(rctx, &rctx->db_misc_state.atom); 2039 r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0); 2040 r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0); 2041 r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0); 2042 r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0); 2043 r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0); 2044 /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change 2045 * does not take effect 2046 */ 2047 r600_init_atom(&rctx->vs_samplers.atom_sampler, r600_emit_vs_sampler, 0, EMIT_EARLY); 2048 r600_init_atom(&rctx->ps_samplers.atom_sampler, r600_emit_ps_sampler, 0, EMIT_EARLY); 2049 2050 r600_init_atom(&rctx->sample_mask.atom, r600_emit_sample_mask, 3, 0); 2051 rctx->sample_mask.sample_mask = ~0; 2052 r600_atom_dirty(rctx, &rctx->sample_mask.atom); 2053 2054 rctx->context.create_blend_state = r600_create_blend_state; 2055 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; 2056 rctx->context.create_fs_state = r600_create_shader_state_ps; 2057 rctx->context.create_rasterizer_state = r600_create_rs_state; 2058 rctx->context.create_sampler_state = r600_create_sampler_state; 2059 rctx->context.create_sampler_view = r600_create_sampler_view; 2060 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 2061 rctx->context.create_vs_state = r600_create_shader_state_vs; 2062 rctx->context.bind_blend_state = r600_bind_blend_state; 2063 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; 2064 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers; 2065 rctx->context.bind_fs_state = r600_bind_ps_shader; 2066 rctx->context.bind_rasterizer_state = r600_bind_rs_state; 2067 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 2068 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers; 2069 rctx->context.bind_vs_state = r600_bind_vs_shader; 2070 rctx->context.delete_blend_state = r600_delete_state; 2071 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 2072 rctx->context.delete_fs_state = r600_delete_ps_shader; 2073 rctx->context.delete_rasterizer_state = r600_delete_rs_state; 2074 rctx->context.delete_sampler_state = r600_delete_sampler; 2075 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 2076 rctx->context.delete_vs_state = r600_delete_vs_shader; 2077 rctx->context.set_blend_color = r600_set_blend_color; 2078 rctx->context.set_clip_state = r600_set_clip_state; 2079 rctx->context.set_constant_buffer = r600_set_constant_buffer; 2080 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views; 2081 rctx->context.set_framebuffer_state = r600_set_framebuffer_state; 2082 rctx->context.set_polygon_stipple = r600_set_polygon_stipple; 2083 rctx->context.set_sample_mask = r600_set_sample_mask; 2084 rctx->context.set_scissor_state = r600_pipe_set_scissor_state; 2085 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref; 2086 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 2087 rctx->context.set_index_buffer = r600_set_index_buffer; 2088 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views; 2089 rctx->context.set_viewport_state = r600_set_viewport_state; 2090 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 2091 rctx->context.texture_barrier = r600_texture_barrier; 2092 rctx->context.create_stream_output_target = r600_create_so_target; 2093 rctx->context.stream_output_target_destroy = r600_so_target_destroy; 2094 rctx->context.set_stream_output_targets = r600_set_so_targets; 2095} 2096 2097/* Adjust GPR allocation on R6xx/R7xx */ 2098void r600_adjust_gprs(struct r600_context *rctx) 2099{ 2100 struct r600_pipe_state rstate; 2101 unsigned num_ps_gprs = rctx->default_ps_gprs; 2102 unsigned num_vs_gprs = rctx->default_vs_gprs; 2103 unsigned tmp; 2104 int diff; 2105 2106 /* XXX: Following call moved from r600_bind_[ps|vs]_shader, 2107 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for 2108 * adjusting the GPR allocation? 2109 * Do we need this if we aren't really changing config below? */ 2110 r600_inval_shader_cache(rctx); 2111 2112 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs) 2113 { 2114 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs; 2115 num_vs_gprs -= diff; 2116 num_ps_gprs += diff; 2117 } 2118 2119 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs) 2120 { 2121 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs; 2122 num_ps_gprs -= diff; 2123 num_vs_gprs += diff; 2124 } 2125 2126 tmp = 0; 2127 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs); 2128 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs); 2129 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs); 2130 rstate.nregs = 0; 2131 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp); 2132 2133 r600_context_pipe_state_set(rctx, &rstate); 2134} 2135 2136void r600_init_atom_start_cs(struct r600_context *rctx) 2137{ 2138 int ps_prio; 2139 int vs_prio; 2140 int gs_prio; 2141 int es_prio; 2142 int num_ps_gprs; 2143 int num_vs_gprs; 2144 int num_gs_gprs; 2145 int num_es_gprs; 2146 int num_temp_gprs; 2147 int num_ps_threads; 2148 int num_vs_threads; 2149 int num_gs_threads; 2150 int num_es_threads; 2151 int num_ps_stack_entries; 2152 int num_vs_stack_entries; 2153 int num_gs_stack_entries; 2154 int num_es_stack_entries; 2155 enum radeon_family family; 2156 struct r600_command_buffer *cb = &rctx->start_cs_cmd; 2157 uint32_t tmp; 2158 2159 r600_init_command_buffer(cb, 256, EMIT_EARLY); 2160 2161 /* R6xx requires this packet at the start of each command buffer */ 2162 if (rctx->chip_class == R600) { 2163 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0)); 2164 r600_store_value(cb, 0); 2165 } 2166 /* All asics require this one */ 2167 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); 2168 r600_store_value(cb, 0x80000000); 2169 r600_store_value(cb, 0x80000000); 2170 2171 family = rctx->family; 2172 ps_prio = 0; 2173 vs_prio = 1; 2174 gs_prio = 2; 2175 es_prio = 3; 2176 switch (family) { 2177 case CHIP_R600: 2178 num_ps_gprs = 192; 2179 num_vs_gprs = 56; 2180 num_temp_gprs = 4; 2181 num_gs_gprs = 0; 2182 num_es_gprs = 0; 2183 num_ps_threads = 136; 2184 num_vs_threads = 48; 2185 num_gs_threads = 4; 2186 num_es_threads = 4; 2187 num_ps_stack_entries = 128; 2188 num_vs_stack_entries = 128; 2189 num_gs_stack_entries = 0; 2190 num_es_stack_entries = 0; 2191 break; 2192 case CHIP_RV630: 2193 case CHIP_RV635: 2194 num_ps_gprs = 84; 2195 num_vs_gprs = 36; 2196 num_temp_gprs = 4; 2197 num_gs_gprs = 0; 2198 num_es_gprs = 0; 2199 num_ps_threads = 144; 2200 num_vs_threads = 40; 2201 num_gs_threads = 4; 2202 num_es_threads = 4; 2203 num_ps_stack_entries = 40; 2204 num_vs_stack_entries = 40; 2205 num_gs_stack_entries = 32; 2206 num_es_stack_entries = 16; 2207 break; 2208 case CHIP_RV610: 2209 case CHIP_RV620: 2210 case CHIP_RS780: 2211 case CHIP_RS880: 2212 default: 2213 num_ps_gprs = 84; 2214 num_vs_gprs = 36; 2215 num_temp_gprs = 4; 2216 num_gs_gprs = 0; 2217 num_es_gprs = 0; 2218 num_ps_threads = 136; 2219 num_vs_threads = 48; 2220 num_gs_threads = 4; 2221 num_es_threads = 4; 2222 num_ps_stack_entries = 40; 2223 num_vs_stack_entries = 40; 2224 num_gs_stack_entries = 32; 2225 num_es_stack_entries = 16; 2226 break; 2227 case CHIP_RV670: 2228 num_ps_gprs = 144; 2229 num_vs_gprs = 40; 2230 num_temp_gprs = 4; 2231 num_gs_gprs = 0; 2232 num_es_gprs = 0; 2233 num_ps_threads = 136; 2234 num_vs_threads = 48; 2235 num_gs_threads = 4; 2236 num_es_threads = 4; 2237 num_ps_stack_entries = 40; 2238 num_vs_stack_entries = 40; 2239 num_gs_stack_entries = 32; 2240 num_es_stack_entries = 16; 2241 break; 2242 case CHIP_RV770: 2243 num_ps_gprs = 192; 2244 num_vs_gprs = 56; 2245 num_temp_gprs = 4; 2246 num_gs_gprs = 0; 2247 num_es_gprs = 0; 2248 num_ps_threads = 188; 2249 num_vs_threads = 60; 2250 num_gs_threads = 0; 2251 num_es_threads = 0; 2252 num_ps_stack_entries = 256; 2253 num_vs_stack_entries = 256; 2254 num_gs_stack_entries = 0; 2255 num_es_stack_entries = 0; 2256 break; 2257 case CHIP_RV730: 2258 case CHIP_RV740: 2259 num_ps_gprs = 84; 2260 num_vs_gprs = 36; 2261 num_temp_gprs = 4; 2262 num_gs_gprs = 0; 2263 num_es_gprs = 0; 2264 num_ps_threads = 188; 2265 num_vs_threads = 60; 2266 num_gs_threads = 0; 2267 num_es_threads = 0; 2268 num_ps_stack_entries = 128; 2269 num_vs_stack_entries = 128; 2270 num_gs_stack_entries = 0; 2271 num_es_stack_entries = 0; 2272 break; 2273 case CHIP_RV710: 2274 num_ps_gprs = 192; 2275 num_vs_gprs = 56; 2276 num_temp_gprs = 4; 2277 num_gs_gprs = 0; 2278 num_es_gprs = 0; 2279 num_ps_threads = 144; 2280 num_vs_threads = 48; 2281 num_gs_threads = 0; 2282 num_es_threads = 0; 2283 num_ps_stack_entries = 128; 2284 num_vs_stack_entries = 128; 2285 num_gs_stack_entries = 0; 2286 num_es_stack_entries = 0; 2287 break; 2288 } 2289 2290 rctx->default_ps_gprs = num_ps_gprs; 2291 rctx->default_vs_gprs = num_vs_gprs; 2292 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs; 2293 2294 /* SQ_CONFIG */ 2295 tmp = 0; 2296 switch (family) { 2297 case CHIP_RV610: 2298 case CHIP_RV620: 2299 case CHIP_RS780: 2300 case CHIP_RS880: 2301 case CHIP_RV710: 2302 break; 2303 default: 2304 tmp |= S_008C00_VC_ENABLE(1); 2305 break; 2306 } 2307 tmp |= S_008C00_DX9_CONSTS(0); 2308 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); 2309 tmp |= S_008C00_PS_PRIO(ps_prio); 2310 tmp |= S_008C00_VS_PRIO(vs_prio); 2311 tmp |= S_008C00_GS_PRIO(gs_prio); 2312 tmp |= S_008C00_ES_PRIO(es_prio); 2313 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp); 2314 2315 /* SQ_GPR_RESOURCE_MGMT_2 */ 2316 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs); 2317 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); 2318 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4); 2319 r600_store_value(cb, tmp); 2320 2321 /* SQ_THREAD_RESOURCE_MGMT */ 2322 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads); 2323 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads); 2324 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads); 2325 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads); 2326 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */ 2327 2328 /* SQ_STACK_RESOURCE_MGMT_1 */ 2329 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 2330 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 2331 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */ 2332 2333 /* SQ_STACK_RESOURCE_MGMT_2 */ 2334 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 2335 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 2336 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */ 2337 2338 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0); 2339 2340 if (rctx->chip_class >= R700) { 2341 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000); 2342 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0); 2343 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204); 2344 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); 2345 } else { 2346 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2347 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000); 2348 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204); 2349 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1); 2350 } 2351 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9); 2352 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */ 2353 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */ 2354 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */ 2355 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */ 2356 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */ 2357 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */ 2358 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */ 2359 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */ 2360 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */ 2361 2362 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); 2363 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ 2364 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ 2365 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ 2366 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ 2367 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ 2368 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ 2369 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ 2370 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ 2371 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ 2372 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ 2373 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ 2374 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ 2375 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */ 2376 2377 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0); 2378 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0); 2379 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0); 2380 2381 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3); 2382 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */ 2383 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */ 2384 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ 2385 2386 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0); 2387 2388 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2); 2389 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */ 2390 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */ 2391 2392 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); 2393 2394 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2); 2395 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */ 2396 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */ 2397 2398 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3); 2399 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */ 2400 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */ 2401 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */ 2402 2403 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2); 2404 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */ 2405 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */ 2406 2407 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); 2408 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0); 2409 2410 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4); 2411 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */ 2412 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */ 2413 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */ 2414 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */ 2415 2416 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2); 2417 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */ 2418 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */ 2419 2420 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F); 2421 2422 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); 2423 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 2424 2425 if (rctx->chip_class >= R700) { 2426 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 2427 } 2428 2429 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4); 2430 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */ 2431 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */ 2432 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */ 2433 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */ 2434 2435 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); 2436 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ 2437 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ 2438 2439 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); 2440 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ 2441 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ 2442 2443 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2); 2444 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */ 2445 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */ 2446 2447 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0); 2448 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0); 2449 2450 if (rctx->chip_class == R700 && rctx->screen->has_streamout) 2451 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); 2452 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); 2453 if (rctx->screen->has_streamout) { 2454 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); 2455 } 2456 2457 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF); 2458 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF); 2459} 2460 2461void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2462{ 2463 struct r600_context *rctx = (struct r600_context *)ctx; 2464 struct r600_pipe_state *rstate = &shader->rstate; 2465 struct r600_shader *rshader = &shader->shader; 2466 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; 2467 int pos_index = -1, face_index = -1; 2468 unsigned tmp, sid, ufi = 0; 2469 int need_linear = 0; 2470 unsigned z_export = 0, stencil_export = 0; 2471 2472 rstate->nregs = 0; 2473 2474 for (i = 0; i < rshader->ninput; i++) { 2475 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) 2476 pos_index = i; 2477 if (rshader->input[i].name == TGSI_SEMANTIC_FACE) 2478 face_index = i; 2479 2480 sid = rshader->input[i].spi_sid; 2481 2482 tmp = S_028644_SEMANTIC(sid); 2483 2484 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || 2485 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 2486 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && 2487 rctx->rasterizer && rctx->rasterizer->flatshade)) 2488 tmp |= S_028644_FLAT_SHADE(1); 2489 2490 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC && 2491 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) { 2492 tmp |= S_028644_PT_SPRITE_TEX(1); 2493 } 2494 2495 if (rshader->input[i].centroid) 2496 tmp |= S_028644_SEL_CENTROID(1); 2497 2498 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) { 2499 need_linear = 1; 2500 tmp |= S_028644_SEL_LINEAR(1); 2501 } 2502 2503 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 2504 tmp); 2505 } 2506 2507 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 2508 for (i = 0; i < rshader->noutput; i++) { 2509 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) 2510 z_export = 1; 2511 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 2512 stencil_export = 1; 2513 } 2514 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export); 2515 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export); 2516 if (rshader->uses_kill) 2517 db_shader_control |= S_02880C_KILL_ENABLE(1); 2518 2519 exports_ps = 0; 2520 for (i = 0; i < rshader->noutput; i++) { 2521 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || 2522 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) { 2523 exports_ps |= 1; 2524 } 2525 } 2526 num_cout = rshader->nr_ps_color_exports; 2527 exports_ps |= S_028854_EXPORT_COLORS(num_cout); 2528 if (!exports_ps) { 2529 /* always at least export 1 component per pixel */ 2530 exports_ps = 2; 2531 } 2532 2533 shader->nr_ps_color_outputs = num_cout; 2534 2535 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) | 2536 S_0286CC_PERSP_GRADIENT_ENA(1)| 2537 S_0286CC_LINEAR_GRADIENT_ENA(need_linear); 2538 spi_input_z = 0; 2539 if (pos_index != -1) { 2540 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) | 2541 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) | 2542 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) | 2543 S_0286CC_BARYC_SAMPLE_CNTL(1)); 2544 spi_input_z |= 1; 2545 } 2546 2547 spi_ps_in_control_1 = 0; 2548 if (face_index != -1) { 2549 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | 2550 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); 2551 } 2552 2553 /* HW bug in original R600 */ 2554 if (rctx->family == CHIP_R600) 2555 ufi = 1; 2556 2557 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0); 2558 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1); 2559 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z); 2560 r600_pipe_state_add_reg_bo(rstate, 2561 R_028840_SQ_PGM_START_PS, 2562 0, shader->bo, RADEON_USAGE_READ); 2563 r600_pipe_state_add_reg(rstate, 2564 R_028850_SQ_PGM_RESOURCES_PS, 2565 S_028850_NUM_GPRS(rshader->bc.ngpr) | 2566 S_028850_STACK_SIZE(rshader->bc.nstack) | 2567 S_028850_UNCACHED_FIRST_INST(ufi)); 2568 r600_pipe_state_add_reg(rstate, 2569 R_028854_SQ_PGM_EXPORTS_PS, 2570 exports_ps); 2571 /* only set some bits here, the other bits are set in the dsa state */ 2572 shader->db_shader_control = db_shader_control; 2573 shader->ps_depth_export = z_export | stencil_export; 2574 2575 shader->sprite_coord_enable = rctx->sprite_coord_enable; 2576 if (rctx->rasterizer) 2577 shader->flatshade = rctx->rasterizer->flatshade; 2578} 2579 2580void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2581{ 2582 struct r600_context *rctx = (struct r600_context *)ctx; 2583 struct r600_pipe_state *rstate = &shader->rstate; 2584 struct r600_shader *rshader = &shader->shader; 2585 unsigned spi_vs_out_id[10] = {}; 2586 unsigned i, tmp, nparams = 0; 2587 2588 /* clear previous register */ 2589 rstate->nregs = 0; 2590 2591 for (i = 0; i < rshader->noutput; i++) { 2592 if (rshader->output[i].spi_sid) { 2593 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); 2594 spi_vs_out_id[nparams / 4] |= tmp; 2595 nparams++; 2596 } 2597 } 2598 2599 for (i = 0; i < 10; i++) { 2600 r600_pipe_state_add_reg(rstate, 2601 R_028614_SPI_VS_OUT_ID_0 + i * 4, 2602 spi_vs_out_id[i]); 2603 } 2604 2605 /* Certain attributes (position, psize, etc.) don't count as params. 2606 * VS is required to export at least one param and r600_shader_from_tgsi() 2607 * takes care of adding a dummy export. 2608 */ 2609 if (nparams < 1) 2610 nparams = 1; 2611 2612 r600_pipe_state_add_reg(rstate, 2613 R_0286C4_SPI_VS_OUT_CONFIG, 2614 S_0286C4_VS_EXPORT_COUNT(nparams - 1)); 2615 r600_pipe_state_add_reg(rstate, 2616 R_028868_SQ_PGM_RESOURCES_VS, 2617 S_028868_NUM_GPRS(rshader->bc.ngpr) | 2618 S_028868_STACK_SIZE(rshader->bc.nstack)); 2619 r600_pipe_state_add_reg_bo(rstate, 2620 R_028858_SQ_PGM_START_VS, 2621 0, shader->bo, RADEON_USAGE_READ); 2622 2623 shader->pa_cl_vs_out_cntl = 2624 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) | 2625 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) | 2626 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) | 2627 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size); 2628} 2629 2630void r600_fetch_shader(struct pipe_context *ctx, 2631 struct r600_vertex_element *ve) 2632{ 2633 struct r600_pipe_state *rstate; 2634 struct r600_context *rctx = (struct r600_context *)ctx; 2635 2636 rstate = &ve->rstate; 2637 rstate->id = R600_PIPE_STATE_FETCH_SHADER; 2638 rstate->nregs = 0; 2639 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS, 2640 0, 2641 ve->fetch_shader, RADEON_USAGE_READ); 2642} 2643 2644void *r600_create_resolve_blend(struct r600_context *rctx) 2645{ 2646 struct pipe_blend_state blend; 2647 struct r600_pipe_state *rstate; 2648 unsigned i; 2649 2650 memset(&blend, 0, sizeof(blend)); 2651 blend.independent_blend_enable = true; 2652 for (i = 0; i < 2; i++) { 2653 blend.rt[i].colormask = 0xf; 2654 blend.rt[i].blend_enable = 1; 2655 blend.rt[i].rgb_func = PIPE_BLEND_ADD; 2656 blend.rt[i].alpha_func = PIPE_BLEND_ADD; 2657 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO; 2658 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO; 2659 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO; 2660 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO; 2661 } 2662 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX); 2663 return rstate; 2664} 2665 2666void *r700_create_resolve_blend(struct r600_context *rctx) 2667{ 2668 struct pipe_blend_state blend; 2669 struct r600_pipe_state *rstate; 2670 2671 memset(&blend, 0, sizeof(blend)); 2672 blend.independent_blend_enable = true; 2673 blend.rt[0].colormask = 0xf; 2674 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX); 2675 return rstate; 2676} 2677 2678void *r600_create_decompress_blend(struct r600_context *rctx) 2679{ 2680 struct pipe_blend_state blend; 2681 struct r600_pipe_state *rstate; 2682 2683 memset(&blend, 0, sizeof(blend)); 2684 blend.independent_blend_enable = true; 2685 blend.rt[0].colormask = 0xf; 2686 rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES); 2687 return rstate; 2688} 2689 2690void *r600_create_db_flush_dsa(struct r600_context *rctx) 2691{ 2692 struct pipe_depth_stencil_alpha_state dsa; 2693 boolean quirk = false; 2694 2695 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 || 2696 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635) 2697 quirk = true; 2698 2699 memset(&dsa, 0, sizeof(dsa)); 2700 2701 if (quirk) { 2702 dsa.depth.enabled = 1; 2703 dsa.depth.func = PIPE_FUNC_LEQUAL; 2704 dsa.stencil[0].enabled = 1; 2705 dsa.stencil[0].func = PIPE_FUNC_ALWAYS; 2706 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP; 2707 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR; 2708 dsa.stencil[0].writemask = 0xff; 2709 } 2710 2711 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 2712} 2713 2714void r600_update_dual_export_state(struct r600_context * rctx) 2715{ 2716 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs && 2717 !rctx->ps_shader->current->ps_depth_export; 2718 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control | 2719 S_02880C_DUAL_EXPORT_ENABLE(dual_export); 2720 2721 if (db_shader_control != rctx->db_shader_control) { 2722 struct r600_pipe_state rstate; 2723 2724 rctx->db_shader_control = db_shader_control; 2725 rstate.nregs = 0; 2726 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control); 2727 r600_context_pipe_state_set(rctx, &rstate); 2728 } 2729} 2730