r600_state.c revision c586fce4fb537e904e35cb5197b6b7fe02217acb 
1e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng/*
2e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng *
4e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * Permission is hereby granted, free of charge, to any person obtaining a
5e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * copy of this software and associated documentation files (the "Software"),
6e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * to deal in the Software without restriction, including without limitation
7e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * on the rights to use, copy, modify, merge, publish, distribute, sub
8e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * license, and/or sell copies of the Software, and to permit persons to whom
9e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * the Software is furnished to do so, subject to the following conditions:
10e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng *
11e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * The above copyright notice and this permission notice (including the next
12e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * paragraph) shall be included in all copies or substantial portions of the
13e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * Software.
14e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng *
15e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng * USE OR OTHER DEALINGS IN THE SOFTWARE.
22e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng */
23e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng#include "r600_formats.h"
24e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng#include "r600d.h"
25e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng
26e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng#include "pipe/p_shader_tokens.h"
27e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng#include "util/u_pack_color.h"
28e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng#include "util/u_memory.h"
29e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng#include "util/u_framebuffer.h"
30e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng#include "util/u_dual_blend.h"
31e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng
32e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Chengstatic uint32_t r600_translate_blend_function(int blend_func)
33e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng{
34e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng	switch (blend_func) {
35e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng	case PIPE_BLEND_ADD:
36e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng		return V_028804_COMB_DST_PLUS_SRC;
37e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng	case PIPE_BLEND_SUBTRACT:
38e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng		return V_028804_COMB_SRC_MINUS_DST;
39e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng	case PIPE_BLEND_REVERSE_SUBTRACT:
40e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng		return V_028804_COMB_DST_MINUS_SRC;
41e6e8a0bd7cffcc9ae2e0e75546fb12a19213d4aeBen Cheng	case PIPE_BLEND_MIN:
42		return V_028804_COMB_MIN_DST_SRC;
43	case PIPE_BLEND_MAX:
44		return V_028804_COMB_MAX_DST_SRC;
45	default:
46		R600_ERR("Unknown blend function %d\n", blend_func);
47		assert(0);
48		break;
49	}
50	return 0;
51}
52
53static uint32_t r600_translate_blend_factor(int blend_fact)
54{
55	switch (blend_fact) {
56	case PIPE_BLENDFACTOR_ONE:
57		return V_028804_BLEND_ONE;
58	case PIPE_BLENDFACTOR_SRC_COLOR:
59		return V_028804_BLEND_SRC_COLOR;
60	case PIPE_BLENDFACTOR_SRC_ALPHA:
61		return V_028804_BLEND_SRC_ALPHA;
62	case PIPE_BLENDFACTOR_DST_ALPHA:
63		return V_028804_BLEND_DST_ALPHA;
64	case PIPE_BLENDFACTOR_DST_COLOR:
65		return V_028804_BLEND_DST_COLOR;
66	case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
67		return V_028804_BLEND_SRC_ALPHA_SATURATE;
68	case PIPE_BLENDFACTOR_CONST_COLOR:
69		return V_028804_BLEND_CONST_COLOR;
70	case PIPE_BLENDFACTOR_CONST_ALPHA:
71		return V_028804_BLEND_CONST_ALPHA;
72	case PIPE_BLENDFACTOR_ZERO:
73		return V_028804_BLEND_ZERO;
74	case PIPE_BLENDFACTOR_INV_SRC_COLOR:
75		return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
76	case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
77		return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
78	case PIPE_BLENDFACTOR_INV_DST_ALPHA:
79		return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
80	case PIPE_BLENDFACTOR_INV_DST_COLOR:
81		return V_028804_BLEND_ONE_MINUS_DST_COLOR;
82	case PIPE_BLENDFACTOR_INV_CONST_COLOR:
83		return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
84	case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
85		return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
86	case PIPE_BLENDFACTOR_SRC1_COLOR:
87		return V_028804_BLEND_SRC1_COLOR;
88	case PIPE_BLENDFACTOR_SRC1_ALPHA:
89		return V_028804_BLEND_SRC1_ALPHA;
90	case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
91		return V_028804_BLEND_INV_SRC1_COLOR;
92	case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
93		return V_028804_BLEND_INV_SRC1_ALPHA;
94	default:
95		R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
96		assert(0);
97		break;
98	}
99	return 0;
100}
101
102static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
103{
104	switch (dim) {
105	default:
106	case PIPE_TEXTURE_1D:
107		return V_038000_SQ_TEX_DIM_1D;
108	case PIPE_TEXTURE_1D_ARRAY:
109		return V_038000_SQ_TEX_DIM_1D_ARRAY;
110	case PIPE_TEXTURE_2D:
111	case PIPE_TEXTURE_RECT:
112		return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
113					V_038000_SQ_TEX_DIM_2D;
114	case PIPE_TEXTURE_2D_ARRAY:
115		return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
116					V_038000_SQ_TEX_DIM_2D_ARRAY;
117	case PIPE_TEXTURE_3D:
118		return V_038000_SQ_TEX_DIM_3D;
119	case PIPE_TEXTURE_CUBE:
120		return V_038000_SQ_TEX_DIM_CUBEMAP;
121	}
122}
123
124static uint32_t r600_translate_dbformat(enum pipe_format format)
125{
126	switch (format) {
127	case PIPE_FORMAT_Z16_UNORM:
128		return V_028010_DEPTH_16;
129	case PIPE_FORMAT_Z24X8_UNORM:
130		return V_028010_DEPTH_X8_24;
131	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
132		return V_028010_DEPTH_8_24;
133	case PIPE_FORMAT_Z32_FLOAT:
134		return V_028010_DEPTH_32_FLOAT;
135	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
136		return V_028010_DEPTH_X24_8_32_FLOAT;
137	default:
138		return ~0U;
139	}
140}
141
142static uint32_t r600_translate_colorswap(enum pipe_format format)
143{
144	switch (format) {
145	/* 8-bit buffers. */
146	case PIPE_FORMAT_A8_UNORM:
147	case PIPE_FORMAT_A8_SNORM:
148	case PIPE_FORMAT_A8_UINT:
149	case PIPE_FORMAT_A8_SINT:
150	case PIPE_FORMAT_A16_UNORM:
151	case PIPE_FORMAT_A16_SNORM:
152	case PIPE_FORMAT_A16_UINT:
153	case PIPE_FORMAT_A16_SINT:
154	case PIPE_FORMAT_A16_FLOAT:
155	case PIPE_FORMAT_A32_UINT:
156	case PIPE_FORMAT_A32_SINT:
157	case PIPE_FORMAT_A32_FLOAT:
158	case PIPE_FORMAT_R4A4_UNORM:
159		return V_0280A0_SWAP_ALT_REV;
160	case PIPE_FORMAT_I8_UNORM:
161	case PIPE_FORMAT_I8_SNORM:
162	case PIPE_FORMAT_I8_UINT:
163	case PIPE_FORMAT_I8_SINT:
164	case PIPE_FORMAT_L8_UNORM:
165	case PIPE_FORMAT_L8_SNORM:
166	case PIPE_FORMAT_L8_UINT:
167	case PIPE_FORMAT_L8_SINT:
168	case PIPE_FORMAT_L8_SRGB:
169	case PIPE_FORMAT_L16_UNORM:
170	case PIPE_FORMAT_L16_SNORM:
171	case PIPE_FORMAT_L16_UINT:
172	case PIPE_FORMAT_L16_SINT:
173	case PIPE_FORMAT_L16_FLOAT:
174	case PIPE_FORMAT_L32_UINT:
175	case PIPE_FORMAT_L32_SINT:
176	case PIPE_FORMAT_L32_FLOAT:
177	case PIPE_FORMAT_I16_UNORM:
178	case PIPE_FORMAT_I16_SNORM:
179	case PIPE_FORMAT_I16_UINT:
180	case PIPE_FORMAT_I16_SINT:
181	case PIPE_FORMAT_I16_FLOAT:
182	case PIPE_FORMAT_I32_UINT:
183	case PIPE_FORMAT_I32_SINT:
184	case PIPE_FORMAT_I32_FLOAT:
185	case PIPE_FORMAT_R8_UNORM:
186	case PIPE_FORMAT_R8_SNORM:
187	case PIPE_FORMAT_R8_UINT:
188	case PIPE_FORMAT_R8_SINT:
189		return V_0280A0_SWAP_STD;
190
191	case PIPE_FORMAT_L4A4_UNORM:
192	case PIPE_FORMAT_A4R4_UNORM:
193		return V_0280A0_SWAP_ALT;
194
195	/* 16-bit buffers. */
196	case PIPE_FORMAT_B5G6R5_UNORM:
197		return V_0280A0_SWAP_STD_REV;
198
199	case PIPE_FORMAT_B5G5R5A1_UNORM:
200	case PIPE_FORMAT_B5G5R5X1_UNORM:
201		return V_0280A0_SWAP_ALT;
202
203	case PIPE_FORMAT_B4G4R4A4_UNORM:
204	case PIPE_FORMAT_B4G4R4X4_UNORM:
205		return V_0280A0_SWAP_ALT;
206
207	case PIPE_FORMAT_Z16_UNORM:
208		return V_0280A0_SWAP_STD;
209
210	case PIPE_FORMAT_L8A8_UNORM:
211	case PIPE_FORMAT_L8A8_SNORM:
212	case PIPE_FORMAT_L8A8_UINT:
213	case PIPE_FORMAT_L8A8_SINT:
214	case PIPE_FORMAT_L8A8_SRGB:
215	case PIPE_FORMAT_L16A16_UNORM:
216	case PIPE_FORMAT_L16A16_SNORM:
217	case PIPE_FORMAT_L16A16_UINT:
218	case PIPE_FORMAT_L16A16_SINT:
219	case PIPE_FORMAT_L16A16_FLOAT:
220	case PIPE_FORMAT_L32A32_UINT:
221	case PIPE_FORMAT_L32A32_SINT:
222	case PIPE_FORMAT_L32A32_FLOAT:
223		return V_0280A0_SWAP_ALT;
224	case PIPE_FORMAT_R8G8_UNORM:
225	case PIPE_FORMAT_R8G8_SNORM:
226	case PIPE_FORMAT_R8G8_UINT:
227	case PIPE_FORMAT_R8G8_SINT:
228		return V_0280A0_SWAP_STD;
229
230	case PIPE_FORMAT_R16_UNORM:
231	case PIPE_FORMAT_R16_SNORM:
232	case PIPE_FORMAT_R16_UINT:
233	case PIPE_FORMAT_R16_SINT:
234	case PIPE_FORMAT_R16_FLOAT:
235		return V_0280A0_SWAP_STD;
236
237	/* 32-bit buffers. */
238
239	case PIPE_FORMAT_A8B8G8R8_SRGB:
240		return V_0280A0_SWAP_STD_REV;
241	case PIPE_FORMAT_B8G8R8A8_SRGB:
242		return V_0280A0_SWAP_ALT;
243
244	case PIPE_FORMAT_B8G8R8A8_UNORM:
245	case PIPE_FORMAT_B8G8R8X8_UNORM:
246		return V_0280A0_SWAP_ALT;
247
248	case PIPE_FORMAT_A8R8G8B8_UNORM:
249	case PIPE_FORMAT_X8R8G8B8_UNORM:
250		return V_0280A0_SWAP_ALT_REV;
251	case PIPE_FORMAT_R8G8B8A8_SNORM:
252	case PIPE_FORMAT_R8G8B8A8_UNORM:
253	case PIPE_FORMAT_R8G8B8X8_UNORM:
254	case PIPE_FORMAT_R8G8B8A8_SINT:
255	case PIPE_FORMAT_R8G8B8A8_UINT:
256		return V_0280A0_SWAP_STD;
257
258	case PIPE_FORMAT_A8B8G8R8_UNORM:
259	case PIPE_FORMAT_X8B8G8R8_UNORM:
260	/* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
261		return V_0280A0_SWAP_STD_REV;
262
263	case PIPE_FORMAT_Z24X8_UNORM:
264	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
265		return V_0280A0_SWAP_STD;
266
267	case PIPE_FORMAT_X8Z24_UNORM:
268	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
269		return V_0280A0_SWAP_STD;
270
271	case PIPE_FORMAT_R10G10B10A2_UNORM:
272	case PIPE_FORMAT_R10G10B10X2_SNORM:
273	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
274		return V_0280A0_SWAP_STD;
275
276	case PIPE_FORMAT_B10G10R10A2_UNORM:
277	case PIPE_FORMAT_B10G10R10A2_UINT:
278		return V_0280A0_SWAP_ALT;
279
280	case PIPE_FORMAT_R11G11B10_FLOAT:
281	case PIPE_FORMAT_R16G16_UNORM:
282	case PIPE_FORMAT_R16G16_SNORM:
283	case PIPE_FORMAT_R16G16_FLOAT:
284	case PIPE_FORMAT_R16G16_UINT:
285	case PIPE_FORMAT_R16G16_SINT:
286	case PIPE_FORMAT_R32_UINT:
287	case PIPE_FORMAT_R32_SINT:
288	case PIPE_FORMAT_R32_FLOAT:
289	case PIPE_FORMAT_Z32_FLOAT:
290		return V_0280A0_SWAP_STD;
291
292	/* 64-bit buffers. */
293	case PIPE_FORMAT_R32G32_FLOAT:
294	case PIPE_FORMAT_R32G32_UINT:
295	case PIPE_FORMAT_R32G32_SINT:
296	case PIPE_FORMAT_R16G16B16A16_UNORM:
297	case PIPE_FORMAT_R16G16B16A16_SNORM:
298	case PIPE_FORMAT_R16G16B16A16_UINT:
299	case PIPE_FORMAT_R16G16B16A16_SINT:
300	case PIPE_FORMAT_R16G16B16A16_FLOAT:
301	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
302
303	/* 128-bit buffers. */
304	case PIPE_FORMAT_R32G32B32A32_FLOAT:
305	case PIPE_FORMAT_R32G32B32A32_SNORM:
306	case PIPE_FORMAT_R32G32B32A32_UNORM:
307	case PIPE_FORMAT_R32G32B32A32_SINT:
308	case PIPE_FORMAT_R32G32B32A32_UINT:
309		return V_0280A0_SWAP_STD;
310	default:
311		R600_ERR("unsupported colorswap format %d\n", format);
312		return ~0U;
313	}
314	return ~0U;
315}
316
317static uint32_t r600_translate_colorformat(enum pipe_format format)
318{
319	switch (format) {
320	case PIPE_FORMAT_L4A4_UNORM:
321	case PIPE_FORMAT_R4A4_UNORM:
322	case PIPE_FORMAT_A4R4_UNORM:
323		return V_0280A0_COLOR_4_4;
324
325	/* 8-bit buffers. */
326	case PIPE_FORMAT_A8_UNORM:
327	case PIPE_FORMAT_A8_SNORM:
328	case PIPE_FORMAT_A8_UINT:
329	case PIPE_FORMAT_A8_SINT:
330	case PIPE_FORMAT_I8_UNORM:
331	case PIPE_FORMAT_I8_SNORM:
332	case PIPE_FORMAT_I8_UINT:
333	case PIPE_FORMAT_I8_SINT:
334	case PIPE_FORMAT_L8_UNORM:
335	case PIPE_FORMAT_L8_SNORM:
336	case PIPE_FORMAT_L8_UINT:
337	case PIPE_FORMAT_L8_SINT:
338	case PIPE_FORMAT_L8_SRGB:
339	case PIPE_FORMAT_R8_UNORM:
340	case PIPE_FORMAT_R8_SNORM:
341	case PIPE_FORMAT_R8_UINT:
342	case PIPE_FORMAT_R8_SINT:
343		return V_0280A0_COLOR_8;
344
345	/* 16-bit buffers. */
346	case PIPE_FORMAT_B5G6R5_UNORM:
347		return V_0280A0_COLOR_5_6_5;
348
349	case PIPE_FORMAT_B5G5R5A1_UNORM:
350	case PIPE_FORMAT_B5G5R5X1_UNORM:
351		return V_0280A0_COLOR_1_5_5_5;
352
353	case PIPE_FORMAT_B4G4R4A4_UNORM:
354	case PIPE_FORMAT_B4G4R4X4_UNORM:
355		return V_0280A0_COLOR_4_4_4_4;
356
357	case PIPE_FORMAT_Z16_UNORM:
358		return V_0280A0_COLOR_16;
359
360	case PIPE_FORMAT_L8A8_UNORM:
361	case PIPE_FORMAT_L8A8_SNORM:
362	case PIPE_FORMAT_L8A8_UINT:
363	case PIPE_FORMAT_L8A8_SINT:
364	case PIPE_FORMAT_L8A8_SRGB:
365	case PIPE_FORMAT_R8G8_UNORM:
366	case PIPE_FORMAT_R8G8_SNORM:
367	case PIPE_FORMAT_R8G8_UINT:
368	case PIPE_FORMAT_R8G8_SINT:
369		return V_0280A0_COLOR_8_8;
370
371	case PIPE_FORMAT_R16_UNORM:
372	case PIPE_FORMAT_R16_SNORM:
373	case PIPE_FORMAT_R16_UINT:
374	case PIPE_FORMAT_R16_SINT:
375	case PIPE_FORMAT_A16_UNORM:
376	case PIPE_FORMAT_A16_SNORM:
377	case PIPE_FORMAT_A16_UINT:
378	case PIPE_FORMAT_A16_SINT:
379	case PIPE_FORMAT_L16_UNORM:
380	case PIPE_FORMAT_L16_SNORM:
381	case PIPE_FORMAT_L16_UINT:
382	case PIPE_FORMAT_L16_SINT:
383	case PIPE_FORMAT_I16_UNORM:
384	case PIPE_FORMAT_I16_SNORM:
385	case PIPE_FORMAT_I16_UINT:
386	case PIPE_FORMAT_I16_SINT:
387		return V_0280A0_COLOR_16;
388
389	case PIPE_FORMAT_R16_FLOAT:
390	case PIPE_FORMAT_A16_FLOAT:
391	case PIPE_FORMAT_L16_FLOAT:
392	case PIPE_FORMAT_I16_FLOAT:
393		return V_0280A0_COLOR_16_FLOAT;
394
395	/* 32-bit buffers. */
396	case PIPE_FORMAT_A8B8G8R8_SRGB:
397	case PIPE_FORMAT_A8B8G8R8_UNORM:
398	case PIPE_FORMAT_A8R8G8B8_UNORM:
399	case PIPE_FORMAT_B8G8R8A8_SRGB:
400	case PIPE_FORMAT_B8G8R8A8_UNORM:
401	case PIPE_FORMAT_B8G8R8X8_UNORM:
402	case PIPE_FORMAT_R8G8B8A8_SNORM:
403	case PIPE_FORMAT_R8G8B8A8_UNORM:
404	case PIPE_FORMAT_R8G8B8X8_UNORM:
405	case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
406	case PIPE_FORMAT_X8B8G8R8_UNORM:
407	case PIPE_FORMAT_X8R8G8B8_UNORM:
408	case PIPE_FORMAT_R8G8B8A8_SINT:
409	case PIPE_FORMAT_R8G8B8A8_UINT:
410		return V_0280A0_COLOR_8_8_8_8;
411
412	case PIPE_FORMAT_R10G10B10A2_UNORM:
413	case PIPE_FORMAT_R10G10B10X2_SNORM:
414	case PIPE_FORMAT_B10G10R10A2_UNORM:
415	case PIPE_FORMAT_B10G10R10A2_UINT:
416	case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
417		return V_0280A0_COLOR_2_10_10_10;
418
419	case PIPE_FORMAT_Z24X8_UNORM:
420	case PIPE_FORMAT_Z24_UNORM_S8_UINT:
421		return V_0280A0_COLOR_8_24;
422
423	case PIPE_FORMAT_X8Z24_UNORM:
424	case PIPE_FORMAT_S8_UINT_Z24_UNORM:
425		return V_0280A0_COLOR_24_8;
426
427	case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
428		return V_0280A0_COLOR_X24_8_32_FLOAT;
429
430	case PIPE_FORMAT_R32_UINT:
431	case PIPE_FORMAT_R32_SINT:
432	case PIPE_FORMAT_A32_UINT:
433	case PIPE_FORMAT_A32_SINT:
434	case PIPE_FORMAT_L32_UINT:
435	case PIPE_FORMAT_L32_SINT:
436	case PIPE_FORMAT_I32_UINT:
437	case PIPE_FORMAT_I32_SINT:
438		return V_0280A0_COLOR_32;
439
440	case PIPE_FORMAT_R32_FLOAT:
441	case PIPE_FORMAT_A32_FLOAT:
442	case PIPE_FORMAT_L32_FLOAT:
443	case PIPE_FORMAT_I32_FLOAT:
444	case PIPE_FORMAT_Z32_FLOAT:
445		return V_0280A0_COLOR_32_FLOAT;
446
447	case PIPE_FORMAT_R16G16_FLOAT:
448	case PIPE_FORMAT_L16A16_FLOAT:
449		return V_0280A0_COLOR_16_16_FLOAT;
450
451	case PIPE_FORMAT_R16G16_UNORM:
452	case PIPE_FORMAT_R16G16_SNORM:
453	case PIPE_FORMAT_R16G16_UINT:
454	case PIPE_FORMAT_R16G16_SINT:
455	case PIPE_FORMAT_L16A16_UNORM:
456	case PIPE_FORMAT_L16A16_SNORM:
457	case PIPE_FORMAT_L16A16_UINT:
458	case PIPE_FORMAT_L16A16_SINT:
459		return V_0280A0_COLOR_16_16;
460
461	case PIPE_FORMAT_R11G11B10_FLOAT:
462		return V_0280A0_COLOR_10_11_11_FLOAT;
463
464	/* 64-bit buffers. */
465	case PIPE_FORMAT_R16G16B16A16_UINT:
466	case PIPE_FORMAT_R16G16B16A16_SINT:
467	case PIPE_FORMAT_R16G16B16A16_UNORM:
468	case PIPE_FORMAT_R16G16B16A16_SNORM:
469		return V_0280A0_COLOR_16_16_16_16;
470
471	case PIPE_FORMAT_R16G16B16A16_FLOAT:
472		return V_0280A0_COLOR_16_16_16_16_FLOAT;
473
474	case PIPE_FORMAT_R32G32_FLOAT:
475	case PIPE_FORMAT_L32A32_FLOAT:
476		return V_0280A0_COLOR_32_32_FLOAT;
477
478	case PIPE_FORMAT_R32G32_SINT:
479	case PIPE_FORMAT_R32G32_UINT:
480	case PIPE_FORMAT_L32A32_UINT:
481	case PIPE_FORMAT_L32A32_SINT:
482		return V_0280A0_COLOR_32_32;
483
484	/* 128-bit buffers. */
485	case PIPE_FORMAT_R32G32B32A32_FLOAT:
486		return V_0280A0_COLOR_32_32_32_32_FLOAT;
487	case PIPE_FORMAT_R32G32B32A32_SNORM:
488	case PIPE_FORMAT_R32G32B32A32_UNORM:
489	case PIPE_FORMAT_R32G32B32A32_SINT:
490	case PIPE_FORMAT_R32G32B32A32_UINT:
491		return V_0280A0_COLOR_32_32_32_32;
492
493	/* YUV buffers. */
494	case PIPE_FORMAT_UYVY:
495	case PIPE_FORMAT_YUYV:
496	default:
497		return ~0U; /* Unsupported. */
498	}
499}
500
501static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
502{
503	if (R600_BIG_ENDIAN) {
504		switch(colorformat) {
505		case V_0280A0_COLOR_4_4:
506			return ENDIAN_NONE;
507
508		/* 8-bit buffers. */
509		case V_0280A0_COLOR_8:
510			return ENDIAN_NONE;
511
512		/* 16-bit buffers. */
513		case V_0280A0_COLOR_5_6_5:
514		case V_0280A0_COLOR_1_5_5_5:
515		case V_0280A0_COLOR_4_4_4_4:
516		case V_0280A0_COLOR_16:
517		case V_0280A0_COLOR_8_8:
518			return ENDIAN_8IN16;
519
520		/* 32-bit buffers. */
521		case V_0280A0_COLOR_8_8_8_8:
522		case V_0280A0_COLOR_2_10_10_10:
523		case V_0280A0_COLOR_8_24:
524		case V_0280A0_COLOR_24_8:
525		case V_0280A0_COLOR_32_FLOAT:
526		case V_0280A0_COLOR_16_16_FLOAT:
527		case V_0280A0_COLOR_16_16:
528			return ENDIAN_8IN32;
529
530		/* 64-bit buffers. */
531		case V_0280A0_COLOR_16_16_16_16:
532		case V_0280A0_COLOR_16_16_16_16_FLOAT:
533			return ENDIAN_8IN16;
534
535		case V_0280A0_COLOR_32_32_FLOAT:
536		case V_0280A0_COLOR_32_32:
537		case V_0280A0_COLOR_X24_8_32_FLOAT:
538			return ENDIAN_8IN32;
539
540		/* 128-bit buffers. */
541		case V_0280A0_COLOR_32_32_32_FLOAT:
542		case V_0280A0_COLOR_32_32_32_32_FLOAT:
543		case V_0280A0_COLOR_32_32_32_32:
544			return ENDIAN_8IN32;
545		default:
546			return ENDIAN_NONE; /* Unsupported. */
547		}
548	} else {
549		return ENDIAN_NONE;
550	}
551}
552
553static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
554{
555	return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
556}
557
558static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
559{
560	return r600_translate_colorformat(format) != ~0U &&
561	       r600_translate_colorswap(format) != ~0U;
562}
563
564static bool r600_is_zs_format_supported(enum pipe_format format)
565{
566	return r600_translate_dbformat(format) != ~0U;
567}
568
569boolean r600_is_format_supported(struct pipe_screen *screen,
570				 enum pipe_format format,
571				 enum pipe_texture_target target,
572				 unsigned sample_count,
573				 unsigned usage)
574{
575	struct r600_screen *rscreen = (struct r600_screen*)screen;
576	unsigned retval = 0;
577
578	if (target >= PIPE_MAX_TEXTURE_TYPES) {
579		R600_ERR("r600: unsupported texture type %d\n", target);
580		return FALSE;
581	}
582
583	if (!util_format_is_supported(format, usage))
584		return FALSE;
585
586	if (sample_count > 1) {
587		if (rscreen->info.drm_minor < 22)
588			return FALSE;
589
590		/* R11G11B10 is broken on R6xx. */
591		if (rscreen->chip_class == R600 &&
592		    format == PIPE_FORMAT_R11G11B10_FLOAT)
593			return FALSE;
594
595		switch (sample_count) {
596		case 2:
597		case 4:
598		case 8:
599			break;
600		default:
601			return FALSE;
602		}
603
604		/* require render-target support for multisample resources */
605		if (util_format_is_depth_or_stencil(format)) {
606			usage |= PIPE_BIND_DEPTH_STENCIL;
607		} else if (util_format_is_pure_integer(format)) {
608			return FALSE; /* no integer textures */
609		} else {
610			usage |= PIPE_BIND_RENDER_TARGET;
611		}
612	}
613
614	if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
615	    r600_is_sampler_format_supported(screen, format)) {
616		retval |= PIPE_BIND_SAMPLER_VIEW;
617	}
618
619	if ((usage & (PIPE_BIND_RENDER_TARGET |
620		      PIPE_BIND_DISPLAY_TARGET |
621		      PIPE_BIND_SCANOUT |
622		      PIPE_BIND_SHARED)) &&
623	    r600_is_colorbuffer_format_supported(format)) {
624		retval |= usage &
625			  (PIPE_BIND_RENDER_TARGET |
626			   PIPE_BIND_DISPLAY_TARGET |
627			   PIPE_BIND_SCANOUT |
628			   PIPE_BIND_SHARED);
629	}
630
631	if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
632	    r600_is_zs_format_supported(format)) {
633		retval |= PIPE_BIND_DEPTH_STENCIL;
634	}
635
636	if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
637	    r600_is_vertex_format_supported(format)) {
638		retval |= PIPE_BIND_VERTEX_BUFFER;
639	}
640
641	if (usage & PIPE_BIND_TRANSFER_READ)
642		retval |= PIPE_BIND_TRANSFER_READ;
643	if (usage & PIPE_BIND_TRANSFER_WRITE)
644		retval |= PIPE_BIND_TRANSFER_WRITE;
645
646	return retval == usage;
647}
648
649void r600_polygon_offset_update(struct r600_context *rctx)
650{
651	struct r600_pipe_state state;
652
653	state.id = R600_PIPE_STATE_POLYGON_OFFSET;
654	state.nregs = 0;
655	if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
656		float offset_units = rctx->rasterizer->offset_units;
657		unsigned offset_db_fmt_cntl = 0, depth;
658
659		switch (rctx->framebuffer.zsbuf->format) {
660		case PIPE_FORMAT_Z24X8_UNORM:
661		case PIPE_FORMAT_Z24_UNORM_S8_UINT:
662			depth = -24;
663			offset_units *= 2.0f;
664			break;
665		case PIPE_FORMAT_Z32_FLOAT:
666		case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
667			depth = -23;
668			offset_units *= 1.0f;
669			offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
670			break;
671		case PIPE_FORMAT_Z16_UNORM:
672			depth = -16;
673			offset_units *= 4.0f;
674			break;
675		default:
676			return;
677		}
678		/* XXX some of those reg can be computed with cso */
679		offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
680		r600_pipe_state_add_reg(&state,
681				R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
682				fui(rctx->rasterizer->offset_scale));
683		r600_pipe_state_add_reg(&state,
684				R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
685				fui(offset_units));
686		r600_pipe_state_add_reg(&state,
687				R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
688				fui(rctx->rasterizer->offset_scale));
689		r600_pipe_state_add_reg(&state,
690				R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
691				fui(offset_units));
692		r600_pipe_state_add_reg(&state,
693				R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
694				offset_db_fmt_cntl);
695		r600_context_pipe_state_set(rctx, &state);
696	}
697}
698
699static void *r600_create_blend_state_mode(struct pipe_context *ctx,
700					  const struct pipe_blend_state *state,
701					  int mode)
702{
703	struct r600_context *rctx = (struct r600_context *)ctx;
704	struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
705	struct r600_pipe_state *rstate;
706	uint32_t color_control = 0, target_mask = 0;
707
708	if (blend == NULL) {
709		return NULL;
710	}
711	rstate = &blend->rstate;
712
713	rstate->id = R600_PIPE_STATE_BLEND;
714
715	/* R600 does not support per-MRT blends */
716	if (rctx->family > CHIP_R600)
717		color_control |= S_028808_PER_MRT_BLEND(1);
718
719	if (state->logicop_enable) {
720		color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
721	} else {
722		color_control |= (0xcc << 16);
723	}
724	/* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
725	if (state->independent_blend_enable) {
726		for (int i = 0; i < 8; i++) {
727			if (state->rt[i].blend_enable) {
728				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
729			}
730			target_mask |= (state->rt[i].colormask << (4 * i));
731		}
732	} else {
733		for (int i = 0; i < 8; i++) {
734			if (state->rt[0].blend_enable) {
735				color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
736			}
737			target_mask |= (state->rt[0].colormask << (4 * i));
738		}
739	}
740
741	if (target_mask)
742		color_control |= S_028808_SPECIAL_OP(mode);
743	else
744		color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
745
746	blend->cb_target_mask = target_mask;
747	blend->cb_color_control = color_control;
748	/* only MRT0 has dual src blend */
749	blend->dual_src_blend = util_blend_state_is_dual(state, 0);
750	for (int i = 0; i < 8; i++) {
751		/* state->rt entries > 0 only written if independent blending */
752		const int j = state->independent_blend_enable ? i : 0;
753
754		unsigned eqRGB = state->rt[j].rgb_func;
755		unsigned srcRGB = state->rt[j].rgb_src_factor;
756		unsigned dstRGB = state->rt[j].rgb_dst_factor;
757
758		unsigned eqA = state->rt[j].alpha_func;
759		unsigned srcA = state->rt[j].alpha_src_factor;
760		unsigned dstA = state->rt[j].alpha_dst_factor;
761		uint32_t bc = 0;
762
763		if (!state->rt[j].blend_enable)
764			continue;
765
766		bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
767		bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
768		bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
769
770		if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
771			bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
772			bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
773			bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
774			bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
775		}
776
777		/* R600 does not support per-MRT blends */
778		if (rctx->family > CHIP_R600)
779			r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
780		if (i == 0)
781			r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
782	}
783
784	r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
785				S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
786				S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
787				S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
788				S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
789				S_028D44_ALPHA_TO_MASK_OFFSET3(2));
790
791	blend->alpha_to_one = state->alpha_to_one;
792	return rstate;
793}
794
795
796static void *r600_create_blend_state(struct pipe_context *ctx,
797				     const struct pipe_blend_state *state)
798{
799	return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
800}
801
802static void *r600_create_dsa_state(struct pipe_context *ctx,
803				   const struct pipe_depth_stencil_alpha_state *state)
804{
805	struct r600_context *rctx = (struct r600_context *)ctx;
806	struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
807	unsigned db_depth_control, alpha_test_control, alpha_ref;
808	struct r600_pipe_state *rstate;
809
810	if (dsa == NULL) {
811		return NULL;
812	}
813
814	dsa->valuemask[0] = state->stencil[0].valuemask;
815	dsa->valuemask[1] = state->stencil[1].valuemask;
816	dsa->writemask[0] = state->stencil[0].writemask;
817	dsa->writemask[1] = state->stencil[1].writemask;
818
819	rstate = &dsa->rstate;
820
821	rstate->id = R600_PIPE_STATE_DSA;
822	db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
823		S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
824		S_028800_ZFUNC(state->depth.func);
825
826	/* stencil */
827	if (state->stencil[0].enabled) {
828		db_depth_control |= S_028800_STENCIL_ENABLE(1);
829		db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
830		db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
831		db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
832		db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
833
834		if (state->stencil[1].enabled) {
835			db_depth_control |= S_028800_BACKFACE_ENABLE(1);
836			db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
837			db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
838			db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
839			db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
840		}
841	}
842
843	/* alpha */
844	alpha_test_control = 0;
845	alpha_ref = 0;
846	if (state->alpha.enabled) {
847		alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
848		alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
849		alpha_ref = fui(state->alpha.ref_value);
850	}
851	dsa->sx_alpha_test_control = alpha_test_control & 0xff;
852	dsa->alpha_ref = alpha_ref;
853
854	r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
855	return rstate;
856}
857
858static void *r600_create_rs_state(struct pipe_context *ctx,
859				  const struct pipe_rasterizer_state *state)
860{
861	struct r600_context *rctx = (struct r600_context *)ctx;
862	struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
863	struct r600_pipe_state *rstate;
864	unsigned tmp;
865	unsigned prov_vtx = 1, polygon_dual_mode;
866	unsigned sc_mode_cntl;
867	float psize_min, psize_max;
868
869	if (rs == NULL) {
870		return NULL;
871	}
872
873	polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
874				state->fill_back != PIPE_POLYGON_MODE_FILL);
875
876	if (state->flatshade_first)
877		prov_vtx = 0;
878
879	rstate = &rs->rstate;
880	rs->flatshade = state->flatshade;
881	rs->sprite_coord_enable = state->sprite_coord_enable;
882	rs->two_side = state->light_twoside;
883	rs->clip_plane_enable = state->clip_plane_enable;
884	rs->pa_sc_line_stipple = state->line_stipple_enable ?
885				S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
886				S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
887	rs->pa_cl_clip_cntl =
888		S_028810_PS_UCP_MODE(3) |
889		S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
890		S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
891		S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
892	rs->multisample_enable = state->multisample;
893
894	/* offset */
895	rs->offset_units = state->offset_units;
896	rs->offset_scale = state->offset_scale * 12.0f;
897
898	rstate->id = R600_PIPE_STATE_RASTERIZER;
899	tmp = S_0286D4_FLAT_SHADE_ENA(1);
900	if (state->sprite_coord_enable) {
901		tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
902			S_0286D4_PNT_SPRITE_OVRD_X(2) |
903			S_0286D4_PNT_SPRITE_OVRD_Y(3) |
904			S_0286D4_PNT_SPRITE_OVRD_Z(0) |
905			S_0286D4_PNT_SPRITE_OVRD_W(1);
906		if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
907			tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
908		}
909	}
910	r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
911
912	/* point size 12.4 fixed point */
913	tmp = r600_pack_float_12p4(state->point_size/2);
914	r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
915
916	if (state->point_size_per_vertex) {
917		psize_min = util_get_min_point_size(state);
918		psize_max = 8192;
919	} else {
920		/* Force the point size to be as if the vertex output was disabled. */
921		psize_min = state->point_size;
922		psize_max = state->point_size;
923	}
924	/* Divide by two, because 0.5 = 1 pixel. */
925	r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
926				S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
927				S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
928
929	tmp = r600_pack_float_12p4(state->line_width/2);
930	r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
931
932	if (rctx->chip_class >= R700) {
933		sc_mode_cntl =
934			S_028A4C_MSAA_ENABLE(state->multisample) |
935			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
936			S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
937			S_028A4C_R700_ZMM_LINE_OFFSET(1) |
938			S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
939	} else {
940		sc_mode_cntl =
941			S_028A4C_MSAA_ENABLE(state->multisample) |
942			S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
943			S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
944		rs->scissor_enable = state->scissor;
945	}
946	sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
947
948	r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
949
950	r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
951				S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
952				S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
953
954	r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
955	r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
956				S_028814_PROVOKING_VTX_LAST(prov_vtx) |
957				S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
958				S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
959				S_028814_FACE(!state->front_ccw) |
960				S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
961				S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
962				S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
963				S_028814_POLY_MODE(polygon_dual_mode) |
964				S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
965				S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
966	r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
967	return rstate;
968}
969
970static void *r600_create_sampler_state(struct pipe_context *ctx,
971					const struct pipe_sampler_state *state)
972{
973	struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
974	union util_color uc;
975	unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
976
977	if (ss == NULL) {
978		return NULL;
979	}
980
981	ss->seamless_cube_map = state->seamless_cube_map;
982	ss->border_color_use = false;
983	util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
984	/* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
985	ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
986				S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
987				S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
988				S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
989				S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
990				S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
991				S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
992				S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
993				S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
994	/* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
995	ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
996				S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
997				S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
998	/* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
999	ss->tex_sampler_words[2] = S_03C008_TYPE(1);
1000	if (uc.ui) {
1001		ss->border_color_use = true;
1002		/* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
1003		ss->border_color[0] = fui(state->border_color.f[0]);
1004		/* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
1005		ss->border_color[1] = fui(state->border_color.f[1]);
1006		/* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
1007		ss->border_color[2] = fui(state->border_color.f[2]);
1008		/* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
1009		ss->border_color[3] = fui(state->border_color.f[3]);
1010	}
1011	return ss;
1012}
1013
1014static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1015							struct pipe_resource *texture,
1016							const struct pipe_sampler_view *state)
1017{
1018	struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1019	struct r600_texture *tmp = (struct r600_texture*)texture;
1020	unsigned format, endian;
1021	uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1022	unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1023	unsigned width, height, depth, offset_level, last_level;
1024
1025	if (view == NULL)
1026		return NULL;
1027
1028	/* initialize base object */
1029	view->base = *state;
1030	view->base.texture = NULL;
1031	pipe_reference(NULL, &texture->reference);
1032	view->base.texture = texture;
1033	view->base.reference.count = 1;
1034	view->base.context = ctx;
1035
1036	swizzle[0] = state->swizzle_r;
1037	swizzle[1] = state->swizzle_g;
1038	swizzle[2] = state->swizzle_b;
1039	swizzle[3] = state->swizzle_a;
1040
1041	format = r600_translate_texformat(ctx->screen, state->format,
1042					  swizzle,
1043					  &word4, &yuv_format);
1044	assert(format != ~0);
1045	if (format == ~0) {
1046		FREE(view);
1047		return NULL;
1048	}
1049
1050	if (tmp->is_depth && !tmp->is_flushing_texture) {
1051		if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1052			FREE(view);
1053			return NULL;
1054		}
1055		tmp = tmp->flushed_depth_texture;
1056	}
1057
1058	endian = r600_colorformat_endian_swap(format);
1059
1060	offset_level = state->u.tex.first_level;
1061	last_level = state->u.tex.last_level - offset_level;
1062	width = tmp->surface.level[offset_level].npix_x;
1063	height = tmp->surface.level[offset_level].npix_y;
1064	depth = tmp->surface.level[offset_level].npix_z;
1065	pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1066	tile_type = tmp->tile_type;
1067
1068	if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1069		height = 1;
1070		depth = texture->array_size;
1071	} else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1072		depth = texture->array_size;
1073	}
1074	switch (tmp->surface.level[offset_level].mode) {
1075	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1076		array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1077		break;
1078	case RADEON_SURF_MODE_1D:
1079		array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1080		break;
1081	case RADEON_SURF_MODE_2D:
1082		array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1083		break;
1084	case RADEON_SURF_MODE_LINEAR:
1085	default:
1086		array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1087		break;
1088	}
1089
1090	view->tex_resource = &tmp->resource;
1091	view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1092				       S_038000_TILE_MODE(array_mode) |
1093				       S_038000_TILE_TYPE(tile_type) |
1094				       S_038000_PITCH((pitch / 8) - 1) |
1095				       S_038000_TEX_WIDTH(width - 1));
1096	view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1097				       S_038004_TEX_DEPTH(depth - 1) |
1098				       S_038004_DATA_FORMAT(format));
1099	view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1100	if (offset_level >= tmp->surface.last_level) {
1101		view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1102	} else {
1103		view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1104	}
1105	view->tex_resource_words[4] = (word4 |
1106				       S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1107				       S_038010_REQUEST_SIZE(1) |
1108				       S_038010_ENDIAN_SWAP(endian) |
1109				       S_038010_BASE_LEVEL(0));
1110	view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1111				       S_038014_LAST_ARRAY(state->u.tex.last_layer));
1112	if (texture->nr_samples > 1) {
1113		/* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1114		view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1115	} else {
1116		view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1117	}
1118	view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1119				       S_038018_MAX_ANISO(4 /* max 16 samples */));
1120	return &view->base;
1121}
1122
1123static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1124				      struct pipe_sampler_view **views)
1125{
1126	r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
1127}
1128
1129static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1130				      struct pipe_sampler_view **views)
1131{
1132	r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
1133}
1134
1135static void r600_set_clip_state(struct pipe_context *ctx,
1136				const struct pipe_clip_state *state)
1137{
1138	struct r600_context *rctx = (struct r600_context *)ctx;
1139	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1140	struct pipe_constant_buffer cb;
1141
1142	if (rstate == NULL)
1143		return;
1144
1145	rctx->clip = *state;
1146	rstate->id = R600_PIPE_STATE_CLIP;
1147	for (int i = 0; i < 6; i++) {
1148		r600_pipe_state_add_reg(rstate,
1149					R_028E20_PA_CL_UCP0_X + i * 16,
1150					fui(state->ucp[i][0]));
1151		r600_pipe_state_add_reg(rstate,
1152					R_028E24_PA_CL_UCP0_Y + i * 16,
1153					fui(state->ucp[i][1]) );
1154		r600_pipe_state_add_reg(rstate,
1155					R_028E28_PA_CL_UCP0_Z + i * 16,
1156					fui(state->ucp[i][2]));
1157		r600_pipe_state_add_reg(rstate,
1158					R_028E2C_PA_CL_UCP0_W + i * 16,
1159					fui(state->ucp[i][3]));
1160	}
1161
1162	free(rctx->states[R600_PIPE_STATE_CLIP]);
1163	rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1164	r600_context_pipe_state_set(rctx, rstate);
1165
1166	cb.buffer = NULL;
1167	cb.user_buffer = state->ucp;
1168	cb.buffer_offset = 0;
1169	cb.buffer_size = 4*4*8;
1170	r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1171	pipe_resource_reference(&cb.buffer, NULL);
1172}
1173
1174static void r600_set_polygon_stipple(struct pipe_context *ctx,
1175					 const struct pipe_poly_stipple *state)
1176{
1177}
1178
1179void r600_set_scissor_state(struct r600_context *rctx,
1180			    const struct pipe_scissor_state *state)
1181{
1182	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1183	uint32_t tl, br;
1184
1185	if (rstate == NULL)
1186		return;
1187
1188	rstate->id = R600_PIPE_STATE_SCISSOR;
1189	tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1190	br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1191	r600_pipe_state_add_reg(rstate,
1192				R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1193	r600_pipe_state_add_reg(rstate,
1194				R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1195
1196	free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1197	rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1198	r600_context_pipe_state_set(rctx, rstate);
1199}
1200
1201static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1202					const struct pipe_scissor_state *state)
1203{
1204	struct r600_context *rctx = (struct r600_context *)ctx;
1205
1206	if (rctx->chip_class == R600) {
1207		rctx->scissor_state = *state;
1208
1209		if (!rctx->scissor_enable)
1210			return;
1211	}
1212
1213	r600_set_scissor_state(rctx, state);
1214}
1215
1216static void r600_set_viewport_state(struct pipe_context *ctx,
1217					const struct pipe_viewport_state *state)
1218{
1219	struct r600_context *rctx = (struct r600_context *)ctx;
1220	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1221
1222	if (rstate == NULL)
1223		return;
1224
1225	rctx->viewport = *state;
1226	rstate->id = R600_PIPE_STATE_VIEWPORT;
1227	r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1228	r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1229	r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1230	r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1231	r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1232	r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1233
1234	free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1235	rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1236	r600_context_pipe_state_set(rctx, rstate);
1237}
1238
1239static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1240						       unsigned size, unsigned alignment)
1241{
1242	struct pipe_resource buffer;
1243
1244	memset(&buffer, 0, sizeof buffer);
1245	buffer.target = PIPE_BUFFER;
1246	buffer.format = PIPE_FORMAT_R8_UNORM;
1247	buffer.bind = PIPE_BIND_CUSTOM;
1248	buffer.usage = PIPE_USAGE_STATIC;
1249	buffer.flags = 0;
1250	buffer.width0 = size;
1251	buffer.height0 = 1;
1252	buffer.depth0 = 1;
1253	buffer.array_size = 1;
1254
1255	return (struct r600_resource*)
1256		r600_buffer_create(&rscreen->screen, &buffer, alignment);
1257}
1258
1259static void r600_init_color_surface(struct r600_context *rctx,
1260				    struct r600_surface *surf,
1261				    bool force_cmask_fmask)
1262{
1263	struct r600_screen *rscreen = rctx->screen;
1264	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1265	unsigned level = surf->base.u.tex.level;
1266	unsigned pitch, slice;
1267	unsigned color_info;
1268	unsigned format, swap, ntype, endian;
1269	unsigned offset;
1270	const struct util_format_description *desc;
1271	int i;
1272	bool blend_bypass = 0, blend_clamp = 1;
1273
1274	if (rtex->is_depth && !rtex->is_flushing_texture) {
1275		r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1276		rtex = rtex->flushed_depth_texture;
1277		assert(rtex);
1278	}
1279
1280	offset = rtex->surface.level[level].offset;
1281	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1282		offset += rtex->surface.level[level].slice_size *
1283			  surf->base.u.tex.first_layer;
1284	}
1285	pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1286	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1287	if (slice) {
1288		slice = slice - 1;
1289	}
1290	color_info = 0;
1291	switch (rtex->surface.level[level].mode) {
1292	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1293		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1294		break;
1295	case RADEON_SURF_MODE_1D:
1296		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1297		break;
1298	case RADEON_SURF_MODE_2D:
1299		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1300		break;
1301	case RADEON_SURF_MODE_LINEAR:
1302	default:
1303		color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1304		break;
1305	}
1306
1307	desc = util_format_description(surf->base.format);
1308
1309	for (i = 0; i < 4; i++) {
1310		if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1311			break;
1312		}
1313	}
1314
1315	ntype = V_0280A0_NUMBER_UNORM;
1316	if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1317		ntype = V_0280A0_NUMBER_SRGB;
1318	else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1319		if (desc->channel[i].normalized)
1320			ntype = V_0280A0_NUMBER_SNORM;
1321		else if (desc->channel[i].pure_integer)
1322			ntype = V_0280A0_NUMBER_SINT;
1323	} else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1324		if (desc->channel[i].normalized)
1325			ntype = V_0280A0_NUMBER_UNORM;
1326		else if (desc->channel[i].pure_integer)
1327			ntype = V_0280A0_NUMBER_UINT;
1328	}
1329
1330	format = r600_translate_colorformat(surf->base.format);
1331	assert(format != ~0);
1332
1333	swap = r600_translate_colorswap(surf->base.format);
1334	assert(swap != ~0);
1335
1336	if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1337		endian = ENDIAN_NONE;
1338	} else {
1339		endian = r600_colorformat_endian_swap(format);
1340	}
1341
1342	/* set blend bypass according to docs if SINT/UINT or
1343	   8/24 COLOR variants */
1344	if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1345	    format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1346	    format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1347		blend_clamp = 0;
1348		blend_bypass = 1;
1349	}
1350
1351	surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1352
1353	color_info |= S_0280A0_FORMAT(format) |
1354		S_0280A0_COMP_SWAP(swap) |
1355		S_0280A0_BLEND_BYPASS(blend_bypass) |
1356		S_0280A0_BLEND_CLAMP(blend_clamp) |
1357		S_0280A0_NUMBER_TYPE(ntype) |
1358		S_0280A0_ENDIAN(endian);
1359
1360	/* EXPORT_NORM is an optimzation that can be enabled for better
1361	 * performance in certain cases
1362	 */
1363	if (rctx->chip_class == R600) {
1364		/* EXPORT_NORM can be enabled if:
1365		 * - 11-bit or smaller UNORM/SNORM/SRGB
1366		 * - BLEND_CLAMP is enabled
1367		 * - BLEND_FLOAT32 is disabled
1368		 */
1369		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1370		    (desc->channel[i].size < 12 &&
1371		     desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1372		     ntype != V_0280A0_NUMBER_UINT &&
1373		     ntype != V_0280A0_NUMBER_SINT) &&
1374		    G_0280A0_BLEND_CLAMP(color_info) &&
1375		    !G_0280A0_BLEND_FLOAT32(color_info)) {
1376			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1377			surf->export_16bpc = true;
1378		}
1379	} else {
1380		/* EXPORT_NORM can be enabled if:
1381		 * - 11-bit or smaller UNORM/SNORM/SRGB
1382		 * - 16-bit or smaller FLOAT
1383		 */
1384		if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1385		    ((desc->channel[i].size < 12 &&
1386		      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1387		      ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1388		    (desc->channel[i].size < 17 &&
1389		     desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1390			color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1391			surf->export_16bpc = true;
1392		}
1393	}
1394
1395	/* These might not always be initialized to zero. */
1396	surf->cb_color_base = offset >> 8;
1397	surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1398			      S_028060_SLICE_TILE_MAX(slice);
1399	surf->cb_color_fmask = surf->cb_color_base;
1400	surf->cb_color_cmask = surf->cb_color_base;
1401	surf->cb_color_mask = 0;
1402
1403	pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1404				&rtex->resource.b.b);
1405	pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1406				&rtex->resource.b.b);
1407
1408	if (rtex->cmask_size) {
1409		surf->cb_color_cmask = rtex->cmask_offset >> 8;
1410		surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1411
1412		if (rtex->fmask_size) {
1413			color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1414			surf->cb_color_fmask = rtex->fmask_offset >> 8;
1415			surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1416		} else { /* cmask only */
1417			color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1418		}
1419	} else if (force_cmask_fmask) {
1420		/* Allocate dummy FMASK and CMASK if they aren't allocated already.
1421		 *
1422		 * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1423		 * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1424		 * because it's not an MSAA buffer.
1425		 */
1426		struct r600_cmask_info cmask;
1427		struct r600_fmask_info fmask;
1428
1429		r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1430		r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1431
1432		/* CMASK. */
1433		if (!rctx->dummy_cmask ||
1434		    rctx->dummy_cmask->buf->size < cmask.size ||
1435		    rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1436			struct pipe_transfer *transfer;
1437			void *ptr;
1438
1439			pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1440			rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1441
1442			/* Set the contents to 0xCC. */
1443			ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1444			memset(ptr, 0xCC, cmask.size);
1445			pipe_buffer_unmap(&rctx->context, transfer);
1446		}
1447		pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1448					&rctx->dummy_cmask->b.b);
1449
1450		/* FMASK. */
1451		if (!rctx->dummy_fmask ||
1452		    rctx->dummy_fmask->buf->size < fmask.size ||
1453		    rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1454			pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1455			rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1456
1457		}
1458		pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1459					&rctx->dummy_fmask->b.b);
1460
1461		/* Init the registers. */
1462		color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1463		surf->cb_color_cmask = 0;
1464		surf->cb_color_fmask = 0;
1465		surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1466				      S_028100_FMASK_TILE_MAX(slice);
1467	}
1468
1469	surf->cb_color_info = color_info;
1470
1471	if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1472		surf->cb_color_view = 0;
1473	} else {
1474		surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1475				      S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1476	}
1477
1478	surf->color_initialized = true;
1479}
1480
1481static void r600_init_depth_surface(struct r600_context *rctx,
1482				    struct r600_surface *surf)
1483{
1484	struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1485	unsigned level, pitch, slice, format, offset, array_mode;
1486
1487	level = surf->base.u.tex.level;
1488	offset = rtex->surface.level[level].offset;
1489	pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1490	slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1491	if (slice) {
1492		slice = slice - 1;
1493	}
1494	switch (rtex->surface.level[level].mode) {
1495	case RADEON_SURF_MODE_2D:
1496		array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1497		break;
1498	case RADEON_SURF_MODE_1D:
1499	case RADEON_SURF_MODE_LINEAR_ALIGNED:
1500	case RADEON_SURF_MODE_LINEAR:
1501	default:
1502		array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1503		break;
1504	}
1505
1506	format = r600_translate_dbformat(surf->base.format);
1507	assert(format != ~0);
1508
1509	surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1510	surf->db_depth_base = offset >> 8;
1511	surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1512			      S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1513	surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1514	surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1515
1516	surf->depth_initialized = true;
1517}
1518
1519#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
1520	(((s0x) & 0xf) | (((s0y) & 0xf) << 4) |		   \
1521	(((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |	   \
1522	(((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |	   \
1523	 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1524
1525static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1526{
1527	static uint32_t sample_locs_2x[] = {
1528		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1529		FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1530	};
1531	static unsigned max_dist_2x = 4;
1532	static uint32_t sample_locs_4x[] = {
1533		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1534		FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1535	};
1536	static unsigned max_dist_4x = 6;
1537	static uint32_t sample_locs_8x[] = {
1538		FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1539		FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1540	};
1541	static unsigned max_dist_8x = 8;
1542	struct r600_context *rctx = (struct r600_context *)ctx;
1543
1544	if (rctx->family == CHIP_R600) {
1545		switch (nsample) {
1546		case 0:
1547		case 1:
1548			return 0;
1549		case 2:
1550			r600_pipe_state_add_reg(rstate, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1551			return max_dist_2x;
1552		case 4:
1553			r600_pipe_state_add_reg(rstate, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1554			return max_dist_4x;
1555		case 8:
1556			r600_pipe_state_add_reg(rstate, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, sample_locs_8x[0]);
1557			r600_pipe_state_add_reg(rstate, R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, sample_locs_8x[1]);
1558			return max_dist_8x;
1559		}
1560	} else {
1561		switch (nsample) {
1562		case 0:
1563		case 1:
1564			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0);
1565			r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, 0);
1566			return 0;
1567		case 2:
1568			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_2x[0]);
1569			r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_2x[1]);
1570			return max_dist_2x;
1571		case 4:
1572			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_4x[0]);
1573			r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_4x[1]);
1574			return max_dist_4x;
1575		case 8:
1576			r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_8x[0]);
1577			r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_8x[1]);
1578			return max_dist_8x;
1579		}
1580	}
1581	R600_ERR("Invalid nr_samples %i\n", nsample);
1582	return 0;
1583}
1584
1585static void r600_set_framebuffer_state(struct pipe_context *ctx,
1586					const struct pipe_framebuffer_state *state)
1587{
1588	struct r600_context *rctx = (struct r600_context *)ctx;
1589	struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1590	struct r600_surface *surf;
1591	struct r600_resource *res;
1592	struct r600_texture *rtex;
1593	uint32_t tl, br, i, nr_samples, max_dist;
1594	bool is_resolve = state->nr_cbufs == 2 &&
1595			  state->cbufs[0]->texture->nr_samples > 1 &&
1596		          state->cbufs[1]->texture->nr_samples <= 1;
1597	/* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1598	bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve;
1599
1600	if (rstate == NULL)
1601		return;
1602
1603	r600_flush_framebuffer(rctx, false);
1604
1605	/* unreference old buffer and reference new one */
1606	rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1607
1608	util_copy_framebuffer_state(&rctx->framebuffer, state);
1609
1610	/* Colorbuffers. */
1611	rctx->export_16bpc = true;
1612	rctx->nr_cbufs = state->nr_cbufs;
1613	rctx->cb0_is_integer = state->nr_cbufs &&
1614			       util_format_is_pure_integer(state->cbufs[0]->format);
1615	rctx->compressed_cb_mask = 0;
1616
1617	for (i = 0; i < state->nr_cbufs; i++) {
1618		bool force_cmask_fmask = cb1_force_cmask_fmask && i == 1;
1619		surf = (struct r600_surface*)state->cbufs[i];
1620		res = (struct r600_resource*)surf->base.texture;
1621		rtex = (struct r600_texture*)res;
1622
1623		if (!surf->color_initialized || force_cmask_fmask) {
1624			r600_init_color_surface(rctx, surf, force_cmask_fmask);
1625			if (force_cmask_fmask) {
1626				/* re-initialize later without compression */
1627				surf->color_initialized = false;
1628			}
1629		}
1630
1631		if (!surf->export_16bpc) {
1632			rctx->export_16bpc = false;
1633		}
1634
1635		r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
1636					   surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1637		r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
1638					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1639		r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
1640					surf->cb_color_size);
1641		r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
1642					surf->cb_color_view);
1643		r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
1644					   surf->cb_color_fmask, surf->cb_buffer_fmask,
1645					   RADEON_USAGE_READWRITE);
1646		r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
1647					   surf->cb_color_cmask, surf->cb_buffer_cmask,
1648					   RADEON_USAGE_READWRITE);
1649		r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4,
1650					surf->cb_color_mask);
1651
1652		if (rtex->fmask_size && rtex->cmask_size) {
1653			rctx->compressed_cb_mask |= 1 << i;
1654		}
1655	}
1656	/* set CB_COLOR1_INFO for possible dual-src blending */
1657	if (i == 1) {
1658		r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
1659					   surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1660		i++;
1661	}
1662	for (; i < 8 ; i++) {
1663		r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0);
1664	}
1665
1666	/* Update alpha-test state dependencies.
1667	 * Alpha-test is done on the first colorbuffer only. */
1668	if (state->nr_cbufs) {
1669		surf = (struct r600_surface*)state->cbufs[0];
1670		if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1671			rctx->alphatest_state.bypass = surf->alphatest_bypass;
1672			r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1673		}
1674	}
1675
1676	/* ZS buffer. */
1677	if (state->zsbuf) {
1678		surf = (struct r600_surface*)state->zsbuf;
1679		res = (struct r600_resource*)surf->base.texture;
1680
1681		if (!surf->depth_initialized) {
1682			r600_init_depth_surface(rctx, surf);
1683		}
1684
1685		r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
1686					   res, RADEON_USAGE_READWRITE);
1687		r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
1688		r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
1689		r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
1690					   res, RADEON_USAGE_READWRITE);
1691		r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1692	}
1693
1694	/* Framebuffer dimensions. */
1695	tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1696	br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1697
1698	r600_pipe_state_add_reg(rstate,
1699				R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1700	r600_pipe_state_add_reg(rstate,
1701				R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1702
1703	/* If we're doing MSAA resolve... */
1704	if (is_resolve) {
1705		r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1);
1706	} else {
1707		/* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1708		 * will assure that the alpha-test will work even if there is
1709		 * no colorbuffer bound. */
1710		r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1711					(1ull << MAX2(state->nr_cbufs, 1)) - 1);
1712	}
1713
1714	/* Multisampling */
1715	if (state->nr_cbufs)
1716		nr_samples = state->cbufs[0]->texture->nr_samples;
1717	else if (state->zsbuf)
1718		nr_samples = state->zsbuf->texture->nr_samples;
1719	else
1720		nr_samples = 0;
1721
1722	max_dist = r600_set_ms_pos(ctx, rstate, nr_samples);
1723
1724	if (nr_samples > 1) {
1725		unsigned log_samples = util_logbase2(nr_samples);
1726
1727		r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL,
1728					S_028C00_LAST_PIXEL(1) |
1729					S_028C00_EXPAND_LINE_WIDTH(1));
1730		r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1731					S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1732					S_028C04_MAX_SAMPLE_DIST(max_dist));
1733	} else {
1734		r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1735		r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1736	}
1737
1738	free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1739	rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1740	r600_context_pipe_state_set(rctx, rstate);
1741
1742	if (state->zsbuf) {
1743		r600_polygon_offset_update(rctx);
1744	}
1745
1746	if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1747		rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1748		r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1749	}
1750
1751	if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1752		rctx->alphatest_state.bypass = false;
1753		r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1754	}
1755}
1756
1757static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1758{
1759	struct radeon_winsys_cs *cs = rctx->cs;
1760	struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1761
1762	if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1763		r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1764		if (rctx->chip_class == R600) {
1765			r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1766			r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1767		} else {
1768			r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1769			r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1770		}
1771		r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1772	} else {
1773		unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1774		unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1775		unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1776
1777		r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1778		r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1779		/* Always enable the first color output to make sure alpha-test works even without one. */
1780		r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1781		r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1782				       a->cb_color_control |
1783				       S_028808_MULTIWRITE_ENABLE(multiwrite));
1784	}
1785}
1786
1787static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1788{
1789	struct radeon_winsys_cs *cs = rctx->cs;
1790	struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1791	unsigned db_render_control = 0;
1792	unsigned db_render_override =
1793		S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1794		S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1795		S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1796
1797	if (a->occlusion_query_enabled) {
1798		if (rctx->chip_class >= R700) {
1799			db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1800		}
1801		db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1802	}
1803	if (a->flush_depthstencil_through_cb) {
1804		assert(a->copy_depth || a->copy_stencil);
1805
1806		db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1807				     S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1808				     S_028D0C_COPY_CENTROID(1) |
1809				     S_028D0C_COPY_SAMPLE(a->copy_sample);
1810	}
1811
1812	r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1813	r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1814	r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1815}
1816
1817static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1818{
1819	struct radeon_winsys_cs *cs = rctx->cs;
1820	uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1821
1822	while (dirty_mask) {
1823		struct pipe_vertex_buffer *vb;
1824		struct r600_resource *rbuffer;
1825		unsigned offset;
1826		unsigned buffer_index = u_bit_scan(&dirty_mask);
1827
1828		vb = &rctx->vertex_buffer_state.vb[buffer_index];
1829		rbuffer = (struct r600_resource*)vb->buffer;
1830		assert(rbuffer);
1831
1832		offset = vb->buffer_offset;
1833
1834		/* fetch resources start at index 320 */
1835		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1836		r600_write_value(cs, (320 + buffer_index) * 7);
1837		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1838		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1839		r600_write_value(cs, /* RESOURCEi_WORD2 */
1840				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1841				 S_038008_STRIDE(vb->stride));
1842		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1843		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1844		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1845		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1846
1847		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1848		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1849	}
1850}
1851
1852static void r600_emit_constant_buffers(struct r600_context *rctx,
1853				       struct r600_constbuf_state *state,
1854				       unsigned buffer_id_base,
1855				       unsigned reg_alu_constbuf_size,
1856				       unsigned reg_alu_const_cache)
1857{
1858	struct radeon_winsys_cs *cs = rctx->cs;
1859	uint32_t dirty_mask = state->dirty_mask;
1860
1861	while (dirty_mask) {
1862		struct pipe_constant_buffer *cb;
1863		struct r600_resource *rbuffer;
1864		unsigned offset;
1865		unsigned buffer_index = ffs(dirty_mask) - 1;
1866
1867		cb = &state->cb[buffer_index];
1868		rbuffer = (struct r600_resource*)cb->buffer;
1869		assert(rbuffer);
1870
1871		offset = cb->buffer_offset;
1872
1873		r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1874				       ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1875		r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1876
1877		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1878		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1879
1880		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1881		r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1882		r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1883		r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1884		r600_write_value(cs, /* RESOURCEi_WORD2 */
1885				 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1886				 S_038008_STRIDE(16));
1887		r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1888		r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1889		r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1890		r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1891
1892		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1893		r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1894
1895		dirty_mask &= ~(1 << buffer_index);
1896	}
1897	state->dirty_mask = 0;
1898}
1899
1900static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1901{
1902	r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1903				   R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1904				   R_028980_ALU_CONST_CACHE_VS_0);
1905}
1906
1907static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1908{
1909	r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1910				   R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1911				   R_028940_ALU_CONST_CACHE_PS_0);
1912}
1913
1914static void r600_emit_sampler_views(struct r600_context *rctx,
1915				    struct r600_samplerview_state *state,
1916				    unsigned resource_id_base)
1917{
1918	struct radeon_winsys_cs *cs = rctx->cs;
1919	uint32_t dirty_mask = state->dirty_mask;
1920
1921	while (dirty_mask) {
1922		struct r600_pipe_sampler_view *rview;
1923		unsigned resource_index = u_bit_scan(&dirty_mask);
1924		unsigned reloc;
1925
1926		rview = state->views[resource_index];
1927		assert(rview);
1928
1929		r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1930		r600_write_value(cs, (resource_id_base + resource_index) * 7);
1931		r600_write_array(cs, 7, rview->tex_resource_words);
1932
1933		/* XXX The kernel needs two relocations. This is stupid. */
1934		reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1935					      RADEON_USAGE_READ);
1936		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1937		r600_write_value(cs, reloc);
1938		r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1939		r600_write_value(cs, reloc);
1940	}
1941	state->dirty_mask = 0;
1942}
1943
1944static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1945{
1946	r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS);
1947}
1948
1949static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1950{
1951	r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1952}
1953
1954static void r600_emit_sampler(struct r600_context *rctx,
1955				struct r600_textures_info *texinfo,
1956				unsigned resource_id_base,
1957				unsigned border_color_reg)
1958{
1959	struct radeon_winsys_cs *cs = rctx->cs;
1960	unsigned i;
1961
1962	for (i = 0; i < texinfo->n_samplers; i++) {
1963
1964		if (texinfo->samplers[i] == NULL) {
1965			continue;
1966		}
1967
1968		/* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1969		 * filtering between layers.
1970		 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1971		 */
1972		if (texinfo->views.views[i]) {
1973			if (texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1974			    texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1975				texinfo->samplers[i]->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1976				texinfo->is_array_sampler[i] = true;
1977			} else {
1978				texinfo->samplers[i]->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1979				texinfo->is_array_sampler[i] = false;
1980			}
1981		}
1982
1983		r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1984		r600_write_value(cs, (resource_id_base + i) * 3);
1985		r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1986
1987		if (texinfo->samplers[i]->border_color_use) {
1988			unsigned offset;
1989
1990			offset = border_color_reg;
1991			offset += i * 16;
1992			r600_write_config_reg_seq(cs, offset, 4);
1993			r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
1994		}
1995	}
1996}
1997
1998static void r600_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
1999{
2000	r600_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2001}
2002
2003static void r600_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
2004{
2005	r600_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2006}
2007
2008static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2009{
2010	struct radeon_winsys_cs *cs = rctx->cs;
2011	unsigned tmp;
2012
2013	tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2014		S_009508_SYNC_GRADIENT(1) |
2015		S_009508_SYNC_WALKER(1) |
2016		S_009508_SYNC_ALIGNER(1);
2017	if (!rctx->seamless_cube_map.enabled) {
2018		tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2019	}
2020	r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2021}
2022
2023static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2024{
2025	struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2026	uint8_t mask = s->sample_mask;
2027
2028	r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2029			       mask | (mask << 8) | (mask << 16) | (mask << 24));
2030}
2031
2032void r600_init_state_functions(struct r600_context *rctx)
2033{
2034	r600_init_atom(&rctx->seamless_cube_map.atom, r600_emit_seamless_cube_map, 3, 0);
2035	r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
2036	r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
2037	r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2038	r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
2039	r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
2040	r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0);
2041	r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0);
2042	r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0);
2043	r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0);
2044	r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0);
2045	/* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2046	 * does not take effect
2047	 */
2048	r600_init_atom(&rctx->vs_samplers.atom_sampler, r600_emit_vs_sampler, 0, EMIT_EARLY);
2049	r600_init_atom(&rctx->ps_samplers.atom_sampler, r600_emit_ps_sampler, 0, EMIT_EARLY);
2050
2051	r600_init_atom(&rctx->sample_mask.atom, r600_emit_sample_mask, 3, 0);
2052	rctx->sample_mask.sample_mask = ~0;
2053	r600_atom_dirty(rctx, &rctx->sample_mask.atom);
2054
2055	rctx->context.create_blend_state = r600_create_blend_state;
2056	rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2057	rctx->context.create_fs_state = r600_create_shader_state_ps;
2058	rctx->context.create_rasterizer_state = r600_create_rs_state;
2059	rctx->context.create_sampler_state = r600_create_sampler_state;
2060	rctx->context.create_sampler_view = r600_create_sampler_view;
2061	rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
2062	rctx->context.create_vs_state = r600_create_shader_state_vs;
2063	rctx->context.bind_blend_state = r600_bind_blend_state;
2064	rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2065	rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
2066	rctx->context.bind_fs_state = r600_bind_ps_shader;
2067	rctx->context.bind_rasterizer_state = r600_bind_rs_state;
2068	rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
2069	rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
2070	rctx->context.bind_vs_state = r600_bind_vs_shader;
2071	rctx->context.delete_blend_state = r600_delete_state;
2072	rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
2073	rctx->context.delete_fs_state = r600_delete_ps_shader;
2074	rctx->context.delete_rasterizer_state = r600_delete_rs_state;
2075	rctx->context.delete_sampler_state = r600_delete_sampler;
2076	rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
2077	rctx->context.delete_vs_state = r600_delete_vs_shader;
2078	rctx->context.set_blend_color = r600_set_blend_color;
2079	rctx->context.set_clip_state = r600_set_clip_state;
2080	rctx->context.set_constant_buffer = r600_set_constant_buffer;
2081	rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
2082	rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2083	rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2084	rctx->context.set_sample_mask = r600_set_sample_mask;
2085	rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
2086	rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
2087	rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
2088	rctx->context.set_index_buffer = r600_set_index_buffer;
2089	rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
2090	rctx->context.set_viewport_state = r600_set_viewport_state;
2091	rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
2092	rctx->context.texture_barrier = r600_texture_barrier;
2093	rctx->context.create_stream_output_target = r600_create_so_target;
2094	rctx->context.stream_output_target_destroy = r600_so_target_destroy;
2095	rctx->context.set_stream_output_targets = r600_set_so_targets;
2096}
2097
2098/* Adjust GPR allocation on R6xx/R7xx */
2099void r600_adjust_gprs(struct r600_context *rctx)
2100{
2101	struct r600_pipe_state rstate;
2102	unsigned num_ps_gprs = rctx->default_ps_gprs;
2103	unsigned num_vs_gprs = rctx->default_vs_gprs;
2104	unsigned tmp;
2105	int diff;
2106
2107	/* XXX: Following call moved from r600_bind_[ps|vs]_shader,
2108	 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
2109	 * adjusting the GPR allocation?
2110	 * Do we need this if we aren't really changing config below? */
2111	r600_inval_shader_cache(rctx);
2112
2113	if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
2114	{
2115		diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2116		num_vs_gprs -= diff;
2117		num_ps_gprs += diff;
2118	}
2119
2120	if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2121	{
2122		diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2123		num_ps_gprs -= diff;
2124		num_vs_gprs += diff;
2125	}
2126
2127	tmp = 0;
2128	tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2129	tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2130	tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2131	rstate.nregs = 0;
2132	r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2133
2134	r600_context_pipe_state_set(rctx, &rstate);
2135}
2136
2137void r600_init_atom_start_cs(struct r600_context *rctx)
2138{
2139	int ps_prio;
2140	int vs_prio;
2141	int gs_prio;
2142	int es_prio;
2143	int num_ps_gprs;
2144	int num_vs_gprs;
2145	int num_gs_gprs;
2146	int num_es_gprs;
2147	int num_temp_gprs;
2148	int num_ps_threads;
2149	int num_vs_threads;
2150	int num_gs_threads;
2151	int num_es_threads;
2152	int num_ps_stack_entries;
2153	int num_vs_stack_entries;
2154	int num_gs_stack_entries;
2155	int num_es_stack_entries;
2156	enum radeon_family family;
2157	struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2158	uint32_t tmp;
2159
2160	r600_init_command_buffer(cb, 256, EMIT_EARLY);
2161
2162	/* R6xx requires this packet at the start of each command buffer */
2163	if (rctx->chip_class == R600) {
2164		r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2165		r600_store_value(cb, 0);
2166	}
2167	/* All asics require this one */
2168	r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2169	r600_store_value(cb, 0x80000000);
2170	r600_store_value(cb, 0x80000000);
2171
2172	family = rctx->family;
2173	ps_prio = 0;
2174	vs_prio = 1;
2175	gs_prio = 2;
2176	es_prio = 3;
2177	switch (family) {
2178	case CHIP_R600:
2179		num_ps_gprs = 192;
2180		num_vs_gprs = 56;
2181		num_temp_gprs = 4;
2182		num_gs_gprs = 0;
2183		num_es_gprs = 0;
2184		num_ps_threads = 136;
2185		num_vs_threads = 48;
2186		num_gs_threads = 4;
2187		num_es_threads = 4;
2188		num_ps_stack_entries = 128;
2189		num_vs_stack_entries = 128;
2190		num_gs_stack_entries = 0;
2191		num_es_stack_entries = 0;
2192		break;
2193	case CHIP_RV630:
2194	case CHIP_RV635:
2195		num_ps_gprs = 84;
2196		num_vs_gprs = 36;
2197		num_temp_gprs = 4;
2198		num_gs_gprs = 0;
2199		num_es_gprs = 0;
2200		num_ps_threads = 144;
2201		num_vs_threads = 40;
2202		num_gs_threads = 4;
2203		num_es_threads = 4;
2204		num_ps_stack_entries = 40;
2205		num_vs_stack_entries = 40;
2206		num_gs_stack_entries = 32;
2207		num_es_stack_entries = 16;
2208		break;
2209	case CHIP_RV610:
2210	case CHIP_RV620:
2211	case CHIP_RS780:
2212	case CHIP_RS880:
2213	default:
2214		num_ps_gprs = 84;
2215		num_vs_gprs = 36;
2216		num_temp_gprs = 4;
2217		num_gs_gprs = 0;
2218		num_es_gprs = 0;
2219		num_ps_threads = 136;
2220		num_vs_threads = 48;
2221		num_gs_threads = 4;
2222		num_es_threads = 4;
2223		num_ps_stack_entries = 40;
2224		num_vs_stack_entries = 40;
2225		num_gs_stack_entries = 32;
2226		num_es_stack_entries = 16;
2227		break;
2228	case CHIP_RV670:
2229		num_ps_gprs = 144;
2230		num_vs_gprs = 40;
2231		num_temp_gprs = 4;
2232		num_gs_gprs = 0;
2233		num_es_gprs = 0;
2234		num_ps_threads = 136;
2235		num_vs_threads = 48;
2236		num_gs_threads = 4;
2237		num_es_threads = 4;
2238		num_ps_stack_entries = 40;
2239		num_vs_stack_entries = 40;
2240		num_gs_stack_entries = 32;
2241		num_es_stack_entries = 16;
2242		break;
2243	case CHIP_RV770:
2244		num_ps_gprs = 192;
2245		num_vs_gprs = 56;
2246		num_temp_gprs = 4;
2247		num_gs_gprs = 0;
2248		num_es_gprs = 0;
2249		num_ps_threads = 188;
2250		num_vs_threads = 60;
2251		num_gs_threads = 0;
2252		num_es_threads = 0;
2253		num_ps_stack_entries = 256;
2254		num_vs_stack_entries = 256;
2255		num_gs_stack_entries = 0;
2256		num_es_stack_entries = 0;
2257		break;
2258	case CHIP_RV730:
2259	case CHIP_RV740:
2260		num_ps_gprs = 84;
2261		num_vs_gprs = 36;
2262		num_temp_gprs = 4;
2263		num_gs_gprs = 0;
2264		num_es_gprs = 0;
2265		num_ps_threads = 188;
2266		num_vs_threads = 60;
2267		num_gs_threads = 0;
2268		num_es_threads = 0;
2269		num_ps_stack_entries = 128;
2270		num_vs_stack_entries = 128;
2271		num_gs_stack_entries = 0;
2272		num_es_stack_entries = 0;
2273		break;
2274	case CHIP_RV710:
2275		num_ps_gprs = 192;
2276		num_vs_gprs = 56;
2277		num_temp_gprs = 4;
2278		num_gs_gprs = 0;
2279		num_es_gprs = 0;
2280		num_ps_threads = 144;
2281		num_vs_threads = 48;
2282		num_gs_threads = 0;
2283		num_es_threads = 0;
2284		num_ps_stack_entries = 128;
2285		num_vs_stack_entries = 128;
2286		num_gs_stack_entries = 0;
2287		num_es_stack_entries = 0;
2288		break;
2289	}
2290
2291	rctx->default_ps_gprs = num_ps_gprs;
2292	rctx->default_vs_gprs = num_vs_gprs;
2293	rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2294
2295	/* SQ_CONFIG */
2296	tmp = 0;
2297	switch (family) {
2298	case CHIP_RV610:
2299	case CHIP_RV620:
2300	case CHIP_RS780:
2301	case CHIP_RS880:
2302	case CHIP_RV710:
2303		break;
2304	default:
2305		tmp |= S_008C00_VC_ENABLE(1);
2306		break;
2307	}
2308	tmp |= S_008C00_DX9_CONSTS(0);
2309	tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2310	tmp |= S_008C00_PS_PRIO(ps_prio);
2311	tmp |= S_008C00_VS_PRIO(vs_prio);
2312	tmp |= S_008C00_GS_PRIO(gs_prio);
2313	tmp |= S_008C00_ES_PRIO(es_prio);
2314	r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2315
2316	/* SQ_GPR_RESOURCE_MGMT_2 */
2317	tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2318	tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2319	r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2320	r600_store_value(cb, tmp);
2321
2322	/* SQ_THREAD_RESOURCE_MGMT */
2323	tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2324	tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2325	tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2326	tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2327	r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2328
2329	/* SQ_STACK_RESOURCE_MGMT_1 */
2330	tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2331	tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2332	r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2333
2334	/* SQ_STACK_RESOURCE_MGMT_2 */
2335	tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2336	tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2337	r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2338
2339	r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2340
2341	if (rctx->chip_class >= R700) {
2342		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2343		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2344		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2345		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2346	} else {
2347		r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2348		r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2349		r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2350		r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2351	}
2352	r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2353	r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2354	r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2355	r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2356	r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2357	r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2358	r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2359	r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2360	r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2361	r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2362
2363	r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2364	r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2365	r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2366	r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2367	r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2368	r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2369	r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2370	r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2371	r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2372	r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2373	r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2374	r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2375	r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2376	r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2377
2378	r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2379	r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2380	r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2381
2382	r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2383	r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2384	r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2385	r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2386
2387	r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2388
2389	r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2390	r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2391	r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2392
2393	r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2394
2395	r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2396	r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2397	r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2398
2399	r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2400	r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2401	r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2402	r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2403
2404	r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2405	r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2406	r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2407
2408	r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2409	r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2410
2411	r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2412	r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2413	r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2414	r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2415	r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2416
2417	r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2418	r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2419	r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2420
2421	r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2422
2423	r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2424	r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2425
2426	if (rctx->chip_class >= R700) {
2427		r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2428	}
2429
2430	r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2431	r600_store_value(cb, 0x1000000);  /* R_028C30_CB_CLRCMP_CONTROL */
2432	r600_store_value(cb, 0);          /* R_028C34_CB_CLRCMP_SRC */
2433	r600_store_value(cb, 0xFF);       /* R_028C38_CB_CLRCMP_DST */
2434	r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2435
2436	r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2437	r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2438	r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2439
2440	r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2441	r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2442	r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2443
2444	r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2445	r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2446	r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2447
2448	r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2449	r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2450
2451	if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2452		r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2453	r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2454	if (rctx->screen->has_streamout) {
2455		r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2456	}
2457
2458	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2459	r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2460}
2461
2462void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2463{
2464	struct r600_context *rctx = (struct r600_context *)ctx;
2465	struct r600_pipe_state *rstate = &shader->rstate;
2466	struct r600_shader *rshader = &shader->shader;
2467	unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2468	int pos_index = -1, face_index = -1;
2469	unsigned tmp, sid, ufi = 0;
2470	int need_linear = 0;
2471	unsigned z_export = 0, stencil_export = 0;
2472
2473	rstate->nregs = 0;
2474
2475	for (i = 0; i < rshader->ninput; i++) {
2476		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2477			pos_index = i;
2478		if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2479			face_index = i;
2480
2481		sid = rshader->input[i].spi_sid;
2482
2483		tmp = S_028644_SEMANTIC(sid);
2484
2485		if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2486			rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2487			(rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2488				rctx->rasterizer && rctx->rasterizer->flatshade))
2489			tmp |= S_028644_FLAT_SHADE(1);
2490
2491		if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2492				rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2493			tmp |= S_028644_PT_SPRITE_TEX(1);
2494		}
2495
2496		if (rshader->input[i].centroid)
2497			tmp |= S_028644_SEL_CENTROID(1);
2498
2499		if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2500			need_linear = 1;
2501			tmp |= S_028644_SEL_LINEAR(1);
2502		}
2503
2504		r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2505				tmp);
2506	}
2507
2508	db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2509	for (i = 0; i < rshader->noutput; i++) {
2510		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2511			z_export = 1;
2512		if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2513			stencil_export = 1;
2514	}
2515	db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2516	db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2517	if (rshader->uses_kill)
2518		db_shader_control |= S_02880C_KILL_ENABLE(1);
2519
2520	exports_ps = 0;
2521	for (i = 0; i < rshader->noutput; i++) {
2522		if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2523		    rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2524			exports_ps |= 1;
2525		}
2526	}
2527	num_cout = rshader->nr_ps_color_exports;
2528	exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2529	if (!exports_ps) {
2530		/* always at least export 1 component per pixel */
2531		exports_ps = 2;
2532	}
2533
2534	shader->nr_ps_color_outputs = num_cout;
2535
2536	spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2537				S_0286CC_PERSP_GRADIENT_ENA(1)|
2538				S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2539	spi_input_z = 0;
2540	if (pos_index != -1) {
2541		spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2542					S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2543					S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2544					S_0286CC_BARYC_SAMPLE_CNTL(1));
2545		spi_input_z |= 1;
2546	}
2547
2548	spi_ps_in_control_1 = 0;
2549	if (face_index != -1) {
2550		spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2551			S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2552	}
2553
2554	/* HW bug in original R600 */
2555	if (rctx->family == CHIP_R600)
2556		ufi = 1;
2557
2558	r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2559	r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2560	r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2561	r600_pipe_state_add_reg_bo(rstate,
2562				   R_028840_SQ_PGM_START_PS,
2563				   0, shader->bo, RADEON_USAGE_READ);
2564	r600_pipe_state_add_reg(rstate,
2565				R_028850_SQ_PGM_RESOURCES_PS,
2566				S_028850_NUM_GPRS(rshader->bc.ngpr) |
2567				S_028850_STACK_SIZE(rshader->bc.nstack) |
2568				S_028850_UNCACHED_FIRST_INST(ufi));
2569	r600_pipe_state_add_reg(rstate,
2570				R_028854_SQ_PGM_EXPORTS_PS,
2571				exports_ps);
2572	/* only set some bits here, the other bits are set in the dsa state */
2573	shader->db_shader_control = db_shader_control;
2574	shader->ps_depth_export = z_export | stencil_export;
2575
2576	shader->sprite_coord_enable = rctx->sprite_coord_enable;
2577	if (rctx->rasterizer)
2578		shader->flatshade = rctx->rasterizer->flatshade;
2579}
2580
2581void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2582{
2583	struct r600_context *rctx = (struct r600_context *)ctx;
2584	struct r600_pipe_state *rstate = &shader->rstate;
2585	struct r600_shader *rshader = &shader->shader;
2586	unsigned spi_vs_out_id[10] = {};
2587	unsigned i, tmp, nparams = 0;
2588
2589	/* clear previous register */
2590	rstate->nregs = 0;
2591
2592	for (i = 0; i < rshader->noutput; i++) {
2593		if (rshader->output[i].spi_sid) {
2594			tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2595			spi_vs_out_id[nparams / 4] |= tmp;
2596			nparams++;
2597		}
2598	}
2599
2600	for (i = 0; i < 10; i++) {
2601		r600_pipe_state_add_reg(rstate,
2602					R_028614_SPI_VS_OUT_ID_0 + i * 4,
2603					spi_vs_out_id[i]);
2604	}
2605
2606	/* Certain attributes (position, psize, etc.) don't count as params.
2607	 * VS is required to export at least one param and r600_shader_from_tgsi()
2608	 * takes care of adding a dummy export.
2609	 */
2610	if (nparams < 1)
2611		nparams = 1;
2612
2613	r600_pipe_state_add_reg(rstate,
2614				R_0286C4_SPI_VS_OUT_CONFIG,
2615				S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2616	r600_pipe_state_add_reg(rstate,
2617				R_028868_SQ_PGM_RESOURCES_VS,
2618				S_028868_NUM_GPRS(rshader->bc.ngpr) |
2619				S_028868_STACK_SIZE(rshader->bc.nstack));
2620	r600_pipe_state_add_reg_bo(rstate,
2621			R_028858_SQ_PGM_START_VS,
2622			0, shader->bo, RADEON_USAGE_READ);
2623
2624	shader->pa_cl_vs_out_cntl =
2625		S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2626		S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2627		S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2628		S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2629}
2630
2631void r600_fetch_shader(struct pipe_context *ctx,
2632		       struct r600_vertex_element *ve)
2633{
2634	struct r600_pipe_state *rstate;
2635	struct r600_context *rctx = (struct r600_context *)ctx;
2636
2637	rstate = &ve->rstate;
2638	rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2639	rstate->nregs = 0;
2640	r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2641				0,
2642				ve->fetch_shader, RADEON_USAGE_READ);
2643}
2644
2645void *r600_create_resolve_blend(struct r600_context *rctx)
2646{
2647	struct pipe_blend_state blend;
2648	struct r600_pipe_state *rstate;
2649	unsigned i;
2650
2651	memset(&blend, 0, sizeof(blend));
2652	blend.independent_blend_enable = true;
2653	for (i = 0; i < 2; i++) {
2654		blend.rt[i].colormask = 0xf;
2655		blend.rt[i].blend_enable = 1;
2656		blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2657		blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2658		blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2659		blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2660		blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2661		blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2662	}
2663	rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2664	return rstate;
2665}
2666
2667void *r700_create_resolve_blend(struct r600_context *rctx)
2668{
2669	struct pipe_blend_state blend;
2670	struct r600_pipe_state *rstate;
2671
2672	memset(&blend, 0, sizeof(blend));
2673	blend.independent_blend_enable = true;
2674	blend.rt[0].colormask = 0xf;
2675	rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2676	return rstate;
2677}
2678
2679void *r600_create_decompress_blend(struct r600_context *rctx)
2680{
2681	struct pipe_blend_state blend;
2682	struct r600_pipe_state *rstate;
2683
2684	memset(&blend, 0, sizeof(blend));
2685	blend.independent_blend_enable = true;
2686	blend.rt[0].colormask = 0xf;
2687	rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2688	return rstate;
2689}
2690
2691void *r600_create_db_flush_dsa(struct r600_context *rctx)
2692{
2693	struct pipe_depth_stencil_alpha_state dsa;
2694	boolean quirk = false;
2695
2696	if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2697		rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2698		quirk = true;
2699
2700	memset(&dsa, 0, sizeof(dsa));
2701
2702	if (quirk) {
2703		dsa.depth.enabled = 1;
2704		dsa.depth.func = PIPE_FUNC_LEQUAL;
2705		dsa.stencil[0].enabled = 1;
2706		dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2707		dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2708		dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2709		dsa.stencil[0].writemask = 0xff;
2710	}
2711
2712	return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2713}
2714
2715void r600_update_dual_export_state(struct r600_context * rctx)
2716{
2717	unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2718			       !rctx->ps_shader->current->ps_depth_export;
2719	unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2720				     S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2721
2722	if (db_shader_control != rctx->db_shader_control) {
2723		struct r600_pipe_state rstate;
2724
2725		rctx->db_shader_control = db_shader_control;
2726		rstate.nregs = 0;
2727		r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2728		r600_context_pipe_state_set(rctx, &rstate);
2729	}
2730}
2731