r600_state.c revision cb922b63eba1d75706354614bc5de4d39dbe9ad3
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#include "r600_formats.h" 24#include "r600d.h" 25 26#include "pipe/p_shader_tokens.h" 27#include "util/u_pack_color.h" 28#include "util/u_memory.h" 29#include "util/u_framebuffer.h" 30#include "util/u_dual_blend.h" 31 32static uint32_t r600_translate_blend_function(int blend_func) 33{ 34 switch (blend_func) { 35 case PIPE_BLEND_ADD: 36 return V_028804_COMB_DST_PLUS_SRC; 37 case PIPE_BLEND_SUBTRACT: 38 return V_028804_COMB_SRC_MINUS_DST; 39 case PIPE_BLEND_REVERSE_SUBTRACT: 40 return V_028804_COMB_DST_MINUS_SRC; 41 case PIPE_BLEND_MIN: 42 return V_028804_COMB_MIN_DST_SRC; 43 case PIPE_BLEND_MAX: 44 return V_028804_COMB_MAX_DST_SRC; 45 default: 46 R600_ERR("Unknown blend function %d\n", blend_func); 47 assert(0); 48 break; 49 } 50 return 0; 51} 52 53static uint32_t r600_translate_blend_factor(int blend_fact) 54{ 55 switch (blend_fact) { 56 case PIPE_BLENDFACTOR_ONE: 57 return V_028804_BLEND_ONE; 58 case PIPE_BLENDFACTOR_SRC_COLOR: 59 return V_028804_BLEND_SRC_COLOR; 60 case PIPE_BLENDFACTOR_SRC_ALPHA: 61 return V_028804_BLEND_SRC_ALPHA; 62 case PIPE_BLENDFACTOR_DST_ALPHA: 63 return V_028804_BLEND_DST_ALPHA; 64 case PIPE_BLENDFACTOR_DST_COLOR: 65 return V_028804_BLEND_DST_COLOR; 66 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE: 67 return V_028804_BLEND_SRC_ALPHA_SATURATE; 68 case PIPE_BLENDFACTOR_CONST_COLOR: 69 return V_028804_BLEND_CONST_COLOR; 70 case PIPE_BLENDFACTOR_CONST_ALPHA: 71 return V_028804_BLEND_CONST_ALPHA; 72 case PIPE_BLENDFACTOR_ZERO: 73 return V_028804_BLEND_ZERO; 74 case PIPE_BLENDFACTOR_INV_SRC_COLOR: 75 return V_028804_BLEND_ONE_MINUS_SRC_COLOR; 76 case PIPE_BLENDFACTOR_INV_SRC_ALPHA: 77 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA; 78 case PIPE_BLENDFACTOR_INV_DST_ALPHA: 79 return V_028804_BLEND_ONE_MINUS_DST_ALPHA; 80 case PIPE_BLENDFACTOR_INV_DST_COLOR: 81 return V_028804_BLEND_ONE_MINUS_DST_COLOR; 82 case PIPE_BLENDFACTOR_INV_CONST_COLOR: 83 return V_028804_BLEND_ONE_MINUS_CONST_COLOR; 84 case PIPE_BLENDFACTOR_INV_CONST_ALPHA: 85 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA; 86 case PIPE_BLENDFACTOR_SRC1_COLOR: 87 return V_028804_BLEND_SRC1_COLOR; 88 case PIPE_BLENDFACTOR_SRC1_ALPHA: 89 return V_028804_BLEND_SRC1_ALPHA; 90 case PIPE_BLENDFACTOR_INV_SRC1_COLOR: 91 return V_028804_BLEND_INV_SRC1_COLOR; 92 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA: 93 return V_028804_BLEND_INV_SRC1_ALPHA; 94 default: 95 R600_ERR("Bad blend factor %d not supported!\n", blend_fact); 96 assert(0); 97 break; 98 } 99 return 0; 100} 101 102static unsigned r600_tex_dim(unsigned dim) 103{ 104 switch (dim) { 105 default: 106 case PIPE_TEXTURE_1D: 107 return V_038000_SQ_TEX_DIM_1D; 108 case PIPE_TEXTURE_1D_ARRAY: 109 return V_038000_SQ_TEX_DIM_1D_ARRAY; 110 case PIPE_TEXTURE_2D: 111 case PIPE_TEXTURE_RECT: 112 return V_038000_SQ_TEX_DIM_2D; 113 case PIPE_TEXTURE_2D_ARRAY: 114 return V_038000_SQ_TEX_DIM_2D_ARRAY; 115 case PIPE_TEXTURE_3D: 116 return V_038000_SQ_TEX_DIM_3D; 117 case PIPE_TEXTURE_CUBE: 118 return V_038000_SQ_TEX_DIM_CUBEMAP; 119 } 120} 121 122static uint32_t r600_translate_dbformat(enum pipe_format format) 123{ 124 switch (format) { 125 case PIPE_FORMAT_Z16_UNORM: 126 return V_028010_DEPTH_16; 127 case PIPE_FORMAT_Z24X8_UNORM: 128 return V_028010_DEPTH_X8_24; 129 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 130 return V_028010_DEPTH_8_24; 131 case PIPE_FORMAT_Z32_FLOAT: 132 return V_028010_DEPTH_32_FLOAT; 133 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 134 return V_028010_DEPTH_X24_8_32_FLOAT; 135 default: 136 return ~0U; 137 } 138} 139 140static uint32_t r600_translate_colorswap(enum pipe_format format) 141{ 142 switch (format) { 143 /* 8-bit buffers. */ 144 case PIPE_FORMAT_A8_UNORM: 145 case PIPE_FORMAT_A8_SNORM: 146 case PIPE_FORMAT_A8_UINT: 147 case PIPE_FORMAT_A8_SINT: 148 case PIPE_FORMAT_A16_UNORM: 149 case PIPE_FORMAT_A16_SNORM: 150 case PIPE_FORMAT_A16_UINT: 151 case PIPE_FORMAT_A16_SINT: 152 case PIPE_FORMAT_A16_FLOAT: 153 case PIPE_FORMAT_A32_UINT: 154 case PIPE_FORMAT_A32_SINT: 155 case PIPE_FORMAT_A32_FLOAT: 156 case PIPE_FORMAT_R4A4_UNORM: 157 return V_0280A0_SWAP_ALT_REV; 158 case PIPE_FORMAT_I8_UNORM: 159 case PIPE_FORMAT_I8_SNORM: 160 case PIPE_FORMAT_I8_UINT: 161 case PIPE_FORMAT_I8_SINT: 162 case PIPE_FORMAT_L8_UNORM: 163 case PIPE_FORMAT_L8_SNORM: 164 case PIPE_FORMAT_L8_UINT: 165 case PIPE_FORMAT_L8_SINT: 166 case PIPE_FORMAT_L8_SRGB: 167 case PIPE_FORMAT_L16_UNORM: 168 case PIPE_FORMAT_L16_SNORM: 169 case PIPE_FORMAT_L16_UINT: 170 case PIPE_FORMAT_L16_SINT: 171 case PIPE_FORMAT_L16_FLOAT: 172 case PIPE_FORMAT_L32_UINT: 173 case PIPE_FORMAT_L32_SINT: 174 case PIPE_FORMAT_L32_FLOAT: 175 case PIPE_FORMAT_I16_UNORM: 176 case PIPE_FORMAT_I16_SNORM: 177 case PIPE_FORMAT_I16_UINT: 178 case PIPE_FORMAT_I16_SINT: 179 case PIPE_FORMAT_I16_FLOAT: 180 case PIPE_FORMAT_I32_UINT: 181 case PIPE_FORMAT_I32_SINT: 182 case PIPE_FORMAT_I32_FLOAT: 183 case PIPE_FORMAT_R8_UNORM: 184 case PIPE_FORMAT_R8_SNORM: 185 case PIPE_FORMAT_R8_UINT: 186 case PIPE_FORMAT_R8_SINT: 187 return V_0280A0_SWAP_STD; 188 189 case PIPE_FORMAT_L4A4_UNORM: 190 case PIPE_FORMAT_A4R4_UNORM: 191 return V_0280A0_SWAP_ALT; 192 193 /* 16-bit buffers. */ 194 case PIPE_FORMAT_B5G6R5_UNORM: 195 return V_0280A0_SWAP_STD_REV; 196 197 case PIPE_FORMAT_B5G5R5A1_UNORM: 198 case PIPE_FORMAT_B5G5R5X1_UNORM: 199 return V_0280A0_SWAP_ALT; 200 201 case PIPE_FORMAT_B4G4R4A4_UNORM: 202 case PIPE_FORMAT_B4G4R4X4_UNORM: 203 return V_0280A0_SWAP_ALT; 204 205 case PIPE_FORMAT_Z16_UNORM: 206 return V_0280A0_SWAP_STD; 207 208 case PIPE_FORMAT_L8A8_UNORM: 209 case PIPE_FORMAT_L8A8_SNORM: 210 case PIPE_FORMAT_L8A8_UINT: 211 case PIPE_FORMAT_L8A8_SINT: 212 case PIPE_FORMAT_L8A8_SRGB: 213 case PIPE_FORMAT_L16A16_UNORM: 214 case PIPE_FORMAT_L16A16_SNORM: 215 case PIPE_FORMAT_L16A16_UINT: 216 case PIPE_FORMAT_L16A16_SINT: 217 case PIPE_FORMAT_L16A16_FLOAT: 218 case PIPE_FORMAT_L32A32_UINT: 219 case PIPE_FORMAT_L32A32_SINT: 220 case PIPE_FORMAT_L32A32_FLOAT: 221 return V_0280A0_SWAP_ALT; 222 case PIPE_FORMAT_R8G8_UNORM: 223 case PIPE_FORMAT_R8G8_SNORM: 224 case PIPE_FORMAT_R8G8_UINT: 225 case PIPE_FORMAT_R8G8_SINT: 226 return V_0280A0_SWAP_STD; 227 228 case PIPE_FORMAT_R16_UNORM: 229 case PIPE_FORMAT_R16_SNORM: 230 case PIPE_FORMAT_R16_UINT: 231 case PIPE_FORMAT_R16_SINT: 232 case PIPE_FORMAT_R16_FLOAT: 233 return V_0280A0_SWAP_STD; 234 235 /* 32-bit buffers. */ 236 237 case PIPE_FORMAT_A8B8G8R8_SRGB: 238 return V_0280A0_SWAP_STD_REV; 239 case PIPE_FORMAT_B8G8R8A8_SRGB: 240 return V_0280A0_SWAP_ALT; 241 242 case PIPE_FORMAT_B8G8R8A8_UNORM: 243 case PIPE_FORMAT_B8G8R8X8_UNORM: 244 return V_0280A0_SWAP_ALT; 245 246 case PIPE_FORMAT_A8R8G8B8_UNORM: 247 case PIPE_FORMAT_X8R8G8B8_UNORM: 248 return V_0280A0_SWAP_ALT_REV; 249 case PIPE_FORMAT_R8G8B8A8_SNORM: 250 case PIPE_FORMAT_R8G8B8A8_UNORM: 251 case PIPE_FORMAT_R8G8B8X8_UNORM: 252 case PIPE_FORMAT_R8G8B8A8_SINT: 253 case PIPE_FORMAT_R8G8B8A8_UINT: 254 return V_0280A0_SWAP_STD; 255 256 case PIPE_FORMAT_A8B8G8R8_UNORM: 257 case PIPE_FORMAT_X8B8G8R8_UNORM: 258 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */ 259 return V_0280A0_SWAP_STD_REV; 260 261 case PIPE_FORMAT_Z24X8_UNORM: 262 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 263 return V_0280A0_SWAP_STD; 264 265 case PIPE_FORMAT_X8Z24_UNORM: 266 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 267 return V_0280A0_SWAP_STD; 268 269 case PIPE_FORMAT_R10G10B10A2_UNORM: 270 case PIPE_FORMAT_R10G10B10X2_SNORM: 271 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 272 return V_0280A0_SWAP_STD; 273 274 case PIPE_FORMAT_B10G10R10A2_UNORM: 275 case PIPE_FORMAT_B10G10R10A2_UINT: 276 return V_0280A0_SWAP_ALT; 277 278 case PIPE_FORMAT_R11G11B10_FLOAT: 279 case PIPE_FORMAT_R16G16_UNORM: 280 case PIPE_FORMAT_R16G16_SNORM: 281 case PIPE_FORMAT_R16G16_FLOAT: 282 case PIPE_FORMAT_R16G16_UINT: 283 case PIPE_FORMAT_R16G16_SINT: 284 case PIPE_FORMAT_R16G16B16_FLOAT: 285 case PIPE_FORMAT_R32G32B32_FLOAT: 286 case PIPE_FORMAT_R32_UINT: 287 case PIPE_FORMAT_R32_SINT: 288 case PIPE_FORMAT_R32_FLOAT: 289 case PIPE_FORMAT_Z32_FLOAT: 290 return V_0280A0_SWAP_STD; 291 292 /* 64-bit buffers. */ 293 case PIPE_FORMAT_R32G32_FLOAT: 294 case PIPE_FORMAT_R32G32_UINT: 295 case PIPE_FORMAT_R32G32_SINT: 296 case PIPE_FORMAT_R16G16B16A16_UNORM: 297 case PIPE_FORMAT_R16G16B16A16_SNORM: 298 case PIPE_FORMAT_R16G16B16A16_UINT: 299 case PIPE_FORMAT_R16G16B16A16_SINT: 300 case PIPE_FORMAT_R16G16B16A16_FLOAT: 301 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 302 303 /* 128-bit buffers. */ 304 case PIPE_FORMAT_R32G32B32A32_FLOAT: 305 case PIPE_FORMAT_R32G32B32A32_SNORM: 306 case PIPE_FORMAT_R32G32B32A32_UNORM: 307 case PIPE_FORMAT_R32G32B32A32_SINT: 308 case PIPE_FORMAT_R32G32B32A32_UINT: 309 return V_0280A0_SWAP_STD; 310 default: 311 R600_ERR("unsupported colorswap format %d\n", format); 312 return ~0U; 313 } 314 return ~0U; 315} 316 317static uint32_t r600_translate_colorformat(enum pipe_format format) 318{ 319 switch (format) { 320 case PIPE_FORMAT_L4A4_UNORM: 321 case PIPE_FORMAT_R4A4_UNORM: 322 case PIPE_FORMAT_A4R4_UNORM: 323 return V_0280A0_COLOR_4_4; 324 325 /* 8-bit buffers. */ 326 case PIPE_FORMAT_A8_UNORM: 327 case PIPE_FORMAT_A8_SNORM: 328 case PIPE_FORMAT_A8_UINT: 329 case PIPE_FORMAT_A8_SINT: 330 case PIPE_FORMAT_I8_UNORM: 331 case PIPE_FORMAT_I8_SNORM: 332 case PIPE_FORMAT_I8_UINT: 333 case PIPE_FORMAT_I8_SINT: 334 case PIPE_FORMAT_L8_UNORM: 335 case PIPE_FORMAT_L8_SNORM: 336 case PIPE_FORMAT_L8_UINT: 337 case PIPE_FORMAT_L8_SINT: 338 case PIPE_FORMAT_L8_SRGB: 339 case PIPE_FORMAT_R8_UNORM: 340 case PIPE_FORMAT_R8_SNORM: 341 case PIPE_FORMAT_R8_UINT: 342 case PIPE_FORMAT_R8_SINT: 343 return V_0280A0_COLOR_8; 344 345 /* 16-bit buffers. */ 346 case PIPE_FORMAT_B5G6R5_UNORM: 347 return V_0280A0_COLOR_5_6_5; 348 349 case PIPE_FORMAT_B5G5R5A1_UNORM: 350 case PIPE_FORMAT_B5G5R5X1_UNORM: 351 return V_0280A0_COLOR_1_5_5_5; 352 353 case PIPE_FORMAT_B4G4R4A4_UNORM: 354 case PIPE_FORMAT_B4G4R4X4_UNORM: 355 return V_0280A0_COLOR_4_4_4_4; 356 357 case PIPE_FORMAT_Z16_UNORM: 358 return V_0280A0_COLOR_16; 359 360 case PIPE_FORMAT_L8A8_UNORM: 361 case PIPE_FORMAT_L8A8_SNORM: 362 case PIPE_FORMAT_L8A8_UINT: 363 case PIPE_FORMAT_L8A8_SINT: 364 case PIPE_FORMAT_L8A8_SRGB: 365 case PIPE_FORMAT_R8G8_UNORM: 366 case PIPE_FORMAT_R8G8_SNORM: 367 case PIPE_FORMAT_R8G8_UINT: 368 case PIPE_FORMAT_R8G8_SINT: 369 return V_0280A0_COLOR_8_8; 370 371 case PIPE_FORMAT_R16_UNORM: 372 case PIPE_FORMAT_R16_SNORM: 373 case PIPE_FORMAT_R16_UINT: 374 case PIPE_FORMAT_R16_SINT: 375 case PIPE_FORMAT_A16_UNORM: 376 case PIPE_FORMAT_A16_SNORM: 377 case PIPE_FORMAT_A16_UINT: 378 case PIPE_FORMAT_A16_SINT: 379 case PIPE_FORMAT_L16_UNORM: 380 case PIPE_FORMAT_L16_SNORM: 381 case PIPE_FORMAT_L16_UINT: 382 case PIPE_FORMAT_L16_SINT: 383 case PIPE_FORMAT_I16_UNORM: 384 case PIPE_FORMAT_I16_SNORM: 385 case PIPE_FORMAT_I16_UINT: 386 case PIPE_FORMAT_I16_SINT: 387 return V_0280A0_COLOR_16; 388 389 case PIPE_FORMAT_R16_FLOAT: 390 case PIPE_FORMAT_A16_FLOAT: 391 case PIPE_FORMAT_L16_FLOAT: 392 case PIPE_FORMAT_I16_FLOAT: 393 return V_0280A0_COLOR_16_FLOAT; 394 395 /* 32-bit buffers. */ 396 case PIPE_FORMAT_A8B8G8R8_SRGB: 397 case PIPE_FORMAT_A8B8G8R8_UNORM: 398 case PIPE_FORMAT_A8R8G8B8_UNORM: 399 case PIPE_FORMAT_B8G8R8A8_SRGB: 400 case PIPE_FORMAT_B8G8R8A8_UNORM: 401 case PIPE_FORMAT_B8G8R8X8_UNORM: 402 case PIPE_FORMAT_R8G8B8A8_SNORM: 403 case PIPE_FORMAT_R8G8B8A8_UNORM: 404 case PIPE_FORMAT_R8G8B8X8_UNORM: 405 case PIPE_FORMAT_R8SG8SB8UX8U_NORM: 406 case PIPE_FORMAT_X8B8G8R8_UNORM: 407 case PIPE_FORMAT_X8R8G8B8_UNORM: 408 case PIPE_FORMAT_R8G8B8_UNORM: 409 case PIPE_FORMAT_R8G8B8A8_SINT: 410 case PIPE_FORMAT_R8G8B8A8_UINT: 411 return V_0280A0_COLOR_8_8_8_8; 412 413 case PIPE_FORMAT_R10G10B10A2_UNORM: 414 case PIPE_FORMAT_R10G10B10X2_SNORM: 415 case PIPE_FORMAT_B10G10R10A2_UNORM: 416 case PIPE_FORMAT_B10G10R10A2_UINT: 417 case PIPE_FORMAT_R10SG10SB10SA2U_NORM: 418 return V_0280A0_COLOR_2_10_10_10; 419 420 case PIPE_FORMAT_Z24X8_UNORM: 421 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 422 return V_0280A0_COLOR_8_24; 423 424 case PIPE_FORMAT_X8Z24_UNORM: 425 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 426 return V_0280A0_COLOR_24_8; 427 428 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 429 return V_0280A0_COLOR_X24_8_32_FLOAT; 430 431 case PIPE_FORMAT_R32_UINT: 432 case PIPE_FORMAT_R32_SINT: 433 case PIPE_FORMAT_A32_UINT: 434 case PIPE_FORMAT_A32_SINT: 435 case PIPE_FORMAT_L32_UINT: 436 case PIPE_FORMAT_L32_SINT: 437 case PIPE_FORMAT_I32_UINT: 438 case PIPE_FORMAT_I32_SINT: 439 return V_0280A0_COLOR_32; 440 441 case PIPE_FORMAT_R32_FLOAT: 442 case PIPE_FORMAT_A32_FLOAT: 443 case PIPE_FORMAT_L32_FLOAT: 444 case PIPE_FORMAT_I32_FLOAT: 445 case PIPE_FORMAT_Z32_FLOAT: 446 return V_0280A0_COLOR_32_FLOAT; 447 448 case PIPE_FORMAT_R16G16_FLOAT: 449 case PIPE_FORMAT_L16A16_FLOAT: 450 return V_0280A0_COLOR_16_16_FLOAT; 451 452 case PIPE_FORMAT_R16G16_UNORM: 453 case PIPE_FORMAT_R16G16_SNORM: 454 case PIPE_FORMAT_R16G16_UINT: 455 case PIPE_FORMAT_R16G16_SINT: 456 case PIPE_FORMAT_L16A16_UNORM: 457 case PIPE_FORMAT_L16A16_SNORM: 458 case PIPE_FORMAT_L16A16_UINT: 459 case PIPE_FORMAT_L16A16_SINT: 460 return V_0280A0_COLOR_16_16; 461 462 case PIPE_FORMAT_R11G11B10_FLOAT: 463 return V_0280A0_COLOR_10_11_11_FLOAT; 464 465 /* 64-bit buffers. */ 466 case PIPE_FORMAT_R16G16B16A16_UINT: 467 case PIPE_FORMAT_R16G16B16A16_SINT: 468 case PIPE_FORMAT_R16G16B16A16_UNORM: 469 case PIPE_FORMAT_R16G16B16A16_SNORM: 470 return V_0280A0_COLOR_16_16_16_16; 471 472 case PIPE_FORMAT_R16G16B16_FLOAT: 473 case PIPE_FORMAT_R16G16B16A16_FLOAT: 474 return V_0280A0_COLOR_16_16_16_16_FLOAT; 475 476 case PIPE_FORMAT_R32G32_FLOAT: 477 case PIPE_FORMAT_L32A32_FLOAT: 478 return V_0280A0_COLOR_32_32_FLOAT; 479 480 case PIPE_FORMAT_R32G32_SINT: 481 case PIPE_FORMAT_R32G32_UINT: 482 case PIPE_FORMAT_L32A32_UINT: 483 case PIPE_FORMAT_L32A32_SINT: 484 return V_0280A0_COLOR_32_32; 485 486 /* 96-bit buffers. */ 487 case PIPE_FORMAT_R32G32B32_FLOAT: 488 return V_0280A0_COLOR_32_32_32_FLOAT; 489 490 /* 128-bit buffers. */ 491 case PIPE_FORMAT_R32G32B32A32_FLOAT: 492 return V_0280A0_COLOR_32_32_32_32_FLOAT; 493 case PIPE_FORMAT_R32G32B32A32_SNORM: 494 case PIPE_FORMAT_R32G32B32A32_UNORM: 495 case PIPE_FORMAT_R32G32B32A32_SINT: 496 case PIPE_FORMAT_R32G32B32A32_UINT: 497 return V_0280A0_COLOR_32_32_32_32; 498 499 /* YUV buffers. */ 500 case PIPE_FORMAT_UYVY: 501 case PIPE_FORMAT_YUYV: 502 default: 503 return ~0U; /* Unsupported. */ 504 } 505} 506 507static uint32_t r600_colorformat_endian_swap(uint32_t colorformat) 508{ 509 if (R600_BIG_ENDIAN) { 510 switch(colorformat) { 511 case V_0280A0_COLOR_4_4: 512 return ENDIAN_NONE; 513 514 /* 8-bit buffers. */ 515 case V_0280A0_COLOR_8: 516 return ENDIAN_NONE; 517 518 /* 16-bit buffers. */ 519 case V_0280A0_COLOR_5_6_5: 520 case V_0280A0_COLOR_1_5_5_5: 521 case V_0280A0_COLOR_4_4_4_4: 522 case V_0280A0_COLOR_16: 523 case V_0280A0_COLOR_8_8: 524 return ENDIAN_8IN16; 525 526 /* 32-bit buffers. */ 527 case V_0280A0_COLOR_8_8_8_8: 528 case V_0280A0_COLOR_2_10_10_10: 529 case V_0280A0_COLOR_8_24: 530 case V_0280A0_COLOR_24_8: 531 case V_0280A0_COLOR_32_FLOAT: 532 case V_0280A0_COLOR_16_16_FLOAT: 533 case V_0280A0_COLOR_16_16: 534 return ENDIAN_8IN32; 535 536 /* 64-bit buffers. */ 537 case V_0280A0_COLOR_16_16_16_16: 538 case V_0280A0_COLOR_16_16_16_16_FLOAT: 539 return ENDIAN_8IN16; 540 541 case V_0280A0_COLOR_32_32_FLOAT: 542 case V_0280A0_COLOR_32_32: 543 case V_0280A0_COLOR_X24_8_32_FLOAT: 544 return ENDIAN_8IN32; 545 546 /* 128-bit buffers. */ 547 case V_0280A0_COLOR_32_32_32_FLOAT: 548 case V_0280A0_COLOR_32_32_32_32_FLOAT: 549 case V_0280A0_COLOR_32_32_32_32: 550 return ENDIAN_8IN32; 551 default: 552 return ENDIAN_NONE; /* Unsupported. */ 553 } 554 } else { 555 return ENDIAN_NONE; 556 } 557} 558 559static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format) 560{ 561 return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U; 562} 563 564static bool r600_is_colorbuffer_format_supported(enum pipe_format format) 565{ 566 return r600_translate_colorformat(format) != ~0U && 567 r600_translate_colorswap(format) != ~0U; 568} 569 570static bool r600_is_zs_format_supported(enum pipe_format format) 571{ 572 return r600_translate_dbformat(format) != ~0U; 573} 574 575boolean r600_is_format_supported(struct pipe_screen *screen, 576 enum pipe_format format, 577 enum pipe_texture_target target, 578 unsigned sample_count, 579 unsigned usage) 580{ 581 unsigned retval = 0; 582 583 if (target >= PIPE_MAX_TEXTURE_TYPES) { 584 R600_ERR("r600: unsupported texture type %d\n", target); 585 return FALSE; 586 } 587 588 if (!util_format_is_supported(format, usage)) 589 return FALSE; 590 591 /* Multisample */ 592 if (sample_count > 1) 593 return FALSE; 594 595 if ((usage & PIPE_BIND_SAMPLER_VIEW) && 596 r600_is_sampler_format_supported(screen, format)) { 597 retval |= PIPE_BIND_SAMPLER_VIEW; 598 } 599 600 if ((usage & (PIPE_BIND_RENDER_TARGET | 601 PIPE_BIND_DISPLAY_TARGET | 602 PIPE_BIND_SCANOUT | 603 PIPE_BIND_SHARED)) && 604 r600_is_colorbuffer_format_supported(format)) { 605 retval |= usage & 606 (PIPE_BIND_RENDER_TARGET | 607 PIPE_BIND_DISPLAY_TARGET | 608 PIPE_BIND_SCANOUT | 609 PIPE_BIND_SHARED); 610 } 611 612 if ((usage & PIPE_BIND_DEPTH_STENCIL) && 613 r600_is_zs_format_supported(format)) { 614 retval |= PIPE_BIND_DEPTH_STENCIL; 615 } 616 617 if ((usage & PIPE_BIND_VERTEX_BUFFER) && 618 r600_is_vertex_format_supported(format)) { 619 retval |= PIPE_BIND_VERTEX_BUFFER; 620 } 621 622 if (usage & PIPE_BIND_TRANSFER_READ) 623 retval |= PIPE_BIND_TRANSFER_READ; 624 if (usage & PIPE_BIND_TRANSFER_WRITE) 625 retval |= PIPE_BIND_TRANSFER_WRITE; 626 627 return retval == usage; 628} 629 630void r600_polygon_offset_update(struct r600_context *rctx) 631{ 632 struct r600_pipe_state state; 633 634 state.id = R600_PIPE_STATE_POLYGON_OFFSET; 635 state.nregs = 0; 636 if (rctx->rasterizer && rctx->framebuffer.zsbuf) { 637 float offset_units = rctx->rasterizer->offset_units; 638 unsigned offset_db_fmt_cntl = 0, depth; 639 640 switch (rctx->framebuffer.zsbuf->format) { 641 case PIPE_FORMAT_Z24X8_UNORM: 642 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 643 depth = -24; 644 offset_units *= 2.0f; 645 break; 646 case PIPE_FORMAT_Z32_FLOAT: 647 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 648 depth = -23; 649 offset_units *= 1.0f; 650 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1); 651 break; 652 case PIPE_FORMAT_Z16_UNORM: 653 depth = -16; 654 offset_units *= 4.0f; 655 break; 656 default: 657 return; 658 } 659 /* XXX some of those reg can be computed with cso */ 660 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth); 661 r600_pipe_state_add_reg(&state, 662 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 663 fui(rctx->rasterizer->offset_scale)); 664 r600_pipe_state_add_reg(&state, 665 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET, 666 fui(offset_units)); 667 r600_pipe_state_add_reg(&state, 668 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE, 669 fui(rctx->rasterizer->offset_scale)); 670 r600_pipe_state_add_reg(&state, 671 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET, 672 fui(offset_units)); 673 r600_pipe_state_add_reg(&state, 674 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, 675 offset_db_fmt_cntl); 676 r600_context_pipe_state_set(rctx, &state); 677 } 678} 679 680static void *r600_create_blend_state(struct pipe_context *ctx, 681 const struct pipe_blend_state *state) 682{ 683 struct r600_context *rctx = (struct r600_context *)ctx; 684 struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend); 685 struct r600_pipe_state *rstate; 686 uint32_t color_control = 0, target_mask; 687 688 if (blend == NULL) { 689 return NULL; 690 } 691 rstate = &blend->rstate; 692 693 rstate->id = R600_PIPE_STATE_BLEND; 694 695 target_mask = 0; 696 697 /* R600 does not support per-MRT blends */ 698 if (rctx->family > CHIP_R600) 699 color_control |= S_028808_PER_MRT_BLEND(1); 700 if (state->logicop_enable) { 701 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20); 702 } else { 703 color_control |= (0xcc << 16); 704 } 705 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */ 706 if (state->independent_blend_enable) { 707 for (int i = 0; i < 8; i++) { 708 if (state->rt[i].blend_enable) { 709 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 710 } 711 target_mask |= (state->rt[i].colormask << (4 * i)); 712 } 713 } else { 714 for (int i = 0; i < 8; i++) { 715 if (state->rt[0].blend_enable) { 716 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i); 717 } 718 target_mask |= (state->rt[0].colormask << (4 * i)); 719 } 720 } 721 722 if (target_mask) 723 color_control |= S_028808_SPECIAL_OP(V_028808_NORMAL); 724 else 725 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE); 726 727 blend->cb_target_mask = target_mask; 728 blend->cb_color_control = color_control; 729 /* only MRT0 has dual src blend */ 730 blend->dual_src_blend = util_blend_state_is_dual(state, 0); 731 for (int i = 0; i < 8; i++) { 732 /* state->rt entries > 0 only written if independent blending */ 733 const int j = state->independent_blend_enable ? i : 0; 734 735 unsigned eqRGB = state->rt[j].rgb_func; 736 unsigned srcRGB = state->rt[j].rgb_src_factor; 737 unsigned dstRGB = state->rt[j].rgb_dst_factor; 738 739 unsigned eqA = state->rt[j].alpha_func; 740 unsigned srcA = state->rt[j].alpha_src_factor; 741 unsigned dstA = state->rt[j].alpha_dst_factor; 742 uint32_t bc = 0; 743 744 if (!state->rt[j].blend_enable) 745 continue; 746 747 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB)); 748 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB)); 749 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB)); 750 751 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 752 bc |= S_028804_SEPARATE_ALPHA_BLEND(1); 753 bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA)); 754 bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA)); 755 bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA)); 756 } 757 758 /* R600 does not support per-MRT blends */ 759 if (rctx->family > CHIP_R600) 760 r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc); 761 if (i == 0) 762 r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc); 763 } 764 return rstate; 765} 766 767static void *r600_create_dsa_state(struct pipe_context *ctx, 768 const struct pipe_depth_stencil_alpha_state *state) 769{ 770 struct r600_context *rctx = (struct r600_context *)ctx; 771 struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa); 772 unsigned db_depth_control, alpha_test_control, alpha_ref; 773 struct r600_pipe_state *rstate; 774 775 if (dsa == NULL) { 776 return NULL; 777 } 778 779 dsa->valuemask[0] = state->stencil[0].valuemask; 780 dsa->valuemask[1] = state->stencil[1].valuemask; 781 dsa->writemask[0] = state->stencil[0].writemask; 782 dsa->writemask[1] = state->stencil[1].writemask; 783 784 rstate = &dsa->rstate; 785 786 rstate->id = R600_PIPE_STATE_DSA; 787 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | 788 S_028800_Z_WRITE_ENABLE(state->depth.writemask) | 789 S_028800_ZFUNC(state->depth.func); 790 791 /* stencil */ 792 if (state->stencil[0].enabled) { 793 db_depth_control |= S_028800_STENCIL_ENABLE(1); 794 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */ 795 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op)); 796 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op)); 797 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op)); 798 799 if (state->stencil[1].enabled) { 800 db_depth_control |= S_028800_BACKFACE_ENABLE(1); 801 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */ 802 db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op)); 803 db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op)); 804 db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op)); 805 } 806 } 807 808 /* alpha */ 809 alpha_test_control = 0; 810 alpha_ref = 0; 811 if (state->alpha.enabled) { 812 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func); 813 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1); 814 alpha_ref = fui(state->alpha.ref_value); 815 } 816 dsa->sx_alpha_test_control = alpha_test_control & 0xff; 817 dsa->alpha_ref = alpha_ref; 818 819 r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control); 820 return rstate; 821} 822 823static void *r600_create_rs_state(struct pipe_context *ctx, 824 const struct pipe_rasterizer_state *state) 825{ 826 struct r600_context *rctx = (struct r600_context *)ctx; 827 struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer); 828 struct r600_pipe_state *rstate; 829 unsigned tmp; 830 unsigned prov_vtx = 1, polygon_dual_mode; 831 unsigned sc_mode_cntl; 832 float psize_min, psize_max; 833 834 if (rs == NULL) { 835 return NULL; 836 } 837 838 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL || 839 state->fill_back != PIPE_POLYGON_MODE_FILL); 840 841 if (state->flatshade_first) 842 prov_vtx = 0; 843 844 rstate = &rs->rstate; 845 rs->flatshade = state->flatshade; 846 rs->sprite_coord_enable = state->sprite_coord_enable; 847 rs->two_side = state->light_twoside; 848 rs->clip_plane_enable = state->clip_plane_enable; 849 rs->pa_sc_line_stipple = state->line_stipple_enable ? 850 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) | 851 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0; 852 rs->pa_cl_clip_cntl = 853 S_028810_PS_UCP_MODE(3) | 854 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) | 855 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) | 856 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1); 857 858 /* offset */ 859 rs->offset_units = state->offset_units; 860 rs->offset_scale = state->offset_scale * 12.0f; 861 862 rstate->id = R600_PIPE_STATE_RASTERIZER; 863 tmp = S_0286D4_FLAT_SHADE_ENA(1); 864 if (state->sprite_coord_enable) { 865 tmp |= S_0286D4_PNT_SPRITE_ENA(1) | 866 S_0286D4_PNT_SPRITE_OVRD_X(2) | 867 S_0286D4_PNT_SPRITE_OVRD_Y(3) | 868 S_0286D4_PNT_SPRITE_OVRD_Z(0) | 869 S_0286D4_PNT_SPRITE_OVRD_W(1); 870 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) { 871 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1); 872 } 873 } 874 r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp); 875 876 /* point size 12.4 fixed point */ 877 tmp = r600_pack_float_12p4(state->point_size/2); 878 r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp)); 879 880 if (state->point_size_per_vertex) { 881 psize_min = util_get_min_point_size(state); 882 psize_max = 8192; 883 } else { 884 /* Force the point size to be as if the vertex output was disabled. */ 885 psize_min = state->point_size; 886 psize_max = state->point_size; 887 } 888 /* Divide by two, because 0.5 = 1 pixel. */ 889 r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 890 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) | 891 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2))); 892 893 tmp = r600_pack_float_12p4(state->line_width/2); 894 r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp)); 895 896 if (rctx->chip_class >= R700) { 897 sc_mode_cntl = 898 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | 899 S_028A4C_FORCE_EOV_REZ_ENABLE(1) | 900 S_028A4C_R700_ZMM_LINE_OFFSET(1) | 901 S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor); 902 } else { 903 sc_mode_cntl = 904 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | 905 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1); 906 rs->scissor_enable = state->scissor; 907 } 908 sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable); 909 910 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl); 911 912 r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL, 913 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules)); 914 915 r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp)); 916 r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL, 917 S_028814_PROVOKING_VTX_LAST(prov_vtx) | 918 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) | 919 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) | 920 S_028814_FACE(!state->front_ccw) | 921 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) | 922 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) | 923 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) | 924 S_028814_POLY_MODE(polygon_dual_mode) | 925 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) | 926 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back))); 927 r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard)); 928 return rstate; 929} 930 931static void *r600_create_sampler_state(struct pipe_context *ctx, 932 const struct pipe_sampler_state *state) 933{ 934 struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state); 935 struct r600_pipe_state *rstate; 936 union util_color uc; 937 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0; 938 939 if (ss == NULL) { 940 return NULL; 941 } 942 943 ss->seamless_cube_map = state->seamless_cube_map; 944 rstate = &ss->rstate; 945 rstate->id = R600_PIPE_STATE_SAMPLER; 946 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 947 r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0, 948 S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) | 949 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) | 950 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) | 951 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) | 952 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) | 953 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) | 954 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) | 955 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) | 956 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0); 957 r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0, 958 S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) | 959 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) | 960 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0); 961 r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0); 962 if (uc.ui) { 963 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0); 964 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0); 965 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0); 966 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0); 967 } 968 return rstate; 969} 970 971static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx, 972 struct pipe_resource *texture, 973 const struct pipe_sampler_view *state) 974{ 975 struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view); 976 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture; 977 unsigned format, endian; 978 uint32_t word4 = 0, yuv_format = 0, pitch = 0; 979 unsigned char swizzle[4], array_mode = 0, tile_type = 0; 980 unsigned width, height, depth, offset_level, last_level; 981 982 if (view == NULL) 983 return NULL; 984 985 /* initialize base object */ 986 view->base = *state; 987 view->base.texture = NULL; 988 pipe_reference(NULL, &texture->reference); 989 view->base.texture = texture; 990 view->base.reference.count = 1; 991 view->base.context = ctx; 992 993 swizzle[0] = state->swizzle_r; 994 swizzle[1] = state->swizzle_g; 995 swizzle[2] = state->swizzle_b; 996 swizzle[3] = state->swizzle_a; 997 998 format = r600_translate_texformat(ctx->screen, state->format, 999 swizzle, 1000 &word4, &yuv_format); 1001 assert(format != ~0); 1002 if (format == ~0) { 1003 FREE(view); 1004 return NULL; 1005 } 1006 1007 if (tmp->is_depth && !tmp->is_flushing_texture) { 1008 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) { 1009 FREE(view); 1010 return NULL; 1011 } 1012 tmp = tmp->flushed_depth_texture; 1013 } 1014 1015 endian = r600_colorformat_endian_swap(format); 1016 1017 offset_level = state->u.tex.first_level; 1018 last_level = state->u.tex.last_level - offset_level; 1019 width = tmp->surface.level[offset_level].npix_x; 1020 height = tmp->surface.level[offset_level].npix_y; 1021 depth = tmp->surface.level[offset_level].npix_z; 1022 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); 1023 tile_type = tmp->tile_type; 1024 1025 if (texture->target == PIPE_TEXTURE_1D_ARRAY) { 1026 height = 1; 1027 depth = texture->array_size; 1028 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) { 1029 depth = texture->array_size; 1030 } 1031 switch (tmp->surface.level[offset_level].mode) { 1032 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1033 array_mode = V_038000_ARRAY_LINEAR_ALIGNED; 1034 break; 1035 case RADEON_SURF_MODE_1D: 1036 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 1037 break; 1038 case RADEON_SURF_MODE_2D: 1039 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 1040 break; 1041 case RADEON_SURF_MODE_LINEAR: 1042 default: 1043 array_mode = V_038000_ARRAY_LINEAR_GENERAL; 1044 break; 1045 } 1046 1047 view->tex_resource = &tmp->resource; 1048 view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target)) | 1049 S_038000_TILE_MODE(array_mode) | 1050 S_038000_TILE_TYPE(tile_type) | 1051 S_038000_PITCH((pitch / 8) - 1) | 1052 S_038000_TEX_WIDTH(width - 1)); 1053 view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) | 1054 S_038004_TEX_DEPTH(depth - 1) | 1055 S_038004_DATA_FORMAT(format)); 1056 view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8; 1057 if (offset_level >= tmp->surface.last_level) { 1058 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8; 1059 } else { 1060 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8; 1061 } 1062 view->tex_resource_words[4] = (word4 | 1063 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) | 1064 S_038010_REQUEST_SIZE(1) | 1065 S_038010_ENDIAN_SWAP(endian) | 1066 S_038010_BASE_LEVEL(0)); 1067 view->tex_resource_words[5] = (S_038014_LAST_LEVEL(last_level) | 1068 S_038014_BASE_ARRAY(state->u.tex.first_layer) | 1069 S_038014_LAST_ARRAY(state->u.tex.last_layer)); 1070 view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) | 1071 S_038018_MAX_ANISO(4 /* max 16 samples */)); 1072 return &view->base; 1073} 1074 1075static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count, 1076 struct pipe_sampler_view **views) 1077{ 1078 struct r600_context *rctx = (struct r600_context *)ctx; 1079 r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views); 1080} 1081 1082static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count, 1083 struct pipe_sampler_view **views) 1084{ 1085 struct r600_context *rctx = (struct r600_context *)ctx; 1086 r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views); 1087} 1088 1089static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable) 1090{ 1091 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1092 if (rstate == NULL) 1093 return; 1094 1095 rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP; 1096 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX, 1097 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) | 1098 S_009508_DISABLE_CUBE_ANISO(1) | 1099 S_009508_SYNC_GRADIENT(1) | 1100 S_009508_SYNC_WALKER(1) | 1101 S_009508_SYNC_ALIGNER(1)); 1102 1103 free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]); 1104 rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate; 1105 r600_context_pipe_state_set(rctx, rstate); 1106} 1107 1108static void r600_bind_samplers(struct r600_context *rctx, 1109 struct r600_textures_info *dst, 1110 unsigned count, void **states) 1111{ 1112 memcpy(dst->samplers, states, sizeof(void*) * count); 1113 dst->n_samplers = count; 1114 dst->samplers_dirty = true; 1115} 1116 1117static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states) 1118{ 1119 struct r600_context *rctx = (struct r600_context *)ctx; 1120 r600_bind_samplers(rctx, &rctx->vs_samplers, count, states); 1121} 1122 1123static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states) 1124{ 1125 struct r600_context *rctx = (struct r600_context *)ctx; 1126 r600_bind_samplers(rctx, &rctx->ps_samplers, count, states); 1127} 1128 1129static void r600_update_samplers(struct r600_context *rctx, 1130 struct r600_textures_info *tex, 1131 void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned)) 1132{ 1133 unsigned i; 1134 1135 if (tex->samplers_dirty) { 1136 int seamless = -1; 1137 for (i = 0; i < tex->n_samplers; i++) { 1138 if (!tex->samplers[i]) 1139 continue; 1140 1141 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable 1142 * filtering between layers. 1143 * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */ 1144 if (tex->views.views[i]) { 1145 if (tex->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 1146 tex->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) { 1147 tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1); 1148 tex->is_array_sampler[i] = true; 1149 } else { 1150 tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE; 1151 tex->is_array_sampler[i] = false; 1152 } 1153 } 1154 1155 set_sampler(rctx, &tex->samplers[i]->rstate, i); 1156 1157 if (tex->samplers[i]) 1158 seamless = tex->samplers[i]->seamless_cube_map; 1159 } 1160 1161 if (seamless != -1) 1162 r600_set_seamless_cubemap(rctx, seamless); 1163 1164 tex->samplers_dirty = false; 1165 } 1166} 1167 1168void r600_update_sampler_states(struct r600_context *rctx) 1169{ 1170 r600_update_samplers(rctx, &rctx->vs_samplers, 1171 r600_context_pipe_state_set_vs_sampler); 1172 r600_update_samplers(rctx, &rctx->ps_samplers, 1173 r600_context_pipe_state_set_ps_sampler); 1174} 1175 1176static void r600_set_clip_state(struct pipe_context *ctx, 1177 const struct pipe_clip_state *state) 1178{ 1179 struct r600_context *rctx = (struct r600_context *)ctx; 1180 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1181 struct pipe_constant_buffer cb; 1182 1183 if (rstate == NULL) 1184 return; 1185 1186 rctx->clip = *state; 1187 rstate->id = R600_PIPE_STATE_CLIP; 1188 for (int i = 0; i < 6; i++) { 1189 r600_pipe_state_add_reg(rstate, 1190 R_028E20_PA_CL_UCP0_X + i * 16, 1191 fui(state->ucp[i][0])); 1192 r600_pipe_state_add_reg(rstate, 1193 R_028E24_PA_CL_UCP0_Y + i * 16, 1194 fui(state->ucp[i][1]) ); 1195 r600_pipe_state_add_reg(rstate, 1196 R_028E28_PA_CL_UCP0_Z + i * 16, 1197 fui(state->ucp[i][2])); 1198 r600_pipe_state_add_reg(rstate, 1199 R_028E2C_PA_CL_UCP0_W + i * 16, 1200 fui(state->ucp[i][3])); 1201 } 1202 1203 free(rctx->states[R600_PIPE_STATE_CLIP]); 1204 rctx->states[R600_PIPE_STATE_CLIP] = rstate; 1205 r600_context_pipe_state_set(rctx, rstate); 1206 1207 cb.buffer = NULL; 1208 cb.user_buffer = state->ucp; 1209 cb.buffer_offset = 0; 1210 cb.buffer_size = 4*4*8; 1211 r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb); 1212 pipe_resource_reference(&cb.buffer, NULL); 1213} 1214 1215static void r600_set_polygon_stipple(struct pipe_context *ctx, 1216 const struct pipe_poly_stipple *state) 1217{ 1218} 1219 1220static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 1221{ 1222} 1223 1224void r600_set_scissor_state(struct r600_context *rctx, 1225 const struct pipe_scissor_state *state) 1226{ 1227 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1228 uint32_t tl, br; 1229 1230 if (rstate == NULL) 1231 return; 1232 1233 rstate->id = R600_PIPE_STATE_SCISSOR; 1234 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1); 1235 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy); 1236 r600_pipe_state_add_reg(rstate, 1237 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl); 1238 r600_pipe_state_add_reg(rstate, 1239 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br); 1240 1241 free(rctx->states[R600_PIPE_STATE_SCISSOR]); 1242 rctx->states[R600_PIPE_STATE_SCISSOR] = rstate; 1243 r600_context_pipe_state_set(rctx, rstate); 1244} 1245 1246static void r600_pipe_set_scissor_state(struct pipe_context *ctx, 1247 const struct pipe_scissor_state *state) 1248{ 1249 struct r600_context *rctx = (struct r600_context *)ctx; 1250 1251 if (rctx->chip_class == R600) { 1252 rctx->scissor_state = *state; 1253 1254 if (!rctx->scissor_enable) 1255 return; 1256 } 1257 1258 r600_set_scissor_state(rctx, state); 1259} 1260 1261static void r600_set_viewport_state(struct pipe_context *ctx, 1262 const struct pipe_viewport_state *state) 1263{ 1264 struct r600_context *rctx = (struct r600_context *)ctx; 1265 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1266 1267 if (rstate == NULL) 1268 return; 1269 1270 rctx->viewport = *state; 1271 rstate->id = R600_PIPE_STATE_VIEWPORT; 1272 r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0])); 1273 r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1])); 1274 r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2])); 1275 r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0])); 1276 r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1])); 1277 r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2])); 1278 1279 free(rctx->states[R600_PIPE_STATE_VIEWPORT]); 1280 rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate; 1281 r600_context_pipe_state_set(rctx, rstate); 1282} 1283 1284static void r600_init_color_surface(struct r600_context *rctx, 1285 struct r600_surface *surf) 1286{ 1287 struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture; 1288 unsigned level = surf->base.u.tex.level; 1289 unsigned pitch, slice; 1290 unsigned color_info; 1291 unsigned format, swap, ntype, endian; 1292 unsigned offset; 1293 const struct util_format_description *desc; 1294 int i; 1295 bool blend_bypass = 0, blend_clamp = 1; 1296 1297 if (rtex->is_depth && !rtex->is_flushing_texture) { 1298 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL); 1299 rtex = rtex->flushed_depth_texture; 1300 assert(rtex); 1301 } 1302 1303 offset = rtex->surface.level[level].offset; 1304 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1305 offset += rtex->surface.level[level].slice_size * 1306 surf->base.u.tex.first_layer; 1307 } 1308 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1309 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1310 if (slice) { 1311 slice = slice - 1; 1312 } 1313 color_info = 0; 1314 switch (rtex->surface.level[level].mode) { 1315 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1316 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED); 1317 break; 1318 case RADEON_SURF_MODE_1D: 1319 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1); 1320 break; 1321 case RADEON_SURF_MODE_2D: 1322 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1); 1323 break; 1324 case RADEON_SURF_MODE_LINEAR: 1325 default: 1326 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL); 1327 break; 1328 } 1329 1330 desc = util_format_description(surf->base.format); 1331 1332 for (i = 0; i < 4; i++) { 1333 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1334 break; 1335 } 1336 } 1337 1338 ntype = V_0280A0_NUMBER_UNORM; 1339 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) 1340 ntype = V_0280A0_NUMBER_SRGB; 1341 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1342 if (desc->channel[i].normalized) 1343 ntype = V_0280A0_NUMBER_SNORM; 1344 else if (desc->channel[i].pure_integer) 1345 ntype = V_0280A0_NUMBER_SINT; 1346 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) { 1347 if (desc->channel[i].normalized) 1348 ntype = V_0280A0_NUMBER_UNORM; 1349 else if (desc->channel[i].pure_integer) 1350 ntype = V_0280A0_NUMBER_UINT; 1351 } 1352 1353 format = r600_translate_colorformat(surf->base.format); 1354 assert(format != ~0); 1355 1356 swap = r600_translate_colorswap(surf->base.format); 1357 assert(swap != ~0); 1358 1359 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) { 1360 endian = ENDIAN_NONE; 1361 } else { 1362 endian = r600_colorformat_endian_swap(format); 1363 } 1364 1365 /* set blend bypass according to docs if SINT/UINT or 1366 8/24 COLOR variants */ 1367 if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT || 1368 format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 || 1369 format == V_0280A0_COLOR_X24_8_32_FLOAT) { 1370 blend_clamp = 0; 1371 blend_bypass = 1; 1372 } 1373 1374 surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT; 1375 1376 color_info |= S_0280A0_FORMAT(format) | 1377 S_0280A0_COMP_SWAP(swap) | 1378 S_0280A0_BLEND_BYPASS(blend_bypass) | 1379 S_0280A0_BLEND_CLAMP(blend_clamp) | 1380 S_0280A0_NUMBER_TYPE(ntype) | 1381 S_0280A0_ENDIAN(endian); 1382 1383 /* EXPORT_NORM is an optimzation that can be enabled for better 1384 * performance in certain cases 1385 */ 1386 if (rctx->chip_class == R600) { 1387 /* EXPORT_NORM can be enabled if: 1388 * - 11-bit or smaller UNORM/SNORM/SRGB 1389 * - BLEND_CLAMP is enabled 1390 * - BLEND_FLOAT32 is disabled 1391 */ 1392 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1393 (desc->channel[i].size < 12 && 1394 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1395 ntype != V_0280A0_NUMBER_UINT && 1396 ntype != V_0280A0_NUMBER_SINT) && 1397 G_0280A0_BLEND_CLAMP(color_info) && 1398 !G_0280A0_BLEND_FLOAT32(color_info)) { 1399 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1400 surf->export_16bpc = true; 1401 } 1402 } else { 1403 /* EXPORT_NORM can be enabled if: 1404 * - 11-bit or smaller UNORM/SNORM/SRGB 1405 * - 16-bit or smaller FLOAT 1406 */ 1407 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS && 1408 ((desc->channel[i].size < 12 && 1409 desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT && 1410 ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) || 1411 (desc->channel[i].size < 17 && 1412 desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) { 1413 color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM); 1414 surf->export_16bpc = true; 1415 } 1416 } 1417 1418 surf->cb_color_base = offset >> 8; 1419 surf->cb_color_info = color_info; 1420 surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) | 1421 S_028060_SLICE_TILE_MAX(slice); 1422 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) { 1423 surf->cb_color_view = 0; 1424 } else { 1425 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) | 1426 S_028080_SLICE_MAX(surf->base.u.tex.last_layer); 1427 } 1428 1429 surf->color_initialized = true; 1430} 1431 1432static void r600_init_depth_surface(struct r600_context *rctx, 1433 struct r600_surface *surf) 1434{ 1435 struct r600_resource_texture *rtex = (struct r600_resource_texture*)surf->base.texture; 1436 unsigned level, pitch, slice, format, offset, array_mode; 1437 1438 level = surf->base.u.tex.level; 1439 offset = rtex->surface.level[level].offset; 1440 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1441 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1442 if (slice) { 1443 slice = slice - 1; 1444 } 1445 switch (rtex->surface.level[level].mode) { 1446 case RADEON_SURF_MODE_2D: 1447 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 1448 break; 1449 case RADEON_SURF_MODE_1D: 1450 case RADEON_SURF_MODE_LINEAR_ALIGNED: 1451 case RADEON_SURF_MODE_LINEAR: 1452 default: 1453 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 1454 break; 1455 } 1456 1457 format = r600_translate_dbformat(surf->base.format); 1458 assert(format != ~0); 1459 1460 surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format); 1461 surf->db_depth_base = offset >> 8; 1462 surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) | 1463 S_028004_SLICE_MAX(surf->base.u.tex.last_layer); 1464 surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice); 1465 surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1; 1466 1467 surf->depth_initialized = true; 1468} 1469 1470static void r600_set_framebuffer_state(struct pipe_context *ctx, 1471 const struct pipe_framebuffer_state *state) 1472{ 1473 struct r600_context *rctx = (struct r600_context *)ctx; 1474 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 1475 struct r600_surface *surf; 1476 struct r600_resource *res; 1477 uint32_t tl, br, i; 1478 1479 if (rstate == NULL) 1480 return; 1481 1482 r600_flush_framebuffer(rctx, false); 1483 1484 /* unreference old buffer and reference new one */ 1485 rstate->id = R600_PIPE_STATE_FRAMEBUFFER; 1486 1487 util_copy_framebuffer_state(&rctx->framebuffer, state); 1488 1489 /* build states */ 1490 rctx->export_16bpc = true; 1491 rctx->nr_cbufs = state->nr_cbufs; 1492 1493 for (i = 0; i < state->nr_cbufs; i++) { 1494 surf = (struct r600_surface*)state->cbufs[i]; 1495 res = (struct r600_resource*)surf->base.texture; 1496 1497 if (!surf->color_initialized) { 1498 r600_init_color_surface(rctx, surf); 1499 } 1500 1501 if (!surf->export_16bpc) { 1502 rctx->export_16bpc = false; 1503 } 1504 1505 r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4, 1506 surf->cb_color_base, res, RADEON_USAGE_READWRITE); 1507 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 1508 surf->cb_color_info, res, RADEON_USAGE_READWRITE); 1509 r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4, 1510 surf->cb_color_size); 1511 r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4, 1512 surf->cb_color_view); 1513 r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4, 1514 surf->cb_color_frag, res, RADEON_USAGE_READWRITE); 1515 r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4, 1516 surf->cb_color_tile, res, RADEON_USAGE_READWRITE); 1517 } 1518 /* set CB_COLOR1_INFO for possible dual-src blending */ 1519 if (i == 1) { 1520 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4, 1521 surf->cb_color_info, res, RADEON_USAGE_READWRITE); 1522 i++; 1523 } 1524 1525 /* Update alpha-test state dependencies. 1526 * Alpha-test is done on the first colorbuffer only. */ 1527 if (state->nr_cbufs) { 1528 surf = (struct r600_surface*)state->cbufs[0]; 1529 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) { 1530 rctx->alphatest_state.bypass = surf->alphatest_bypass; 1531 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 1532 } 1533 } 1534 1535 if (state->zsbuf) { 1536 surf = (struct r600_surface*)state->zsbuf; 1537 res = (struct r600_resource*)surf->base.texture; 1538 1539 if (!surf->depth_initialized) { 1540 r600_init_depth_surface(rctx, surf); 1541 } 1542 1543 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base, 1544 res, RADEON_USAGE_READWRITE); 1545 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size); 1546 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view); 1547 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info, 1548 res, RADEON_USAGE_READWRITE); 1549 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit); 1550 } 1551 1552 tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1); 1553 br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height); 1554 1555 r600_pipe_state_add_reg(rstate, 1556 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl); 1557 r600_pipe_state_add_reg(rstate, 1558 R_028208_PA_SC_WINDOW_SCISSOR_BR, br); 1559 1560 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This 1561 * will assure that the alpha-test will work even if there is 1562 * no colorbuffer bound. */ 1563 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1564 (1ull << MAX2(state->nr_cbufs, 1)) - 1); 1565 1566 if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) { 1567 rctx->alphatest_state.bypass = false; 1568 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 1569 } 1570 1571 free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]); 1572 rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate; 1573 r600_context_pipe_state_set(rctx, rstate); 1574 1575 if (state->zsbuf) { 1576 r600_polygon_offset_update(rctx); 1577 } 1578 1579 if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) { 1580 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs; 1581 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 1582 } 1583} 1584 1585static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom) 1586{ 1587 struct radeon_winsys_cs *cs = rctx->cs; 1588 struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom; 1589 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1; 1590 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1; 1591 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1; 1592 1593 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2); 1594 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */ 1595 r600_write_value(cs, (a->dual_src_blend ? ps_colormask : 0) | fb_colormask); /* R_02823C_CB_SHADER_MASK */ 1596 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, 1597 a->cb_color_control | 1598 S_028808_MULTIWRITE_ENABLE(multiwrite)); 1599} 1600 1601static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom) 1602{ 1603 struct radeon_winsys_cs *cs = rctx->cs; 1604 struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom; 1605 unsigned db_render_control = 0; 1606 unsigned db_render_override = 1607 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) | 1608 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) | 1609 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE); 1610 1611 if (a->occlusion_query_enabled) { 1612 if (rctx->chip_class >= R700) { 1613 db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1); 1614 } 1615 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1); 1616 } 1617 if (a->flush_depthstencil_through_cb) { 1618 assert(a->copy_depth || a->copy_stencil); 1619 1620 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) | 1621 S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) | 1622 S_028D0C_COPY_CENTROID(1); 1623 } 1624 1625 r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2); 1626 r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */ 1627 r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */ 1628} 1629 1630static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom) 1631{ 1632 struct radeon_winsys_cs *cs = rctx->cs; 1633 uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask; 1634 1635 while (dirty_mask) { 1636 struct pipe_vertex_buffer *vb; 1637 struct r600_resource *rbuffer; 1638 unsigned offset; 1639 unsigned buffer_index = u_bit_scan(&dirty_mask); 1640 1641 vb = &rctx->vertex_buffer_state.vb[buffer_index]; 1642 rbuffer = (struct r600_resource*)vb->buffer; 1643 assert(rbuffer); 1644 1645 offset = vb->buffer_offset; 1646 1647 /* fetch resources start at index 320 */ 1648 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1649 r600_write_value(cs, (320 + buffer_index) * 7); 1650 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */ 1651 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */ 1652 r600_write_value(cs, /* RESOURCEi_WORD2 */ 1653 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 1654 S_038008_STRIDE(vb->stride)); 1655 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */ 1656 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */ 1657 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */ 1658 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */ 1659 1660 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1661 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ)); 1662 } 1663} 1664 1665static void r600_emit_constant_buffers(struct r600_context *rctx, 1666 struct r600_constbuf_state *state, 1667 unsigned buffer_id_base, 1668 unsigned reg_alu_constbuf_size, 1669 unsigned reg_alu_const_cache) 1670{ 1671 struct radeon_winsys_cs *cs = rctx->cs; 1672 uint32_t dirty_mask = state->dirty_mask; 1673 1674 while (dirty_mask) { 1675 struct pipe_constant_buffer *cb; 1676 struct r600_resource *rbuffer; 1677 unsigned offset; 1678 unsigned buffer_index = ffs(dirty_mask) - 1; 1679 1680 cb = &state->cb[buffer_index]; 1681 rbuffer = (struct r600_resource*)cb->buffer; 1682 assert(rbuffer); 1683 1684 offset = cb->buffer_offset; 1685 1686 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4, 1687 ALIGN_DIVUP(cb->buffer_size >> 4, 16)); 1688 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8); 1689 1690 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1691 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ)); 1692 1693 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1694 r600_write_value(cs, (buffer_id_base + buffer_index) * 7); 1695 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */ 1696 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */ 1697 r600_write_value(cs, /* RESOURCEi_WORD2 */ 1698 S_038008_ENDIAN_SWAP(r600_endian_swap(32)) | 1699 S_038008_STRIDE(16)); 1700 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */ 1701 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */ 1702 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */ 1703 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */ 1704 1705 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1706 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ)); 1707 1708 dirty_mask &= ~(1 << buffer_index); 1709 } 1710 state->dirty_mask = 0; 1711} 1712 1713static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 1714{ 1715 r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160, 1716 R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 1717 R_028980_ALU_CONST_CACHE_VS_0); 1718} 1719 1720static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom) 1721{ 1722 r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0, 1723 R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 1724 R_028940_ALU_CONST_CACHE_PS_0); 1725} 1726 1727static void r600_emit_sampler_views(struct r600_context *rctx, 1728 struct r600_samplerview_state *state, 1729 unsigned resource_id_base) 1730{ 1731 struct radeon_winsys_cs *cs = rctx->cs; 1732 uint32_t dirty_mask = state->dirty_mask; 1733 1734 while (dirty_mask) { 1735 struct r600_pipe_sampler_view *rview; 1736 unsigned resource_index = u_bit_scan(&dirty_mask); 1737 unsigned reloc; 1738 1739 rview = state->views[resource_index]; 1740 assert(rview); 1741 1742 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0)); 1743 r600_write_value(cs, (resource_id_base + resource_index) * 7); 1744 r600_write_array(cs, 7, rview->tex_resource_words); 1745 1746 /* XXX The kernel needs two relocations. This is stupid. */ 1747 reloc = r600_context_bo_reloc(rctx, rview->tex_resource, 1748 RADEON_USAGE_READ); 1749 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1750 r600_write_value(cs, reloc); 1751 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0)); 1752 r600_write_value(cs, reloc); 1753 } 1754 state->dirty_mask = 0; 1755} 1756 1757static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 1758{ 1759 r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS); 1760} 1761 1762static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom) 1763{ 1764 r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS); 1765} 1766 1767void r600_init_state_functions(struct r600_context *rctx) 1768{ 1769 r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0); 1770 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 1771 r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0); 1772 r600_atom_dirty(rctx, &rctx->db_misc_state.atom); 1773 r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0); 1774 r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0); 1775 r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0); 1776 r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0); 1777 r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0); 1778 1779 rctx->context.create_blend_state = r600_create_blend_state; 1780 rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state; 1781 rctx->context.create_fs_state = r600_create_shader_state_ps; 1782 rctx->context.create_rasterizer_state = r600_create_rs_state; 1783 rctx->context.create_sampler_state = r600_create_sampler_state; 1784 rctx->context.create_sampler_view = r600_create_sampler_view; 1785 rctx->context.create_vertex_elements_state = r600_create_vertex_elements; 1786 rctx->context.create_vs_state = r600_create_shader_state_vs; 1787 rctx->context.bind_blend_state = r600_bind_blend_state; 1788 rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state; 1789 rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers; 1790 rctx->context.bind_fs_state = r600_bind_ps_shader; 1791 rctx->context.bind_rasterizer_state = r600_bind_rs_state; 1792 rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements; 1793 rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers; 1794 rctx->context.bind_vs_state = r600_bind_vs_shader; 1795 rctx->context.delete_blend_state = r600_delete_state; 1796 rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; 1797 rctx->context.delete_fs_state = r600_delete_ps_shader; 1798 rctx->context.delete_rasterizer_state = r600_delete_rs_state; 1799 rctx->context.delete_sampler_state = r600_delete_state; 1800 rctx->context.delete_vertex_elements_state = r600_delete_vertex_element; 1801 rctx->context.delete_vs_state = r600_delete_vs_shader; 1802 rctx->context.set_blend_color = r600_set_blend_color; 1803 rctx->context.set_clip_state = r600_set_clip_state; 1804 rctx->context.set_constant_buffer = r600_set_constant_buffer; 1805 rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views; 1806 rctx->context.set_framebuffer_state = r600_set_framebuffer_state; 1807 rctx->context.set_polygon_stipple = r600_set_polygon_stipple; 1808 rctx->context.set_sample_mask = r600_set_sample_mask; 1809 rctx->context.set_scissor_state = r600_pipe_set_scissor_state; 1810 rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref; 1811 rctx->context.set_vertex_buffers = r600_set_vertex_buffers; 1812 rctx->context.set_index_buffer = r600_set_index_buffer; 1813 rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views; 1814 rctx->context.set_viewport_state = r600_set_viewport_state; 1815 rctx->context.sampler_view_destroy = r600_sampler_view_destroy; 1816 rctx->context.texture_barrier = r600_texture_barrier; 1817 rctx->context.create_stream_output_target = r600_create_so_target; 1818 rctx->context.stream_output_target_destroy = r600_so_target_destroy; 1819 rctx->context.set_stream_output_targets = r600_set_so_targets; 1820} 1821 1822/* Adjust GPR allocation on R6xx/R7xx */ 1823void r600_adjust_gprs(struct r600_context *rctx) 1824{ 1825 struct r600_pipe_state rstate; 1826 unsigned num_ps_gprs = rctx->default_ps_gprs; 1827 unsigned num_vs_gprs = rctx->default_vs_gprs; 1828 unsigned tmp; 1829 int diff; 1830 1831 /* XXX: Following call moved from r600_bind_[ps|vs]_shader, 1832 * it seems eg+ doesn't need it, r6xx/7xx probably need it only for 1833 * adjusting the GPR allocation? 1834 * Do we need this if we aren't really changing config below? */ 1835 r600_inval_shader_cache(rctx); 1836 1837 if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs) 1838 { 1839 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs; 1840 num_vs_gprs -= diff; 1841 num_ps_gprs += diff; 1842 } 1843 1844 if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs) 1845 { 1846 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs; 1847 num_ps_gprs -= diff; 1848 num_vs_gprs += diff; 1849 } 1850 1851 tmp = 0; 1852 tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs); 1853 tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs); 1854 tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs); 1855 rstate.nregs = 0; 1856 r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp); 1857 1858 r600_context_pipe_state_set(rctx, &rstate); 1859} 1860 1861void r600_init_atom_start_cs(struct r600_context *rctx) 1862{ 1863 int ps_prio; 1864 int vs_prio; 1865 int gs_prio; 1866 int es_prio; 1867 int num_ps_gprs; 1868 int num_vs_gprs; 1869 int num_gs_gprs; 1870 int num_es_gprs; 1871 int num_temp_gprs; 1872 int num_ps_threads; 1873 int num_vs_threads; 1874 int num_gs_threads; 1875 int num_es_threads; 1876 int num_ps_stack_entries; 1877 int num_vs_stack_entries; 1878 int num_gs_stack_entries; 1879 int num_es_stack_entries; 1880 enum radeon_family family; 1881 struct r600_command_buffer *cb = &rctx->start_cs_cmd; 1882 uint32_t tmp; 1883 unsigned i; 1884 1885 r600_init_command_buffer(cb, 256, EMIT_EARLY); 1886 1887 /* R6xx requires this packet at the start of each command buffer */ 1888 if (rctx->chip_class == R600) { 1889 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0)); 1890 r600_store_value(cb, 0); 1891 } 1892 /* All asics require this one */ 1893 r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0)); 1894 r600_store_value(cb, 0x80000000); 1895 r600_store_value(cb, 0x80000000); 1896 1897 family = rctx->family; 1898 ps_prio = 0; 1899 vs_prio = 1; 1900 gs_prio = 2; 1901 es_prio = 3; 1902 switch (family) { 1903 case CHIP_R600: 1904 num_ps_gprs = 192; 1905 num_vs_gprs = 56; 1906 num_temp_gprs = 4; 1907 num_gs_gprs = 0; 1908 num_es_gprs = 0; 1909 num_ps_threads = 136; 1910 num_vs_threads = 48; 1911 num_gs_threads = 4; 1912 num_es_threads = 4; 1913 num_ps_stack_entries = 128; 1914 num_vs_stack_entries = 128; 1915 num_gs_stack_entries = 0; 1916 num_es_stack_entries = 0; 1917 break; 1918 case CHIP_RV630: 1919 case CHIP_RV635: 1920 num_ps_gprs = 84; 1921 num_vs_gprs = 36; 1922 num_temp_gprs = 4; 1923 num_gs_gprs = 0; 1924 num_es_gprs = 0; 1925 num_ps_threads = 144; 1926 num_vs_threads = 40; 1927 num_gs_threads = 4; 1928 num_es_threads = 4; 1929 num_ps_stack_entries = 40; 1930 num_vs_stack_entries = 40; 1931 num_gs_stack_entries = 32; 1932 num_es_stack_entries = 16; 1933 break; 1934 case CHIP_RV610: 1935 case CHIP_RV620: 1936 case CHIP_RS780: 1937 case CHIP_RS880: 1938 default: 1939 num_ps_gprs = 84; 1940 num_vs_gprs = 36; 1941 num_temp_gprs = 4; 1942 num_gs_gprs = 0; 1943 num_es_gprs = 0; 1944 num_ps_threads = 136; 1945 num_vs_threads = 48; 1946 num_gs_threads = 4; 1947 num_es_threads = 4; 1948 num_ps_stack_entries = 40; 1949 num_vs_stack_entries = 40; 1950 num_gs_stack_entries = 32; 1951 num_es_stack_entries = 16; 1952 break; 1953 case CHIP_RV670: 1954 num_ps_gprs = 144; 1955 num_vs_gprs = 40; 1956 num_temp_gprs = 4; 1957 num_gs_gprs = 0; 1958 num_es_gprs = 0; 1959 num_ps_threads = 136; 1960 num_vs_threads = 48; 1961 num_gs_threads = 4; 1962 num_es_threads = 4; 1963 num_ps_stack_entries = 40; 1964 num_vs_stack_entries = 40; 1965 num_gs_stack_entries = 32; 1966 num_es_stack_entries = 16; 1967 break; 1968 case CHIP_RV770: 1969 num_ps_gprs = 192; 1970 num_vs_gprs = 56; 1971 num_temp_gprs = 4; 1972 num_gs_gprs = 0; 1973 num_es_gprs = 0; 1974 num_ps_threads = 188; 1975 num_vs_threads = 60; 1976 num_gs_threads = 0; 1977 num_es_threads = 0; 1978 num_ps_stack_entries = 256; 1979 num_vs_stack_entries = 256; 1980 num_gs_stack_entries = 0; 1981 num_es_stack_entries = 0; 1982 break; 1983 case CHIP_RV730: 1984 case CHIP_RV740: 1985 num_ps_gprs = 84; 1986 num_vs_gprs = 36; 1987 num_temp_gprs = 4; 1988 num_gs_gprs = 0; 1989 num_es_gprs = 0; 1990 num_ps_threads = 188; 1991 num_vs_threads = 60; 1992 num_gs_threads = 0; 1993 num_es_threads = 0; 1994 num_ps_stack_entries = 128; 1995 num_vs_stack_entries = 128; 1996 num_gs_stack_entries = 0; 1997 num_es_stack_entries = 0; 1998 break; 1999 case CHIP_RV710: 2000 num_ps_gprs = 192; 2001 num_vs_gprs = 56; 2002 num_temp_gprs = 4; 2003 num_gs_gprs = 0; 2004 num_es_gprs = 0; 2005 num_ps_threads = 144; 2006 num_vs_threads = 48; 2007 num_gs_threads = 0; 2008 num_es_threads = 0; 2009 num_ps_stack_entries = 128; 2010 num_vs_stack_entries = 128; 2011 num_gs_stack_entries = 0; 2012 num_es_stack_entries = 0; 2013 break; 2014 } 2015 2016 rctx->default_ps_gprs = num_ps_gprs; 2017 rctx->default_vs_gprs = num_vs_gprs; 2018 rctx->r6xx_num_clause_temp_gprs = num_temp_gprs; 2019 2020 /* SQ_CONFIG */ 2021 tmp = 0; 2022 switch (family) { 2023 case CHIP_RV610: 2024 case CHIP_RV620: 2025 case CHIP_RS780: 2026 case CHIP_RS880: 2027 case CHIP_RV710: 2028 break; 2029 default: 2030 tmp |= S_008C00_VC_ENABLE(1); 2031 break; 2032 } 2033 tmp |= S_008C00_DX9_CONSTS(0); 2034 tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1); 2035 tmp |= S_008C00_PS_PRIO(ps_prio); 2036 tmp |= S_008C00_VS_PRIO(vs_prio); 2037 tmp |= S_008C00_GS_PRIO(gs_prio); 2038 tmp |= S_008C00_ES_PRIO(es_prio); 2039 r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp); 2040 2041 /* SQ_GPR_RESOURCE_MGMT_2 */ 2042 tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs); 2043 tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs); 2044 r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4); 2045 r600_store_value(cb, tmp); 2046 2047 /* SQ_THREAD_RESOURCE_MGMT */ 2048 tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads); 2049 tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads); 2050 tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads); 2051 tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads); 2052 r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */ 2053 2054 /* SQ_STACK_RESOURCE_MGMT_1 */ 2055 tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries); 2056 tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries); 2057 r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */ 2058 2059 /* SQ_STACK_RESOURCE_MGMT_2 */ 2060 tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries); 2061 tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries); 2062 r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */ 2063 2064 r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0); 2065 2066 if (rctx->chip_class >= R700) { 2067 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000); 2068 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0); 2069 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204); 2070 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0); 2071 } else { 2072 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0); 2073 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000); 2074 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204); 2075 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1); 2076 } 2077 r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9); 2078 r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */ 2079 r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */ 2080 r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */ 2081 r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */ 2082 r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */ 2083 r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */ 2084 r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */ 2085 r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */ 2086 r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */ 2087 2088 r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); 2089 r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ 2090 r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ 2091 r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */ 2092 r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */ 2093 r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */ 2094 r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */ 2095 r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */ 2096 r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */ 2097 r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */ 2098 r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */ 2099 r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */ 2100 r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */ 2101 r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */ 2102 2103 r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0); 2104 r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0); 2105 r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0); 2106 2107 r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3); 2108 r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */ 2109 r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */ 2110 r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */ 2111 2112 r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0); 2113 2114 r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2); 2115 r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */ 2116 r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */ 2117 2118 r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0); 2119 2120 r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2); 2121 r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */ 2122 r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */ 2123 2124 r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3); 2125 r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */ 2126 r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */ 2127 r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */ 2128 2129 r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2); 2130 r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */ 2131 r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */ 2132 2133 r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00); 2134 2135 r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0); 2136 r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0); 2137 2138 r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2); 2139 r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */ 2140 r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */ 2141 2142 r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6); 2143 r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */ 2144 r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */ 2145 r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */ 2146 r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */ 2147 r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */ 2148 r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */ 2149 2150 r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2); 2151 r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */ 2152 r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */ 2153 2154 r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F); 2155 2156 r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8); 2157 for (i = 0; i < 8; i++) { 2158 r600_store_value(cb, 0); 2159 } 2160 2161 r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0); 2162 r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF); 2163 2164 if (rctx->chip_class >= R700) { 2165 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA); 2166 } 2167 2168 r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4); 2169 r600_store_value(cb, 0x1000000); /* R_028C30_CB_CLRCMP_CONTROL */ 2170 r600_store_value(cb, 0); /* R_028C34_CB_CLRCMP_SRC */ 2171 r600_store_value(cb, 0xFF); /* R_028C38_CB_CLRCMP_DST */ 2172 r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */ 2173 2174 r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF); 2175 2176 r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2); 2177 r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */ 2178 r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */ 2179 2180 r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2); 2181 r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */ 2182 r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */ 2183 2184 r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2); 2185 r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */ 2186 r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */ 2187 2188 r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0); 2189 r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0); 2190 2191 if (rctx->chip_class == R700 && rctx->screen->has_streamout) 2192 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); 2193 r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0); 2194 if (rctx->screen->has_streamout) { 2195 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0); 2196 } 2197 2198 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF); 2199 r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF); 2200} 2201 2202void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2203{ 2204 struct r600_context *rctx = (struct r600_context *)ctx; 2205 struct r600_pipe_state *rstate = &shader->rstate; 2206 struct r600_shader *rshader = &shader->shader; 2207 unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control; 2208 int pos_index = -1, face_index = -1; 2209 unsigned tmp, sid, ufi = 0; 2210 int need_linear = 0; 2211 unsigned z_export = 0, stencil_export = 0; 2212 2213 rstate->nregs = 0; 2214 2215 for (i = 0; i < rshader->ninput; i++) { 2216 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION) 2217 pos_index = i; 2218 if (rshader->input[i].name == TGSI_SEMANTIC_FACE) 2219 face_index = i; 2220 2221 sid = rshader->input[i].spi_sid; 2222 2223 tmp = S_028644_SEMANTIC(sid); 2224 2225 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION || 2226 rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT || 2227 (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR && 2228 rctx->rasterizer && rctx->rasterizer->flatshade)) 2229 tmp |= S_028644_FLAT_SHADE(1); 2230 2231 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC && 2232 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) { 2233 tmp |= S_028644_PT_SPRITE_TEX(1); 2234 } 2235 2236 if (rshader->input[i].centroid) 2237 tmp |= S_028644_SEL_CENTROID(1); 2238 2239 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) { 2240 need_linear = 1; 2241 tmp |= S_028644_SEL_LINEAR(1); 2242 } 2243 2244 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 2245 tmp); 2246 } 2247 2248 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z); 2249 for (i = 0; i < rshader->noutput; i++) { 2250 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION) 2251 z_export = 1; 2252 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL) 2253 stencil_export = 1; 2254 } 2255 db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export); 2256 db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export); 2257 if (rshader->uses_kill) 2258 db_shader_control |= S_02880C_KILL_ENABLE(1); 2259 2260 exports_ps = 0; 2261 for (i = 0; i < rshader->noutput; i++) { 2262 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION || 2263 rshader->output[i].name == TGSI_SEMANTIC_STENCIL) { 2264 exports_ps |= 1; 2265 } 2266 } 2267 num_cout = rshader->nr_ps_color_exports; 2268 exports_ps |= S_028854_EXPORT_COLORS(num_cout); 2269 if (!exports_ps) { 2270 /* always at least export 1 component per pixel */ 2271 exports_ps = 2; 2272 } 2273 2274 shader->nr_ps_color_outputs = num_cout; 2275 2276 spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) | 2277 S_0286CC_PERSP_GRADIENT_ENA(1)| 2278 S_0286CC_LINEAR_GRADIENT_ENA(need_linear); 2279 spi_input_z = 0; 2280 if (pos_index != -1) { 2281 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) | 2282 S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) | 2283 S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) | 2284 S_0286CC_BARYC_SAMPLE_CNTL(1)); 2285 spi_input_z |= 1; 2286 } 2287 2288 spi_ps_in_control_1 = 0; 2289 if (face_index != -1) { 2290 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) | 2291 S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr); 2292 } 2293 2294 /* HW bug in original R600 */ 2295 if (rctx->family == CHIP_R600) 2296 ufi = 1; 2297 2298 r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0); 2299 r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1); 2300 r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z); 2301 r600_pipe_state_add_reg_bo(rstate, 2302 R_028840_SQ_PGM_START_PS, 2303 0, shader->bo, RADEON_USAGE_READ); 2304 r600_pipe_state_add_reg(rstate, 2305 R_028850_SQ_PGM_RESOURCES_PS, 2306 S_028850_NUM_GPRS(rshader->bc.ngpr) | 2307 S_028850_STACK_SIZE(rshader->bc.nstack) | 2308 S_028850_UNCACHED_FIRST_INST(ufi)); 2309 r600_pipe_state_add_reg(rstate, 2310 R_028854_SQ_PGM_EXPORTS_PS, 2311 exports_ps); 2312 /* only set some bits here, the other bits are set in the dsa state */ 2313 shader->db_shader_control = db_shader_control; 2314 shader->ps_depth_export = z_export | stencil_export; 2315 2316 shader->sprite_coord_enable = rctx->sprite_coord_enable; 2317 if (rctx->rasterizer) 2318 shader->flatshade = rctx->rasterizer->flatshade; 2319} 2320 2321void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader) 2322{ 2323 struct r600_context *rctx = (struct r600_context *)ctx; 2324 struct r600_pipe_state *rstate = &shader->rstate; 2325 struct r600_shader *rshader = &shader->shader; 2326 unsigned spi_vs_out_id[10] = {}; 2327 unsigned i, tmp, nparams = 0; 2328 2329 /* clear previous register */ 2330 rstate->nregs = 0; 2331 2332 for (i = 0; i < rshader->noutput; i++) { 2333 if (rshader->output[i].spi_sid) { 2334 tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8); 2335 spi_vs_out_id[nparams / 4] |= tmp; 2336 nparams++; 2337 } 2338 } 2339 2340 for (i = 0; i < 10; i++) { 2341 r600_pipe_state_add_reg(rstate, 2342 R_028614_SPI_VS_OUT_ID_0 + i * 4, 2343 spi_vs_out_id[i]); 2344 } 2345 2346 /* Certain attributes (position, psize, etc.) don't count as params. 2347 * VS is required to export at least one param and r600_shader_from_tgsi() 2348 * takes care of adding a dummy export. 2349 */ 2350 if (nparams < 1) 2351 nparams = 1; 2352 2353 r600_pipe_state_add_reg(rstate, 2354 R_0286C4_SPI_VS_OUT_CONFIG, 2355 S_0286C4_VS_EXPORT_COUNT(nparams - 1)); 2356 r600_pipe_state_add_reg(rstate, 2357 R_028868_SQ_PGM_RESOURCES_VS, 2358 S_028868_NUM_GPRS(rshader->bc.ngpr) | 2359 S_028868_STACK_SIZE(rshader->bc.nstack)); 2360 r600_pipe_state_add_reg_bo(rstate, 2361 R_028858_SQ_PGM_START_VS, 2362 0, shader->bo, RADEON_USAGE_READ); 2363 2364 shader->pa_cl_vs_out_cntl = 2365 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) | 2366 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) | 2367 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) | 2368 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size); 2369} 2370 2371void r600_fetch_shader(struct pipe_context *ctx, 2372 struct r600_vertex_element *ve) 2373{ 2374 struct r600_pipe_state *rstate; 2375 struct r600_context *rctx = (struct r600_context *)ctx; 2376 2377 rstate = &ve->rstate; 2378 rstate->id = R600_PIPE_STATE_FETCH_SHADER; 2379 rstate->nregs = 0; 2380 r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS, 2381 0, 2382 ve->fetch_shader, RADEON_USAGE_READ); 2383} 2384 2385void *r600_create_db_flush_dsa(struct r600_context *rctx) 2386{ 2387 struct pipe_depth_stencil_alpha_state dsa; 2388 boolean quirk = false; 2389 2390 if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 || 2391 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635) 2392 quirk = true; 2393 2394 memset(&dsa, 0, sizeof(dsa)); 2395 2396 if (quirk) { 2397 dsa.depth.enabled = 1; 2398 dsa.depth.func = PIPE_FUNC_LEQUAL; 2399 dsa.stencil[0].enabled = 1; 2400 dsa.stencil[0].func = PIPE_FUNC_ALWAYS; 2401 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP; 2402 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR; 2403 dsa.stencil[0].writemask = 0xff; 2404 } 2405 2406 return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa); 2407} 2408 2409void r600_update_dual_export_state(struct r600_context * rctx) 2410{ 2411 unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs && 2412 !rctx->ps_shader->current->ps_depth_export; 2413 unsigned db_shader_control = rctx->ps_shader->current->db_shader_control | 2414 S_02880C_DUAL_EXPORT_ENABLE(dual_export); 2415 2416 if (db_shader_control != rctx->db_shader_control) { 2417 struct r600_pipe_state rstate; 2418 2419 rctx->db_shader_control = db_shader_control; 2420 rstate.nregs = 0; 2421 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control); 2422 r600_context_pipe_state_set(rctx, &rstate); 2423 } 2424} 2425