r600_state_common.c revision 8d1a9a984f33d8e45f932a9f47cdd57da617a919
1/* 2 * Copyright 2010 Red Hat Inc. 3 * 2010 Jerome Glisse 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie <airlied@redhat.com> 25 * Jerome Glisse <jglisse@redhat.com> 26 */ 27#include "r600_formats.h" 28#include "r600d.h" 29 30#include "util/u_blitter.h" 31#include "util/u_upload_mgr.h" 32#include "tgsi/tgsi_parse.h" 33#include <byteswap.h> 34 35static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom) 36{ 37 struct radeon_winsys_cs *cs = rctx->cs; 38 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom; 39 40 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS); 41 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw); 42 cs->cdw += cb->atom.num_dw; 43} 44 45void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags) 46{ 47 cb->atom.emit = r600_emit_command_buffer; 48 cb->atom.num_dw = 0; 49 cb->atom.flags = flags; 50 cb->buf = CALLOC(1, 4 * num_dw); 51 cb->max_num_dw = num_dw; 52} 53 54void r600_release_command_buffer(struct r600_command_buffer *cb) 55{ 56 FREE(cb->buf); 57} 58 59static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom) 60{ 61 struct radeon_winsys_cs *cs = rctx->cs; 62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom; 63 64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0); 65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */ 66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */ 67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */ 68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */ 69 70 a->flush_flags = 0; 71} 72 73static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom) 74{ 75 struct radeon_winsys_cs *cs = rctx->cs; 76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0); 78} 79 80void r600_init_atom(struct r600_atom *atom, 81 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 82 unsigned num_dw, enum r600_atom_flags flags) 83{ 84 atom->emit = emit; 85 atom->num_dw = num_dw; 86 atom->flags = flags; 87} 88 89static void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom) 90{ 91 struct radeon_winsys_cs *cs = rctx->cs; 92 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom; 93 unsigned alpha_ref = a->sx_alpha_ref; 94 95 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) { 96 alpha_ref &= ~0x1FFF; 97 } 98 99 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL, 100 a->sx_alpha_test_control | 101 S_028410_ALPHA_TEST_BYPASS(a->bypass)); 102 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref); 103} 104 105void r600_init_common_atoms(struct r600_context *rctx) 106{ 107 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY); 108 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY); 109 r600_init_atom(&rctx->alphatest_state.atom, r600_emit_alphatest_state, 3, 0); 110 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 111} 112 113unsigned r600_get_cb_flush_flags(struct r600_context *rctx) 114{ 115 unsigned flags = 0; 116 117 if (rctx->framebuffer.nr_cbufs) { 118 flags |= S_0085F0_CB_ACTION_ENA(1) | 119 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT); 120 } 121 122 /* Workaround for broken flushing on some R6xx chipsets. */ 123 if (rctx->family == CHIP_RV670 || 124 rctx->family == CHIP_RS780 || 125 rctx->family == CHIP_RS880) { 126 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) | 127 S_0085F0_DEST_BASE_0_ENA(1); 128 } 129 return flags; 130} 131 132void r600_texture_barrier(struct pipe_context *ctx) 133{ 134 struct r600_context *rctx = (struct r600_context *)ctx; 135 136 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx); 137 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom); 138} 139 140static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim) 141{ 142 static const int prim_conv[] = { 143 V_008958_DI_PT_POINTLIST, 144 V_008958_DI_PT_LINELIST, 145 V_008958_DI_PT_LINELOOP, 146 V_008958_DI_PT_LINESTRIP, 147 V_008958_DI_PT_TRILIST, 148 V_008958_DI_PT_TRISTRIP, 149 V_008958_DI_PT_TRIFAN, 150 V_008958_DI_PT_QUADLIST, 151 V_008958_DI_PT_QUADSTRIP, 152 V_008958_DI_PT_POLYGON, 153 -1, 154 -1, 155 -1, 156 -1 157 }; 158 159 *prim = prim_conv[pprim]; 160 if (*prim == -1) { 161 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim); 162 return false; 163 } 164 return true; 165} 166 167/* common state between evergreen and r600 */ 168 169static void r600_bind_blend_state_internal(struct r600_context *rctx, 170 struct r600_pipe_blend *blend) 171{ 172 struct r600_pipe_state *rstate; 173 bool update_cb = false; 174 175 rstate = &blend->rstate; 176 rctx->states[rstate->id] = rstate; 177 r600_context_pipe_state_set(rctx, rstate); 178 179 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) { 180 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask; 181 update_cb = true; 182 } 183 if (rctx->chip_class <= R700 && 184 rctx->cb_misc_state.cb_color_control != blend->cb_color_control) { 185 rctx->cb_misc_state.cb_color_control = blend->cb_color_control; 186 update_cb = true; 187 } 188 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) { 189 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend; 190 update_cb = true; 191 } 192 if (update_cb) { 193 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 194 } 195} 196 197void r600_bind_blend_state(struct pipe_context *ctx, void *state) 198{ 199 struct r600_context *rctx = (struct r600_context *)ctx; 200 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state; 201 202 if (blend == NULL) 203 return; 204 205 rctx->blend = blend; 206 rctx->alpha_to_one = blend->alpha_to_one; 207 rctx->dual_src_blend = blend->dual_src_blend; 208 209 if (!rctx->blend_override) 210 r600_bind_blend_state_internal(rctx, blend); 211} 212 213void r600_set_blend_color(struct pipe_context *ctx, 214 const struct pipe_blend_color *state) 215{ 216 struct r600_context *rctx = (struct r600_context *)ctx; 217 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 218 219 if (rstate == NULL) 220 return; 221 222 rstate->id = R600_PIPE_STATE_BLEND_COLOR; 223 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0])); 224 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1])); 225 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); 226 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); 227 228 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]); 229 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate; 230 r600_context_pipe_state_set(rctx, rstate); 231} 232 233static void r600_set_stencil_ref(struct pipe_context *ctx, 234 const struct r600_stencil_ref *state) 235{ 236 struct r600_context *rctx = (struct r600_context *)ctx; 237 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 238 239 if (rstate == NULL) 240 return; 241 242 rstate->id = R600_PIPE_STATE_STENCIL_REF; 243 r600_pipe_state_add_reg(rstate, 244 R_028430_DB_STENCILREFMASK, 245 S_028430_STENCILREF(state->ref_value[0]) | 246 S_028430_STENCILMASK(state->valuemask[0]) | 247 S_028430_STENCILWRITEMASK(state->writemask[0])); 248 r600_pipe_state_add_reg(rstate, 249 R_028434_DB_STENCILREFMASK_BF, 250 S_028434_STENCILREF_BF(state->ref_value[1]) | 251 S_028434_STENCILMASK_BF(state->valuemask[1]) | 252 S_028434_STENCILWRITEMASK_BF(state->writemask[1])); 253 254 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]); 255 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate; 256 r600_context_pipe_state_set(rctx, rstate); 257} 258 259void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 260 const struct pipe_stencil_ref *state) 261{ 262 struct r600_context *rctx = (struct r600_context *)ctx; 263 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA]; 264 struct r600_stencil_ref ref; 265 266 rctx->stencil_ref = *state; 267 268 if (!dsa) 269 return; 270 271 ref.ref_value[0] = state->ref_value[0]; 272 ref.ref_value[1] = state->ref_value[1]; 273 ref.valuemask[0] = dsa->valuemask[0]; 274 ref.valuemask[1] = dsa->valuemask[1]; 275 ref.writemask[0] = dsa->writemask[0]; 276 ref.writemask[1] = dsa->writemask[1]; 277 278 r600_set_stencil_ref(ctx, &ref); 279} 280 281void r600_bind_dsa_state(struct pipe_context *ctx, void *state) 282{ 283 struct r600_context *rctx = (struct r600_context *)ctx; 284 struct r600_pipe_dsa *dsa = state; 285 struct r600_pipe_state *rstate; 286 struct r600_stencil_ref ref; 287 288 if (state == NULL) 289 return; 290 rstate = &dsa->rstate; 291 rctx->states[rstate->id] = rstate; 292 r600_context_pipe_state_set(rctx, rstate); 293 294 ref.ref_value[0] = rctx->stencil_ref.ref_value[0]; 295 ref.ref_value[1] = rctx->stencil_ref.ref_value[1]; 296 ref.valuemask[0] = dsa->valuemask[0]; 297 ref.valuemask[1] = dsa->valuemask[1]; 298 ref.writemask[0] = dsa->writemask[0]; 299 ref.writemask[1] = dsa->writemask[1]; 300 301 r600_set_stencil_ref(ctx, &ref); 302 303 /* Update alphatest state. */ 304 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control || 305 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) { 306 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control; 307 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref; 308 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 309 } 310} 311 312void r600_set_max_scissor(struct r600_context *rctx) 313{ 314 /* Set a scissor state such that it doesn't do anything. */ 315 struct pipe_scissor_state scissor; 316 scissor.minx = 0; 317 scissor.miny = 0; 318 scissor.maxx = 8192; 319 scissor.maxy = 8192; 320 321 r600_set_scissor_state(rctx, &scissor); 322} 323 324void r600_bind_rs_state(struct pipe_context *ctx, void *state) 325{ 326 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state; 327 struct r600_context *rctx = (struct r600_context *)ctx; 328 329 if (state == NULL) 330 return; 331 332 rctx->sprite_coord_enable = rs->sprite_coord_enable; 333 rctx->two_side = rs->two_side; 334 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; 335 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl; 336 rctx->multisample_enable = rs->multisample_enable; 337 338 rctx->rasterizer = rs; 339 340 rctx->states[rs->rstate.id] = &rs->rstate; 341 r600_context_pipe_state_set(rctx, &rs->rstate); 342 343 if (rctx->chip_class >= EVERGREEN) { 344 evergreen_polygon_offset_update(rctx); 345 } else { 346 r600_polygon_offset_update(rctx); 347 } 348 349 /* Workaround for a missing scissor enable on r600. */ 350 if (rctx->chip_class == R600) { 351 if (rs->scissor_enable != rctx->scissor_enable) { 352 rctx->scissor_enable = rs->scissor_enable; 353 354 if (rs->scissor_enable) { 355 r600_set_scissor_state(rctx, &rctx->scissor_state); 356 } else { 357 r600_set_max_scissor(rctx); 358 } 359 } 360 } 361} 362 363void r600_delete_rs_state(struct pipe_context *ctx, void *state) 364{ 365 struct r600_context *rctx = (struct r600_context *)ctx; 366 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state; 367 368 if (rctx->rasterizer == rs) { 369 rctx->rasterizer = NULL; 370 } 371 if (rctx->states[rs->rstate.id] == &rs->rstate) { 372 rctx->states[rs->rstate.id] = NULL; 373 } 374 free(rs); 375} 376 377void r600_sampler_view_destroy(struct pipe_context *ctx, 378 struct pipe_sampler_view *state) 379{ 380 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; 381 382 pipe_resource_reference(&state->texture, NULL); 383 FREE(resource); 384} 385 386static void r600_bind_samplers(struct pipe_context *pipe, 387 unsigned shader, 388 unsigned start, 389 unsigned count, void **states) 390{ 391 struct r600_context *rctx = (struct r600_context *)pipe; 392 struct r600_textures_info *dst; 393 int seamless_cube_map = -1; 394 unsigned i; 395 396 assert(start == 0); /* XXX fix below */ 397 398 switch (shader) { 399 case PIPE_SHADER_VERTEX: 400 dst = &rctx->vs_samplers; 401 break; 402 case PIPE_SHADER_FRAGMENT: 403 dst = &rctx->ps_samplers; 404 break; 405 default: 406 debug_error("bad shader in r600_bind_samplers()"); 407 return; 408 } 409 410 memcpy(dst->samplers, states, sizeof(void*) * count); 411 dst->n_samplers = count; 412 dst->atom_sampler.num_dw = 0; 413 414 for (i = 0; i < count; i++) { 415 struct r600_pipe_sampler_state *sampler = states[i]; 416 417 if (sampler == NULL) { 418 continue; 419 } 420 if (sampler->border_color_use) { 421 dst->atom_sampler.num_dw += 11; 422 rctx->flags |= R600_PARTIAL_FLUSH; 423 } else { 424 dst->atom_sampler.num_dw += 5; 425 } 426 seamless_cube_map = sampler->seamless_cube_map; 427 } 428 if (rctx->chip_class <= R700 && seamless_cube_map != -1 && seamless_cube_map != rctx->seamless_cube_map.enabled) { 429 /* change in TA_CNTL_AUX need a pipeline flush */ 430 rctx->flags |= R600_PARTIAL_FLUSH; 431 rctx->seamless_cube_map.enabled = seamless_cube_map; 432 r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom); 433 } 434 if (dst->atom_sampler.num_dw) { 435 r600_atom_dirty(rctx, &dst->atom_sampler); 436 } 437} 438 439void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states) 440{ 441 r600_bind_samplers(ctx, PIPE_SHADER_VERTEX, 0, count, states); 442} 443 444void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states) 445{ 446 r600_bind_samplers(ctx, PIPE_SHADER_FRAGMENT, 0, count, states); 447} 448 449void r600_delete_sampler(struct pipe_context *ctx, void *state) 450{ 451 free(state); 452} 453 454void r600_delete_state(struct pipe_context *ctx, void *state) 455{ 456 struct r600_context *rctx = (struct r600_context *)ctx; 457 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state; 458 459 if (rctx->states[rstate->id] == rstate) { 460 rctx->states[rstate->id] = NULL; 461 } 462 for (int i = 0; i < rstate->nregs; i++) { 463 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL); 464 } 465 free(rstate); 466} 467 468void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) 469{ 470 struct r600_context *rctx = (struct r600_context *)ctx; 471 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 472 473 rctx->vertex_elements = v; 474 if (v) { 475 r600_inval_shader_cache(rctx); 476 477 rctx->states[v->rstate.id] = &v->rstate; 478 r600_context_pipe_state_set(rctx, &v->rstate); 479 } 480} 481 482void r600_delete_vertex_element(struct pipe_context *ctx, void *state) 483{ 484 struct r600_context *rctx = (struct r600_context *)ctx; 485 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 486 487 if (rctx->states[v->rstate.id] == &v->rstate) { 488 rctx->states[v->rstate.id] = NULL; 489 } 490 if (rctx->vertex_elements == state) 491 rctx->vertex_elements = NULL; 492 493 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL); 494 FREE(state); 495} 496 497void r600_set_index_buffer(struct pipe_context *ctx, 498 const struct pipe_index_buffer *ib) 499{ 500 struct r600_context *rctx = (struct r600_context *)ctx; 501 502 if (ib) { 503 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); 504 memcpy(&rctx->index_buffer, ib, sizeof(*ib)); 505 } else { 506 pipe_resource_reference(&rctx->index_buffer.buffer, NULL); 507 } 508} 509 510void r600_vertex_buffers_dirty(struct r600_context *rctx) 511{ 512 if (rctx->vertex_buffer_state.dirty_mask) { 513 r600_inval_vertex_cache(rctx); 514 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) * 515 util_bitcount(rctx->vertex_buffer_state.dirty_mask); 516 r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom); 517 } 518} 519 520void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 521 const struct pipe_vertex_buffer *input) 522{ 523 struct r600_context *rctx = (struct r600_context *)ctx; 524 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state; 525 struct pipe_vertex_buffer *vb = state->vb; 526 unsigned i; 527 /* This sets 1-bit for buffers with index >= count. */ 528 uint32_t disable_mask = ~((1ull << count) - 1); 529 /* These are the new buffers set by this function. */ 530 uint32_t new_buffer_mask = 0; 531 532 /* Set buffers with index >= count to NULL. */ 533 uint32_t remaining_buffers_mask = 534 rctx->vertex_buffer_state.enabled_mask & disable_mask; 535 536 while (remaining_buffers_mask) { 537 i = u_bit_scan(&remaining_buffers_mask); 538 pipe_resource_reference(&vb[i].buffer, NULL); 539 } 540 541 /* Set vertex buffers. */ 542 for (i = 0; i < count; i++) { 543 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) { 544 if (input[i].buffer) { 545 vb[i].stride = input[i].stride; 546 vb[i].buffer_offset = input[i].buffer_offset; 547 pipe_resource_reference(&vb[i].buffer, input[i].buffer); 548 new_buffer_mask |= 1 << i; 549 } else { 550 pipe_resource_reference(&vb[i].buffer, NULL); 551 disable_mask |= 1 << i; 552 } 553 } 554 } 555 556 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask; 557 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask; 558 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask; 559 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask; 560 561 r600_vertex_buffers_dirty(rctx); 562} 563 564void r600_sampler_views_dirty(struct r600_context *rctx, 565 struct r600_samplerview_state *state) 566{ 567 if (state->dirty_mask) { 568 r600_inval_texture_cache(rctx); 569 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) * 570 util_bitcount(state->dirty_mask); 571 r600_atom_dirty(rctx, &state->atom); 572 } 573} 574 575void r600_set_sampler_views(struct pipe_context *pipe, 576 unsigned shader, 577 unsigned start, 578 unsigned count, 579 struct pipe_sampler_view **views) 580{ 581 struct r600_context *rctx = (struct r600_context *) pipe; 582 struct r600_textures_info *dst; 583 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views; 584 unsigned i; 585 /* This sets 1-bit for textures with index >= count. */ 586 uint32_t disable_mask = ~((1ull << count) - 1); 587 /* These are the new textures set by this function. */ 588 uint32_t new_mask = 0; 589 590 /* Set textures with index >= count to NULL. */ 591 uint32_t remaining_mask; 592 593 assert(start == 0); /* XXX fix below */ 594 595 switch (shader) { 596 case PIPE_SHADER_VERTEX: 597 dst = &rctx->vs_samplers; 598 break; 599 case PIPE_SHADER_FRAGMENT: 600 dst = &rctx->ps_samplers; 601 break; 602 default: 603 debug_error("bad shader in r600_set_sampler_views()"); 604 return; 605 } 606 607 remaining_mask = dst->views.enabled_mask & disable_mask; 608 609 while (remaining_mask) { 610 i = u_bit_scan(&remaining_mask); 611 assert(dst->views.views[i]); 612 613 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL); 614 } 615 616 for (i = 0; i < count; i++) { 617 if (rviews[i] == dst->views.views[i]) { 618 continue; 619 } 620 621 if (rviews[i]) { 622 struct r600_texture *rtex = 623 (struct r600_texture*)rviews[i]->base.texture; 624 625 if (rtex->is_depth && !rtex->is_flushing_texture) { 626 dst->views.depth_texture_mask |= 1 << i; 627 } else { 628 dst->views.depth_texture_mask &= ~(1 << i); 629 } 630 631 /* Changing from array to non-arrays textures and vice 632 * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */ 633 if (rctx->chip_class <= R700 && 634 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 635 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) { 636 r600_atom_dirty(rctx, &dst->atom_sampler); 637 } 638 639 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]); 640 new_mask |= 1 << i; 641 } else { 642 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL); 643 disable_mask |= 1 << i; 644 } 645 } 646 647 dst->views.enabled_mask &= ~disable_mask; 648 dst->views.dirty_mask &= dst->views.enabled_mask; 649 dst->views.enabled_mask |= new_mask; 650 dst->views.dirty_mask |= new_mask; 651 dst->views.depth_texture_mask &= dst->views.enabled_mask; 652 653 r600_sampler_views_dirty(rctx, &dst->views); 654} 655 656void *r600_create_vertex_elements(struct pipe_context *ctx, 657 unsigned count, 658 const struct pipe_vertex_element *elements) 659{ 660 struct r600_context *rctx = (struct r600_context *)ctx; 661 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element); 662 663 assert(count < 32); 664 if (!v) 665 return NULL; 666 667 v->count = count; 668 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 669 670 if (r600_vertex_elements_build_fetch_shader(rctx, v)) { 671 FREE(v); 672 return NULL; 673 } 674 675 return v; 676} 677 678/* Compute the key for the hw shader variant */ 679static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx, 680 struct r600_pipe_shader_selector * sel) 681{ 682 struct r600_context *rctx = (struct r600_context *)ctx; 683 unsigned key; 684 685 if (sel->type == PIPE_SHADER_FRAGMENT) { 686 key = rctx->two_side | 687 ((rctx->alpha_to_one && rctx->multisample_enable && !rctx->cb0_is_integer) << 1) | 688 (MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 2); 689 } else 690 key = 0; 691 692 return key; 693} 694 695/* Select the hw shader variant depending on the current state. 696 * (*dirty) is set to 1 if current variant was changed */ 697static int r600_shader_select(struct pipe_context *ctx, 698 struct r600_pipe_shader_selector* sel, 699 unsigned *dirty) 700{ 701 unsigned key; 702 struct r600_context *rctx = (struct r600_context *)ctx; 703 struct r600_pipe_shader * shader = NULL; 704 int r; 705 706 key = r600_shader_selector_key(ctx, sel); 707 708 /* Check if we don't need to change anything. 709 * This path is also used for most shaders that don't need multiple 710 * variants, it will cost just a computation of the key and this 711 * test. */ 712 if (likely(sel->current && sel->current->key == key)) { 713 return 0; 714 } 715 716 /* lookup if we have other variants in the list */ 717 if (sel->num_shaders > 1) { 718 struct r600_pipe_shader *p = sel->current, *c = p->next_variant; 719 720 while (c && c->key != key) { 721 p = c; 722 c = c->next_variant; 723 } 724 725 if (c) { 726 p->next_variant = c->next_variant; 727 shader = c; 728 } 729 } 730 731 if (unlikely(!shader)) { 732 shader = CALLOC(1, sizeof(struct r600_pipe_shader)); 733 shader->selector = sel; 734 735 r = r600_pipe_shader_create(ctx, shader); 736 if (unlikely(r)) { 737 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n", 738 sel->type, key, r); 739 sel->current = NULL; 740 return r; 741 } 742 743 /* We don't know the value of nr_ps_max_color_exports until we built 744 * at least one variant, so we may need to recompute the key after 745 * building first variant. */ 746 if (sel->type == PIPE_SHADER_FRAGMENT && 747 sel->num_shaders == 0) { 748 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports; 749 key = r600_shader_selector_key(ctx, sel); 750 } 751 752 shader->key = key; 753 sel->num_shaders++; 754 } 755 756 if (dirty) 757 *dirty = 1; 758 759 shader->next_variant = sel->current; 760 sel->current = shader; 761 762 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) { 763 r600_adjust_gprs(rctx); 764 } 765 766 if (rctx->ps_shader && 767 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) { 768 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs; 769 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 770 } 771 return 0; 772} 773 774static void *r600_create_shader_state(struct pipe_context *ctx, 775 const struct pipe_shader_state *state, 776 unsigned pipe_shader_type) 777{ 778 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector); 779 int r; 780 781 sel->type = pipe_shader_type; 782 sel->tokens = tgsi_dup_tokens(state->tokens); 783 sel->so = state->stream_output; 784 785 r = r600_shader_select(ctx, sel, NULL); 786 if (r) 787 return NULL; 788 789 return sel; 790} 791 792void *r600_create_shader_state_ps(struct pipe_context *ctx, 793 const struct pipe_shader_state *state) 794{ 795 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT); 796} 797 798void *r600_create_shader_state_vs(struct pipe_context *ctx, 799 const struct pipe_shader_state *state) 800{ 801 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX); 802} 803 804void r600_bind_ps_shader(struct pipe_context *ctx, void *state) 805{ 806 struct r600_context *rctx = (struct r600_context *)ctx; 807 808 if (!state) 809 state = rctx->dummy_pixel_shader; 810 811 rctx->ps_shader = (struct r600_pipe_shader_selector *)state; 812 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate); 813 814 if (rctx->chip_class <= R700) { 815 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all; 816 817 if (rctx->cb_misc_state.multiwrite != multiwrite) { 818 rctx->cb_misc_state.multiwrite = multiwrite; 819 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 820 } 821 822 if (rctx->vs_shader) 823 r600_adjust_gprs(rctx); 824 } 825 826 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) { 827 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs; 828 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 829 } 830} 831 832void r600_bind_vs_shader(struct pipe_context *ctx, void *state) 833{ 834 struct r600_context *rctx = (struct r600_context *)ctx; 835 836 rctx->vs_shader = (struct r600_pipe_shader_selector *)state; 837 if (state) { 838 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate); 839 840 if (rctx->chip_class < EVERGREEN && rctx->ps_shader) 841 r600_adjust_gprs(rctx); 842 } 843} 844 845static void r600_delete_shader_selector(struct pipe_context *ctx, 846 struct r600_pipe_shader_selector *sel) 847{ 848 struct r600_pipe_shader *p = sel->current, *c; 849 while (p) { 850 c = p->next_variant; 851 r600_pipe_shader_destroy(ctx, p); 852 free(p); 853 p = c; 854 } 855 856 free(sel->tokens); 857 free(sel); 858} 859 860 861void r600_delete_ps_shader(struct pipe_context *ctx, void *state) 862{ 863 struct r600_context *rctx = (struct r600_context *)ctx; 864 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state; 865 866 if (rctx->ps_shader == sel) { 867 rctx->ps_shader = NULL; 868 } 869 870 r600_delete_shader_selector(ctx, sel); 871} 872 873void r600_delete_vs_shader(struct pipe_context *ctx, void *state) 874{ 875 struct r600_context *rctx = (struct r600_context *)ctx; 876 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state; 877 878 if (rctx->vs_shader == sel) { 879 rctx->vs_shader = NULL; 880 } 881 882 r600_delete_shader_selector(ctx, sel); 883} 884 885void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state) 886{ 887 if (state->dirty_mask) { 888 r600_inval_shader_cache(rctx); 889 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20 890 : util_bitcount(state->dirty_mask)*19; 891 r600_atom_dirty(rctx, &state->atom); 892 } 893} 894 895void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 896 struct pipe_constant_buffer *input) 897{ 898 struct r600_context *rctx = (struct r600_context *)ctx; 899 struct r600_constbuf_state *state; 900 struct pipe_constant_buffer *cb; 901 const uint8_t *ptr; 902 903 switch (shader) { 904 case PIPE_SHADER_VERTEX: 905 state = &rctx->vs_constbuf_state; 906 break; 907 case PIPE_SHADER_FRAGMENT: 908 state = &rctx->ps_constbuf_state; 909 break; 910 default: 911 return; 912 } 913 914 /* Note that the state tracker can unbind constant buffers by 915 * passing NULL here. 916 */ 917 if (unlikely(!input)) { 918 state->enabled_mask &= ~(1 << index); 919 state->dirty_mask &= ~(1 << index); 920 pipe_resource_reference(&state->cb[index].buffer, NULL); 921 return; 922 } 923 924 cb = &state->cb[index]; 925 cb->buffer_size = input->buffer_size; 926 927 ptr = input->user_buffer; 928 929 if (ptr) { 930 /* Upload the user buffer. */ 931 if (R600_BIG_ENDIAN) { 932 uint32_t *tmpPtr; 933 unsigned i, size = input->buffer_size; 934 935 if (!(tmpPtr = malloc(size))) { 936 R600_ERR("Failed to allocate BE swap buffer.\n"); 937 return; 938 } 939 940 for (i = 0; i < size / 4; ++i) { 941 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]); 942 } 943 944 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer); 945 free(tmpPtr); 946 } else { 947 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer); 948 } 949 } else { 950 /* Setup the hw buffer. */ 951 cb->buffer_offset = input->buffer_offset; 952 pipe_resource_reference(&cb->buffer, input->buffer); 953 } 954 955 state->enabled_mask |= 1 << index; 956 state->dirty_mask |= 1 << index; 957 r600_constant_buffers_dirty(rctx, state); 958} 959 960struct pipe_stream_output_target * 961r600_create_so_target(struct pipe_context *ctx, 962 struct pipe_resource *buffer, 963 unsigned buffer_offset, 964 unsigned buffer_size) 965{ 966 struct r600_context *rctx = (struct r600_context *)ctx; 967 struct r600_so_target *t; 968 void *ptr; 969 970 t = CALLOC_STRUCT(r600_so_target); 971 if (!t) { 972 return NULL; 973 } 974 975 t->b.reference.count = 1; 976 t->b.context = ctx; 977 pipe_resource_reference(&t->b.buffer, buffer); 978 t->b.buffer_offset = buffer_offset; 979 t->b.buffer_size = buffer_size; 980 981 t->filled_size = (struct r600_resource*) 982 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4); 983 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE); 984 memset(ptr, 0, t->filled_size->buf->size); 985 rctx->ws->buffer_unmap(t->filled_size->cs_buf); 986 987 return &t->b; 988} 989 990void r600_so_target_destroy(struct pipe_context *ctx, 991 struct pipe_stream_output_target *target) 992{ 993 struct r600_so_target *t = (struct r600_so_target*)target; 994 pipe_resource_reference(&t->b.buffer, NULL); 995 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL); 996 FREE(t); 997} 998 999void r600_set_so_targets(struct pipe_context *ctx, 1000 unsigned num_targets, 1001 struct pipe_stream_output_target **targets, 1002 unsigned append_bitmask) 1003{ 1004 struct r600_context *rctx = (struct r600_context *)ctx; 1005 unsigned i; 1006 1007 /* Stop streamout. */ 1008 if (rctx->num_so_targets && !rctx->streamout_start) { 1009 r600_context_streamout_end(rctx); 1010 } 1011 1012 /* Set the new targets. */ 1013 for (i = 0; i < num_targets; i++) { 1014 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]); 1015 } 1016 for (; i < rctx->num_so_targets; i++) { 1017 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL); 1018 } 1019 1020 rctx->num_so_targets = num_targets; 1021 rctx->streamout_start = num_targets != 0; 1022 rctx->streamout_append_bitmask = append_bitmask; 1023} 1024 1025void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 1026{ 1027 struct r600_context *rctx = (struct r600_context*)pipe; 1028 1029 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask) 1030 return; 1031 1032 rctx->sample_mask.sample_mask = sample_mask; 1033 r600_atom_dirty(rctx, &rctx->sample_mask.atom); 1034} 1035 1036static void r600_update_derived_state(struct r600_context *rctx) 1037{ 1038 struct pipe_context * ctx = (struct pipe_context*)rctx; 1039 unsigned ps_dirty = 0, blend_override; 1040 1041 if (!rctx->blitter->running) { 1042 /* Flush depth textures which need to be flushed. */ 1043 if (rctx->vs_samplers.views.depth_texture_mask) { 1044 r600_flush_depth_textures(rctx, &rctx->vs_samplers.views); 1045 } 1046 if (rctx->ps_samplers.views.depth_texture_mask) { 1047 r600_flush_depth_textures(rctx, &rctx->ps_samplers.views); 1048 } 1049 } 1050 1051 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty); 1052 1053 if (rctx->ps_shader && ((rctx->sprite_coord_enable && 1054 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) || 1055 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) { 1056 1057 if (rctx->chip_class >= EVERGREEN) 1058 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current); 1059 else 1060 r600_pipe_shader_ps(ctx, rctx->ps_shader->current); 1061 1062 ps_dirty = 1; 1063 } 1064 1065 if (ps_dirty) 1066 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate); 1067 1068 blend_override = (rctx->dual_src_blend && 1069 rctx->ps_shader->current->nr_ps_color_outputs < 2); 1070 1071 if (blend_override != rctx->blend_override) { 1072 rctx->blend_override = blend_override; 1073 r600_bind_blend_state_internal(rctx, 1074 blend_override ? rctx->no_blend : rctx->blend); 1075 } 1076 1077 if (rctx->chip_class >= EVERGREEN) { 1078 evergreen_update_dual_export_state(rctx); 1079 } else { 1080 r600_update_dual_export_state(rctx); 1081 } 1082} 1083 1084static unsigned r600_conv_prim_to_gs_out(unsigned mode) 1085{ 1086 static const int prim_conv[] = { 1087 V_028A6C_OUTPRIM_TYPE_POINTLIST, 1088 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 1089 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 1090 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 1091 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1092 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1093 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1094 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1095 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1096 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1097 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 1098 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 1099 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1100 V_028A6C_OUTPRIM_TYPE_TRISTRIP 1101 }; 1102 assert(mode < Elements(prim_conv)); 1103 1104 return prim_conv[mode]; 1105} 1106 1107void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) 1108{ 1109 struct r600_context *rctx = (struct r600_context *)ctx; 1110 struct pipe_draw_info info = *dinfo; 1111 struct pipe_index_buffer ib = {}; 1112 unsigned prim, ls_mask = 0; 1113 struct r600_block *dirty_block = NULL, *next_block = NULL; 1114 struct r600_atom *state = NULL, *next_state = NULL; 1115 struct radeon_winsys_cs *cs = rctx->cs; 1116 uint64_t va; 1117 uint8_t *ptr; 1118 1119 if ((!info.count && (info.indexed || !info.count_from_stream_output)) || 1120 !r600_conv_pipe_prim(info.mode, &prim)) { 1121 assert(0); 1122 return; 1123 } 1124 1125 if (!rctx->vs_shader) { 1126 assert(0); 1127 return; 1128 } 1129 1130 r600_update_derived_state(rctx); 1131 1132 /* partial flush triggered by border color change */ 1133 if (rctx->flags & R600_PARTIAL_FLUSH) { 1134 rctx->flags &= ~R600_PARTIAL_FLUSH; 1135 r600_write_value(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); 1136 r600_write_value(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); 1137 } 1138 1139 if (info.indexed) { 1140 /* Initialize the index buffer struct. */ 1141 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer); 1142 ib.user_buffer = rctx->index_buffer.user_buffer; 1143 ib.index_size = rctx->index_buffer.index_size; 1144 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size; 1145 1146 /* Translate or upload, if needed. */ 1147 r600_translate_index_buffer(rctx, &ib, info.count); 1148 1149 ptr = (uint8_t*)ib.user_buffer; 1150 if (!ib.buffer && ptr) { 1151 u_upload_data(rctx->uploader, 0, info.count * ib.index_size, 1152 ptr, &ib.offset, &ib.buffer); 1153 } 1154 } else { 1155 info.index_bias = info.start; 1156 } 1157 1158 if (rctx->vgt.id != R600_PIPE_STATE_VGT) { 1159 rctx->vgt.id = R600_PIPE_STATE_VGT; 1160 rctx->vgt.nregs = 0; 1161 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim); 1162 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0); 1163 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias); 1164 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index); 1165 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart); 1166 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance); 1167 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0); 1168 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0); 1169 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0); 1170 } 1171 1172 rctx->vgt.nregs = 0; 1173 r600_pipe_state_mod_reg(&rctx->vgt, prim); 1174 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode)); 1175 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias); 1176 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index); 1177 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart); 1178 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance); 1179 1180 if (prim == V_008958_DI_PT_LINELIST) 1181 ls_mask = 1; 1182 else if (prim == V_008958_DI_PT_LINESTRIP || 1183 prim == V_008958_DI_PT_LINELOOP) 1184 ls_mask = 2; 1185 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple); 1186 r600_pipe_state_mod_reg(&rctx->vgt, 1187 rctx->vs_shader->current->pa_cl_vs_out_cntl | 1188 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write)); 1189 r600_pipe_state_mod_reg(&rctx->vgt, 1190 rctx->pa_cl_clip_cntl | 1191 (rctx->vs_shader->current->shader.clip_dist_write || 1192 rctx->vs_shader->current->shader.vs_prohibit_ucps ? 1193 0 : rctx->rasterizer->clip_plane_enable & 0x3F)); 1194 1195 r600_context_pipe_state_set(rctx, &rctx->vgt); 1196 1197 /* Enable stream out if needed. */ 1198 if (rctx->streamout_start) { 1199 r600_context_streamout_begin(rctx); 1200 rctx->streamout_start = FALSE; 1201 } 1202 1203 /* Emit states (the function expects that we emit at most 17 dwords here). */ 1204 r600_need_cs_space(rctx, 0, TRUE); 1205 1206 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) { 1207 r600_emit_atom(rctx, state); 1208 } 1209 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) { 1210 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */); 1211 } 1212 rctx->pm4_dirty_cdwords = 0; 1213 1214 /* draw packet */ 1215 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing); 1216 cs->buf[cs->cdw++] = info.instance_count; 1217 if (info.indexed) { 1218 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing); 1219 cs->buf[cs->cdw++] = ib.index_size == 4 ? 1220 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) : 1221 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)); 1222 1223 va = r600_resource_va(ctx->screen, ib.buffer); 1224 va += ib.offset; 1225 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing); 1226 cs->buf[cs->cdw++] = va; 1227 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; 1228 cs->buf[cs->cdw++] = info.count; 1229 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA; 1230 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing); 1231 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ); 1232 } else { 1233 if (info.count_from_stream_output) { 1234 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output; 1235 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size); 1236 1237 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw); 1238 1239 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0); 1240 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG; 1241 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */ 1242 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */ 1243 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */ 1244 cs->buf[cs->cdw++] = 0; /* unused */ 1245 1246 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1247 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ); 1248 } 1249 1250 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing); 1251 cs->buf[cs->cdw++] = info.count; 1252 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX | 1253 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0); 1254 } 1255 1256 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING; 1257 1258 /* Set the depth buffer as dirty. */ 1259 if (rctx->framebuffer.zsbuf) { 1260 struct pipe_surface *surf = rctx->framebuffer.zsbuf; 1261 struct r600_texture *rtex = (struct r600_texture *)surf->texture; 1262 1263 rtex->dirty_db_mask |= 1 << surf->u.tex.level; 1264 } 1265 1266 pipe_resource_reference(&ib.buffer, NULL); 1267} 1268 1269void _r600_pipe_state_add_reg_bo(struct r600_context *ctx, 1270 struct r600_pipe_state *state, 1271 uint32_t offset, uint32_t value, 1272 uint32_t range_id, uint32_t block_id, 1273 struct r600_resource *bo, 1274 enum radeon_bo_usage usage) 1275 1276{ 1277 struct r600_range *range; 1278 struct r600_block *block; 1279 1280 if (bo) assert(usage); 1281 1282 range = &ctx->range[range_id]; 1283 block = range->blocks[block_id]; 1284 state->regs[state->nregs].block = block; 1285 state->regs[state->nregs].id = (offset - block->start_offset) >> 2; 1286 1287 state->regs[state->nregs].value = value; 1288 state->regs[state->nregs].bo = bo; 1289 state->regs[state->nregs].bo_usage = usage; 1290 1291 state->nregs++; 1292 assert(state->nregs < R600_BLOCK_MAX_REG); 1293} 1294 1295void _r600_pipe_state_add_reg(struct r600_context *ctx, 1296 struct r600_pipe_state *state, 1297 uint32_t offset, uint32_t value, 1298 uint32_t range_id, uint32_t block_id) 1299{ 1300 _r600_pipe_state_add_reg_bo(ctx, state, offset, value, 1301 range_id, block_id, NULL, 0); 1302} 1303 1304void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, 1305 uint32_t offset, uint32_t value, 1306 struct r600_resource *bo, 1307 enum radeon_bo_usage usage) 1308{ 1309 if (bo) assert(usage); 1310 1311 state->regs[state->nregs].id = offset; 1312 state->regs[state->nregs].block = NULL; 1313 state->regs[state->nregs].value = value; 1314 state->regs[state->nregs].bo = bo; 1315 state->regs[state->nregs].bo_usage = usage; 1316 1317 state->nregs++; 1318 assert(state->nregs < R600_BLOCK_MAX_REG); 1319} 1320 1321uint32_t r600_translate_stencil_op(int s_op) 1322{ 1323 switch (s_op) { 1324 case PIPE_STENCIL_OP_KEEP: 1325 return V_028800_STENCIL_KEEP; 1326 case PIPE_STENCIL_OP_ZERO: 1327 return V_028800_STENCIL_ZERO; 1328 case PIPE_STENCIL_OP_REPLACE: 1329 return V_028800_STENCIL_REPLACE; 1330 case PIPE_STENCIL_OP_INCR: 1331 return V_028800_STENCIL_INCR; 1332 case PIPE_STENCIL_OP_DECR: 1333 return V_028800_STENCIL_DECR; 1334 case PIPE_STENCIL_OP_INCR_WRAP: 1335 return V_028800_STENCIL_INCR_WRAP; 1336 case PIPE_STENCIL_OP_DECR_WRAP: 1337 return V_028800_STENCIL_DECR_WRAP; 1338 case PIPE_STENCIL_OP_INVERT: 1339 return V_028800_STENCIL_INVERT; 1340 default: 1341 R600_ERR("Unknown stencil op %d", s_op); 1342 assert(0); 1343 break; 1344 } 1345 return 0; 1346} 1347 1348uint32_t r600_translate_fill(uint32_t func) 1349{ 1350 switch(func) { 1351 case PIPE_POLYGON_MODE_FILL: 1352 return 2; 1353 case PIPE_POLYGON_MODE_LINE: 1354 return 1; 1355 case PIPE_POLYGON_MODE_POINT: 1356 return 0; 1357 default: 1358 assert(0); 1359 return 0; 1360 } 1361} 1362 1363unsigned r600_tex_wrap(unsigned wrap) 1364{ 1365 switch (wrap) { 1366 default: 1367 case PIPE_TEX_WRAP_REPEAT: 1368 return V_03C000_SQ_TEX_WRAP; 1369 case PIPE_TEX_WRAP_CLAMP: 1370 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER; 1371 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1372 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL; 1373 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1374 return V_03C000_SQ_TEX_CLAMP_BORDER; 1375 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1376 return V_03C000_SQ_TEX_MIRROR; 1377 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1378 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1379 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1380 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1381 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1382 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER; 1383 } 1384} 1385 1386unsigned r600_tex_filter(unsigned filter) 1387{ 1388 switch (filter) { 1389 default: 1390 case PIPE_TEX_FILTER_NEAREST: 1391 return V_03C000_SQ_TEX_XY_FILTER_POINT; 1392 case PIPE_TEX_FILTER_LINEAR: 1393 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR; 1394 } 1395} 1396 1397unsigned r600_tex_mipfilter(unsigned filter) 1398{ 1399 switch (filter) { 1400 case PIPE_TEX_MIPFILTER_NEAREST: 1401 return V_03C000_SQ_TEX_Z_FILTER_POINT; 1402 case PIPE_TEX_MIPFILTER_LINEAR: 1403 return V_03C000_SQ_TEX_Z_FILTER_LINEAR; 1404 default: 1405 case PIPE_TEX_MIPFILTER_NONE: 1406 return V_03C000_SQ_TEX_Z_FILTER_NONE; 1407 } 1408} 1409 1410unsigned r600_tex_compare(unsigned compare) 1411{ 1412 switch (compare) { 1413 default: 1414 case PIPE_FUNC_NEVER: 1415 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER; 1416 case PIPE_FUNC_LESS: 1417 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS; 1418 case PIPE_FUNC_EQUAL: 1419 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL; 1420 case PIPE_FUNC_LEQUAL: 1421 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1422 case PIPE_FUNC_GREATER: 1423 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER; 1424 case PIPE_FUNC_NOTEQUAL: 1425 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1426 case PIPE_FUNC_GEQUAL: 1427 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1428 case PIPE_FUNC_ALWAYS: 1429 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1430 } 1431} 1432