r600_state_common.c revision a3d9d7ec79d6f7205fab2324e47d8ea185431de0
1/* 2 * Copyright 2010 Red Hat Inc. 3 * 2010 Jerome Glisse 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie <airlied@redhat.com> 25 * Jerome Glisse <jglisse@redhat.com> 26 */ 27#include "r600_formats.h" 28#include "r600d.h" 29 30#include "util/u_blitter.h" 31#include "util/u_upload_mgr.h" 32#include "tgsi/tgsi_parse.h" 33#include <byteswap.h> 34 35static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom) 36{ 37 struct radeon_winsys_cs *cs = rctx->cs; 38 struct r600_command_buffer *cb = (struct r600_command_buffer*)atom; 39 40 assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS); 41 memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw); 42 cs->cdw += cb->atom.num_dw; 43} 44 45void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags) 46{ 47 cb->atom.emit = r600_emit_command_buffer; 48 cb->atom.num_dw = 0; 49 cb->atom.flags = flags; 50 cb->buf = CALLOC(1, 4 * num_dw); 51 cb->max_num_dw = num_dw; 52} 53 54void r600_release_command_buffer(struct r600_command_buffer *cb) 55{ 56 FREE(cb->buf); 57} 58 59static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom) 60{ 61 struct radeon_winsys_cs *cs = rctx->cs; 62 struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom; 63 64 cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0); 65 cs->buf[cs->cdw++] = a->flush_flags; /* CP_COHER_CNTL */ 66 cs->buf[cs->cdw++] = 0xffffffff; /* CP_COHER_SIZE */ 67 cs->buf[cs->cdw++] = 0; /* CP_COHER_BASE */ 68 cs->buf[cs->cdw++] = 0x0000000A; /* POLL_INTERVAL */ 69 70 a->flush_flags = 0; 71} 72 73static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom) 74{ 75 struct radeon_winsys_cs *cs = rctx->cs; 76 cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0); 77 cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0); 78} 79 80void r600_init_atom(struct r600_atom *atom, 81 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 82 unsigned num_dw, enum r600_atom_flags flags) 83{ 84 atom->emit = emit; 85 atom->num_dw = num_dw; 86 atom->flags = flags; 87} 88 89static void r600_emit_alphatest_state(struct r600_context *rctx, struct r600_atom *atom) 90{ 91 struct radeon_winsys_cs *cs = rctx->cs; 92 struct r600_alphatest_state *a = (struct r600_alphatest_state*)atom; 93 unsigned alpha_ref = a->sx_alpha_ref; 94 95 if (rctx->chip_class >= EVERGREEN && a->cb0_export_16bpc) { 96 alpha_ref &= ~0x1FFF; 97 } 98 99 r600_write_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL, 100 a->sx_alpha_test_control | 101 S_028410_ALPHA_TEST_BYPASS(a->bypass)); 102 r600_write_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref); 103} 104 105void r600_init_common_atoms(struct r600_context *rctx) 106{ 107 r600_init_atom(&rctx->surface_sync_cmd.atom, r600_emit_surface_sync, 5, EMIT_EARLY); 108 r600_init_atom(&rctx->r6xx_flush_and_inv_cmd, r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY); 109 r600_init_atom(&rctx->alphatest_state.atom, r600_emit_alphatest_state, 3, 0); 110 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 111} 112 113unsigned r600_get_cb_flush_flags(struct r600_context *rctx) 114{ 115 unsigned flags = 0; 116 117 if (rctx->framebuffer.nr_cbufs) { 118 flags |= S_0085F0_CB_ACTION_ENA(1) | 119 (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT); 120 } 121 122 /* Workaround for broken flushing on some R6xx chipsets. */ 123 if (rctx->family == CHIP_RV670 || 124 rctx->family == CHIP_RS780 || 125 rctx->family == CHIP_RS880) { 126 flags |= S_0085F0_CB1_DEST_BASE_ENA(1) | 127 S_0085F0_DEST_BASE_0_ENA(1); 128 } 129 return flags; 130} 131 132void r600_texture_barrier(struct pipe_context *ctx) 133{ 134 struct r600_context *rctx = (struct r600_context *)ctx; 135 136 rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx); 137 r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom); 138} 139 140static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim) 141{ 142 static const int prim_conv[] = { 143 V_008958_DI_PT_POINTLIST, 144 V_008958_DI_PT_LINELIST, 145 V_008958_DI_PT_LINELOOP, 146 V_008958_DI_PT_LINESTRIP, 147 V_008958_DI_PT_TRILIST, 148 V_008958_DI_PT_TRISTRIP, 149 V_008958_DI_PT_TRIFAN, 150 V_008958_DI_PT_QUADLIST, 151 V_008958_DI_PT_QUADSTRIP, 152 V_008958_DI_PT_POLYGON, 153 -1, 154 -1, 155 -1, 156 -1 157 }; 158 159 *prim = prim_conv[pprim]; 160 if (*prim == -1) { 161 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim); 162 return false; 163 } 164 return true; 165} 166 167/* common state between evergreen and r600 */ 168 169static void r600_bind_blend_state_internal(struct r600_context *rctx, 170 struct r600_pipe_blend *blend) 171{ 172 struct r600_pipe_state *rstate; 173 bool update_cb = false; 174 175 rstate = &blend->rstate; 176 rctx->states[rstate->id] = rstate; 177 r600_context_pipe_state_set(rctx, rstate); 178 179 if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) { 180 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask; 181 update_cb = true; 182 } 183 if (rctx->chip_class <= R700 && 184 rctx->cb_misc_state.cb_color_control != blend->cb_color_control) { 185 rctx->cb_misc_state.cb_color_control = blend->cb_color_control; 186 update_cb = true; 187 } 188 if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) { 189 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend; 190 update_cb = true; 191 } 192 if (update_cb) { 193 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 194 } 195} 196 197void r600_bind_blend_state(struct pipe_context *ctx, void *state) 198{ 199 struct r600_context *rctx = (struct r600_context *)ctx; 200 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state; 201 202 if (blend == NULL) 203 return; 204 205 rctx->blend = blend; 206 rctx->alpha_to_one = blend->alpha_to_one; 207 rctx->dual_src_blend = blend->dual_src_blend; 208 209 if (!rctx->blend_override) 210 r600_bind_blend_state_internal(rctx, blend); 211} 212 213void r600_set_blend_color(struct pipe_context *ctx, 214 const struct pipe_blend_color *state) 215{ 216 struct r600_context *rctx = (struct r600_context *)ctx; 217 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 218 219 if (rstate == NULL) 220 return; 221 222 rstate->id = R600_PIPE_STATE_BLEND_COLOR; 223 r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0])); 224 r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1])); 225 r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2])); 226 r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3])); 227 228 free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]); 229 rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate; 230 r600_context_pipe_state_set(rctx, rstate); 231} 232 233static void r600_set_stencil_ref(struct pipe_context *ctx, 234 const struct r600_stencil_ref *state) 235{ 236 struct r600_context *rctx = (struct r600_context *)ctx; 237 struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state); 238 239 if (rstate == NULL) 240 return; 241 242 rstate->id = R600_PIPE_STATE_STENCIL_REF; 243 r600_pipe_state_add_reg(rstate, 244 R_028430_DB_STENCILREFMASK, 245 S_028430_STENCILREF(state->ref_value[0]) | 246 S_028430_STENCILMASK(state->valuemask[0]) | 247 S_028430_STENCILWRITEMASK(state->writemask[0])); 248 r600_pipe_state_add_reg(rstate, 249 R_028434_DB_STENCILREFMASK_BF, 250 S_028434_STENCILREF_BF(state->ref_value[1]) | 251 S_028434_STENCILMASK_BF(state->valuemask[1]) | 252 S_028434_STENCILWRITEMASK_BF(state->writemask[1])); 253 254 free(rctx->states[R600_PIPE_STATE_STENCIL_REF]); 255 rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate; 256 r600_context_pipe_state_set(rctx, rstate); 257} 258 259void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 260 const struct pipe_stencil_ref *state) 261{ 262 struct r600_context *rctx = (struct r600_context *)ctx; 263 struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA]; 264 struct r600_stencil_ref ref; 265 266 rctx->stencil_ref = *state; 267 268 if (!dsa) 269 return; 270 271 ref.ref_value[0] = state->ref_value[0]; 272 ref.ref_value[1] = state->ref_value[1]; 273 ref.valuemask[0] = dsa->valuemask[0]; 274 ref.valuemask[1] = dsa->valuemask[1]; 275 ref.writemask[0] = dsa->writemask[0]; 276 ref.writemask[1] = dsa->writemask[1]; 277 278 r600_set_stencil_ref(ctx, &ref); 279} 280 281void r600_bind_dsa_state(struct pipe_context *ctx, void *state) 282{ 283 struct r600_context *rctx = (struct r600_context *)ctx; 284 struct r600_pipe_dsa *dsa = state; 285 struct r600_pipe_state *rstate; 286 struct r600_stencil_ref ref; 287 288 if (state == NULL) 289 return; 290 rstate = &dsa->rstate; 291 rctx->states[rstate->id] = rstate; 292 r600_context_pipe_state_set(rctx, rstate); 293 294 ref.ref_value[0] = rctx->stencil_ref.ref_value[0]; 295 ref.ref_value[1] = rctx->stencil_ref.ref_value[1]; 296 ref.valuemask[0] = dsa->valuemask[0]; 297 ref.valuemask[1] = dsa->valuemask[1]; 298 ref.writemask[0] = dsa->writemask[0]; 299 ref.writemask[1] = dsa->writemask[1]; 300 301 r600_set_stencil_ref(ctx, &ref); 302 303 /* Update alphatest state. */ 304 if (rctx->alphatest_state.sx_alpha_test_control != dsa->sx_alpha_test_control || 305 rctx->alphatest_state.sx_alpha_ref != dsa->alpha_ref) { 306 rctx->alphatest_state.sx_alpha_test_control = dsa->sx_alpha_test_control; 307 rctx->alphatest_state.sx_alpha_ref = dsa->alpha_ref; 308 r600_atom_dirty(rctx, &rctx->alphatest_state.atom); 309 } 310} 311 312void r600_set_max_scissor(struct r600_context *rctx) 313{ 314 /* Set a scissor state such that it doesn't do anything. */ 315 struct pipe_scissor_state scissor; 316 scissor.minx = 0; 317 scissor.miny = 0; 318 scissor.maxx = 8192; 319 scissor.maxy = 8192; 320 321 r600_set_scissor_state(rctx, &scissor); 322} 323 324void r600_bind_rs_state(struct pipe_context *ctx, void *state) 325{ 326 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state; 327 struct r600_context *rctx = (struct r600_context *)ctx; 328 329 if (state == NULL) 330 return; 331 332 rctx->sprite_coord_enable = rs->sprite_coord_enable; 333 rctx->two_side = rs->two_side; 334 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple; 335 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl; 336 rctx->multisample_enable = rs->multisample_enable; 337 338 rctx->rasterizer = rs; 339 340 rctx->states[rs->rstate.id] = &rs->rstate; 341 r600_context_pipe_state_set(rctx, &rs->rstate); 342 343 if (rctx->chip_class >= EVERGREEN) { 344 evergreen_polygon_offset_update(rctx); 345 } else { 346 r600_polygon_offset_update(rctx); 347 } 348 349 /* Workaround for a missing scissor enable on r600. */ 350 if (rctx->chip_class == R600) { 351 if (rs->scissor_enable != rctx->scissor_enable) { 352 rctx->scissor_enable = rs->scissor_enable; 353 354 if (rs->scissor_enable) { 355 r600_set_scissor_state(rctx, &rctx->scissor_state); 356 } else { 357 r600_set_max_scissor(rctx); 358 } 359 } 360 } 361} 362 363void r600_delete_rs_state(struct pipe_context *ctx, void *state) 364{ 365 struct r600_context *rctx = (struct r600_context *)ctx; 366 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state; 367 368 if (rctx->rasterizer == rs) { 369 rctx->rasterizer = NULL; 370 } 371 if (rctx->states[rs->rstate.id] == &rs->rstate) { 372 rctx->states[rs->rstate.id] = NULL; 373 } 374 free(rs); 375} 376 377void r600_sampler_view_destroy(struct pipe_context *ctx, 378 struct pipe_sampler_view *state) 379{ 380 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state; 381 382 pipe_resource_reference(&state->texture, NULL); 383 FREE(resource); 384} 385 386static void r600_bind_samplers(struct pipe_context *pipe, 387 unsigned shader, 388 unsigned start, 389 unsigned count, void **states) 390{ 391 struct r600_context *rctx = (struct r600_context *)pipe; 392 struct r600_textures_info *dst; 393 int seamless_cube_map = -1; 394 unsigned i; 395 396 assert(start == 0); /* XXX fix below */ 397 398 switch (shader) { 399 case PIPE_SHADER_VERTEX: 400 dst = &rctx->vs_samplers; 401 break; 402 case PIPE_SHADER_FRAGMENT: 403 dst = &rctx->ps_samplers; 404 break; 405 default: 406 debug_error("bad shader in r600_bind_samplers()"); 407 return; 408 } 409 410 memcpy(dst->samplers, states, sizeof(void*) * count); 411 dst->n_samplers = count; 412 dst->atom_sampler.num_dw = 0; 413 414 for (i = 0; i < count; i++) { 415 struct r600_pipe_sampler_state *sampler = states[i]; 416 417 if (sampler == NULL) { 418 continue; 419 } 420 if (sampler->border_color_use) { 421 dst->atom_sampler.num_dw += 11; 422 rctx->flags |= R600_PARTIAL_FLUSH; 423 } else { 424 dst->atom_sampler.num_dw += 5; 425 } 426 seamless_cube_map = sampler->seamless_cube_map; 427 } 428 if (rctx->chip_class <= R700 && seamless_cube_map != -1 && seamless_cube_map != rctx->seamless_cube_map.enabled) { 429 /* change in TA_CNTL_AUX need a pipeline flush */ 430 rctx->flags |= R600_PARTIAL_FLUSH; 431 rctx->seamless_cube_map.enabled = seamless_cube_map; 432 r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom); 433 } 434 if (dst->atom_sampler.num_dw) { 435 r600_atom_dirty(rctx, &dst->atom_sampler); 436 } 437} 438 439void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states) 440{ 441 r600_bind_samplers(ctx, PIPE_SHADER_VERTEX, 0, count, states); 442} 443 444void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states) 445{ 446 r600_bind_samplers(ctx, PIPE_SHADER_FRAGMENT, 0, count, states); 447} 448 449void r600_delete_sampler(struct pipe_context *ctx, void *state) 450{ 451 free(state); 452} 453 454void r600_delete_state(struct pipe_context *ctx, void *state) 455{ 456 struct r600_context *rctx = (struct r600_context *)ctx; 457 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state; 458 459 if (rctx->states[rstate->id] == rstate) { 460 rctx->states[rstate->id] = NULL; 461 } 462 for (int i = 0; i < rstate->nregs; i++) { 463 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL); 464 } 465 free(rstate); 466} 467 468void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) 469{ 470 struct r600_context *rctx = (struct r600_context *)ctx; 471 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 472 473 rctx->vertex_elements = v; 474 if (v) { 475 r600_inval_shader_cache(rctx); 476 477 rctx->states[v->rstate.id] = &v->rstate; 478 r600_context_pipe_state_set(rctx, &v->rstate); 479 } 480} 481 482void r600_delete_vertex_element(struct pipe_context *ctx, void *state) 483{ 484 struct r600_context *rctx = (struct r600_context *)ctx; 485 struct r600_vertex_element *v = (struct r600_vertex_element*)state; 486 487 if (rctx->states[v->rstate.id] == &v->rstate) { 488 rctx->states[v->rstate.id] = NULL; 489 } 490 if (rctx->vertex_elements == state) 491 rctx->vertex_elements = NULL; 492 493 pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL); 494 FREE(state); 495} 496 497void r600_set_index_buffer(struct pipe_context *ctx, 498 const struct pipe_index_buffer *ib) 499{ 500 struct r600_context *rctx = (struct r600_context *)ctx; 501 502 if (ib) { 503 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer); 504 memcpy(&rctx->index_buffer, ib, sizeof(*ib)); 505 } else { 506 pipe_resource_reference(&rctx->index_buffer.buffer, NULL); 507 } 508} 509 510void r600_vertex_buffers_dirty(struct r600_context *rctx) 511{ 512 if (rctx->vertex_buffer_state.dirty_mask) { 513 r600_inval_vertex_cache(rctx); 514 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) * 515 util_bitcount(rctx->vertex_buffer_state.dirty_mask); 516 r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom); 517 } 518} 519 520void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 521 const struct pipe_vertex_buffer *input) 522{ 523 struct r600_context *rctx = (struct r600_context *)ctx; 524 struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state; 525 struct pipe_vertex_buffer *vb = state->vb; 526 unsigned i; 527 /* This sets 1-bit for buffers with index >= count. */ 528 uint32_t disable_mask = ~((1ull << count) - 1); 529 /* These are the new buffers set by this function. */ 530 uint32_t new_buffer_mask = 0; 531 532 /* Set buffers with index >= count to NULL. */ 533 uint32_t remaining_buffers_mask = 534 rctx->vertex_buffer_state.enabled_mask & disable_mask; 535 536 while (remaining_buffers_mask) { 537 i = u_bit_scan(&remaining_buffers_mask); 538 pipe_resource_reference(&vb[i].buffer, NULL); 539 } 540 541 /* Set vertex buffers. */ 542 for (i = 0; i < count; i++) { 543 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) { 544 if (input[i].buffer) { 545 vb[i].stride = input[i].stride; 546 vb[i].buffer_offset = input[i].buffer_offset; 547 pipe_resource_reference(&vb[i].buffer, input[i].buffer); 548 new_buffer_mask |= 1 << i; 549 } else { 550 pipe_resource_reference(&vb[i].buffer, NULL); 551 disable_mask |= 1 << i; 552 } 553 } 554 } 555 556 rctx->vertex_buffer_state.enabled_mask &= ~disable_mask; 557 rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask; 558 rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask; 559 rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask; 560 561 r600_vertex_buffers_dirty(rctx); 562} 563 564void r600_sampler_views_dirty(struct r600_context *rctx, 565 struct r600_samplerview_state *state) 566{ 567 if (state->dirty_mask) { 568 r600_inval_texture_cache(rctx); 569 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) * 570 util_bitcount(state->dirty_mask); 571 r600_atom_dirty(rctx, &state->atom); 572 } 573} 574 575void r600_set_sampler_views(struct pipe_context *pipe, 576 unsigned shader, 577 unsigned start, 578 unsigned count, 579 struct pipe_sampler_view **views) 580{ 581 struct r600_context *rctx = (struct r600_context *) pipe; 582 struct r600_textures_info *dst; 583 struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views; 584 unsigned i; 585 /* This sets 1-bit for textures with index >= count. */ 586 uint32_t disable_mask = ~((1ull << count) - 1); 587 /* These are the new textures set by this function. */ 588 uint32_t new_mask = 0; 589 590 /* Set textures with index >= count to NULL. */ 591 uint32_t remaining_mask; 592 593 assert(start == 0); /* XXX fix below */ 594 595 switch (shader) { 596 case PIPE_SHADER_VERTEX: 597 dst = &rctx->vs_samplers; 598 break; 599 case PIPE_SHADER_FRAGMENT: 600 dst = &rctx->ps_samplers; 601 break; 602 default: 603 debug_error("bad shader in r600_set_sampler_views()"); 604 return; 605 } 606 607 remaining_mask = dst->views.enabled_mask & disable_mask; 608 609 while (remaining_mask) { 610 i = u_bit_scan(&remaining_mask); 611 assert(dst->views.views[i]); 612 613 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL); 614 } 615 616 for (i = 0; i < count; i++) { 617 if (rviews[i] == dst->views.views[i]) { 618 continue; 619 } 620 621 if (rviews[i]) { 622 struct r600_texture *rtex = 623 (struct r600_texture*)rviews[i]->base.texture; 624 625 if (rtex->is_depth && !rtex->is_flushing_texture) { 626 dst->views.compressed_depthtex_mask |= 1 << i; 627 } else { 628 dst->views.compressed_depthtex_mask &= ~(1 << i); 629 } 630 631 if (rtex->cmask_size && rtex->fmask_size) { 632 dst->views.compressed_colortex_mask |= 1 << i; 633 } else { 634 dst->views.compressed_colortex_mask &= ~(1 << i); 635 } 636 637 /* Changing from array to non-arrays textures and vice 638 * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */ 639 if (rctx->chip_class <= R700 && 640 (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY || 641 rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) { 642 r600_atom_dirty(rctx, &dst->atom_sampler); 643 } 644 645 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]); 646 new_mask |= 1 << i; 647 } else { 648 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL); 649 disable_mask |= 1 << i; 650 } 651 } 652 653 dst->views.enabled_mask &= ~disable_mask; 654 dst->views.dirty_mask &= dst->views.enabled_mask; 655 dst->views.enabled_mask |= new_mask; 656 dst->views.dirty_mask |= new_mask; 657 dst->views.compressed_depthtex_mask &= dst->views.enabled_mask; 658 dst->views.compressed_colortex_mask &= dst->views.enabled_mask; 659 660 r600_sampler_views_dirty(rctx, &dst->views); 661} 662 663void *r600_create_vertex_elements(struct pipe_context *ctx, 664 unsigned count, 665 const struct pipe_vertex_element *elements) 666{ 667 struct r600_context *rctx = (struct r600_context *)ctx; 668 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element); 669 670 assert(count < 32); 671 if (!v) 672 return NULL; 673 674 v->count = count; 675 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count); 676 677 if (r600_vertex_elements_build_fetch_shader(rctx, v)) { 678 FREE(v); 679 return NULL; 680 } 681 682 return v; 683} 684 685/* Compute the key for the hw shader variant */ 686static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx, 687 struct r600_pipe_shader_selector * sel) 688{ 689 struct r600_context *rctx = (struct r600_context *)ctx; 690 unsigned key; 691 692 if (sel->type == PIPE_SHADER_FRAGMENT) { 693 key = rctx->two_side | 694 ((rctx->alpha_to_one && rctx->multisample_enable && !rctx->cb0_is_integer) << 1) | 695 (MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 2); 696 } else 697 key = 0; 698 699 return key; 700} 701 702/* Select the hw shader variant depending on the current state. 703 * (*dirty) is set to 1 if current variant was changed */ 704static int r600_shader_select(struct pipe_context *ctx, 705 struct r600_pipe_shader_selector* sel, 706 unsigned *dirty) 707{ 708 unsigned key; 709 struct r600_context *rctx = (struct r600_context *)ctx; 710 struct r600_pipe_shader * shader = NULL; 711 int r; 712 713 key = r600_shader_selector_key(ctx, sel); 714 715 /* Check if we don't need to change anything. 716 * This path is also used for most shaders that don't need multiple 717 * variants, it will cost just a computation of the key and this 718 * test. */ 719 if (likely(sel->current && sel->current->key == key)) { 720 return 0; 721 } 722 723 /* lookup if we have other variants in the list */ 724 if (sel->num_shaders > 1) { 725 struct r600_pipe_shader *p = sel->current, *c = p->next_variant; 726 727 while (c && c->key != key) { 728 p = c; 729 c = c->next_variant; 730 } 731 732 if (c) { 733 p->next_variant = c->next_variant; 734 shader = c; 735 } 736 } 737 738 if (unlikely(!shader)) { 739 shader = CALLOC(1, sizeof(struct r600_pipe_shader)); 740 shader->selector = sel; 741 742 r = r600_pipe_shader_create(ctx, shader); 743 if (unlikely(r)) { 744 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n", 745 sel->type, key, r); 746 sel->current = NULL; 747 return r; 748 } 749 750 /* We don't know the value of nr_ps_max_color_exports until we built 751 * at least one variant, so we may need to recompute the key after 752 * building first variant. */ 753 if (sel->type == PIPE_SHADER_FRAGMENT && 754 sel->num_shaders == 0) { 755 sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports; 756 key = r600_shader_selector_key(ctx, sel); 757 } 758 759 shader->key = key; 760 sel->num_shaders++; 761 } 762 763 if (dirty) 764 *dirty = 1; 765 766 shader->next_variant = sel->current; 767 sel->current = shader; 768 769 if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) { 770 r600_adjust_gprs(rctx); 771 } 772 773 if (rctx->ps_shader && 774 rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) { 775 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs; 776 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 777 } 778 return 0; 779} 780 781static void *r600_create_shader_state(struct pipe_context *ctx, 782 const struct pipe_shader_state *state, 783 unsigned pipe_shader_type) 784{ 785 struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector); 786 int r; 787 788 sel->type = pipe_shader_type; 789 sel->tokens = tgsi_dup_tokens(state->tokens); 790 sel->so = state->stream_output; 791 792 r = r600_shader_select(ctx, sel, NULL); 793 if (r) 794 return NULL; 795 796 return sel; 797} 798 799void *r600_create_shader_state_ps(struct pipe_context *ctx, 800 const struct pipe_shader_state *state) 801{ 802 return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT); 803} 804 805void *r600_create_shader_state_vs(struct pipe_context *ctx, 806 const struct pipe_shader_state *state) 807{ 808 return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX); 809} 810 811void r600_bind_ps_shader(struct pipe_context *ctx, void *state) 812{ 813 struct r600_context *rctx = (struct r600_context *)ctx; 814 815 if (!state) 816 state = rctx->dummy_pixel_shader; 817 818 rctx->ps_shader = (struct r600_pipe_shader_selector *)state; 819 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate); 820 821 if (rctx->chip_class <= R700) { 822 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all; 823 824 if (rctx->cb_misc_state.multiwrite != multiwrite) { 825 rctx->cb_misc_state.multiwrite = multiwrite; 826 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 827 } 828 829 if (rctx->vs_shader) 830 r600_adjust_gprs(rctx); 831 } 832 833 if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) { 834 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs; 835 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom); 836 } 837} 838 839void r600_bind_vs_shader(struct pipe_context *ctx, void *state) 840{ 841 struct r600_context *rctx = (struct r600_context *)ctx; 842 843 rctx->vs_shader = (struct r600_pipe_shader_selector *)state; 844 if (state) { 845 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate); 846 847 if (rctx->chip_class < EVERGREEN && rctx->ps_shader) 848 r600_adjust_gprs(rctx); 849 } 850} 851 852static void r600_delete_shader_selector(struct pipe_context *ctx, 853 struct r600_pipe_shader_selector *sel) 854{ 855 struct r600_pipe_shader *p = sel->current, *c; 856 while (p) { 857 c = p->next_variant; 858 r600_pipe_shader_destroy(ctx, p); 859 free(p); 860 p = c; 861 } 862 863 free(sel->tokens); 864 free(sel); 865} 866 867 868void r600_delete_ps_shader(struct pipe_context *ctx, void *state) 869{ 870 struct r600_context *rctx = (struct r600_context *)ctx; 871 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state; 872 873 if (rctx->ps_shader == sel) { 874 rctx->ps_shader = NULL; 875 } 876 877 r600_delete_shader_selector(ctx, sel); 878} 879 880void r600_delete_vs_shader(struct pipe_context *ctx, void *state) 881{ 882 struct r600_context *rctx = (struct r600_context *)ctx; 883 struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state; 884 885 if (rctx->vs_shader == sel) { 886 rctx->vs_shader = NULL; 887 } 888 889 r600_delete_shader_selector(ctx, sel); 890} 891 892void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state) 893{ 894 if (state->dirty_mask) { 895 r600_inval_shader_cache(rctx); 896 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20 897 : util_bitcount(state->dirty_mask)*19; 898 r600_atom_dirty(rctx, &state->atom); 899 } 900} 901 902void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 903 struct pipe_constant_buffer *input) 904{ 905 struct r600_context *rctx = (struct r600_context *)ctx; 906 struct r600_constbuf_state *state; 907 struct pipe_constant_buffer *cb; 908 const uint8_t *ptr; 909 910 switch (shader) { 911 case PIPE_SHADER_VERTEX: 912 state = &rctx->vs_constbuf_state; 913 break; 914 case PIPE_SHADER_FRAGMENT: 915 state = &rctx->ps_constbuf_state; 916 break; 917 default: 918 return; 919 } 920 921 /* Note that the state tracker can unbind constant buffers by 922 * passing NULL here. 923 */ 924 if (unlikely(!input)) { 925 state->enabled_mask &= ~(1 << index); 926 state->dirty_mask &= ~(1 << index); 927 pipe_resource_reference(&state->cb[index].buffer, NULL); 928 return; 929 } 930 931 cb = &state->cb[index]; 932 cb->buffer_size = input->buffer_size; 933 934 ptr = input->user_buffer; 935 936 if (ptr) { 937 /* Upload the user buffer. */ 938 if (R600_BIG_ENDIAN) { 939 uint32_t *tmpPtr; 940 unsigned i, size = input->buffer_size; 941 942 if (!(tmpPtr = malloc(size))) { 943 R600_ERR("Failed to allocate BE swap buffer.\n"); 944 return; 945 } 946 947 for (i = 0; i < size / 4; ++i) { 948 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]); 949 } 950 951 u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer); 952 free(tmpPtr); 953 } else { 954 u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer); 955 } 956 } else { 957 /* Setup the hw buffer. */ 958 cb->buffer_offset = input->buffer_offset; 959 pipe_resource_reference(&cb->buffer, input->buffer); 960 } 961 962 state->enabled_mask |= 1 << index; 963 state->dirty_mask |= 1 << index; 964 r600_constant_buffers_dirty(rctx, state); 965} 966 967struct pipe_stream_output_target * 968r600_create_so_target(struct pipe_context *ctx, 969 struct pipe_resource *buffer, 970 unsigned buffer_offset, 971 unsigned buffer_size) 972{ 973 struct r600_context *rctx = (struct r600_context *)ctx; 974 struct r600_so_target *t; 975 void *ptr; 976 977 t = CALLOC_STRUCT(r600_so_target); 978 if (!t) { 979 return NULL; 980 } 981 982 t->b.reference.count = 1; 983 t->b.context = ctx; 984 pipe_resource_reference(&t->b.buffer, buffer); 985 t->b.buffer_offset = buffer_offset; 986 t->b.buffer_size = buffer_size; 987 988 t->filled_size = (struct r600_resource*) 989 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4); 990 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE); 991 memset(ptr, 0, t->filled_size->buf->size); 992 rctx->ws->buffer_unmap(t->filled_size->cs_buf); 993 994 return &t->b; 995} 996 997void r600_so_target_destroy(struct pipe_context *ctx, 998 struct pipe_stream_output_target *target) 999{ 1000 struct r600_so_target *t = (struct r600_so_target*)target; 1001 pipe_resource_reference(&t->b.buffer, NULL); 1002 pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL); 1003 FREE(t); 1004} 1005 1006void r600_set_so_targets(struct pipe_context *ctx, 1007 unsigned num_targets, 1008 struct pipe_stream_output_target **targets, 1009 unsigned append_bitmask) 1010{ 1011 struct r600_context *rctx = (struct r600_context *)ctx; 1012 unsigned i; 1013 1014 /* Stop streamout. */ 1015 if (rctx->num_so_targets && !rctx->streamout_start) { 1016 r600_context_streamout_end(rctx); 1017 } 1018 1019 /* Set the new targets. */ 1020 for (i = 0; i < num_targets; i++) { 1021 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]); 1022 } 1023 for (; i < rctx->num_so_targets; i++) { 1024 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL); 1025 } 1026 1027 rctx->num_so_targets = num_targets; 1028 rctx->streamout_start = num_targets != 0; 1029 rctx->streamout_append_bitmask = append_bitmask; 1030} 1031 1032void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask) 1033{ 1034 struct r600_context *rctx = (struct r600_context*)pipe; 1035 1036 if (rctx->sample_mask.sample_mask == (uint16_t)sample_mask) 1037 return; 1038 1039 rctx->sample_mask.sample_mask = sample_mask; 1040 r600_atom_dirty(rctx, &rctx->sample_mask.atom); 1041} 1042 1043static void r600_update_derived_state(struct r600_context *rctx) 1044{ 1045 struct pipe_context * ctx = (struct pipe_context*)rctx; 1046 unsigned ps_dirty = 0, blend_override; 1047 1048 if (!rctx->blitter->running) { 1049 /* Decompress textures if needed. */ 1050 if (rctx->vs_samplers.views.compressed_depthtex_mask) { 1051 r600_decompress_depth_textures(rctx, &rctx->vs_samplers.views); 1052 } 1053 if (rctx->ps_samplers.views.compressed_depthtex_mask) { 1054 r600_decompress_depth_textures(rctx, &rctx->ps_samplers.views); 1055 } 1056 if (rctx->vs_samplers.views.compressed_colortex_mask) { 1057 r600_decompress_color_textures(rctx, &rctx->vs_samplers.views); 1058 } 1059 if (rctx->ps_samplers.views.compressed_colortex_mask) { 1060 r600_decompress_color_textures(rctx, &rctx->ps_samplers.views); 1061 } 1062 } 1063 1064 r600_shader_select(ctx, rctx->ps_shader, &ps_dirty); 1065 1066 if (rctx->ps_shader && ((rctx->sprite_coord_enable && 1067 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) || 1068 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) { 1069 1070 if (rctx->chip_class >= EVERGREEN) 1071 evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current); 1072 else 1073 r600_pipe_shader_ps(ctx, rctx->ps_shader->current); 1074 1075 ps_dirty = 1; 1076 } 1077 1078 if (ps_dirty) 1079 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate); 1080 1081 blend_override = (rctx->dual_src_blend && 1082 rctx->ps_shader->current->nr_ps_color_outputs < 2); 1083 1084 if (blend_override != rctx->blend_override) { 1085 rctx->blend_override = blend_override; 1086 r600_bind_blend_state_internal(rctx, 1087 blend_override ? rctx->no_blend : rctx->blend); 1088 } 1089 1090 if (rctx->chip_class >= EVERGREEN) { 1091 evergreen_update_dual_export_state(rctx); 1092 } else { 1093 r600_update_dual_export_state(rctx); 1094 } 1095} 1096 1097static unsigned r600_conv_prim_to_gs_out(unsigned mode) 1098{ 1099 static const int prim_conv[] = { 1100 V_028A6C_OUTPRIM_TYPE_POINTLIST, 1101 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 1102 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 1103 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 1104 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1105 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1106 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1107 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1108 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1109 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1110 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 1111 V_028A6C_OUTPRIM_TYPE_LINESTRIP, 1112 V_028A6C_OUTPRIM_TYPE_TRISTRIP, 1113 V_028A6C_OUTPRIM_TYPE_TRISTRIP 1114 }; 1115 assert(mode < Elements(prim_conv)); 1116 1117 return prim_conv[mode]; 1118} 1119 1120void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo) 1121{ 1122 struct r600_context *rctx = (struct r600_context *)ctx; 1123 struct pipe_draw_info info = *dinfo; 1124 struct pipe_index_buffer ib = {}; 1125 unsigned prim, ls_mask = 0; 1126 struct r600_block *dirty_block = NULL, *next_block = NULL; 1127 struct r600_atom *state = NULL, *next_state = NULL; 1128 struct radeon_winsys_cs *cs = rctx->cs; 1129 uint64_t va; 1130 uint8_t *ptr; 1131 1132 if ((!info.count && (info.indexed || !info.count_from_stream_output)) || 1133 !r600_conv_pipe_prim(info.mode, &prim)) { 1134 assert(0); 1135 return; 1136 } 1137 1138 if (!rctx->vs_shader) { 1139 assert(0); 1140 return; 1141 } 1142 1143 r600_update_derived_state(rctx); 1144 1145 /* partial flush triggered by border color change */ 1146 if (rctx->flags & R600_PARTIAL_FLUSH) { 1147 rctx->flags &= ~R600_PARTIAL_FLUSH; 1148 r600_write_value(cs, PKT3(PKT3_EVENT_WRITE, 0, 0)); 1149 r600_write_value(cs, EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4)); 1150 } 1151 1152 if (info.indexed) { 1153 /* Initialize the index buffer struct. */ 1154 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer); 1155 ib.user_buffer = rctx->index_buffer.user_buffer; 1156 ib.index_size = rctx->index_buffer.index_size; 1157 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size; 1158 1159 /* Translate or upload, if needed. */ 1160 r600_translate_index_buffer(rctx, &ib, info.count); 1161 1162 ptr = (uint8_t*)ib.user_buffer; 1163 if (!ib.buffer && ptr) { 1164 u_upload_data(rctx->uploader, 0, info.count * ib.index_size, 1165 ptr, &ib.offset, &ib.buffer); 1166 } 1167 } else { 1168 info.index_bias = info.start; 1169 } 1170 1171 if (rctx->vgt.id != R600_PIPE_STATE_VGT) { 1172 rctx->vgt.id = R600_PIPE_STATE_VGT; 1173 rctx->vgt.nregs = 0; 1174 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim); 1175 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0); 1176 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias); 1177 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index); 1178 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart); 1179 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance); 1180 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0); 1181 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0); 1182 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0); 1183 } 1184 1185 rctx->vgt.nregs = 0; 1186 r600_pipe_state_mod_reg(&rctx->vgt, prim); 1187 r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode)); 1188 r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias); 1189 r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index); 1190 r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart); 1191 r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance); 1192 1193 if (prim == V_008958_DI_PT_LINELIST) 1194 ls_mask = 1; 1195 else if (prim == V_008958_DI_PT_LINESTRIP || 1196 prim == V_008958_DI_PT_LINELOOP) 1197 ls_mask = 2; 1198 r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple); 1199 r600_pipe_state_mod_reg(&rctx->vgt, 1200 rctx->vs_shader->current->pa_cl_vs_out_cntl | 1201 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write)); 1202 r600_pipe_state_mod_reg(&rctx->vgt, 1203 rctx->pa_cl_clip_cntl | 1204 (rctx->vs_shader->current->shader.clip_dist_write || 1205 rctx->vs_shader->current->shader.vs_prohibit_ucps ? 1206 0 : rctx->rasterizer->clip_plane_enable & 0x3F)); 1207 1208 r600_context_pipe_state_set(rctx, &rctx->vgt); 1209 1210 /* Enable stream out if needed. */ 1211 if (rctx->streamout_start) { 1212 r600_context_streamout_begin(rctx); 1213 rctx->streamout_start = FALSE; 1214 } 1215 1216 /* Emit states (the function expects that we emit at most 17 dwords here). */ 1217 r600_need_cs_space(rctx, 0, TRUE); 1218 1219 LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) { 1220 r600_emit_atom(rctx, state); 1221 } 1222 LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) { 1223 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */); 1224 } 1225 rctx->pm4_dirty_cdwords = 0; 1226 1227 /* draw packet */ 1228 cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing); 1229 cs->buf[cs->cdw++] = info.instance_count; 1230 if (info.indexed) { 1231 cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing); 1232 cs->buf[cs->cdw++] = ib.index_size == 4 ? 1233 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) : 1234 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0)); 1235 1236 va = r600_resource_va(ctx->screen, ib.buffer); 1237 va += ib.offset; 1238 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing); 1239 cs->buf[cs->cdw++] = va; 1240 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; 1241 cs->buf[cs->cdw++] = info.count; 1242 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA; 1243 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing); 1244 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ); 1245 } else { 1246 if (info.count_from_stream_output) { 1247 struct r600_so_target *t = (struct r600_so_target*)info.count_from_stream_output; 1248 uint64_t va = r600_resource_va(&rctx->screen->screen, (void*)t->filled_size); 1249 1250 r600_write_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw); 1251 1252 cs->buf[cs->cdw++] = PKT3(PKT3_COPY_DW, 4, 0); 1253 cs->buf[cs->cdw++] = COPY_DW_SRC_IS_MEM | COPY_DW_DST_IS_REG; 1254 cs->buf[cs->cdw++] = va & 0xFFFFFFFFUL; /* src address lo */ 1255 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFFUL; /* src address hi */ 1256 cs->buf[cs->cdw++] = R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2; /* dst register */ 1257 cs->buf[cs->cdw++] = 0; /* unused */ 1258 1259 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, 0); 1260 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, t->filled_size, RADEON_USAGE_READ); 1261 } 1262 1263 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing); 1264 cs->buf[cs->cdw++] = info.count; 1265 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX | 1266 (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0); 1267 } 1268 1269 rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING; 1270 1271 /* Set the depth buffer as dirty. */ 1272 if (rctx->framebuffer.zsbuf) { 1273 struct pipe_surface *surf = rctx->framebuffer.zsbuf; 1274 struct r600_texture *rtex = (struct r600_texture *)surf->texture; 1275 1276 rtex->dirty_level_mask |= 1 << surf->u.tex.level; 1277 } 1278 if (rctx->compressed_cb_mask) { 1279 struct pipe_surface *surf; 1280 struct r600_texture *rtex; 1281 unsigned mask = rctx->compressed_cb_mask; 1282 1283 do { 1284 unsigned i = u_bit_scan(&mask); 1285 surf = rctx->framebuffer.cbufs[i]; 1286 rtex = (struct r600_texture*)surf->texture; 1287 1288 rtex->dirty_level_mask |= 1 << surf->u.tex.level; 1289 1290 } while (mask); 1291 } 1292 1293 pipe_resource_reference(&ib.buffer, NULL); 1294} 1295 1296void _r600_pipe_state_add_reg_bo(struct r600_context *ctx, 1297 struct r600_pipe_state *state, 1298 uint32_t offset, uint32_t value, 1299 uint32_t range_id, uint32_t block_id, 1300 struct r600_resource *bo, 1301 enum radeon_bo_usage usage) 1302 1303{ 1304 struct r600_range *range; 1305 struct r600_block *block; 1306 1307 if (bo) assert(usage); 1308 1309 range = &ctx->range[range_id]; 1310 block = range->blocks[block_id]; 1311 state->regs[state->nregs].block = block; 1312 state->regs[state->nregs].id = (offset - block->start_offset) >> 2; 1313 1314 state->regs[state->nregs].value = value; 1315 state->regs[state->nregs].bo = bo; 1316 state->regs[state->nregs].bo_usage = usage; 1317 1318 state->nregs++; 1319 assert(state->nregs < R600_BLOCK_MAX_REG); 1320} 1321 1322void _r600_pipe_state_add_reg(struct r600_context *ctx, 1323 struct r600_pipe_state *state, 1324 uint32_t offset, uint32_t value, 1325 uint32_t range_id, uint32_t block_id) 1326{ 1327 _r600_pipe_state_add_reg_bo(ctx, state, offset, value, 1328 range_id, block_id, NULL, 0); 1329} 1330 1331void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state, 1332 uint32_t offset, uint32_t value, 1333 struct r600_resource *bo, 1334 enum radeon_bo_usage usage) 1335{ 1336 if (bo) assert(usage); 1337 1338 state->regs[state->nregs].id = offset; 1339 state->regs[state->nregs].block = NULL; 1340 state->regs[state->nregs].value = value; 1341 state->regs[state->nregs].bo = bo; 1342 state->regs[state->nregs].bo_usage = usage; 1343 1344 state->nregs++; 1345 assert(state->nregs < R600_BLOCK_MAX_REG); 1346} 1347 1348uint32_t r600_translate_stencil_op(int s_op) 1349{ 1350 switch (s_op) { 1351 case PIPE_STENCIL_OP_KEEP: 1352 return V_028800_STENCIL_KEEP; 1353 case PIPE_STENCIL_OP_ZERO: 1354 return V_028800_STENCIL_ZERO; 1355 case PIPE_STENCIL_OP_REPLACE: 1356 return V_028800_STENCIL_REPLACE; 1357 case PIPE_STENCIL_OP_INCR: 1358 return V_028800_STENCIL_INCR; 1359 case PIPE_STENCIL_OP_DECR: 1360 return V_028800_STENCIL_DECR; 1361 case PIPE_STENCIL_OP_INCR_WRAP: 1362 return V_028800_STENCIL_INCR_WRAP; 1363 case PIPE_STENCIL_OP_DECR_WRAP: 1364 return V_028800_STENCIL_DECR_WRAP; 1365 case PIPE_STENCIL_OP_INVERT: 1366 return V_028800_STENCIL_INVERT; 1367 default: 1368 R600_ERR("Unknown stencil op %d", s_op); 1369 assert(0); 1370 break; 1371 } 1372 return 0; 1373} 1374 1375uint32_t r600_translate_fill(uint32_t func) 1376{ 1377 switch(func) { 1378 case PIPE_POLYGON_MODE_FILL: 1379 return 2; 1380 case PIPE_POLYGON_MODE_LINE: 1381 return 1; 1382 case PIPE_POLYGON_MODE_POINT: 1383 return 0; 1384 default: 1385 assert(0); 1386 return 0; 1387 } 1388} 1389 1390unsigned r600_tex_wrap(unsigned wrap) 1391{ 1392 switch (wrap) { 1393 default: 1394 case PIPE_TEX_WRAP_REPEAT: 1395 return V_03C000_SQ_TEX_WRAP; 1396 case PIPE_TEX_WRAP_CLAMP: 1397 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER; 1398 case PIPE_TEX_WRAP_CLAMP_TO_EDGE: 1399 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL; 1400 case PIPE_TEX_WRAP_CLAMP_TO_BORDER: 1401 return V_03C000_SQ_TEX_CLAMP_BORDER; 1402 case PIPE_TEX_WRAP_MIRROR_REPEAT: 1403 return V_03C000_SQ_TEX_MIRROR; 1404 case PIPE_TEX_WRAP_MIRROR_CLAMP: 1405 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER; 1406 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE: 1407 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL; 1408 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER: 1409 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER; 1410 } 1411} 1412 1413unsigned r600_tex_filter(unsigned filter) 1414{ 1415 switch (filter) { 1416 default: 1417 case PIPE_TEX_FILTER_NEAREST: 1418 return V_03C000_SQ_TEX_XY_FILTER_POINT; 1419 case PIPE_TEX_FILTER_LINEAR: 1420 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR; 1421 } 1422} 1423 1424unsigned r600_tex_mipfilter(unsigned filter) 1425{ 1426 switch (filter) { 1427 case PIPE_TEX_MIPFILTER_NEAREST: 1428 return V_03C000_SQ_TEX_Z_FILTER_POINT; 1429 case PIPE_TEX_MIPFILTER_LINEAR: 1430 return V_03C000_SQ_TEX_Z_FILTER_LINEAR; 1431 default: 1432 case PIPE_TEX_MIPFILTER_NONE: 1433 return V_03C000_SQ_TEX_Z_FILTER_NONE; 1434 } 1435} 1436 1437unsigned r600_tex_compare(unsigned compare) 1438{ 1439 switch (compare) { 1440 default: 1441 case PIPE_FUNC_NEVER: 1442 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER; 1443 case PIPE_FUNC_LESS: 1444 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS; 1445 case PIPE_FUNC_EQUAL: 1446 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL; 1447 case PIPE_FUNC_LEQUAL: 1448 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL; 1449 case PIPE_FUNC_GREATER: 1450 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER; 1451 case PIPE_FUNC_NOTEQUAL: 1452 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL; 1453 case PIPE_FUNC_GEQUAL: 1454 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL; 1455 case PIPE_FUNC_ALWAYS: 1456 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS; 1457 } 1458} 1459