r600_texture.c revision 362a25aac5f8cd71c08ad92b4b19be6712d8fd72
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include "r600_formats.h" 28#include "r600d.h" 29 30#include <errno.h> 31#include "util/u_format_s3tc.h" 32#include "util/u_memory.h" 33 34/* Copy from a full GPU texture to a transfer's staging one. */ 35static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 36{ 37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 38 struct pipe_resource *texture = transfer->resource; 39 40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b, 41 0, 0, 0, 0, texture, transfer->level, 42 &transfer->box); 43} 44 45 46/* Copy from a transfer's staging texture to a full GPU one. */ 47static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 48{ 49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 50 struct pipe_resource *texture = transfer->resource; 51 struct pipe_box sbox; 52 53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox); 54 55 ctx->resource_copy_region(ctx, texture, transfer->level, 56 transfer->box.x, transfer->box.y, transfer->box.z, 57 &rtransfer->staging->b.b, 58 0, &sbox); 59} 60 61unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 62 unsigned level, unsigned layer) 63{ 64 return rtex->offset[level] + layer * rtex->layer_size[level]; 65} 66 67static int r600_init_surface(struct r600_screen *rscreen, 68 struct radeon_surface *surface, 69 const struct pipe_resource *ptex, 70 unsigned array_mode, 71 bool is_transfer, bool is_flushed_depth) 72{ 73 const struct util_format_description *desc = 74 util_format_description(ptex->format); 75 bool is_depth, is_stencil; 76 77 is_depth = util_format_has_depth(desc); 78 is_stencil = util_format_has_stencil(desc); 79 80 surface->npix_x = ptex->width0; 81 surface->npix_y = ptex->height0; 82 surface->npix_z = ptex->depth0; 83 surface->blk_w = util_format_get_blockwidth(ptex->format); 84 surface->blk_h = util_format_get_blockheight(ptex->format); 85 surface->blk_d = 1; 86 surface->array_size = 1; 87 surface->last_level = ptex->last_level; 88 89 if (rscreen->chip_class >= EVERGREEN && 90 !is_transfer && !is_flushed_depth && 91 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { 92 surface->bpe = 4; /* stencil is allocated separately on evergreen */ 93 } else { 94 surface->bpe = util_format_get_blocksize(ptex->format); 95 /* align byte per element on dword */ 96 if (surface->bpe == 3) { 97 surface->bpe = 4; 98 } 99 } 100 101 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1; 102 surface->flags = 0; 103 104 switch (array_mode) { 105 case V_038000_ARRAY_1D_TILED_THIN1: 106 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 107 break; 108 case V_038000_ARRAY_2D_TILED_THIN1: 109 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 110 break; 111 case V_038000_ARRAY_LINEAR_ALIGNED: 112 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 113 break; 114 case V_038000_ARRAY_LINEAR_GENERAL: 115 default: 116 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); 117 break; 118 } 119 switch (ptex->target) { 120 case PIPE_TEXTURE_1D: 121 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); 122 break; 123 case PIPE_TEXTURE_RECT: 124 case PIPE_TEXTURE_2D: 125 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 126 break; 127 case PIPE_TEXTURE_3D: 128 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); 129 break; 130 case PIPE_TEXTURE_1D_ARRAY: 131 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); 132 surface->array_size = ptex->array_size; 133 break; 134 case PIPE_TEXTURE_2D_ARRAY: 135 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); 136 surface->array_size = ptex->array_size; 137 break; 138 case PIPE_TEXTURE_CUBE: 139 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); 140 break; 141 case PIPE_BUFFER: 142 default: 143 return -EINVAL; 144 } 145 if (ptex->bind & PIPE_BIND_SCANOUT) { 146 surface->flags |= RADEON_SURF_SCANOUT; 147 } 148 149 if (!is_transfer && !is_flushed_depth && is_depth) { 150 surface->flags |= RADEON_SURF_ZBUFFER; 151 152 if (is_stencil) { 153 surface->flags |= RADEON_SURF_SBUFFER; 154 } 155 } 156 return 0; 157} 158 159static int r600_setup_surface(struct pipe_screen *screen, 160 struct r600_resource_texture *rtex, 161 unsigned pitch_in_bytes_override) 162{ 163 struct pipe_resource *ptex = &rtex->resource.b.b; 164 struct r600_screen *rscreen = (struct r600_screen*)screen; 165 unsigned i; 166 int r; 167 168 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); 169 if (r) { 170 return r; 171 } 172 rtex->size = rtex->surface.bo_size; 173 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { 174 /* old ddx on evergreen over estimate alignment for 1d, only 1 level 175 * for those 176 */ 177 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; 178 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; 179 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; 180 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 181 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size; 182 } 183 } 184 for (i = 0; i <= ptex->last_level; i++) { 185 rtex->offset[i] = rtex->surface.level[i].offset; 186 rtex->layer_size[i] = rtex->surface.level[i].slice_size; 187 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes; 188 switch (rtex->surface.level[i].mode) { 189 case RADEON_SURF_MODE_LINEAR_ALIGNED: 190 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED; 191 break; 192 case RADEON_SURF_MODE_1D: 193 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1; 194 break; 195 case RADEON_SURF_MODE_2D: 196 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1; 197 break; 198 default: 199 case RADEON_SURF_MODE_LINEAR: 200 rtex->array_mode[i] = 0; 201 break; 202 } 203 } 204 return 0; 205} 206 207static boolean r600_texture_get_handle(struct pipe_screen* screen, 208 struct pipe_resource *ptex, 209 struct winsys_handle *whandle) 210{ 211 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 212 struct r600_resource *resource = &rtex->resource; 213 struct radeon_surface *surface = &rtex->surface; 214 struct r600_screen *rscreen = (struct r600_screen*)screen; 215 216 rscreen->ws->buffer_set_tiling(resource->buf, 217 NULL, 218 surface->level[0].mode >= RADEON_SURF_MODE_1D ? 219 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 220 surface->level[0].mode >= RADEON_SURF_MODE_2D ? 221 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 222 surface->bankw, surface->bankh, 223 surface->tile_split, 224 surface->stencil_tile_split, 225 surface->mtilea, 226 rtex->pitch_in_bytes[0]); 227 228 return rscreen->ws->buffer_get_handle(resource->buf, 229 rtex->pitch_in_bytes[0], whandle); 230} 231 232static void r600_texture_destroy(struct pipe_screen *screen, 233 struct pipe_resource *ptex) 234{ 235 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 236 struct r600_resource *resource = &rtex->resource; 237 238 if (rtex->flushed_depth_texture) 239 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 240 241 pb_reference(&resource->buf, NULL); 242 FREE(rtex); 243} 244 245static const struct u_resource_vtbl r600_texture_vtbl = 246{ 247 r600_texture_get_handle, /* get_handle */ 248 r600_texture_destroy, /* resource_destroy */ 249 r600_texture_get_transfer, /* get_transfer */ 250 r600_texture_transfer_destroy, /* transfer_destroy */ 251 r600_texture_transfer_map, /* transfer_map */ 252 NULL, /* transfer_flush_region */ 253 r600_texture_transfer_unmap, /* transfer_unmap */ 254 NULL /* transfer_inline_write */ 255}; 256 257static struct r600_resource_texture * 258r600_texture_create_object(struct pipe_screen *screen, 259 const struct pipe_resource *base, 260 unsigned pitch_in_bytes_override, 261 struct pb_buffer *buf, 262 boolean alloc_bo, 263 struct radeon_surface *surface) 264{ 265 struct r600_resource_texture *rtex; 266 struct r600_resource *resource; 267 struct r600_screen *rscreen = (struct r600_screen*)screen; 268 int r; 269 270 rtex = CALLOC_STRUCT(r600_resource_texture); 271 if (rtex == NULL) 272 return NULL; 273 274 resource = &rtex->resource; 275 resource->b.b = *base; 276 resource->b.vtbl = &r600_texture_vtbl; 277 pipe_reference_init(&resource->b.b.reference, 1); 278 resource->b.b.screen = screen; 279 rtex->pitch_override = pitch_in_bytes_override; 280 rtex->real_format = base->format; 281 282 /* don't include stencil-only formats which we don't support for rendering */ 283 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format)); 284 285 rtex->surface = *surface; 286 r = r600_setup_surface(screen, rtex, 287 pitch_in_bytes_override); 288 if (r) { 289 FREE(rtex); 290 return NULL; 291 } 292 293 /* Now create the backing buffer. */ 294 if (!buf && alloc_bo) { 295 unsigned base_align = rtex->surface.bo_alignment; 296 297 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) { 298 FREE(rtex); 299 return NULL; 300 } 301 } else if (buf) { 302 resource->buf = buf; 303 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); 304 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; 305 } 306 return rtex; 307} 308 309struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 310 const struct pipe_resource *templ) 311{ 312 struct r600_screen *rscreen = (struct r600_screen*)screen; 313 struct radeon_surface surface; 314 unsigned array_mode = 0; 315 int r; 316 317 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) { 318 if (!(templ->bind & PIPE_BIND_SCANOUT) && 319 templ->usage != PIPE_USAGE_STAGING && 320 templ->usage != PIPE_USAGE_STREAM) { 321 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 322 } else if (util_format_is_compressed(templ->format)) { 323 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 324 } 325 } 326 327 r = r600_init_surface(rscreen, &surface, templ, array_mode, 328 templ->flags & R600_RESOURCE_FLAG_TRANSFER, 329 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); 330 if (r) { 331 return NULL; 332 } 333 r = rscreen->ws->surface_best(rscreen->ws, &surface); 334 if (r) { 335 return NULL; 336 } 337 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 338 0, NULL, TRUE, &surface); 339} 340 341static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 342 struct pipe_resource *texture, 343 const struct pipe_surface *templ) 344{ 345 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 346 unsigned level = templ->u.tex.level; 347 348 assert(templ->u.tex.first_layer == templ->u.tex.last_layer); 349 if (surface == NULL) 350 return NULL; 351 pipe_reference_init(&surface->base.reference, 1); 352 pipe_resource_reference(&surface->base.texture, texture); 353 surface->base.context = pipe; 354 surface->base.format = templ->format; 355 surface->base.width = u_minify(texture->width0, level); 356 surface->base.height = u_minify(texture->height0, level); 357 surface->base.usage = templ->usage; 358 surface->base.u = templ->u; 359 return &surface->base; 360} 361 362static void r600_surface_destroy(struct pipe_context *pipe, 363 struct pipe_surface *surface) 364{ 365 pipe_resource_reference(&surface->texture, NULL); 366 FREE(surface); 367} 368 369struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 370 const struct pipe_resource *templ, 371 struct winsys_handle *whandle) 372{ 373 struct r600_screen *rscreen = (struct r600_screen*)screen; 374 struct pb_buffer *buf = NULL; 375 unsigned stride = 0; 376 unsigned array_mode = 0; 377 enum radeon_bo_layout micro, macro; 378 struct radeon_surface surface; 379 int r; 380 381 /* Support only 2D textures without mipmaps */ 382 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 383 templ->depth0 != 1 || templ->last_level != 0) 384 return NULL; 385 386 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); 387 if (!buf) 388 return NULL; 389 390 rscreen->ws->buffer_get_tiling(buf, µ, ¯o, 391 &surface.bankw, &surface.bankh, 392 &surface.tile_split, 393 &surface.stencil_tile_split, 394 &surface.mtilea); 395 396 if (macro == RADEON_LAYOUT_TILED) 397 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 398 else if (micro == RADEON_LAYOUT_TILED) 399 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 400 else 401 array_mode = 0; 402 403 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false); 404 if (r) { 405 return NULL; 406 } 407 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 408 stride, buf, FALSE, &surface); 409} 410 411bool r600_init_flushed_depth_texture(struct pipe_context *ctx, 412 struct pipe_resource *texture, 413 struct r600_resource_texture **staging) 414{ 415 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 416 struct pipe_resource resource; 417 struct r600_resource_texture **flushed_depth_texture = staging ? 418 staging : &rtex->flushed_depth_texture; 419 420 if (!staging && rtex->flushed_depth_texture) 421 return true; /* it's ready */ 422 423 resource.target = texture->target; 424 resource.format = texture->format; 425 resource.width0 = texture->width0; 426 resource.height0 = texture->height0; 427 resource.depth0 = texture->depth0; 428 resource.array_size = texture->array_size; 429 resource.last_level = texture->last_level; 430 resource.nr_samples = texture->nr_samples; 431 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC; 432 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; 433 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH; 434 435 if (staging) 436 resource.flags |= R600_RESOURCE_FLAG_TRANSFER; 437 438 *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); 439 if (*flushed_depth_texture == NULL) { 440 R600_ERR("failed to create temporary texture to hold flushed depth\n"); 441 return false; 442 } 443 444 (*flushed_depth_texture)->is_flushing_texture = TRUE; 445 return true; 446} 447 448/* Needs adjustment for pixelformat: 449 */ 450static INLINE unsigned u_box_volume( const struct pipe_box *box ) 451{ 452 return box->width * box->depth * box->height; 453} 454 455struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 456 struct pipe_resource *texture, 457 unsigned level, 458 unsigned usage, 459 const struct pipe_box *box) 460{ 461 struct r600_context *rctx = (struct r600_context*)ctx; 462 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 463 struct pipe_resource resource; 464 struct r600_transfer *trans; 465 boolean use_staging_texture = FALSE; 466 467 /* We cannot map a tiled texture directly because the data is 468 * in a different order, therefore we do detiling using a blit. 469 * 470 * Also, use a temporary in GTT memory for read transfers, as 471 * the CPU is much happier reading out of cached system memory 472 * than uncached VRAM. 473 */ 474 if (R600_TEX_IS_TILED(rtex, level)) { 475 use_staging_texture = TRUE; 476 } 477 478 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 479 use_staging_texture = TRUE; 480 481 /* Use a staging texture for uploads if the underlying BO is busy. */ 482 if (!(usage & PIPE_TRANSFER_READ) && 483 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) || 484 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) { 485 use_staging_texture = TRUE; 486 } 487 488 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) { 489 use_staging_texture = FALSE; 490 } 491 492 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) { 493 return NULL; 494 } 495 496 trans = CALLOC_STRUCT(r600_transfer); 497 if (trans == NULL) 498 return NULL; 499 pipe_resource_reference(&trans->transfer.resource, texture); 500 trans->transfer.level = level; 501 trans->transfer.usage = usage; 502 trans->transfer.box = *box; 503 if (rtex->is_depth) { 504 /* XXX: only readback the rectangle which is being mapped? 505 */ 506 /* XXX: when discard is true, no need to read back from depth texture 507 */ 508 struct r600_resource_texture *staging_depth; 509 510 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) { 511 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 512 pipe_resource_reference(&trans->transfer.resource, NULL); 513 FREE(trans); 514 return NULL; 515 } 516 517 r600_blit_uncompress_depth(ctx, rtex, staging_depth, 518 level, level, 519 box->z, box->z + box->depth - 1, 520 0, 0); 521 522 trans->transfer.stride = staging_depth->pitch_in_bytes[level]; 523 trans->offset = r600_texture_get_offset(staging_depth, level, box->z); 524 trans->staging = (struct r600_resource*)staging_depth; 525 return &trans->transfer; 526 } else if (use_staging_texture) { 527 resource.target = PIPE_TEXTURE_2D; 528 resource.format = texture->format; 529 resource.width0 = box->width; 530 resource.height0 = box->height; 531 resource.depth0 = 1; 532 resource.array_size = 1; 533 resource.last_level = 0; 534 resource.nr_samples = 0; 535 resource.usage = PIPE_USAGE_STAGING; 536 resource.bind = 0; 537 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 538 /* For texture reading, the temporary (detiled) texture is used as 539 * a render target when blitting from a tiled texture. */ 540 if (usage & PIPE_TRANSFER_READ) { 541 resource.bind |= PIPE_BIND_RENDER_TARGET; 542 } 543 /* For texture writing, the temporary texture is used as a sampler 544 * when blitting into a tiled texture. */ 545 if (usage & PIPE_TRANSFER_WRITE) { 546 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 547 } 548 /* Create the temporary texture. */ 549 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource); 550 if (trans->staging == NULL) { 551 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 552 pipe_resource_reference(&trans->transfer.resource, NULL); 553 FREE(trans); 554 return NULL; 555 } 556 557 trans->transfer.stride = 558 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0]; 559 if (usage & PIPE_TRANSFER_READ) { 560 r600_copy_to_staging_texture(ctx, trans); 561 /* Always referenced in the blit. */ 562 r600_flush(ctx, NULL, 0); 563 } 564 return &trans->transfer; 565 } 566 trans->transfer.stride = rtex->pitch_in_bytes[level]; 567 trans->transfer.layer_stride = rtex->layer_size[level]; 568 trans->offset = r600_texture_get_offset(rtex, level, box->z); 569 return &trans->transfer; 570} 571 572void r600_texture_transfer_destroy(struct pipe_context *ctx, 573 struct pipe_transfer *transfer) 574{ 575 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 576 struct pipe_resource *texture = transfer->resource; 577 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 578 579 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) { 580 if (rtex->is_depth) { 581 ctx->resource_copy_region(ctx, texture, transfer->level, 582 transfer->box.x, transfer->box.y, transfer->box.z, 583 &rtransfer->staging->b.b, transfer->level, 584 &transfer->box); 585 } else { 586 r600_copy_from_staging_texture(ctx, rtransfer); 587 } 588 } 589 590 if (rtransfer->staging) 591 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); 592 593 pipe_resource_reference(&transfer->resource, NULL); 594 FREE(transfer); 595} 596 597void* r600_texture_transfer_map(struct pipe_context *ctx, 598 struct pipe_transfer* transfer) 599{ 600 struct r600_context *rctx = (struct r600_context *)ctx; 601 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 602 struct radeon_winsys_cs_handle *buf; 603 struct r600_resource_texture *rtex = 604 (struct r600_resource_texture*)transfer->resource; 605 enum pipe_format format = transfer->resource->format; 606 unsigned offset = 0; 607 char *map; 608 609 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 610 return r600_compute_global_transfer_map(ctx, transfer); 611 } 612 613 if (rtransfer->staging) { 614 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 615 } else { 616 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 617 } 618 619 if (rtex->is_depth || !rtransfer->staging) 620 offset = rtransfer->offset + 621 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 622 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 623 624 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) { 625 return NULL; 626 } 627 628 return map + offset; 629} 630 631void r600_texture_transfer_unmap(struct pipe_context *ctx, 632 struct pipe_transfer* transfer) 633{ 634 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 635 struct r600_context *rctx = (struct r600_context*)ctx; 636 struct radeon_winsys_cs_handle *buf; 637 638 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 639 return r600_compute_global_transfer_unmap(ctx, transfer); 640 } 641 642 if (rtransfer->staging) { 643 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 644 } else { 645 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 646 } 647 rctx->ws->buffer_unmap(buf); 648} 649 650void r600_init_surface_functions(struct r600_context *r600) 651{ 652 r600->context.create_surface = r600_create_surface; 653 r600->context.surface_destroy = r600_surface_destroy; 654} 655 656static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 657 const unsigned char *swizzle_view) 658{ 659 unsigned i; 660 unsigned char swizzle[4]; 661 unsigned result = 0; 662 const uint32_t swizzle_shift[4] = { 663 16, 19, 22, 25, 664 }; 665 const uint32_t swizzle_bit[4] = { 666 0, 1, 2, 3, 667 }; 668 669 if (swizzle_view) { 670 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 671 } else { 672 memcpy(swizzle, swizzle_format, 4); 673 } 674 675 /* Get swizzle. */ 676 for (i = 0; i < 4; i++) { 677 switch (swizzle[i]) { 678 case UTIL_FORMAT_SWIZZLE_Y: 679 result |= swizzle_bit[1] << swizzle_shift[i]; 680 break; 681 case UTIL_FORMAT_SWIZZLE_Z: 682 result |= swizzle_bit[2] << swizzle_shift[i]; 683 break; 684 case UTIL_FORMAT_SWIZZLE_W: 685 result |= swizzle_bit[3] << swizzle_shift[i]; 686 break; 687 case UTIL_FORMAT_SWIZZLE_0: 688 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 689 break; 690 case UTIL_FORMAT_SWIZZLE_1: 691 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 692 break; 693 default: /* UTIL_FORMAT_SWIZZLE_X */ 694 result |= swizzle_bit[0] << swizzle_shift[i]; 695 } 696 } 697 return result; 698} 699 700/* texture format translate */ 701uint32_t r600_translate_texformat(struct pipe_screen *screen, 702 enum pipe_format format, 703 const unsigned char *swizzle_view, 704 uint32_t *word4_p, uint32_t *yuv_format_p) 705{ 706 uint32_t result = 0, word4 = 0, yuv_format = 0; 707 const struct util_format_description *desc; 708 boolean uniform = TRUE; 709 static int r600_enable_s3tc = -1; 710 bool is_srgb_valid = FALSE; 711 712 int i; 713 const uint32_t sign_bit[4] = { 714 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 715 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 716 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 717 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 718 }; 719 desc = util_format_description(format); 720 721 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 722 723 /* Colorspace (return non-RGB formats directly). */ 724 switch (desc->colorspace) { 725 /* Depth stencil formats */ 726 case UTIL_FORMAT_COLORSPACE_ZS: 727 switch (format) { 728 case PIPE_FORMAT_Z16_UNORM: 729 result = FMT_16; 730 goto out_word4; 731 case PIPE_FORMAT_X24S8_UINT: 732 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 733 case PIPE_FORMAT_Z24X8_UNORM: 734 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 735 result = FMT_8_24; 736 goto out_word4; 737 case PIPE_FORMAT_S8X24_UINT: 738 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 739 case PIPE_FORMAT_X8Z24_UNORM: 740 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 741 result = FMT_24_8; 742 goto out_word4; 743 case PIPE_FORMAT_S8_UINT: 744 result = FMT_8; 745 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 746 goto out_word4; 747 case PIPE_FORMAT_Z32_FLOAT: 748 result = FMT_32_FLOAT; 749 goto out_word4; 750 case PIPE_FORMAT_X32_S8X24_UINT: 751 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 752 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 753 result = FMT_X24_8_32_FLOAT; 754 goto out_word4; 755 default: 756 goto out_unknown; 757 } 758 759 case UTIL_FORMAT_COLORSPACE_YUV: 760 yuv_format |= (1 << 30); 761 switch (format) { 762 case PIPE_FORMAT_UYVY: 763 case PIPE_FORMAT_YUYV: 764 default: 765 break; 766 } 767 goto out_unknown; /* XXX */ 768 769 case UTIL_FORMAT_COLORSPACE_SRGB: 770 word4 |= S_038010_FORCE_DEGAMMA(1); 771 break; 772 773 default: 774 break; 775 } 776 777 if (r600_enable_s3tc == -1) { 778 struct r600_screen *rscreen = (struct r600_screen *)screen; 779 if (rscreen->info.drm_minor >= 9) 780 r600_enable_s3tc = 1; 781 else 782 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 783 } 784 785 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 786 if (!r600_enable_s3tc) 787 goto out_unknown; 788 789 switch (format) { 790 case PIPE_FORMAT_RGTC1_SNORM: 791 case PIPE_FORMAT_LATC1_SNORM: 792 word4 |= sign_bit[0]; 793 case PIPE_FORMAT_RGTC1_UNORM: 794 case PIPE_FORMAT_LATC1_UNORM: 795 result = FMT_BC4; 796 goto out_word4; 797 case PIPE_FORMAT_RGTC2_SNORM: 798 case PIPE_FORMAT_LATC2_SNORM: 799 word4 |= sign_bit[0] | sign_bit[1]; 800 case PIPE_FORMAT_RGTC2_UNORM: 801 case PIPE_FORMAT_LATC2_UNORM: 802 result = FMT_BC5; 803 goto out_word4; 804 default: 805 goto out_unknown; 806 } 807 } 808 809 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 810 811 if (!r600_enable_s3tc) 812 goto out_unknown; 813 814 if (!util_format_s3tc_enabled) { 815 goto out_unknown; 816 } 817 818 switch (format) { 819 case PIPE_FORMAT_DXT1_RGB: 820 case PIPE_FORMAT_DXT1_RGBA: 821 case PIPE_FORMAT_DXT1_SRGB: 822 case PIPE_FORMAT_DXT1_SRGBA: 823 result = FMT_BC1; 824 is_srgb_valid = TRUE; 825 goto out_word4; 826 case PIPE_FORMAT_DXT3_RGBA: 827 case PIPE_FORMAT_DXT3_SRGBA: 828 result = FMT_BC2; 829 is_srgb_valid = TRUE; 830 goto out_word4; 831 case PIPE_FORMAT_DXT5_RGBA: 832 case PIPE_FORMAT_DXT5_SRGBA: 833 result = FMT_BC3; 834 is_srgb_valid = TRUE; 835 goto out_word4; 836 default: 837 goto out_unknown; 838 } 839 } 840 841 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { 842 switch (format) { 843 case PIPE_FORMAT_R8G8_B8G8_UNORM: 844 case PIPE_FORMAT_G8R8_B8R8_UNORM: 845 result = FMT_GB_GR; 846 goto out_word4; 847 case PIPE_FORMAT_G8R8_G8B8_UNORM: 848 case PIPE_FORMAT_R8G8_R8B8_UNORM: 849 result = FMT_BG_RG; 850 goto out_word4; 851 default: 852 goto out_unknown; 853 } 854 } 855 856 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 857 result = FMT_5_9_9_9_SHAREDEXP; 858 goto out_word4; 859 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 860 result = FMT_10_11_11_FLOAT; 861 goto out_word4; 862 } 863 864 865 for (i = 0; i < desc->nr_channels; i++) { 866 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 867 word4 |= sign_bit[i]; 868 } 869 } 870 871 /* R8G8Bx_SNORM - XXX CxV8U8 */ 872 873 /* See whether the components are of the same size. */ 874 for (i = 1; i < desc->nr_channels; i++) { 875 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 876 } 877 878 /* Non-uniform formats. */ 879 if (!uniform) { 880 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 881 desc->channel[0].pure_integer) 882 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 883 switch(desc->nr_channels) { 884 case 3: 885 if (desc->channel[0].size == 5 && 886 desc->channel[1].size == 6 && 887 desc->channel[2].size == 5) { 888 result = FMT_5_6_5; 889 goto out_word4; 890 } 891 goto out_unknown; 892 case 4: 893 if (desc->channel[0].size == 5 && 894 desc->channel[1].size == 5 && 895 desc->channel[2].size == 5 && 896 desc->channel[3].size == 1) { 897 result = FMT_1_5_5_5; 898 goto out_word4; 899 } 900 if (desc->channel[0].size == 10 && 901 desc->channel[1].size == 10 && 902 desc->channel[2].size == 10 && 903 desc->channel[3].size == 2) { 904 result = FMT_2_10_10_10; 905 goto out_word4; 906 } 907 goto out_unknown; 908 } 909 goto out_unknown; 910 } 911 912 /* Find the first non-VOID channel. */ 913 for (i = 0; i < 4; i++) { 914 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 915 break; 916 } 917 } 918 919 if (i == 4) 920 goto out_unknown; 921 922 /* uniform formats */ 923 switch (desc->channel[i].type) { 924 case UTIL_FORMAT_TYPE_UNSIGNED: 925 case UTIL_FORMAT_TYPE_SIGNED: 926#if 0 927 if (!desc->channel[i].normalized && 928 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 929 goto out_unknown; 930 } 931#endif 932 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 933 desc->channel[i].pure_integer) 934 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 935 936 switch (desc->channel[i].size) { 937 case 4: 938 switch (desc->nr_channels) { 939 case 2: 940 result = FMT_4_4; 941 goto out_word4; 942 case 4: 943 result = FMT_4_4_4_4; 944 goto out_word4; 945 } 946 goto out_unknown; 947 case 8: 948 switch (desc->nr_channels) { 949 case 1: 950 result = FMT_8; 951 goto out_word4; 952 case 2: 953 result = FMT_8_8; 954 goto out_word4; 955 case 4: 956 result = FMT_8_8_8_8; 957 is_srgb_valid = TRUE; 958 goto out_word4; 959 } 960 goto out_unknown; 961 case 16: 962 switch (desc->nr_channels) { 963 case 1: 964 result = FMT_16; 965 goto out_word4; 966 case 2: 967 result = FMT_16_16; 968 goto out_word4; 969 case 4: 970 result = FMT_16_16_16_16; 971 goto out_word4; 972 } 973 goto out_unknown; 974 case 32: 975 switch (desc->nr_channels) { 976 case 1: 977 result = FMT_32; 978 goto out_word4; 979 case 2: 980 result = FMT_32_32; 981 goto out_word4; 982 case 4: 983 result = FMT_32_32_32_32; 984 goto out_word4; 985 } 986 } 987 goto out_unknown; 988 989 case UTIL_FORMAT_TYPE_FLOAT: 990 switch (desc->channel[i].size) { 991 case 16: 992 switch (desc->nr_channels) { 993 case 1: 994 result = FMT_16_FLOAT; 995 goto out_word4; 996 case 2: 997 result = FMT_16_16_FLOAT; 998 goto out_word4; 999 case 4: 1000 result = FMT_16_16_16_16_FLOAT; 1001 goto out_word4; 1002 } 1003 goto out_unknown; 1004 case 32: 1005 switch (desc->nr_channels) { 1006 case 1: 1007 result = FMT_32_FLOAT; 1008 goto out_word4; 1009 case 2: 1010 result = FMT_32_32_FLOAT; 1011 goto out_word4; 1012 case 4: 1013 result = FMT_32_32_32_32_FLOAT; 1014 goto out_word4; 1015 } 1016 } 1017 goto out_unknown; 1018 } 1019 1020out_word4: 1021 1022 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid) 1023 return ~0; 1024 if (word4_p) 1025 *word4_p = word4; 1026 if (yuv_format_p) 1027 *yuv_format_p = yuv_format; 1028 return result; 1029out_unknown: 1030 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1031 return ~0; 1032} 1033