r600_texture.c revision 581f7e3101980a4e1068bb75c2eca60bb2071229
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include "r600_formats.h" 28#include "r600d.h" 29 30#include <errno.h> 31#include "util/u_format_s3tc.h" 32#include "util/u_memory.h" 33 34/* Copy from a full GPU texture to a transfer's staging one. */ 35static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 36{ 37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 38 struct pipe_resource *texture = transfer->resource; 39 40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b, 41 0, 0, 0, 0, texture, transfer->level, 42 &transfer->box); 43} 44 45 46/* Copy from a transfer's staging texture to a full GPU one. */ 47static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 48{ 49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 50 struct pipe_resource *texture = transfer->resource; 51 struct pipe_box sbox; 52 53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox); 54 55 ctx->resource_copy_region(ctx, texture, transfer->level, 56 transfer->box.x, transfer->box.y, transfer->box.z, 57 &rtransfer->staging->b.b, 58 0, &sbox); 59} 60 61unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 62 unsigned level, unsigned layer) 63{ 64 return rtex->offset[level] + layer * rtex->layer_size[level]; 65} 66 67static unsigned mip_minify(unsigned size, unsigned level) 68{ 69 unsigned val; 70 val = u_minify(size, level); 71 if (level > 0) 72 val = util_next_power_of_two(val); 73 return val; 74} 75 76static int r600_init_surface(struct r600_screen *rscreen, 77 struct radeon_surface *surface, 78 const struct pipe_resource *ptex, 79 unsigned array_mode, 80 bool is_transfer, bool is_flushed_depth) 81{ 82 const struct util_format_description *desc = 83 util_format_description(ptex->format); 84 bool is_depth, is_stencil; 85 86 is_depth = util_format_has_depth(desc); 87 is_stencil = util_format_has_stencil(desc); 88 89 surface->npix_x = ptex->width0; 90 surface->npix_y = ptex->height0; 91 surface->npix_z = ptex->depth0; 92 surface->blk_w = util_format_get_blockwidth(ptex->format); 93 surface->blk_h = util_format_get_blockheight(ptex->format); 94 surface->blk_d = 1; 95 surface->array_size = 1; 96 surface->last_level = ptex->last_level; 97 98 if (rscreen->chip_class >= EVERGREEN && 99 !is_transfer && !is_flushed_depth && 100 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { 101 surface->bpe = 4; /* stencil is allocated separately on evergreen */ 102 } else { 103 surface->bpe = util_format_get_blocksize(ptex->format); 104 /* align byte per element on dword */ 105 if (surface->bpe == 3) { 106 surface->bpe = 4; 107 } 108 } 109 110 surface->nsamples = 1; 111 surface->flags = 0; 112 switch (array_mode) { 113 case V_038000_ARRAY_1D_TILED_THIN1: 114 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 115 break; 116 case V_038000_ARRAY_2D_TILED_THIN1: 117 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 118 break; 119 case V_038000_ARRAY_LINEAR_ALIGNED: 120 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 121 break; 122 case V_038000_ARRAY_LINEAR_GENERAL: 123 default: 124 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); 125 break; 126 } 127 switch (ptex->target) { 128 case PIPE_TEXTURE_1D: 129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); 130 break; 131 case PIPE_TEXTURE_RECT: 132 case PIPE_TEXTURE_2D: 133 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 134 break; 135 case PIPE_TEXTURE_3D: 136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); 137 break; 138 case PIPE_TEXTURE_1D_ARRAY: 139 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); 140 surface->array_size = ptex->array_size; 141 break; 142 case PIPE_TEXTURE_2D_ARRAY: 143 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); 144 surface->array_size = ptex->array_size; 145 break; 146 case PIPE_TEXTURE_CUBE: 147 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); 148 break; 149 case PIPE_BUFFER: 150 default: 151 return -EINVAL; 152 } 153 if (ptex->bind & PIPE_BIND_SCANOUT) { 154 surface->flags |= RADEON_SURF_SCANOUT; 155 } 156 157 if (!is_transfer && !is_flushed_depth && is_depth) { 158 surface->flags |= RADEON_SURF_ZBUFFER; 159 160 if (is_stencil) { 161 surface->flags |= RADEON_SURF_SBUFFER; 162 } 163 } 164 return 0; 165} 166 167static int r600_setup_surface(struct pipe_screen *screen, 168 struct r600_resource_texture *rtex, 169 unsigned array_mode, 170 unsigned pitch_in_bytes_override) 171{ 172 struct pipe_resource *ptex = &rtex->resource.b.b; 173 struct r600_screen *rscreen = (struct r600_screen*)screen; 174 unsigned i; 175 int r; 176 177 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); 178 if (r) { 179 return r; 180 } 181 rtex->size = rtex->surface.bo_size; 182 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { 183 /* old ddx on evergreen over estimate alignment for 1d, only 1 level 184 * for those 185 */ 186 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; 187 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; 188 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; 189 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 190 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size; 191 } 192 } 193 for (i = 0; i <= ptex->last_level; i++) { 194 rtex->offset[i] = rtex->surface.level[i].offset; 195 rtex->layer_size[i] = rtex->surface.level[i].slice_size; 196 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes; 197 switch (rtex->surface.level[i].mode) { 198 case RADEON_SURF_MODE_LINEAR_ALIGNED: 199 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED; 200 break; 201 case RADEON_SURF_MODE_1D: 202 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1; 203 break; 204 case RADEON_SURF_MODE_2D: 205 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1; 206 break; 207 default: 208 case RADEON_SURF_MODE_LINEAR: 209 rtex->array_mode[i] = 0; 210 break; 211 } 212 } 213 return 0; 214} 215 216static boolean r600_texture_get_handle(struct pipe_screen* screen, 217 struct pipe_resource *ptex, 218 struct winsys_handle *whandle) 219{ 220 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 221 struct r600_resource *resource = &rtex->resource; 222 struct radeon_surface *surface = &rtex->surface; 223 struct r600_screen *rscreen = (struct r600_screen*)screen; 224 225 rscreen->ws->buffer_set_tiling(resource->buf, 226 NULL, 227 surface->level[0].mode >= RADEON_SURF_MODE_1D ? 228 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 229 surface->level[0].mode >= RADEON_SURF_MODE_2D ? 230 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 231 surface->bankw, surface->bankh, 232 surface->tile_split, 233 surface->stencil_tile_split, 234 surface->mtilea, 235 rtex->pitch_in_bytes[0]); 236 237 return rscreen->ws->buffer_get_handle(resource->buf, 238 rtex->pitch_in_bytes[0], whandle); 239} 240 241static void r600_texture_destroy(struct pipe_screen *screen, 242 struct pipe_resource *ptex) 243{ 244 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 245 struct r600_resource *resource = &rtex->resource; 246 247 if (rtex->flushed_depth_texture) 248 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 249 250 pb_reference(&resource->buf, NULL); 251 FREE(rtex); 252} 253 254static const struct u_resource_vtbl r600_texture_vtbl = 255{ 256 r600_texture_get_handle, /* get_handle */ 257 r600_texture_destroy, /* resource_destroy */ 258 r600_texture_get_transfer, /* get_transfer */ 259 r600_texture_transfer_destroy, /* transfer_destroy */ 260 r600_texture_transfer_map, /* transfer_map */ 261 NULL, /* transfer_flush_region */ 262 r600_texture_transfer_unmap, /* transfer_unmap */ 263 NULL /* transfer_inline_write */ 264}; 265 266static struct r600_resource_texture * 267r600_texture_create_object(struct pipe_screen *screen, 268 const struct pipe_resource *base, 269 unsigned array_mode, 270 unsigned pitch_in_bytes_override, 271 unsigned max_buffer_size, 272 struct pb_buffer *buf, 273 boolean alloc_bo, 274 struct radeon_surface *surface) 275{ 276 struct r600_resource_texture *rtex; 277 struct r600_resource *resource; 278 struct r600_screen *rscreen = (struct r600_screen*)screen; 279 int r; 280 281 rtex = CALLOC_STRUCT(r600_resource_texture); 282 if (rtex == NULL) 283 return NULL; 284 285 resource = &rtex->resource; 286 resource->b.b = *base; 287 resource->b.vtbl = &r600_texture_vtbl; 288 pipe_reference_init(&resource->b.b.reference, 1); 289 resource->b.b.screen = screen; 290 rtex->pitch_override = pitch_in_bytes_override; 291 rtex->real_format = base->format; 292 293 /* don't include stencil-only formats which we don't support for rendering */ 294 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format)); 295 296 rtex->surface = *surface; 297 r = r600_setup_surface(screen, rtex, array_mode, 298 pitch_in_bytes_override); 299 if (r) { 300 FREE(rtex); 301 return NULL; 302 } 303 304 /* Now create the backing buffer. */ 305 if (!buf && alloc_bo) { 306 unsigned base_align = rtex->surface.bo_alignment; 307 308 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) { 309 FREE(rtex); 310 return NULL; 311 } 312 } else if (buf) { 313 resource->buf = buf; 314 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); 315 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; 316 } 317 return rtex; 318} 319 320struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 321 const struct pipe_resource *templ) 322{ 323 struct r600_screen *rscreen = (struct r600_screen*)screen; 324 struct radeon_surface surface; 325 unsigned array_mode = 0; 326 int r; 327 328 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) { 329 if (!(templ->bind & PIPE_BIND_SCANOUT) && 330 templ->usage != PIPE_USAGE_STAGING && 331 templ->usage != PIPE_USAGE_STREAM) { 332 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 333 } else if (util_format_is_compressed(templ->format)) { 334 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 335 } 336 } 337 338 r = r600_init_surface(rscreen, &surface, templ, array_mode, 339 templ->flags & R600_RESOURCE_FLAG_TRANSFER, 340 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); 341 if (r) { 342 return NULL; 343 } 344 r = rscreen->ws->surface_best(rscreen->ws, &surface); 345 if (r) { 346 return NULL; 347 } 348 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 349 0, 0, NULL, TRUE, &surface); 350} 351 352static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 353 struct pipe_resource *texture, 354 const struct pipe_surface *surf_tmpl) 355{ 356 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 357 unsigned level = surf_tmpl->u.tex.level; 358 359 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); 360 if (surface == NULL) 361 return NULL; 362 pipe_reference_init(&surface->base.reference, 1); 363 pipe_resource_reference(&surface->base.texture, texture); 364 surface->base.context = pipe; 365 surface->base.format = surf_tmpl->format; 366 surface->base.width = mip_minify(texture->width0, level); 367 surface->base.height = mip_minify(texture->height0, level); 368 surface->base.usage = surf_tmpl->usage; 369 surface->base.texture = texture; 370 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; 371 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; 372 surface->base.u.tex.level = level; 373 return &surface->base; 374} 375 376static void r600_surface_destroy(struct pipe_context *pipe, 377 struct pipe_surface *surface) 378{ 379 pipe_resource_reference(&surface->texture, NULL); 380 FREE(surface); 381} 382 383struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 384 const struct pipe_resource *templ, 385 struct winsys_handle *whandle) 386{ 387 struct r600_screen *rscreen = (struct r600_screen*)screen; 388 struct pb_buffer *buf = NULL; 389 unsigned stride = 0; 390 unsigned array_mode = 0; 391 enum radeon_bo_layout micro, macro; 392 struct radeon_surface surface; 393 int r; 394 395 /* Support only 2D textures without mipmaps */ 396 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 397 templ->depth0 != 1 || templ->last_level != 0) 398 return NULL; 399 400 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); 401 if (!buf) 402 return NULL; 403 404 rscreen->ws->buffer_get_tiling(buf, µ, ¯o, 405 &surface.bankw, &surface.bankh, 406 &surface.tile_split, 407 &surface.stencil_tile_split, 408 &surface.mtilea); 409 410 if (macro == RADEON_LAYOUT_TILED) 411 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 412 else if (micro == RADEON_LAYOUT_TILED) 413 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 414 else 415 array_mode = 0; 416 417 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false); 418 if (r) { 419 return NULL; 420 } 421 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 422 stride, 0, buf, FALSE, &surface); 423} 424 425bool r600_init_flushed_depth_texture(struct pipe_context *ctx, 426 struct pipe_resource *texture, 427 struct r600_resource_texture **staging) 428{ 429 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 430 struct pipe_resource resource; 431 struct r600_resource_texture **flushed_depth_texture = staging ? 432 staging : &rtex->flushed_depth_texture; 433 434 if (!staging && rtex->flushed_depth_texture) 435 return true; /* it's ready */ 436 437 resource.target = texture->target; 438 resource.format = texture->format; 439 resource.width0 = texture->width0; 440 resource.height0 = texture->height0; 441 resource.depth0 = texture->depth0; 442 resource.array_size = texture->array_size; 443 resource.last_level = texture->last_level; 444 resource.nr_samples = texture->nr_samples; 445 resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT; 446 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; 447 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH; 448 449 if (staging) 450 resource.flags |= R600_RESOURCE_FLAG_TRANSFER; 451 452 *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); 453 if (*flushed_depth_texture == NULL) { 454 R600_ERR("failed to create temporary texture to hold flushed depth\n"); 455 return false; 456 } 457 458 (*flushed_depth_texture)->is_flushing_texture = TRUE; 459 return true; 460} 461 462/* Needs adjustment for pixelformat: 463 */ 464static INLINE unsigned u_box_volume( const struct pipe_box *box ) 465{ 466 return box->width * box->depth * box->height; 467} 468 469struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 470 struct pipe_resource *texture, 471 unsigned level, 472 unsigned usage, 473 const struct pipe_box *box) 474{ 475 struct r600_context *rctx = (struct r600_context*)ctx; 476 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 477 struct pipe_resource resource; 478 struct r600_transfer *trans; 479 boolean use_staging_texture = FALSE; 480 481 /* We cannot map a tiled texture directly because the data is 482 * in a different order, therefore we do detiling using a blit. 483 * 484 * Also, use a temporary in GTT memory for read transfers, as 485 * the CPU is much happier reading out of cached system memory 486 * than uncached VRAM. 487 */ 488 if (R600_TEX_IS_TILED(rtex, level)) { 489 use_staging_texture = TRUE; 490 } 491 492 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 493 use_staging_texture = TRUE; 494 495 /* Use a staging texture for uploads if the underlying BO is busy. */ 496 if (!(usage & PIPE_TRANSFER_READ) && 497 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) || 498 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) { 499 use_staging_texture = TRUE; 500 } 501 502 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) { 503 use_staging_texture = FALSE; 504 } 505 506 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) { 507 return NULL; 508 } 509 510 trans = CALLOC_STRUCT(r600_transfer); 511 if (trans == NULL) 512 return NULL; 513 pipe_resource_reference(&trans->transfer.resource, texture); 514 trans->transfer.level = level; 515 trans->transfer.usage = usage; 516 trans->transfer.box = *box; 517 if (rtex->is_depth) { 518 /* XXX: only readback the rectangle which is being mapped? 519 */ 520 /* XXX: when discard is true, no need to read back from depth texture 521 */ 522 struct r600_resource_texture *staging_depth; 523 524 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) { 525 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 526 pipe_resource_reference(&trans->transfer.resource, NULL); 527 FREE(trans); 528 return NULL; 529 } 530 531 r600_blit_uncompress_depth(ctx, rtex, staging_depth, 532 level, level, 533 box->z, box->z + box->depth - 1); 534 535 trans->transfer.stride = staging_depth->pitch_in_bytes[level]; 536 trans->offset = r600_texture_get_offset(staging_depth, level, box->z); 537 trans->staging = (struct r600_resource*)staging_depth; 538 return &trans->transfer; 539 } else if (use_staging_texture) { 540 resource.target = PIPE_TEXTURE_2D; 541 resource.format = texture->format; 542 resource.width0 = box->width; 543 resource.height0 = box->height; 544 resource.depth0 = 1; 545 resource.array_size = 1; 546 resource.last_level = 0; 547 resource.nr_samples = 0; 548 resource.usage = PIPE_USAGE_STAGING; 549 resource.bind = 0; 550 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 551 /* For texture reading, the temporary (detiled) texture is used as 552 * a render target when blitting from a tiled texture. */ 553 if (usage & PIPE_TRANSFER_READ) { 554 resource.bind |= PIPE_BIND_RENDER_TARGET; 555 } 556 /* For texture writing, the temporary texture is used as a sampler 557 * when blitting into a tiled texture. */ 558 if (usage & PIPE_TRANSFER_WRITE) { 559 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 560 } 561 /* Create the temporary texture. */ 562 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource); 563 if (trans->staging == NULL) { 564 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 565 pipe_resource_reference(&trans->transfer.resource, NULL); 566 FREE(trans); 567 return NULL; 568 } 569 570 trans->transfer.stride = 571 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0]; 572 if (usage & PIPE_TRANSFER_READ) { 573 r600_copy_to_staging_texture(ctx, trans); 574 /* Always referenced in the blit. */ 575 r600_flush(ctx, NULL, 0); 576 } 577 return &trans->transfer; 578 } 579 trans->transfer.stride = rtex->pitch_in_bytes[level]; 580 trans->transfer.layer_stride = rtex->layer_size[level]; 581 trans->offset = r600_texture_get_offset(rtex, level, box->z); 582 return &trans->transfer; 583} 584 585void r600_texture_transfer_destroy(struct pipe_context *ctx, 586 struct pipe_transfer *transfer) 587{ 588 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 589 struct pipe_resource *texture = transfer->resource; 590 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 591 592 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) { 593 if (rtex->is_depth) { 594 ctx->resource_copy_region(ctx, texture, transfer->level, 595 transfer->box.x, transfer->box.y, transfer->box.z, 596 &rtransfer->staging->b.b, transfer->level, 597 &transfer->box); 598 } else { 599 r600_copy_from_staging_texture(ctx, rtransfer); 600 } 601 } 602 603 if (rtransfer->staging) 604 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); 605 606 pipe_resource_reference(&transfer->resource, NULL); 607 FREE(transfer); 608} 609 610void* r600_texture_transfer_map(struct pipe_context *ctx, 611 struct pipe_transfer* transfer) 612{ 613 struct r600_context *rctx = (struct r600_context *)ctx; 614 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 615 struct radeon_winsys_cs_handle *buf; 616 struct r600_resource_texture *rtex = 617 (struct r600_resource_texture*)transfer->resource; 618 enum pipe_format format = transfer->resource->format; 619 unsigned offset = 0; 620 char *map; 621 622 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 623 return r600_compute_global_transfer_map(ctx, transfer); 624 } 625 626 if (rtransfer->staging) { 627 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 628 } else { 629 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 630 } 631 632 if (rtex->is_depth || !rtransfer->staging) 633 offset = rtransfer->offset + 634 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 635 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 636 637 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) { 638 return NULL; 639 } 640 641 return map + offset; 642} 643 644void r600_texture_transfer_unmap(struct pipe_context *ctx, 645 struct pipe_transfer* transfer) 646{ 647 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 648 struct r600_context *rctx = (struct r600_context*)ctx; 649 struct radeon_winsys_cs_handle *buf; 650 651 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 652 return r600_compute_global_transfer_unmap(ctx, transfer); 653 } 654 655 if (rtransfer->staging) { 656 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 657 } else { 658 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 659 } 660 rctx->ws->buffer_unmap(buf); 661} 662 663void r600_init_surface_functions(struct r600_context *r600) 664{ 665 r600->context.create_surface = r600_create_surface; 666 r600->context.surface_destroy = r600_surface_destroy; 667} 668 669static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 670 const unsigned char *swizzle_view) 671{ 672 unsigned i; 673 unsigned char swizzle[4]; 674 unsigned result = 0; 675 const uint32_t swizzle_shift[4] = { 676 16, 19, 22, 25, 677 }; 678 const uint32_t swizzle_bit[4] = { 679 0, 1, 2, 3, 680 }; 681 682 if (swizzle_view) { 683 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 684 } else { 685 memcpy(swizzle, swizzle_format, 4); 686 } 687 688 /* Get swizzle. */ 689 for (i = 0; i < 4; i++) { 690 switch (swizzle[i]) { 691 case UTIL_FORMAT_SWIZZLE_Y: 692 result |= swizzle_bit[1] << swizzle_shift[i]; 693 break; 694 case UTIL_FORMAT_SWIZZLE_Z: 695 result |= swizzle_bit[2] << swizzle_shift[i]; 696 break; 697 case UTIL_FORMAT_SWIZZLE_W: 698 result |= swizzle_bit[3] << swizzle_shift[i]; 699 break; 700 case UTIL_FORMAT_SWIZZLE_0: 701 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 702 break; 703 case UTIL_FORMAT_SWIZZLE_1: 704 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 705 break; 706 default: /* UTIL_FORMAT_SWIZZLE_X */ 707 result |= swizzle_bit[0] << swizzle_shift[i]; 708 } 709 } 710 return result; 711} 712 713/* texture format translate */ 714uint32_t r600_translate_texformat(struct pipe_screen *screen, 715 enum pipe_format format, 716 const unsigned char *swizzle_view, 717 uint32_t *word4_p, uint32_t *yuv_format_p) 718{ 719 uint32_t result = 0, word4 = 0, yuv_format = 0; 720 const struct util_format_description *desc; 721 boolean uniform = TRUE; 722 static int r600_enable_s3tc = -1; 723 bool is_srgb_valid = FALSE; 724 725 int i; 726 const uint32_t sign_bit[4] = { 727 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 728 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 729 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 730 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 731 }; 732 desc = util_format_description(format); 733 734 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 735 736 /* Colorspace (return non-RGB formats directly). */ 737 switch (desc->colorspace) { 738 /* Depth stencil formats */ 739 case UTIL_FORMAT_COLORSPACE_ZS: 740 switch (format) { 741 case PIPE_FORMAT_Z16_UNORM: 742 result = FMT_16; 743 goto out_word4; 744 case PIPE_FORMAT_X24S8_UINT: 745 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 746 case PIPE_FORMAT_Z24X8_UNORM: 747 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 748 result = FMT_8_24; 749 goto out_word4; 750 case PIPE_FORMAT_S8X24_UINT: 751 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 752 case PIPE_FORMAT_X8Z24_UNORM: 753 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 754 result = FMT_24_8; 755 goto out_word4; 756 case PIPE_FORMAT_S8_UINT: 757 result = FMT_8; 758 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 759 goto out_word4; 760 case PIPE_FORMAT_Z32_FLOAT: 761 result = FMT_32_FLOAT; 762 goto out_word4; 763 case PIPE_FORMAT_X32_S8X24_UINT: 764 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 765 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 766 result = FMT_X24_8_32_FLOAT; 767 goto out_word4; 768 default: 769 goto out_unknown; 770 } 771 772 case UTIL_FORMAT_COLORSPACE_YUV: 773 yuv_format |= (1 << 30); 774 switch (format) { 775 case PIPE_FORMAT_UYVY: 776 case PIPE_FORMAT_YUYV: 777 default: 778 break; 779 } 780 goto out_unknown; /* XXX */ 781 782 case UTIL_FORMAT_COLORSPACE_SRGB: 783 word4 |= S_038010_FORCE_DEGAMMA(1); 784 break; 785 786 default: 787 break; 788 } 789 790 if (r600_enable_s3tc == -1) { 791 struct r600_screen *rscreen = (struct r600_screen *)screen; 792 if (rscreen->info.drm_minor >= 9) 793 r600_enable_s3tc = 1; 794 else 795 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 796 } 797 798 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 799 if (!r600_enable_s3tc) 800 goto out_unknown; 801 802 switch (format) { 803 case PIPE_FORMAT_RGTC1_SNORM: 804 case PIPE_FORMAT_LATC1_SNORM: 805 word4 |= sign_bit[0]; 806 case PIPE_FORMAT_RGTC1_UNORM: 807 case PIPE_FORMAT_LATC1_UNORM: 808 result = FMT_BC4; 809 goto out_word4; 810 case PIPE_FORMAT_RGTC2_SNORM: 811 case PIPE_FORMAT_LATC2_SNORM: 812 word4 |= sign_bit[0] | sign_bit[1]; 813 case PIPE_FORMAT_RGTC2_UNORM: 814 case PIPE_FORMAT_LATC2_UNORM: 815 result = FMT_BC5; 816 goto out_word4; 817 default: 818 goto out_unknown; 819 } 820 } 821 822 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 823 824 if (!r600_enable_s3tc) 825 goto out_unknown; 826 827 if (!util_format_s3tc_enabled) { 828 goto out_unknown; 829 } 830 831 switch (format) { 832 case PIPE_FORMAT_DXT1_RGB: 833 case PIPE_FORMAT_DXT1_RGBA: 834 case PIPE_FORMAT_DXT1_SRGB: 835 case PIPE_FORMAT_DXT1_SRGBA: 836 result = FMT_BC1; 837 is_srgb_valid = TRUE; 838 goto out_word4; 839 case PIPE_FORMAT_DXT3_RGBA: 840 case PIPE_FORMAT_DXT3_SRGBA: 841 result = FMT_BC2; 842 is_srgb_valid = TRUE; 843 goto out_word4; 844 case PIPE_FORMAT_DXT5_RGBA: 845 case PIPE_FORMAT_DXT5_SRGBA: 846 result = FMT_BC3; 847 is_srgb_valid = TRUE; 848 goto out_word4; 849 default: 850 goto out_unknown; 851 } 852 } 853 854 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { 855 switch (format) { 856 case PIPE_FORMAT_R8G8_B8G8_UNORM: 857 case PIPE_FORMAT_G8R8_B8R8_UNORM: 858 result = FMT_GB_GR; 859 goto out_word4; 860 case PIPE_FORMAT_G8R8_G8B8_UNORM: 861 case PIPE_FORMAT_R8G8_R8B8_UNORM: 862 result = FMT_BG_RG; 863 goto out_word4; 864 default: 865 goto out_unknown; 866 } 867 } 868 869 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 870 result = FMT_5_9_9_9_SHAREDEXP; 871 goto out_word4; 872 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 873 result = FMT_10_11_11_FLOAT; 874 goto out_word4; 875 } 876 877 878 for (i = 0; i < desc->nr_channels; i++) { 879 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 880 word4 |= sign_bit[i]; 881 } 882 } 883 884 /* R8G8Bx_SNORM - XXX CxV8U8 */ 885 886 /* See whether the components are of the same size. */ 887 for (i = 1; i < desc->nr_channels; i++) { 888 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 889 } 890 891 /* Non-uniform formats. */ 892 if (!uniform) { 893 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 894 desc->channel[0].pure_integer) 895 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 896 switch(desc->nr_channels) { 897 case 3: 898 if (desc->channel[0].size == 5 && 899 desc->channel[1].size == 6 && 900 desc->channel[2].size == 5) { 901 result = FMT_5_6_5; 902 goto out_word4; 903 } 904 goto out_unknown; 905 case 4: 906 if (desc->channel[0].size == 5 && 907 desc->channel[1].size == 5 && 908 desc->channel[2].size == 5 && 909 desc->channel[3].size == 1) { 910 result = FMT_1_5_5_5; 911 goto out_word4; 912 } 913 if (desc->channel[0].size == 10 && 914 desc->channel[1].size == 10 && 915 desc->channel[2].size == 10 && 916 desc->channel[3].size == 2) { 917 result = FMT_2_10_10_10; 918 goto out_word4; 919 } 920 goto out_unknown; 921 } 922 goto out_unknown; 923 } 924 925 /* Find the first non-VOID channel. */ 926 for (i = 0; i < 4; i++) { 927 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 928 break; 929 } 930 } 931 932 if (i == 4) 933 goto out_unknown; 934 935 /* uniform formats */ 936 switch (desc->channel[i].type) { 937 case UTIL_FORMAT_TYPE_UNSIGNED: 938 case UTIL_FORMAT_TYPE_SIGNED: 939#if 0 940 if (!desc->channel[i].normalized && 941 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 942 goto out_unknown; 943 } 944#endif 945 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 946 desc->channel[i].pure_integer) 947 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 948 949 switch (desc->channel[i].size) { 950 case 4: 951 switch (desc->nr_channels) { 952 case 2: 953 result = FMT_4_4; 954 goto out_word4; 955 case 4: 956 result = FMT_4_4_4_4; 957 goto out_word4; 958 } 959 goto out_unknown; 960 case 8: 961 switch (desc->nr_channels) { 962 case 1: 963 result = FMT_8; 964 goto out_word4; 965 case 2: 966 result = FMT_8_8; 967 goto out_word4; 968 case 4: 969 result = FMT_8_8_8_8; 970 is_srgb_valid = TRUE; 971 goto out_word4; 972 } 973 goto out_unknown; 974 case 16: 975 switch (desc->nr_channels) { 976 case 1: 977 result = FMT_16; 978 goto out_word4; 979 case 2: 980 result = FMT_16_16; 981 goto out_word4; 982 case 4: 983 result = FMT_16_16_16_16; 984 goto out_word4; 985 } 986 goto out_unknown; 987 case 32: 988 switch (desc->nr_channels) { 989 case 1: 990 result = FMT_32; 991 goto out_word4; 992 case 2: 993 result = FMT_32_32; 994 goto out_word4; 995 case 4: 996 result = FMT_32_32_32_32; 997 goto out_word4; 998 } 999 } 1000 goto out_unknown; 1001 1002 case UTIL_FORMAT_TYPE_FLOAT: 1003 switch (desc->channel[i].size) { 1004 case 16: 1005 switch (desc->nr_channels) { 1006 case 1: 1007 result = FMT_16_FLOAT; 1008 goto out_word4; 1009 case 2: 1010 result = FMT_16_16_FLOAT; 1011 goto out_word4; 1012 case 4: 1013 result = FMT_16_16_16_16_FLOAT; 1014 goto out_word4; 1015 } 1016 goto out_unknown; 1017 case 32: 1018 switch (desc->nr_channels) { 1019 case 1: 1020 result = FMT_32_FLOAT; 1021 goto out_word4; 1022 case 2: 1023 result = FMT_32_32_FLOAT; 1024 goto out_word4; 1025 case 4: 1026 result = FMT_32_32_32_32_FLOAT; 1027 goto out_word4; 1028 } 1029 } 1030 goto out_unknown; 1031 } 1032 1033out_word4: 1034 1035 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid) 1036 return ~0; 1037 if (word4_p) 1038 *word4_p = word4; 1039 if (yuv_format_p) 1040 *yuv_format_p = yuv_format; 1041 return result; 1042out_unknown: 1043 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1044 return ~0; 1045} 1046