r600_texture.c revision 6fd9218bb44b8719da60ce325d4f41c4a611e871
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include "r600_formats.h" 28#include "r600d.h" 29 30#include <errno.h> 31#include "util/u_format_s3tc.h" 32#include "util/u_memory.h" 33 34/* Copy from a full GPU texture to a transfer's staging one. */ 35static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 36{ 37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 38 struct pipe_resource *texture = transfer->resource; 39 40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b, 41 0, 0, 0, 0, texture, transfer->level, 42 &transfer->box); 43} 44 45 46/* Copy from a transfer's staging texture to a full GPU one. */ 47static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 48{ 49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 50 struct pipe_resource *texture = transfer->resource; 51 struct pipe_box sbox; 52 53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox); 54 55 ctx->resource_copy_region(ctx, texture, transfer->level, 56 transfer->box.x, transfer->box.y, transfer->box.z, 57 &rtransfer->staging->b.b, 58 0, &sbox); 59} 60 61unsigned r600_texture_get_offset(struct r600_texture *rtex, 62 unsigned level, unsigned layer) 63{ 64 return rtex->surface.level[level].offset + 65 layer * rtex->surface.level[level].slice_size; 66} 67 68static int r600_init_surface(struct r600_screen *rscreen, 69 struct radeon_surface *surface, 70 const struct pipe_resource *ptex, 71 unsigned array_mode, 72 bool is_transfer, bool is_flushed_depth) 73{ 74 const struct util_format_description *desc = 75 util_format_description(ptex->format); 76 bool is_depth, is_stencil; 77 78 is_depth = util_format_has_depth(desc); 79 is_stencil = util_format_has_stencil(desc); 80 81 surface->npix_x = ptex->width0; 82 surface->npix_y = ptex->height0; 83 surface->npix_z = ptex->depth0; 84 surface->blk_w = util_format_get_blockwidth(ptex->format); 85 surface->blk_h = util_format_get_blockheight(ptex->format); 86 surface->blk_d = 1; 87 surface->array_size = 1; 88 surface->last_level = ptex->last_level; 89 90 if (rscreen->chip_class >= EVERGREEN && 91 !is_transfer && !is_flushed_depth && 92 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { 93 surface->bpe = 4; /* stencil is allocated separately on evergreen */ 94 } else { 95 surface->bpe = util_format_get_blocksize(ptex->format); 96 /* align byte per element on dword */ 97 if (surface->bpe == 3) { 98 surface->bpe = 4; 99 } 100 } 101 102 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1; 103 surface->flags = 0; 104 105 switch (array_mode) { 106 case V_038000_ARRAY_1D_TILED_THIN1: 107 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 108 break; 109 case V_038000_ARRAY_2D_TILED_THIN1: 110 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 111 break; 112 case V_038000_ARRAY_LINEAR_ALIGNED: 113 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 114 break; 115 case V_038000_ARRAY_LINEAR_GENERAL: 116 default: 117 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); 118 break; 119 } 120 switch (ptex->target) { 121 case PIPE_TEXTURE_1D: 122 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); 123 break; 124 case PIPE_TEXTURE_RECT: 125 case PIPE_TEXTURE_2D: 126 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 127 break; 128 case PIPE_TEXTURE_3D: 129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); 130 break; 131 case PIPE_TEXTURE_1D_ARRAY: 132 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); 133 surface->array_size = ptex->array_size; 134 break; 135 case PIPE_TEXTURE_2D_ARRAY: 136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); 137 surface->array_size = ptex->array_size; 138 break; 139 case PIPE_TEXTURE_CUBE: 140 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); 141 break; 142 case PIPE_BUFFER: 143 default: 144 return -EINVAL; 145 } 146 if (ptex->bind & PIPE_BIND_SCANOUT) { 147 surface->flags |= RADEON_SURF_SCANOUT; 148 } 149 150 if (!is_transfer && !is_flushed_depth && is_depth) { 151 surface->flags |= RADEON_SURF_ZBUFFER; 152 153 if (is_stencil) { 154 surface->flags |= RADEON_SURF_SBUFFER; 155 } 156 } 157 return 0; 158} 159 160static int r600_setup_surface(struct pipe_screen *screen, 161 struct r600_texture *rtex, 162 unsigned pitch_in_bytes_override) 163{ 164 struct pipe_resource *ptex = &rtex->resource.b.b; 165 struct r600_screen *rscreen = (struct r600_screen*)screen; 166 unsigned i; 167 int r; 168 169 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); 170 if (r) { 171 return r; 172 } 173 rtex->size = rtex->surface.bo_size; 174 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { 175 /* old ddx on evergreen over estimate alignment for 1d, only 1 level 176 * for those 177 */ 178 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; 179 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; 180 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; 181 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 182 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size; 183 } 184 } 185 for (i = 0; i <= ptex->last_level; i++) { 186 switch (rtex->surface.level[i].mode) { 187 case RADEON_SURF_MODE_LINEAR_ALIGNED: 188 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED; 189 break; 190 case RADEON_SURF_MODE_1D: 191 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1; 192 break; 193 case RADEON_SURF_MODE_2D: 194 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1; 195 break; 196 default: 197 case RADEON_SURF_MODE_LINEAR: 198 rtex->array_mode[i] = 0; 199 break; 200 } 201 } 202 return 0; 203} 204 205static boolean r600_texture_get_handle(struct pipe_screen* screen, 206 struct pipe_resource *ptex, 207 struct winsys_handle *whandle) 208{ 209 struct r600_texture *rtex = (struct r600_texture*)ptex; 210 struct r600_resource *resource = &rtex->resource; 211 struct radeon_surface *surface = &rtex->surface; 212 struct r600_screen *rscreen = (struct r600_screen*)screen; 213 214 rscreen->ws->buffer_set_tiling(resource->buf, 215 NULL, 216 surface->level[0].mode >= RADEON_SURF_MODE_1D ? 217 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 218 surface->level[0].mode >= RADEON_SURF_MODE_2D ? 219 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 220 surface->bankw, surface->bankh, 221 surface->tile_split, 222 surface->stencil_tile_split, 223 surface->mtilea, 224 rtex->surface.level[0].pitch_bytes); 225 226 return rscreen->ws->buffer_get_handle(resource->buf, 227 rtex->surface.level[0].pitch_bytes, whandle); 228} 229 230static void r600_texture_destroy(struct pipe_screen *screen, 231 struct pipe_resource *ptex) 232{ 233 struct r600_texture *rtex = (struct r600_texture*)ptex; 234 struct r600_resource *resource = &rtex->resource; 235 236 if (rtex->flushed_depth_texture) 237 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 238 239 pb_reference(&resource->buf, NULL); 240 FREE(rtex); 241} 242 243static const struct u_resource_vtbl r600_texture_vtbl = 244{ 245 r600_texture_get_handle, /* get_handle */ 246 r600_texture_destroy, /* resource_destroy */ 247 r600_texture_get_transfer, /* get_transfer */ 248 r600_texture_transfer_destroy, /* transfer_destroy */ 249 r600_texture_transfer_map, /* transfer_map */ 250 NULL, /* transfer_flush_region */ 251 r600_texture_transfer_unmap, /* transfer_unmap */ 252 NULL /* transfer_inline_write */ 253}; 254 255static struct r600_texture * 256r600_texture_create_object(struct pipe_screen *screen, 257 const struct pipe_resource *base, 258 unsigned pitch_in_bytes_override, 259 struct pb_buffer *buf, 260 boolean alloc_bo, 261 struct radeon_surface *surface) 262{ 263 struct r600_texture *rtex; 264 struct r600_resource *resource; 265 struct r600_screen *rscreen = (struct r600_screen*)screen; 266 int r; 267 268 rtex = CALLOC_STRUCT(r600_texture); 269 if (rtex == NULL) 270 return NULL; 271 272 resource = &rtex->resource; 273 resource->b.b = *base; 274 resource->b.vtbl = &r600_texture_vtbl; 275 pipe_reference_init(&resource->b.b.reference, 1); 276 resource->b.b.screen = screen; 277 rtex->pitch_override = pitch_in_bytes_override; 278 279 /* don't include stencil-only formats which we don't support for rendering */ 280 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format)); 281 282 rtex->surface = *surface; 283 r = r600_setup_surface(screen, rtex, 284 pitch_in_bytes_override); 285 if (r) { 286 FREE(rtex); 287 return NULL; 288 } 289 290 /* Now create the backing buffer. */ 291 if (!buf && alloc_bo) { 292 unsigned base_align = rtex->surface.bo_alignment; 293 unsigned usage = R600_TEX_IS_TILED(rtex, 0) ? PIPE_USAGE_STATIC : base->usage; 294 295 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, usage)) { 296 FREE(rtex); 297 return NULL; 298 } 299 } else if (buf) { 300 resource->buf = buf; 301 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); 302 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; 303 } 304 return rtex; 305} 306 307struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 308 const struct pipe_resource *templ) 309{ 310 struct r600_screen *rscreen = (struct r600_screen*)screen; 311 struct radeon_surface surface; 312 unsigned array_mode = 0; 313 int r; 314 315 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) { 316 if (!(templ->bind & PIPE_BIND_SCANOUT) && 317 templ->usage != PIPE_USAGE_STAGING && 318 templ->usage != PIPE_USAGE_STREAM) { 319 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 320 } else if (util_format_is_compressed(templ->format)) { 321 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 322 } 323 } 324 325 r = r600_init_surface(rscreen, &surface, templ, array_mode, 326 templ->flags & R600_RESOURCE_FLAG_TRANSFER, 327 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); 328 if (r) { 329 return NULL; 330 } 331 r = rscreen->ws->surface_best(rscreen->ws, &surface); 332 if (r) { 333 return NULL; 334 } 335 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 336 0, NULL, TRUE, &surface); 337} 338 339static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 340 struct pipe_resource *texture, 341 const struct pipe_surface *templ) 342{ 343 struct r600_texture *rtex = (struct r600_texture*)texture; 344 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 345 unsigned level = templ->u.tex.level; 346 347 assert(templ->u.tex.first_layer == templ->u.tex.last_layer); 348 if (surface == NULL) 349 return NULL; 350 pipe_reference_init(&surface->base.reference, 1); 351 pipe_resource_reference(&surface->base.texture, texture); 352 surface->base.context = pipe; 353 surface->base.format = templ->format; 354 surface->base.width = rtex->surface.level[level].npix_x; 355 surface->base.height = rtex->surface.level[level].npix_y; 356 surface->base.usage = templ->usage; 357 surface->base.u = templ->u; 358 return &surface->base; 359} 360 361static void r600_surface_destroy(struct pipe_context *pipe, 362 struct pipe_surface *surface) 363{ 364 pipe_resource_reference(&surface->texture, NULL); 365 FREE(surface); 366} 367 368struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 369 const struct pipe_resource *templ, 370 struct winsys_handle *whandle) 371{ 372 struct r600_screen *rscreen = (struct r600_screen*)screen; 373 struct pb_buffer *buf = NULL; 374 unsigned stride = 0; 375 unsigned array_mode = 0; 376 enum radeon_bo_layout micro, macro; 377 struct radeon_surface surface; 378 int r; 379 380 /* Support only 2D textures without mipmaps */ 381 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 382 templ->depth0 != 1 || templ->last_level != 0) 383 return NULL; 384 385 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); 386 if (!buf) 387 return NULL; 388 389 rscreen->ws->buffer_get_tiling(buf, µ, ¯o, 390 &surface.bankw, &surface.bankh, 391 &surface.tile_split, 392 &surface.stencil_tile_split, 393 &surface.mtilea); 394 395 if (macro == RADEON_LAYOUT_TILED) 396 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 397 else if (micro == RADEON_LAYOUT_TILED) 398 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 399 else 400 array_mode = 0; 401 402 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false); 403 if (r) { 404 return NULL; 405 } 406 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 407 stride, buf, FALSE, &surface); 408} 409 410bool r600_init_flushed_depth_texture(struct pipe_context *ctx, 411 struct pipe_resource *texture, 412 struct r600_texture **staging) 413{ 414 struct r600_texture *rtex = (struct r600_texture*)texture; 415 struct pipe_resource resource; 416 struct r600_texture **flushed_depth_texture = staging ? 417 staging : &rtex->flushed_depth_texture; 418 419 if (!staging && rtex->flushed_depth_texture) 420 return true; /* it's ready */ 421 422 resource.target = texture->target; 423 resource.format = texture->format; 424 resource.width0 = texture->width0; 425 resource.height0 = texture->height0; 426 resource.depth0 = texture->depth0; 427 resource.array_size = texture->array_size; 428 resource.last_level = texture->last_level; 429 resource.nr_samples = texture->nr_samples; 430 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC; 431 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; 432 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH; 433 434 if (staging) 435 resource.flags |= R600_RESOURCE_FLAG_TRANSFER; 436 437 *flushed_depth_texture = (struct r600_texture *)ctx->screen->resource_create(ctx->screen, &resource); 438 if (*flushed_depth_texture == NULL) { 439 R600_ERR("failed to create temporary texture to hold flushed depth\n"); 440 return false; 441 } 442 443 (*flushed_depth_texture)->is_flushing_texture = TRUE; 444 return true; 445} 446 447/* Needs adjustment for pixelformat: 448 */ 449static INLINE unsigned u_box_volume( const struct pipe_box *box ) 450{ 451 return box->width * box->depth * box->height; 452} 453 454struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 455 struct pipe_resource *texture, 456 unsigned level, 457 unsigned usage, 458 const struct pipe_box *box) 459{ 460 struct r600_context *rctx = (struct r600_context*)ctx; 461 struct r600_texture *rtex = (struct r600_texture*)texture; 462 struct pipe_resource resource; 463 struct r600_transfer *trans; 464 boolean use_staging_texture = FALSE; 465 466 /* We cannot map a tiled texture directly because the data is 467 * in a different order, therefore we do detiling using a blit. 468 * 469 * Also, use a temporary in GTT memory for read transfers, as 470 * the CPU is much happier reading out of cached system memory 471 * than uncached VRAM. 472 */ 473 if (R600_TEX_IS_TILED(rtex, level)) { 474 use_staging_texture = TRUE; 475 } 476 477 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 478 use_staging_texture = TRUE; 479 480 /* Use a staging texture for uploads if the underlying BO is busy. */ 481 if (!(usage & PIPE_TRANSFER_READ) && 482 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) || 483 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) { 484 use_staging_texture = TRUE; 485 } 486 487 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) { 488 use_staging_texture = FALSE; 489 } 490 491 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) { 492 return NULL; 493 } 494 495 trans = CALLOC_STRUCT(r600_transfer); 496 if (trans == NULL) 497 return NULL; 498 pipe_resource_reference(&trans->transfer.resource, texture); 499 trans->transfer.level = level; 500 trans->transfer.usage = usage; 501 trans->transfer.box = *box; 502 if (rtex->is_depth) { 503 /* XXX: only readback the rectangle which is being mapped? 504 */ 505 /* XXX: when discard is true, no need to read back from depth texture 506 */ 507 struct r600_texture *staging_depth; 508 509 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) { 510 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 511 pipe_resource_reference(&trans->transfer.resource, NULL); 512 FREE(trans); 513 return NULL; 514 } 515 516 r600_blit_uncompress_depth(ctx, rtex, staging_depth, 517 level, level, 518 box->z, box->z + box->depth - 1, 519 0, 0); 520 521 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes; 522 trans->offset = r600_texture_get_offset(staging_depth, level, box->z); 523 trans->staging = (struct r600_resource*)staging_depth; 524 return &trans->transfer; 525 } else if (use_staging_texture) { 526 resource.target = PIPE_TEXTURE_2D; 527 resource.format = texture->format; 528 resource.width0 = box->width; 529 resource.height0 = box->height; 530 resource.depth0 = 1; 531 resource.array_size = 1; 532 resource.last_level = 0; 533 resource.nr_samples = 0; 534 resource.usage = PIPE_USAGE_STAGING; 535 resource.bind = 0; 536 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 537 /* For texture reading, the temporary (detiled) texture is used as 538 * a render target when blitting from a tiled texture. */ 539 if (usage & PIPE_TRANSFER_READ) { 540 resource.bind |= PIPE_BIND_RENDER_TARGET; 541 } 542 /* For texture writing, the temporary texture is used as a sampler 543 * when blitting into a tiled texture. */ 544 if (usage & PIPE_TRANSFER_WRITE) { 545 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 546 } 547 /* Create the temporary texture. */ 548 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource); 549 if (trans->staging == NULL) { 550 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 551 pipe_resource_reference(&trans->transfer.resource, NULL); 552 FREE(trans); 553 return NULL; 554 } 555 556 trans->transfer.stride = 557 ((struct r600_texture *)trans->staging)->surface.level[0].pitch_bytes; 558 if (usage & PIPE_TRANSFER_READ) { 559 r600_copy_to_staging_texture(ctx, trans); 560 /* Always referenced in the blit. */ 561 r600_flush(ctx, NULL, 0); 562 } 563 return &trans->transfer; 564 } 565 trans->transfer.stride = rtex->surface.level[level].pitch_bytes; 566 trans->transfer.layer_stride = rtex->surface.level[level].slice_size; 567 trans->offset = r600_texture_get_offset(rtex, level, box->z); 568 return &trans->transfer; 569} 570 571void r600_texture_transfer_destroy(struct pipe_context *ctx, 572 struct pipe_transfer *transfer) 573{ 574 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 575 struct pipe_resource *texture = transfer->resource; 576 struct r600_texture *rtex = (struct r600_texture*)texture; 577 578 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) { 579 if (rtex->is_depth) { 580 ctx->resource_copy_region(ctx, texture, transfer->level, 581 transfer->box.x, transfer->box.y, transfer->box.z, 582 &rtransfer->staging->b.b, transfer->level, 583 &transfer->box); 584 } else { 585 r600_copy_from_staging_texture(ctx, rtransfer); 586 } 587 } 588 589 if (rtransfer->staging) 590 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); 591 592 pipe_resource_reference(&transfer->resource, NULL); 593 FREE(transfer); 594} 595 596void* r600_texture_transfer_map(struct pipe_context *ctx, 597 struct pipe_transfer* transfer) 598{ 599 struct r600_context *rctx = (struct r600_context *)ctx; 600 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 601 struct radeon_winsys_cs_handle *buf; 602 struct r600_texture *rtex = 603 (struct r600_texture*)transfer->resource; 604 enum pipe_format format = transfer->resource->format; 605 unsigned offset = 0; 606 char *map; 607 608 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 609 return r600_compute_global_transfer_map(ctx, transfer); 610 } 611 612 if (rtransfer->staging) { 613 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 614 } else { 615 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 616 } 617 618 if (rtex->is_depth || !rtransfer->staging) 619 offset = rtransfer->offset + 620 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 621 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 622 623 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) { 624 return NULL; 625 } 626 627 return map + offset; 628} 629 630void r600_texture_transfer_unmap(struct pipe_context *ctx, 631 struct pipe_transfer* transfer) 632{ 633 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 634 struct r600_context *rctx = (struct r600_context*)ctx; 635 struct radeon_winsys_cs_handle *buf; 636 637 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 638 return r600_compute_global_transfer_unmap(ctx, transfer); 639 } 640 641 if (rtransfer->staging) { 642 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 643 } else { 644 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 645 } 646 rctx->ws->buffer_unmap(buf); 647} 648 649void r600_init_surface_functions(struct r600_context *r600) 650{ 651 r600->context.create_surface = r600_create_surface; 652 r600->context.surface_destroy = r600_surface_destroy; 653} 654 655static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 656 const unsigned char *swizzle_view) 657{ 658 unsigned i; 659 unsigned char swizzle[4]; 660 unsigned result = 0; 661 const uint32_t swizzle_shift[4] = { 662 16, 19, 22, 25, 663 }; 664 const uint32_t swizzle_bit[4] = { 665 0, 1, 2, 3, 666 }; 667 668 if (swizzle_view) { 669 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 670 } else { 671 memcpy(swizzle, swizzle_format, 4); 672 } 673 674 /* Get swizzle. */ 675 for (i = 0; i < 4; i++) { 676 switch (swizzle[i]) { 677 case UTIL_FORMAT_SWIZZLE_Y: 678 result |= swizzle_bit[1] << swizzle_shift[i]; 679 break; 680 case UTIL_FORMAT_SWIZZLE_Z: 681 result |= swizzle_bit[2] << swizzle_shift[i]; 682 break; 683 case UTIL_FORMAT_SWIZZLE_W: 684 result |= swizzle_bit[3] << swizzle_shift[i]; 685 break; 686 case UTIL_FORMAT_SWIZZLE_0: 687 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 688 break; 689 case UTIL_FORMAT_SWIZZLE_1: 690 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 691 break; 692 default: /* UTIL_FORMAT_SWIZZLE_X */ 693 result |= swizzle_bit[0] << swizzle_shift[i]; 694 } 695 } 696 return result; 697} 698 699/* texture format translate */ 700uint32_t r600_translate_texformat(struct pipe_screen *screen, 701 enum pipe_format format, 702 const unsigned char *swizzle_view, 703 uint32_t *word4_p, uint32_t *yuv_format_p) 704{ 705 uint32_t result = 0, word4 = 0, yuv_format = 0; 706 const struct util_format_description *desc; 707 boolean uniform = TRUE; 708 static int r600_enable_s3tc = -1; 709 bool is_srgb_valid = FALSE; 710 711 int i; 712 const uint32_t sign_bit[4] = { 713 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 714 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 715 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 716 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 717 }; 718 desc = util_format_description(format); 719 720 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 721 722 /* Colorspace (return non-RGB formats directly). */ 723 switch (desc->colorspace) { 724 /* Depth stencil formats */ 725 case UTIL_FORMAT_COLORSPACE_ZS: 726 switch (format) { 727 case PIPE_FORMAT_Z16_UNORM: 728 result = FMT_16; 729 goto out_word4; 730 case PIPE_FORMAT_X24S8_UINT: 731 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 732 case PIPE_FORMAT_Z24X8_UNORM: 733 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 734 result = FMT_8_24; 735 goto out_word4; 736 case PIPE_FORMAT_S8X24_UINT: 737 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 738 case PIPE_FORMAT_X8Z24_UNORM: 739 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 740 result = FMT_24_8; 741 goto out_word4; 742 case PIPE_FORMAT_S8_UINT: 743 result = FMT_8; 744 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 745 goto out_word4; 746 case PIPE_FORMAT_Z32_FLOAT: 747 result = FMT_32_FLOAT; 748 goto out_word4; 749 case PIPE_FORMAT_X32_S8X24_UINT: 750 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 751 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 752 result = FMT_X24_8_32_FLOAT; 753 goto out_word4; 754 default: 755 goto out_unknown; 756 } 757 758 case UTIL_FORMAT_COLORSPACE_YUV: 759 yuv_format |= (1 << 30); 760 switch (format) { 761 case PIPE_FORMAT_UYVY: 762 case PIPE_FORMAT_YUYV: 763 default: 764 break; 765 } 766 goto out_unknown; /* XXX */ 767 768 case UTIL_FORMAT_COLORSPACE_SRGB: 769 word4 |= S_038010_FORCE_DEGAMMA(1); 770 break; 771 772 default: 773 break; 774 } 775 776 if (r600_enable_s3tc == -1) { 777 struct r600_screen *rscreen = (struct r600_screen *)screen; 778 if (rscreen->info.drm_minor >= 9) 779 r600_enable_s3tc = 1; 780 else 781 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 782 } 783 784 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 785 if (!r600_enable_s3tc) 786 goto out_unknown; 787 788 switch (format) { 789 case PIPE_FORMAT_RGTC1_SNORM: 790 case PIPE_FORMAT_LATC1_SNORM: 791 word4 |= sign_bit[0]; 792 case PIPE_FORMAT_RGTC1_UNORM: 793 case PIPE_FORMAT_LATC1_UNORM: 794 result = FMT_BC4; 795 goto out_word4; 796 case PIPE_FORMAT_RGTC2_SNORM: 797 case PIPE_FORMAT_LATC2_SNORM: 798 word4 |= sign_bit[0] | sign_bit[1]; 799 case PIPE_FORMAT_RGTC2_UNORM: 800 case PIPE_FORMAT_LATC2_UNORM: 801 result = FMT_BC5; 802 goto out_word4; 803 default: 804 goto out_unknown; 805 } 806 } 807 808 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 809 810 if (!r600_enable_s3tc) 811 goto out_unknown; 812 813 if (!util_format_s3tc_enabled) { 814 goto out_unknown; 815 } 816 817 switch (format) { 818 case PIPE_FORMAT_DXT1_RGB: 819 case PIPE_FORMAT_DXT1_RGBA: 820 case PIPE_FORMAT_DXT1_SRGB: 821 case PIPE_FORMAT_DXT1_SRGBA: 822 result = FMT_BC1; 823 is_srgb_valid = TRUE; 824 goto out_word4; 825 case PIPE_FORMAT_DXT3_RGBA: 826 case PIPE_FORMAT_DXT3_SRGBA: 827 result = FMT_BC2; 828 is_srgb_valid = TRUE; 829 goto out_word4; 830 case PIPE_FORMAT_DXT5_RGBA: 831 case PIPE_FORMAT_DXT5_SRGBA: 832 result = FMT_BC3; 833 is_srgb_valid = TRUE; 834 goto out_word4; 835 default: 836 goto out_unknown; 837 } 838 } 839 840 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { 841 switch (format) { 842 case PIPE_FORMAT_R8G8_B8G8_UNORM: 843 case PIPE_FORMAT_G8R8_B8R8_UNORM: 844 result = FMT_GB_GR; 845 goto out_word4; 846 case PIPE_FORMAT_G8R8_G8B8_UNORM: 847 case PIPE_FORMAT_R8G8_R8B8_UNORM: 848 result = FMT_BG_RG; 849 goto out_word4; 850 default: 851 goto out_unknown; 852 } 853 } 854 855 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 856 result = FMT_5_9_9_9_SHAREDEXP; 857 goto out_word4; 858 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 859 result = FMT_10_11_11_FLOAT; 860 goto out_word4; 861 } 862 863 864 for (i = 0; i < desc->nr_channels; i++) { 865 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 866 word4 |= sign_bit[i]; 867 } 868 } 869 870 /* R8G8Bx_SNORM - XXX CxV8U8 */ 871 872 /* See whether the components are of the same size. */ 873 for (i = 1; i < desc->nr_channels; i++) { 874 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 875 } 876 877 /* Non-uniform formats. */ 878 if (!uniform) { 879 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 880 desc->channel[0].pure_integer) 881 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 882 switch(desc->nr_channels) { 883 case 3: 884 if (desc->channel[0].size == 5 && 885 desc->channel[1].size == 6 && 886 desc->channel[2].size == 5) { 887 result = FMT_5_6_5; 888 goto out_word4; 889 } 890 goto out_unknown; 891 case 4: 892 if (desc->channel[0].size == 5 && 893 desc->channel[1].size == 5 && 894 desc->channel[2].size == 5 && 895 desc->channel[3].size == 1) { 896 result = FMT_1_5_5_5; 897 goto out_word4; 898 } 899 if (desc->channel[0].size == 10 && 900 desc->channel[1].size == 10 && 901 desc->channel[2].size == 10 && 902 desc->channel[3].size == 2) { 903 result = FMT_2_10_10_10; 904 goto out_word4; 905 } 906 goto out_unknown; 907 } 908 goto out_unknown; 909 } 910 911 /* Find the first non-VOID channel. */ 912 for (i = 0; i < 4; i++) { 913 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 914 break; 915 } 916 } 917 918 if (i == 4) 919 goto out_unknown; 920 921 /* uniform formats */ 922 switch (desc->channel[i].type) { 923 case UTIL_FORMAT_TYPE_UNSIGNED: 924 case UTIL_FORMAT_TYPE_SIGNED: 925#if 0 926 if (!desc->channel[i].normalized && 927 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 928 goto out_unknown; 929 } 930#endif 931 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 932 desc->channel[i].pure_integer) 933 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 934 935 switch (desc->channel[i].size) { 936 case 4: 937 switch (desc->nr_channels) { 938 case 2: 939 result = FMT_4_4; 940 goto out_word4; 941 case 4: 942 result = FMT_4_4_4_4; 943 goto out_word4; 944 } 945 goto out_unknown; 946 case 8: 947 switch (desc->nr_channels) { 948 case 1: 949 result = FMT_8; 950 goto out_word4; 951 case 2: 952 result = FMT_8_8; 953 goto out_word4; 954 case 4: 955 result = FMT_8_8_8_8; 956 is_srgb_valid = TRUE; 957 goto out_word4; 958 } 959 goto out_unknown; 960 case 16: 961 switch (desc->nr_channels) { 962 case 1: 963 result = FMT_16; 964 goto out_word4; 965 case 2: 966 result = FMT_16_16; 967 goto out_word4; 968 case 4: 969 result = FMT_16_16_16_16; 970 goto out_word4; 971 } 972 goto out_unknown; 973 case 32: 974 switch (desc->nr_channels) { 975 case 1: 976 result = FMT_32; 977 goto out_word4; 978 case 2: 979 result = FMT_32_32; 980 goto out_word4; 981 case 4: 982 result = FMT_32_32_32_32; 983 goto out_word4; 984 } 985 } 986 goto out_unknown; 987 988 case UTIL_FORMAT_TYPE_FLOAT: 989 switch (desc->channel[i].size) { 990 case 16: 991 switch (desc->nr_channels) { 992 case 1: 993 result = FMT_16_FLOAT; 994 goto out_word4; 995 case 2: 996 result = FMT_16_16_FLOAT; 997 goto out_word4; 998 case 4: 999 result = FMT_16_16_16_16_FLOAT; 1000 goto out_word4; 1001 } 1002 goto out_unknown; 1003 case 32: 1004 switch (desc->nr_channels) { 1005 case 1: 1006 result = FMT_32_FLOAT; 1007 goto out_word4; 1008 case 2: 1009 result = FMT_32_32_FLOAT; 1010 goto out_word4; 1011 case 4: 1012 result = FMT_32_32_32_32_FLOAT; 1013 goto out_word4; 1014 } 1015 } 1016 goto out_unknown; 1017 } 1018 1019out_word4: 1020 1021 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid) 1022 return ~0; 1023 if (word4_p) 1024 *word4_p = word4; 1025 if (yuv_format_p) 1026 *yuv_format_p = yuv_format; 1027 return result; 1028out_unknown: 1029 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1030 return ~0; 1031} 1032