r600_texture.c revision 773ff5705f3b2d88fb7094b8d2e051bb684c2323
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include "r600_formats.h" 28#include "r600d.h" 29 30#include <errno.h> 31#include "util/u_format_s3tc.h" 32#include "util/u_memory.h" 33 34/* Copy from a full GPU texture to a transfer's staging one. */ 35static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 36{ 37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 38 struct pipe_resource *texture = transfer->resource; 39 40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b, 41 0, 0, 0, 0, texture, transfer->level, 42 &transfer->box); 43} 44 45 46/* Copy from a transfer's staging texture to a full GPU one. */ 47static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 48{ 49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 50 struct pipe_resource *texture = transfer->resource; 51 struct pipe_box sbox; 52 53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox); 54 55 ctx->resource_copy_region(ctx, texture, transfer->level, 56 transfer->box.x, transfer->box.y, transfer->box.z, 57 &rtransfer->staging->b.b, 58 0, &sbox); 59} 60 61unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 62 unsigned level, unsigned layer) 63{ 64 return rtex->surface.level[level].offset + 65 layer * rtex->surface.level[level].slice_size; 66} 67 68static int r600_init_surface(struct r600_screen *rscreen, 69 struct radeon_surface *surface, 70 const struct pipe_resource *ptex, 71 unsigned array_mode, 72 bool is_transfer, bool is_flushed_depth) 73{ 74 const struct util_format_description *desc = 75 util_format_description(ptex->format); 76 bool is_depth, is_stencil; 77 78 is_depth = util_format_has_depth(desc); 79 is_stencil = util_format_has_stencil(desc); 80 81 surface->npix_x = ptex->width0; 82 surface->npix_y = ptex->height0; 83 surface->npix_z = ptex->depth0; 84 surface->blk_w = util_format_get_blockwidth(ptex->format); 85 surface->blk_h = util_format_get_blockheight(ptex->format); 86 surface->blk_d = 1; 87 surface->array_size = 1; 88 surface->last_level = ptex->last_level; 89 90 if (rscreen->chip_class >= EVERGREEN && 91 !is_transfer && !is_flushed_depth && 92 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { 93 surface->bpe = 4; /* stencil is allocated separately on evergreen */ 94 } else { 95 surface->bpe = util_format_get_blocksize(ptex->format); 96 /* align byte per element on dword */ 97 if (surface->bpe == 3) { 98 surface->bpe = 4; 99 } 100 } 101 102 surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1; 103 surface->flags = 0; 104 105 switch (array_mode) { 106 case V_038000_ARRAY_1D_TILED_THIN1: 107 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 108 break; 109 case V_038000_ARRAY_2D_TILED_THIN1: 110 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 111 break; 112 case V_038000_ARRAY_LINEAR_ALIGNED: 113 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 114 break; 115 case V_038000_ARRAY_LINEAR_GENERAL: 116 default: 117 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); 118 break; 119 } 120 switch (ptex->target) { 121 case PIPE_TEXTURE_1D: 122 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); 123 break; 124 case PIPE_TEXTURE_RECT: 125 case PIPE_TEXTURE_2D: 126 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 127 break; 128 case PIPE_TEXTURE_3D: 129 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); 130 break; 131 case PIPE_TEXTURE_1D_ARRAY: 132 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); 133 surface->array_size = ptex->array_size; 134 break; 135 case PIPE_TEXTURE_2D_ARRAY: 136 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); 137 surface->array_size = ptex->array_size; 138 break; 139 case PIPE_TEXTURE_CUBE: 140 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); 141 break; 142 case PIPE_BUFFER: 143 default: 144 return -EINVAL; 145 } 146 if (ptex->bind & PIPE_BIND_SCANOUT) { 147 surface->flags |= RADEON_SURF_SCANOUT; 148 } 149 150 if (!is_transfer && !is_flushed_depth && is_depth) { 151 surface->flags |= RADEON_SURF_ZBUFFER; 152 153 if (is_stencil) { 154 surface->flags |= RADEON_SURF_SBUFFER; 155 } 156 } 157 return 0; 158} 159 160static int r600_setup_surface(struct pipe_screen *screen, 161 struct r600_resource_texture *rtex, 162 unsigned pitch_in_bytes_override) 163{ 164 struct pipe_resource *ptex = &rtex->resource.b.b; 165 struct r600_screen *rscreen = (struct r600_screen*)screen; 166 unsigned i; 167 int r; 168 169 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); 170 if (r) { 171 return r; 172 } 173 rtex->size = rtex->surface.bo_size; 174 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { 175 /* old ddx on evergreen over estimate alignment for 1d, only 1 level 176 * for those 177 */ 178 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; 179 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; 180 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; 181 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 182 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size; 183 } 184 } 185 for (i = 0; i <= ptex->last_level; i++) { 186 switch (rtex->surface.level[i].mode) { 187 case RADEON_SURF_MODE_LINEAR_ALIGNED: 188 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED; 189 break; 190 case RADEON_SURF_MODE_1D: 191 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1; 192 break; 193 case RADEON_SURF_MODE_2D: 194 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1; 195 break; 196 default: 197 case RADEON_SURF_MODE_LINEAR: 198 rtex->array_mode[i] = 0; 199 break; 200 } 201 } 202 return 0; 203} 204 205static boolean r600_texture_get_handle(struct pipe_screen* screen, 206 struct pipe_resource *ptex, 207 struct winsys_handle *whandle) 208{ 209 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 210 struct r600_resource *resource = &rtex->resource; 211 struct radeon_surface *surface = &rtex->surface; 212 struct r600_screen *rscreen = (struct r600_screen*)screen; 213 214 rscreen->ws->buffer_set_tiling(resource->buf, 215 NULL, 216 surface->level[0].mode >= RADEON_SURF_MODE_1D ? 217 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 218 surface->level[0].mode >= RADEON_SURF_MODE_2D ? 219 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 220 surface->bankw, surface->bankh, 221 surface->tile_split, 222 surface->stencil_tile_split, 223 surface->mtilea, 224 rtex->surface.level[0].pitch_bytes); 225 226 return rscreen->ws->buffer_get_handle(resource->buf, 227 rtex->surface.level[0].pitch_bytes, whandle); 228} 229 230static void r600_texture_destroy(struct pipe_screen *screen, 231 struct pipe_resource *ptex) 232{ 233 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 234 struct r600_resource *resource = &rtex->resource; 235 236 if (rtex->flushed_depth_texture) 237 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 238 239 pb_reference(&resource->buf, NULL); 240 FREE(rtex); 241} 242 243static const struct u_resource_vtbl r600_texture_vtbl = 244{ 245 r600_texture_get_handle, /* get_handle */ 246 r600_texture_destroy, /* resource_destroy */ 247 r600_texture_get_transfer, /* get_transfer */ 248 r600_texture_transfer_destroy, /* transfer_destroy */ 249 r600_texture_transfer_map, /* transfer_map */ 250 NULL, /* transfer_flush_region */ 251 r600_texture_transfer_unmap, /* transfer_unmap */ 252 NULL /* transfer_inline_write */ 253}; 254 255static struct r600_resource_texture * 256r600_texture_create_object(struct pipe_screen *screen, 257 const struct pipe_resource *base, 258 unsigned pitch_in_bytes_override, 259 struct pb_buffer *buf, 260 boolean alloc_bo, 261 struct radeon_surface *surface) 262{ 263 struct r600_resource_texture *rtex; 264 struct r600_resource *resource; 265 struct r600_screen *rscreen = (struct r600_screen*)screen; 266 int r; 267 268 rtex = CALLOC_STRUCT(r600_resource_texture); 269 if (rtex == NULL) 270 return NULL; 271 272 resource = &rtex->resource; 273 resource->b.b = *base; 274 resource->b.vtbl = &r600_texture_vtbl; 275 pipe_reference_init(&resource->b.b.reference, 1); 276 resource->b.b.screen = screen; 277 rtex->pitch_override = pitch_in_bytes_override; 278 279 /* don't include stencil-only formats which we don't support for rendering */ 280 rtex->is_depth = util_format_has_depth(util_format_description(rtex->resource.b.b.format)); 281 282 rtex->surface = *surface; 283 r = r600_setup_surface(screen, rtex, 284 pitch_in_bytes_override); 285 if (r) { 286 FREE(rtex); 287 return NULL; 288 } 289 290 /* Now create the backing buffer. */ 291 if (!buf && alloc_bo) { 292 unsigned base_align = rtex->surface.bo_alignment; 293 294 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) { 295 FREE(rtex); 296 return NULL; 297 } 298 } else if (buf) { 299 resource->buf = buf; 300 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); 301 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; 302 } 303 return rtex; 304} 305 306struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 307 const struct pipe_resource *templ) 308{ 309 struct r600_screen *rscreen = (struct r600_screen*)screen; 310 struct radeon_surface surface; 311 unsigned array_mode = 0; 312 int r; 313 314 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) { 315 if (!(templ->bind & PIPE_BIND_SCANOUT) && 316 templ->usage != PIPE_USAGE_STAGING && 317 templ->usage != PIPE_USAGE_STREAM) { 318 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 319 } else if (util_format_is_compressed(templ->format)) { 320 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 321 } 322 } 323 324 r = r600_init_surface(rscreen, &surface, templ, array_mode, 325 templ->flags & R600_RESOURCE_FLAG_TRANSFER, 326 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); 327 if (r) { 328 return NULL; 329 } 330 r = rscreen->ws->surface_best(rscreen->ws, &surface); 331 if (r) { 332 return NULL; 333 } 334 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 335 0, NULL, TRUE, &surface); 336} 337 338static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 339 struct pipe_resource *texture, 340 const struct pipe_surface *templ) 341{ 342 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 343 unsigned level = templ->u.tex.level; 344 345 assert(templ->u.tex.first_layer == templ->u.tex.last_layer); 346 if (surface == NULL) 347 return NULL; 348 pipe_reference_init(&surface->base.reference, 1); 349 pipe_resource_reference(&surface->base.texture, texture); 350 surface->base.context = pipe; 351 surface->base.format = templ->format; 352 surface->base.width = u_minify(texture->width0, level); 353 surface->base.height = u_minify(texture->height0, level); 354 surface->base.usage = templ->usage; 355 surface->base.u = templ->u; 356 return &surface->base; 357} 358 359static void r600_surface_destroy(struct pipe_context *pipe, 360 struct pipe_surface *surface) 361{ 362 pipe_resource_reference(&surface->texture, NULL); 363 FREE(surface); 364} 365 366struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 367 const struct pipe_resource *templ, 368 struct winsys_handle *whandle) 369{ 370 struct r600_screen *rscreen = (struct r600_screen*)screen; 371 struct pb_buffer *buf = NULL; 372 unsigned stride = 0; 373 unsigned array_mode = 0; 374 enum radeon_bo_layout micro, macro; 375 struct radeon_surface surface; 376 int r; 377 378 /* Support only 2D textures without mipmaps */ 379 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 380 templ->depth0 != 1 || templ->last_level != 0) 381 return NULL; 382 383 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); 384 if (!buf) 385 return NULL; 386 387 rscreen->ws->buffer_get_tiling(buf, µ, ¯o, 388 &surface.bankw, &surface.bankh, 389 &surface.tile_split, 390 &surface.stencil_tile_split, 391 &surface.mtilea); 392 393 if (macro == RADEON_LAYOUT_TILED) 394 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 395 else if (micro == RADEON_LAYOUT_TILED) 396 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 397 else 398 array_mode = 0; 399 400 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false); 401 if (r) { 402 return NULL; 403 } 404 return (struct pipe_resource *)r600_texture_create_object(screen, templ, 405 stride, buf, FALSE, &surface); 406} 407 408bool r600_init_flushed_depth_texture(struct pipe_context *ctx, 409 struct pipe_resource *texture, 410 struct r600_resource_texture **staging) 411{ 412 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 413 struct pipe_resource resource; 414 struct r600_resource_texture **flushed_depth_texture = staging ? 415 staging : &rtex->flushed_depth_texture; 416 417 if (!staging && rtex->flushed_depth_texture) 418 return true; /* it's ready */ 419 420 resource.target = texture->target; 421 resource.format = texture->format; 422 resource.width0 = texture->width0; 423 resource.height0 = texture->height0; 424 resource.depth0 = texture->depth0; 425 resource.array_size = texture->array_size; 426 resource.last_level = texture->last_level; 427 resource.nr_samples = texture->nr_samples; 428 resource.usage = staging ? PIPE_USAGE_STAGING : PIPE_USAGE_STATIC; 429 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; 430 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH; 431 432 if (staging) 433 resource.flags |= R600_RESOURCE_FLAG_TRANSFER; 434 435 *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); 436 if (*flushed_depth_texture == NULL) { 437 R600_ERR("failed to create temporary texture to hold flushed depth\n"); 438 return false; 439 } 440 441 (*flushed_depth_texture)->is_flushing_texture = TRUE; 442 return true; 443} 444 445/* Needs adjustment for pixelformat: 446 */ 447static INLINE unsigned u_box_volume( const struct pipe_box *box ) 448{ 449 return box->width * box->depth * box->height; 450} 451 452struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 453 struct pipe_resource *texture, 454 unsigned level, 455 unsigned usage, 456 const struct pipe_box *box) 457{ 458 struct r600_context *rctx = (struct r600_context*)ctx; 459 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 460 struct pipe_resource resource; 461 struct r600_transfer *trans; 462 boolean use_staging_texture = FALSE; 463 464 /* We cannot map a tiled texture directly because the data is 465 * in a different order, therefore we do detiling using a blit. 466 * 467 * Also, use a temporary in GTT memory for read transfers, as 468 * the CPU is much happier reading out of cached system memory 469 * than uncached VRAM. 470 */ 471 if (R600_TEX_IS_TILED(rtex, level)) { 472 use_staging_texture = TRUE; 473 } 474 475 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 476 use_staging_texture = TRUE; 477 478 /* Use a staging texture for uploads if the underlying BO is busy. */ 479 if (!(usage & PIPE_TRANSFER_READ) && 480 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) || 481 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) { 482 use_staging_texture = TRUE; 483 } 484 485 if (texture->flags & R600_RESOURCE_FLAG_TRANSFER) { 486 use_staging_texture = FALSE; 487 } 488 489 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) { 490 return NULL; 491 } 492 493 trans = CALLOC_STRUCT(r600_transfer); 494 if (trans == NULL) 495 return NULL; 496 pipe_resource_reference(&trans->transfer.resource, texture); 497 trans->transfer.level = level; 498 trans->transfer.usage = usage; 499 trans->transfer.box = *box; 500 if (rtex->is_depth) { 501 /* XXX: only readback the rectangle which is being mapped? 502 */ 503 /* XXX: when discard is true, no need to read back from depth texture 504 */ 505 struct r600_resource_texture *staging_depth; 506 507 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) { 508 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 509 pipe_resource_reference(&trans->transfer.resource, NULL); 510 FREE(trans); 511 return NULL; 512 } 513 514 r600_blit_uncompress_depth(ctx, rtex, staging_depth, 515 level, level, 516 box->z, box->z + box->depth - 1, 517 0, 0); 518 519 trans->transfer.stride = staging_depth->surface.level[level].pitch_bytes; 520 trans->offset = r600_texture_get_offset(staging_depth, level, box->z); 521 trans->staging = (struct r600_resource*)staging_depth; 522 return &trans->transfer; 523 } else if (use_staging_texture) { 524 resource.target = PIPE_TEXTURE_2D; 525 resource.format = texture->format; 526 resource.width0 = box->width; 527 resource.height0 = box->height; 528 resource.depth0 = 1; 529 resource.array_size = 1; 530 resource.last_level = 0; 531 resource.nr_samples = 0; 532 resource.usage = PIPE_USAGE_STAGING; 533 resource.bind = 0; 534 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 535 /* For texture reading, the temporary (detiled) texture is used as 536 * a render target when blitting from a tiled texture. */ 537 if (usage & PIPE_TRANSFER_READ) { 538 resource.bind |= PIPE_BIND_RENDER_TARGET; 539 } 540 /* For texture writing, the temporary texture is used as a sampler 541 * when blitting into a tiled texture. */ 542 if (usage & PIPE_TRANSFER_WRITE) { 543 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 544 } 545 /* Create the temporary texture. */ 546 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource); 547 if (trans->staging == NULL) { 548 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 549 pipe_resource_reference(&trans->transfer.resource, NULL); 550 FREE(trans); 551 return NULL; 552 } 553 554 trans->transfer.stride = 555 ((struct r600_resource_texture *)trans->staging)->surface.level[0].pitch_bytes; 556 if (usage & PIPE_TRANSFER_READ) { 557 r600_copy_to_staging_texture(ctx, trans); 558 /* Always referenced in the blit. */ 559 r600_flush(ctx, NULL, 0); 560 } 561 return &trans->transfer; 562 } 563 trans->transfer.stride = rtex->surface.level[level].pitch_bytes; 564 trans->transfer.layer_stride = rtex->surface.level[level].slice_size; 565 trans->offset = r600_texture_get_offset(rtex, level, box->z); 566 return &trans->transfer; 567} 568 569void r600_texture_transfer_destroy(struct pipe_context *ctx, 570 struct pipe_transfer *transfer) 571{ 572 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 573 struct pipe_resource *texture = transfer->resource; 574 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 575 576 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) { 577 if (rtex->is_depth) { 578 ctx->resource_copy_region(ctx, texture, transfer->level, 579 transfer->box.x, transfer->box.y, transfer->box.z, 580 &rtransfer->staging->b.b, transfer->level, 581 &transfer->box); 582 } else { 583 r600_copy_from_staging_texture(ctx, rtransfer); 584 } 585 } 586 587 if (rtransfer->staging) 588 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); 589 590 pipe_resource_reference(&transfer->resource, NULL); 591 FREE(transfer); 592} 593 594void* r600_texture_transfer_map(struct pipe_context *ctx, 595 struct pipe_transfer* transfer) 596{ 597 struct r600_context *rctx = (struct r600_context *)ctx; 598 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 599 struct radeon_winsys_cs_handle *buf; 600 struct r600_resource_texture *rtex = 601 (struct r600_resource_texture*)transfer->resource; 602 enum pipe_format format = transfer->resource->format; 603 unsigned offset = 0; 604 char *map; 605 606 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 607 return r600_compute_global_transfer_map(ctx, transfer); 608 } 609 610 if (rtransfer->staging) { 611 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 612 } else { 613 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 614 } 615 616 if (rtex->is_depth || !rtransfer->staging) 617 offset = rtransfer->offset + 618 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 619 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 620 621 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) { 622 return NULL; 623 } 624 625 return map + offset; 626} 627 628void r600_texture_transfer_unmap(struct pipe_context *ctx, 629 struct pipe_transfer* transfer) 630{ 631 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 632 struct r600_context *rctx = (struct r600_context*)ctx; 633 struct radeon_winsys_cs_handle *buf; 634 635 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 636 return r600_compute_global_transfer_unmap(ctx, transfer); 637 } 638 639 if (rtransfer->staging) { 640 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 641 } else { 642 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 643 } 644 rctx->ws->buffer_unmap(buf); 645} 646 647void r600_init_surface_functions(struct r600_context *r600) 648{ 649 r600->context.create_surface = r600_create_surface; 650 r600->context.surface_destroy = r600_surface_destroy; 651} 652 653static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 654 const unsigned char *swizzle_view) 655{ 656 unsigned i; 657 unsigned char swizzle[4]; 658 unsigned result = 0; 659 const uint32_t swizzle_shift[4] = { 660 16, 19, 22, 25, 661 }; 662 const uint32_t swizzle_bit[4] = { 663 0, 1, 2, 3, 664 }; 665 666 if (swizzle_view) { 667 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 668 } else { 669 memcpy(swizzle, swizzle_format, 4); 670 } 671 672 /* Get swizzle. */ 673 for (i = 0; i < 4; i++) { 674 switch (swizzle[i]) { 675 case UTIL_FORMAT_SWIZZLE_Y: 676 result |= swizzle_bit[1] << swizzle_shift[i]; 677 break; 678 case UTIL_FORMAT_SWIZZLE_Z: 679 result |= swizzle_bit[2] << swizzle_shift[i]; 680 break; 681 case UTIL_FORMAT_SWIZZLE_W: 682 result |= swizzle_bit[3] << swizzle_shift[i]; 683 break; 684 case UTIL_FORMAT_SWIZZLE_0: 685 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 686 break; 687 case UTIL_FORMAT_SWIZZLE_1: 688 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 689 break; 690 default: /* UTIL_FORMAT_SWIZZLE_X */ 691 result |= swizzle_bit[0] << swizzle_shift[i]; 692 } 693 } 694 return result; 695} 696 697/* texture format translate */ 698uint32_t r600_translate_texformat(struct pipe_screen *screen, 699 enum pipe_format format, 700 const unsigned char *swizzle_view, 701 uint32_t *word4_p, uint32_t *yuv_format_p) 702{ 703 uint32_t result = 0, word4 = 0, yuv_format = 0; 704 const struct util_format_description *desc; 705 boolean uniform = TRUE; 706 static int r600_enable_s3tc = -1; 707 bool is_srgb_valid = FALSE; 708 709 int i; 710 const uint32_t sign_bit[4] = { 711 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 712 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 713 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 714 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 715 }; 716 desc = util_format_description(format); 717 718 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 719 720 /* Colorspace (return non-RGB formats directly). */ 721 switch (desc->colorspace) { 722 /* Depth stencil formats */ 723 case UTIL_FORMAT_COLORSPACE_ZS: 724 switch (format) { 725 case PIPE_FORMAT_Z16_UNORM: 726 result = FMT_16; 727 goto out_word4; 728 case PIPE_FORMAT_X24S8_UINT: 729 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 730 case PIPE_FORMAT_Z24X8_UNORM: 731 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 732 result = FMT_8_24; 733 goto out_word4; 734 case PIPE_FORMAT_S8X24_UINT: 735 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 736 case PIPE_FORMAT_X8Z24_UNORM: 737 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 738 result = FMT_24_8; 739 goto out_word4; 740 case PIPE_FORMAT_S8_UINT: 741 result = FMT_8; 742 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 743 goto out_word4; 744 case PIPE_FORMAT_Z32_FLOAT: 745 result = FMT_32_FLOAT; 746 goto out_word4; 747 case PIPE_FORMAT_X32_S8X24_UINT: 748 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 749 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 750 result = FMT_X24_8_32_FLOAT; 751 goto out_word4; 752 default: 753 goto out_unknown; 754 } 755 756 case UTIL_FORMAT_COLORSPACE_YUV: 757 yuv_format |= (1 << 30); 758 switch (format) { 759 case PIPE_FORMAT_UYVY: 760 case PIPE_FORMAT_YUYV: 761 default: 762 break; 763 } 764 goto out_unknown; /* XXX */ 765 766 case UTIL_FORMAT_COLORSPACE_SRGB: 767 word4 |= S_038010_FORCE_DEGAMMA(1); 768 break; 769 770 default: 771 break; 772 } 773 774 if (r600_enable_s3tc == -1) { 775 struct r600_screen *rscreen = (struct r600_screen *)screen; 776 if (rscreen->info.drm_minor >= 9) 777 r600_enable_s3tc = 1; 778 else 779 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 780 } 781 782 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 783 if (!r600_enable_s3tc) 784 goto out_unknown; 785 786 switch (format) { 787 case PIPE_FORMAT_RGTC1_SNORM: 788 case PIPE_FORMAT_LATC1_SNORM: 789 word4 |= sign_bit[0]; 790 case PIPE_FORMAT_RGTC1_UNORM: 791 case PIPE_FORMAT_LATC1_UNORM: 792 result = FMT_BC4; 793 goto out_word4; 794 case PIPE_FORMAT_RGTC2_SNORM: 795 case PIPE_FORMAT_LATC2_SNORM: 796 word4 |= sign_bit[0] | sign_bit[1]; 797 case PIPE_FORMAT_RGTC2_UNORM: 798 case PIPE_FORMAT_LATC2_UNORM: 799 result = FMT_BC5; 800 goto out_word4; 801 default: 802 goto out_unknown; 803 } 804 } 805 806 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 807 808 if (!r600_enable_s3tc) 809 goto out_unknown; 810 811 if (!util_format_s3tc_enabled) { 812 goto out_unknown; 813 } 814 815 switch (format) { 816 case PIPE_FORMAT_DXT1_RGB: 817 case PIPE_FORMAT_DXT1_RGBA: 818 case PIPE_FORMAT_DXT1_SRGB: 819 case PIPE_FORMAT_DXT1_SRGBA: 820 result = FMT_BC1; 821 is_srgb_valid = TRUE; 822 goto out_word4; 823 case PIPE_FORMAT_DXT3_RGBA: 824 case PIPE_FORMAT_DXT3_SRGBA: 825 result = FMT_BC2; 826 is_srgb_valid = TRUE; 827 goto out_word4; 828 case PIPE_FORMAT_DXT5_RGBA: 829 case PIPE_FORMAT_DXT5_SRGBA: 830 result = FMT_BC3; 831 is_srgb_valid = TRUE; 832 goto out_word4; 833 default: 834 goto out_unknown; 835 } 836 } 837 838 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { 839 switch (format) { 840 case PIPE_FORMAT_R8G8_B8G8_UNORM: 841 case PIPE_FORMAT_G8R8_B8R8_UNORM: 842 result = FMT_GB_GR; 843 goto out_word4; 844 case PIPE_FORMAT_G8R8_G8B8_UNORM: 845 case PIPE_FORMAT_R8G8_R8B8_UNORM: 846 result = FMT_BG_RG; 847 goto out_word4; 848 default: 849 goto out_unknown; 850 } 851 } 852 853 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 854 result = FMT_5_9_9_9_SHAREDEXP; 855 goto out_word4; 856 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 857 result = FMT_10_11_11_FLOAT; 858 goto out_word4; 859 } 860 861 862 for (i = 0; i < desc->nr_channels; i++) { 863 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 864 word4 |= sign_bit[i]; 865 } 866 } 867 868 /* R8G8Bx_SNORM - XXX CxV8U8 */ 869 870 /* See whether the components are of the same size. */ 871 for (i = 1; i < desc->nr_channels; i++) { 872 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 873 } 874 875 /* Non-uniform formats. */ 876 if (!uniform) { 877 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 878 desc->channel[0].pure_integer) 879 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 880 switch(desc->nr_channels) { 881 case 3: 882 if (desc->channel[0].size == 5 && 883 desc->channel[1].size == 6 && 884 desc->channel[2].size == 5) { 885 result = FMT_5_6_5; 886 goto out_word4; 887 } 888 goto out_unknown; 889 case 4: 890 if (desc->channel[0].size == 5 && 891 desc->channel[1].size == 5 && 892 desc->channel[2].size == 5 && 893 desc->channel[3].size == 1) { 894 result = FMT_1_5_5_5; 895 goto out_word4; 896 } 897 if (desc->channel[0].size == 10 && 898 desc->channel[1].size == 10 && 899 desc->channel[2].size == 10 && 900 desc->channel[3].size == 2) { 901 result = FMT_2_10_10_10; 902 goto out_word4; 903 } 904 goto out_unknown; 905 } 906 goto out_unknown; 907 } 908 909 /* Find the first non-VOID channel. */ 910 for (i = 0; i < 4; i++) { 911 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 912 break; 913 } 914 } 915 916 if (i == 4) 917 goto out_unknown; 918 919 /* uniform formats */ 920 switch (desc->channel[i].type) { 921 case UTIL_FORMAT_TYPE_UNSIGNED: 922 case UTIL_FORMAT_TYPE_SIGNED: 923#if 0 924 if (!desc->channel[i].normalized && 925 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 926 goto out_unknown; 927 } 928#endif 929 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 930 desc->channel[i].pure_integer) 931 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 932 933 switch (desc->channel[i].size) { 934 case 4: 935 switch (desc->nr_channels) { 936 case 2: 937 result = FMT_4_4; 938 goto out_word4; 939 case 4: 940 result = FMT_4_4_4_4; 941 goto out_word4; 942 } 943 goto out_unknown; 944 case 8: 945 switch (desc->nr_channels) { 946 case 1: 947 result = FMT_8; 948 goto out_word4; 949 case 2: 950 result = FMT_8_8; 951 goto out_word4; 952 case 4: 953 result = FMT_8_8_8_8; 954 is_srgb_valid = TRUE; 955 goto out_word4; 956 } 957 goto out_unknown; 958 case 16: 959 switch (desc->nr_channels) { 960 case 1: 961 result = FMT_16; 962 goto out_word4; 963 case 2: 964 result = FMT_16_16; 965 goto out_word4; 966 case 4: 967 result = FMT_16_16_16_16; 968 goto out_word4; 969 } 970 goto out_unknown; 971 case 32: 972 switch (desc->nr_channels) { 973 case 1: 974 result = FMT_32; 975 goto out_word4; 976 case 2: 977 result = FMT_32_32; 978 goto out_word4; 979 case 4: 980 result = FMT_32_32_32_32; 981 goto out_word4; 982 } 983 } 984 goto out_unknown; 985 986 case UTIL_FORMAT_TYPE_FLOAT: 987 switch (desc->channel[i].size) { 988 case 16: 989 switch (desc->nr_channels) { 990 case 1: 991 result = FMT_16_FLOAT; 992 goto out_word4; 993 case 2: 994 result = FMT_16_16_FLOAT; 995 goto out_word4; 996 case 4: 997 result = FMT_16_16_16_16_FLOAT; 998 goto out_word4; 999 } 1000 goto out_unknown; 1001 case 32: 1002 switch (desc->nr_channels) { 1003 case 1: 1004 result = FMT_32_FLOAT; 1005 goto out_word4; 1006 case 2: 1007 result = FMT_32_32_FLOAT; 1008 goto out_word4; 1009 case 4: 1010 result = FMT_32_32_32_32_FLOAT; 1011 goto out_word4; 1012 } 1013 } 1014 goto out_unknown; 1015 } 1016 1017out_word4: 1018 1019 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid) 1020 return ~0; 1021 if (word4_p) 1022 *word4_p = word4; 1023 if (yuv_format_p) 1024 *yuv_format_p = yuv_format; 1025 return result; 1026out_unknown: 1027 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1028 return ~0; 1029} 1030