r600_texture.c revision ea72351a919c594e7f40e901dca42aebb866f8a6
1/* 2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 * Corbin Simpson 26 */ 27#include "r600_formats.h" 28#include "r600d.h" 29 30#include <errno.h> 31#include "util/u_format_s3tc.h" 32#include "util/u_memory.h" 33 34/* Copy from a full GPU texture to a transfer's staging one. */ 35static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 36{ 37 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 38 struct pipe_resource *texture = transfer->resource; 39 40 ctx->resource_copy_region(ctx, &rtransfer->staging->b.b, 41 0, 0, 0, 0, texture, transfer->level, 42 &transfer->box); 43} 44 45 46/* Copy from a transfer's staging texture to a full GPU one. */ 47static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600_transfer *rtransfer) 48{ 49 struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer; 50 struct pipe_resource *texture = transfer->resource; 51 struct pipe_box sbox; 52 53 u_box_origin_2d(transfer->box.width, transfer->box.height, &sbox); 54 55 ctx->resource_copy_region(ctx, texture, transfer->level, 56 transfer->box.x, transfer->box.y, transfer->box.z, 57 &rtransfer->staging->b.b, 58 0, &sbox); 59} 60 61unsigned r600_texture_get_offset(struct r600_resource_texture *rtex, 62 unsigned level, unsigned layer) 63{ 64 unsigned offset = rtex->offset[level]; 65 66 switch (rtex->resource.b.b.target) { 67 case PIPE_TEXTURE_3D: 68 case PIPE_TEXTURE_CUBE: 69 default: 70 return offset + layer * rtex->layer_size[level]; 71 } 72} 73 74static unsigned r600_get_block_alignment(struct pipe_screen *screen, 75 enum pipe_format format, 76 unsigned array_mode) 77{ 78 struct r600_screen* rscreen = (struct r600_screen *)screen; 79 unsigned pixsize = util_format_get_blocksize(format); 80 int p_align; 81 82 switch(array_mode) { 83 case V_038000_ARRAY_1D_TILED_THIN1: 84 p_align = MAX2(8, 85 ((rscreen->tiling_info.group_bytes / 8 / pixsize))); 86 break; 87 case V_038000_ARRAY_2D_TILED_THIN1: 88 p_align = MAX2(rscreen->tiling_info.num_banks, 89 (((rscreen->tiling_info.group_bytes / 8 / pixsize)) * 90 rscreen->tiling_info.num_banks)) * 8; 91 break; 92 case V_038000_ARRAY_LINEAR_ALIGNED: 93 p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize); 94 break; 95 case V_038000_ARRAY_LINEAR_GENERAL: 96 default: 97 p_align = rscreen->tiling_info.group_bytes / pixsize; 98 break; 99 } 100 return p_align; 101} 102 103static unsigned r600_get_height_alignment(struct pipe_screen *screen, 104 unsigned array_mode) 105{ 106 struct r600_screen* rscreen = (struct r600_screen *)screen; 107 int h_align; 108 109 switch (array_mode) { 110 case V_038000_ARRAY_2D_TILED_THIN1: 111 h_align = rscreen->tiling_info.num_channels * 8; 112 break; 113 case V_038000_ARRAY_1D_TILED_THIN1: 114 case V_038000_ARRAY_LINEAR_ALIGNED: 115 h_align = 8; 116 break; 117 case V_038000_ARRAY_LINEAR_GENERAL: 118 default: 119 h_align = 1; 120 break; 121 } 122 return h_align; 123} 124 125static unsigned r600_get_base_alignment(struct pipe_screen *screen, 126 enum pipe_format format, 127 unsigned array_mode) 128{ 129 struct r600_screen* rscreen = (struct r600_screen *)screen; 130 unsigned pixsize = util_format_get_blocksize(format); 131 int p_align = r600_get_block_alignment(screen, format, array_mode); 132 int h_align = r600_get_height_alignment(screen, array_mode); 133 int b_align; 134 135 switch (array_mode) { 136 case V_038000_ARRAY_2D_TILED_THIN1: 137 b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize, 138 p_align * pixsize * h_align); 139 break; 140 case V_038000_ARRAY_1D_TILED_THIN1: 141 case V_038000_ARRAY_LINEAR_ALIGNED: 142 case V_038000_ARRAY_LINEAR_GENERAL: 143 default: 144 b_align = rscreen->tiling_info.group_bytes; 145 break; 146 } 147 return b_align; 148} 149 150static unsigned mip_minify(unsigned size, unsigned level) 151{ 152 unsigned val; 153 val = u_minify(size, level); 154 if (level > 0) 155 val = util_next_power_of_two(val); 156 return val; 157} 158 159static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen, 160 struct r600_resource_texture *rtex, 161 unsigned level) 162{ 163 struct pipe_resource *ptex = &rtex->resource.b.b; 164 unsigned nblocksx, block_align, width; 165 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 166 167 if (rtex->pitch_override) 168 return rtex->pitch_override / blocksize; 169 170 width = mip_minify(ptex->width0, level); 171 nblocksx = util_format_get_nblocksx(rtex->real_format, width); 172 173 block_align = r600_get_block_alignment(screen, rtex->real_format, 174 rtex->array_mode[level]); 175 nblocksx = align(nblocksx, block_align); 176 return nblocksx; 177} 178 179static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen, 180 struct r600_resource_texture *rtex, 181 unsigned level) 182{ 183 struct pipe_resource *ptex = &rtex->resource.b.b; 184 unsigned height, tile_height; 185 186 height = mip_minify(ptex->height0, level); 187 height = util_format_get_nblocksy(rtex->real_format, height); 188 tile_height = r600_get_height_alignment(screen, 189 rtex->array_mode[level]); 190 191 /* XXX Hack around an alignment issue. Less tests fail with this. 192 * 193 * The thing is depth-stencil buffers should be tiled, i.e. 194 * the alignment should be >=8. If I make them tiled, stencil starts 195 * working because it no longer overlaps with the depth buffer 196 * in memory, but texturing like drawpix-stencil breaks. */ 197 if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8) 198 tile_height = 8; 199 200 height = align(height, tile_height); 201 return height; 202} 203 204static void r600_texture_set_array_mode(struct pipe_screen *screen, 205 struct r600_resource_texture *rtex, 206 unsigned level, unsigned array_mode) 207{ 208 struct pipe_resource *ptex = &rtex->resource.b.b; 209 210 switch (array_mode) { 211 case V_0280A0_ARRAY_LINEAR_GENERAL: 212 case V_0280A0_ARRAY_LINEAR_ALIGNED: 213 case V_0280A0_ARRAY_1D_TILED_THIN1: 214 default: 215 rtex->array_mode[level] = array_mode; 216 break; 217 case V_0280A0_ARRAY_2D_TILED_THIN1: 218 { 219 unsigned w, h, tile_height, tile_width; 220 221 tile_height = r600_get_height_alignment(screen, array_mode); 222 tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode); 223 224 w = mip_minify(ptex->width0, level); 225 h = mip_minify(ptex->height0, level); 226 if (w <= tile_width || h <= tile_height) 227 rtex->array_mode[level] = V_0280A0_ARRAY_1D_TILED_THIN1; 228 else 229 rtex->array_mode[level] = array_mode; 230 } 231 break; 232 } 233} 234 235static int r600_init_surface(struct r600_screen *rscreen, 236 struct radeon_surface *surface, 237 const struct pipe_resource *ptex, 238 unsigned array_mode, 239 bool is_transfer, bool is_flushed_depth) 240{ 241 const struct util_format_description *desc = 242 util_format_description(ptex->format); 243 bool is_depth, is_stencil; 244 245 is_depth = util_format_has_depth(desc); 246 is_stencil = util_format_has_stencil(desc); 247 248 surface->npix_x = ptex->width0; 249 surface->npix_y = ptex->height0; 250 surface->npix_z = ptex->depth0; 251 surface->blk_w = util_format_get_blockwidth(ptex->format); 252 surface->blk_h = util_format_get_blockheight(ptex->format); 253 surface->blk_d = 1; 254 surface->array_size = 1; 255 surface->last_level = ptex->last_level; 256 257 if (rscreen->chip_class >= EVERGREEN && 258 !is_transfer && !is_flushed_depth && 259 ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) { 260 surface->bpe = 4; /* stencil is allocated separately on evergreen */ 261 } else { 262 surface->bpe = util_format_get_blocksize(ptex->format); 263 /* align byte per element on dword */ 264 if (surface->bpe == 3) { 265 surface->bpe = 4; 266 } 267 } 268 269 surface->nsamples = 1; 270 surface->flags = 0; 271 switch (array_mode) { 272 case V_038000_ARRAY_1D_TILED_THIN1: 273 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); 274 break; 275 case V_038000_ARRAY_2D_TILED_THIN1: 276 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); 277 break; 278 case V_038000_ARRAY_LINEAR_ALIGNED: 279 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE); 280 break; 281 case V_038000_ARRAY_LINEAR_GENERAL: 282 default: 283 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR, MODE); 284 break; 285 } 286 switch (ptex->target) { 287 case PIPE_TEXTURE_1D: 288 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE); 289 break; 290 case PIPE_TEXTURE_RECT: 291 case PIPE_TEXTURE_2D: 292 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE); 293 break; 294 case PIPE_TEXTURE_3D: 295 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE); 296 break; 297 case PIPE_TEXTURE_1D_ARRAY: 298 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE); 299 surface->array_size = ptex->array_size; 300 break; 301 case PIPE_TEXTURE_2D_ARRAY: 302 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE); 303 surface->array_size = ptex->array_size; 304 break; 305 case PIPE_TEXTURE_CUBE: 306 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE); 307 break; 308 case PIPE_BUFFER: 309 default: 310 return -EINVAL; 311 } 312 if (ptex->bind & PIPE_BIND_SCANOUT) { 313 surface->flags |= RADEON_SURF_SCANOUT; 314 } 315 316 if (!is_transfer && !is_flushed_depth && is_depth) { 317 surface->flags |= RADEON_SURF_ZBUFFER; 318 319 if (is_stencil) { 320 surface->flags |= RADEON_SURF_SBUFFER; 321 } 322 } 323 return 0; 324} 325 326static int r600_setup_surface(struct pipe_screen *screen, 327 struct r600_resource_texture *rtex, 328 unsigned array_mode, 329 unsigned pitch_in_bytes_override) 330{ 331 struct pipe_resource *ptex = &rtex->resource.b.b; 332 struct r600_screen *rscreen = (struct r600_screen*)screen; 333 unsigned i; 334 int r; 335 336 r = rscreen->ws->surface_init(rscreen->ws, &rtex->surface); 337 if (r) { 338 return r; 339 } 340 rtex->size = rtex->surface.bo_size; 341 if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) { 342 /* old ddx on evergreen over estimate alignment for 1d, only 1 level 343 * for those 344 */ 345 rtex->surface.level[0].nblk_x = pitch_in_bytes_override / rtex->surface.bpe; 346 rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override; 347 rtex->surface.level[0].slice_size = pitch_in_bytes_override * rtex->surface.level[0].nblk_y; 348 if (rtex->surface.flags & RADEON_SURF_SBUFFER) { 349 rtex->surface.stencil_offset = rtex->surface.level[0].slice_size; 350 } 351 } 352 for (i = 0; i <= ptex->last_level; i++) { 353 rtex->offset[i] = rtex->surface.level[i].offset; 354 rtex->layer_size[i] = rtex->surface.level[i].slice_size; 355 rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes; 356 switch (rtex->surface.level[i].mode) { 357 case RADEON_SURF_MODE_LINEAR_ALIGNED: 358 rtex->array_mode[i] = V_038000_ARRAY_LINEAR_ALIGNED; 359 break; 360 case RADEON_SURF_MODE_1D: 361 rtex->array_mode[i] = V_038000_ARRAY_1D_TILED_THIN1; 362 break; 363 case RADEON_SURF_MODE_2D: 364 rtex->array_mode[i] = V_038000_ARRAY_2D_TILED_THIN1; 365 break; 366 default: 367 case RADEON_SURF_MODE_LINEAR: 368 rtex->array_mode[i] = 0; 369 break; 370 } 371 } 372 return 0; 373} 374 375static void r600_setup_miptree(struct pipe_screen *screen, 376 struct r600_resource_texture *rtex, 377 unsigned array_mode) 378{ 379 struct pipe_resource *ptex = &rtex->resource.b.b; 380 enum chip_class chipc = ((struct r600_screen*)screen)->chip_class; 381 unsigned size, layer_size, i, offset; 382 unsigned nblocksx, nblocksy; 383 384 for (i = 0, offset = 0; i <= ptex->last_level; i++) { 385 unsigned blocksize = util_format_get_blocksize(rtex->real_format); 386 unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode); 387 388 r600_texture_set_array_mode(screen, rtex, i, array_mode); 389 390 nblocksx = r600_texture_get_nblocksx(screen, rtex, i); 391 nblocksy = r600_texture_get_nblocksy(screen, rtex, i); 392 393 if (chipc >= EVERGREEN && array_mode == V_038000_ARRAY_LINEAR_GENERAL) 394 layer_size = align(nblocksx, 64) * nblocksy * blocksize; 395 else 396 layer_size = nblocksx * nblocksy * blocksize; 397 398 if (ptex->target == PIPE_TEXTURE_CUBE) { 399 if (chipc >= R700) 400 size = layer_size * 8; 401 else 402 size = layer_size * 6; 403 } 404 else if (ptex->target == PIPE_TEXTURE_3D) 405 size = layer_size * u_minify(ptex->depth0, i); 406 else 407 size = layer_size * ptex->array_size; 408 409 /* align base image and start of miptree */ 410 if ((i == 0) || (i == 1)) 411 offset = align(offset, base_align); 412 rtex->offset[i] = offset; 413 rtex->layer_size[i] = layer_size; 414 rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */ 415 rtex->pitch_in_bytes[i] = nblocksx * blocksize; 416 417 offset += size; 418 } 419 rtex->size = offset; 420} 421 422/* Figure out whether u_blitter will fallback to a transfer operation. 423 * If so, don't use a staging resource. 424 */ 425static boolean permit_hardware_blit(struct pipe_screen *screen, 426 const struct pipe_resource *res) 427{ 428 unsigned bind; 429 430 if (util_format_is_depth_or_stencil(res->format)) 431 bind = PIPE_BIND_DEPTH_STENCIL; 432 else 433 bind = PIPE_BIND_RENDER_TARGET; 434 435 /* hackaround for S3TC */ 436 if (util_format_is_compressed(res->format)) 437 return TRUE; 438 439 if (!screen->is_format_supported(screen, 440 res->format, 441 res->target, 442 res->nr_samples, 443 bind)) 444 return FALSE; 445 446 if (!screen->is_format_supported(screen, 447 res->format, 448 res->target, 449 res->nr_samples, 450 PIPE_BIND_SAMPLER_VIEW)) 451 return FALSE; 452 453 return TRUE; 454} 455 456static boolean r600_texture_get_handle(struct pipe_screen* screen, 457 struct pipe_resource *ptex, 458 struct winsys_handle *whandle) 459{ 460 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 461 struct r600_resource *resource = &rtex->resource; 462 struct radeon_surface *surface = &rtex->surface; 463 struct r600_screen *rscreen = (struct r600_screen*)screen; 464 465 rscreen->ws->buffer_set_tiling(resource->buf, 466 NULL, 467 surface->level[0].mode >= RADEON_SURF_MODE_1D ? 468 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 469 surface->level[0].mode >= RADEON_SURF_MODE_2D ? 470 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR, 471 surface->bankw, surface->bankh, 472 surface->tile_split, 473 surface->stencil_tile_split, 474 surface->mtilea, 475 rtex->pitch_in_bytes[0]); 476 477 return rscreen->ws->buffer_get_handle(resource->buf, 478 rtex->pitch_in_bytes[0], whandle); 479} 480 481static void r600_texture_destroy(struct pipe_screen *screen, 482 struct pipe_resource *ptex) 483{ 484 struct r600_resource_texture *rtex = (struct r600_resource_texture*)ptex; 485 struct r600_resource *resource = &rtex->resource; 486 487 if (rtex->flushed_depth_texture) 488 pipe_resource_reference((struct pipe_resource **)&rtex->flushed_depth_texture, NULL); 489 490 if (rtex->stencil) 491 pipe_resource_reference((struct pipe_resource **)&rtex->stencil, NULL); 492 493 pb_reference(&resource->buf, NULL); 494 FREE(rtex); 495} 496 497static const struct u_resource_vtbl r600_texture_vtbl = 498{ 499 r600_texture_get_handle, /* get_handle */ 500 r600_texture_destroy, /* resource_destroy */ 501 r600_texture_get_transfer, /* get_transfer */ 502 r600_texture_transfer_destroy, /* transfer_destroy */ 503 r600_texture_transfer_map, /* transfer_map */ 504 NULL, /* transfer_flush_region */ 505 r600_texture_transfer_unmap, /* transfer_unmap */ 506 NULL /* transfer_inline_write */ 507}; 508 509static struct r600_resource_texture * 510r600_texture_create_object(struct pipe_screen *screen, 511 const struct pipe_resource *base, 512 unsigned array_mode, 513 unsigned pitch_in_bytes_override, 514 unsigned max_buffer_size, 515 struct pb_buffer *buf, 516 boolean alloc_bo, 517 struct radeon_surface *surface) 518{ 519 struct r600_resource_texture *rtex; 520 struct r600_resource *resource; 521 struct r600_screen *rscreen = (struct r600_screen*)screen; 522 int r; 523 524 rtex = CALLOC_STRUCT(r600_resource_texture); 525 if (rtex == NULL) 526 return NULL; 527 528 resource = &rtex->resource; 529 resource->b.b = *base; 530 resource->b.vtbl = &r600_texture_vtbl; 531 pipe_reference_init(&resource->b.b.reference, 1); 532 resource->b.b.screen = screen; 533 rtex->pitch_override = pitch_in_bytes_override; 534 rtex->real_format = base->format; 535 536 /* We must split depth and stencil into two separate buffers on Evergreen. */ 537 if ((base->bind & PIPE_BIND_DEPTH_STENCIL) && 538 ((struct r600_screen*)screen)->chip_class >= EVERGREEN && 539 util_format_is_depth_and_stencil(base->format) && 540 !rscreen->use_surface_alloc) { 541 struct pipe_resource stencil; 542 unsigned stencil_pitch_override = 0; 543 544 switch (base->format) { 545 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 546 rtex->real_format = PIPE_FORMAT_Z24X8_UNORM; 547 break; 548 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 549 rtex->real_format = PIPE_FORMAT_X8Z24_UNORM; 550 break; 551 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 552 rtex->real_format = PIPE_FORMAT_Z32_FLOAT; 553 break; 554 default: 555 assert(0); 556 FREE(rtex); 557 return NULL; 558 } 559 560 /* Divide the pitch in bytes by 4 for stencil, because it has a smaller pixel size. */ 561 if (pitch_in_bytes_override) { 562 assert(base->format == PIPE_FORMAT_Z24_UNORM_S8_UINT || 563 base->format == PIPE_FORMAT_S8_UINT_Z24_UNORM); 564 stencil_pitch_override = pitch_in_bytes_override / 4; 565 } 566 567 /* Allocate the stencil buffer. */ 568 stencil = *base; 569 stencil.format = PIPE_FORMAT_S8_UINT; 570 rtex->stencil = r600_texture_create_object(screen, &stencil, array_mode, 571 stencil_pitch_override, 572 max_buffer_size, NULL, FALSE, surface); 573 if (!rtex->stencil) { 574 FREE(rtex); 575 return NULL; 576 } 577 /* Proceed in creating the depth buffer. */ 578 } 579 580 /* only mark depth textures the HW can hit as depth textures */ 581 if (util_format_is_depth_or_stencil(rtex->real_format) && 582 permit_hardware_blit(screen, base)) 583 rtex->is_depth = true; 584 585 r600_setup_miptree(screen, rtex, array_mode); 586 if (rscreen->use_surface_alloc) { 587 rtex->surface = *surface; 588 r = r600_setup_surface(screen, rtex, array_mode, 589 pitch_in_bytes_override); 590 if (r) { 591 FREE(rtex); 592 return NULL; 593 } 594 } 595 596 /* If we initialized separate stencil for Evergreen. place it after depth. */ 597 if (rtex->stencil) { 598 unsigned stencil_align, stencil_offset; 599 600 stencil_align = r600_get_base_alignment(screen, rtex->stencil->real_format, array_mode); 601 stencil_offset = align(rtex->size, stencil_align); 602 603 for (unsigned i = 0; i <= rtex->stencil->resource.b.b.last_level; i++) 604 rtex->stencil->offset[i] += stencil_offset; 605 606 rtex->size = stencil_offset + rtex->stencil->size; 607 } 608 609 /* Now create the backing buffer. */ 610 if (!buf && alloc_bo) { 611 struct pipe_resource *ptex = &rtex->resource.b.b; 612 unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode); 613 614 if (rscreen->use_surface_alloc) { 615 base_align = rtex->surface.bo_alignment; 616 } else if (util_format_is_depth_or_stencil(rtex->real_format)) { 617 /* ugly work around depth buffer need stencil room at end of bo */ 618 rtex->size += ptex->width0 * ptex->height0; 619 } 620 if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) { 621 pipe_resource_reference((struct pipe_resource**)&rtex->stencil, NULL); 622 FREE(rtex); 623 return NULL; 624 } 625 } else if (buf) { 626 resource->buf = buf; 627 resource->cs_buf = rscreen->ws->buffer_get_cs_handle(buf); 628 resource->domains = RADEON_DOMAIN_GTT | RADEON_DOMAIN_VRAM; 629 } 630 631 if (rtex->stencil) { 632 pb_reference(&rtex->stencil->resource.buf, rtex->resource.buf); 633 rtex->stencil->resource.cs_buf = rtex->resource.cs_buf; 634 rtex->stencil->resource.domains = rtex->resource.domains; 635 } 636 return rtex; 637} 638 639struct pipe_resource *r600_texture_create(struct pipe_screen *screen, 640 const struct pipe_resource *templ) 641{ 642 struct r600_screen *rscreen = (struct r600_screen*)screen; 643 struct radeon_surface surface; 644 unsigned array_mode = 0; 645 int r; 646 647 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER)) { 648 if (rscreen->use_surface_alloc && 649 !(templ->bind & PIPE_BIND_SCANOUT) && 650 templ->usage != PIPE_USAGE_STAGING && 651 templ->usage != PIPE_USAGE_STREAM && 652 permit_hardware_blit(screen, templ)) { 653 array_mode = V_038000_ARRAY_2D_TILED_THIN1; 654 } else if (util_format_is_compressed(templ->format)) { 655 array_mode = V_038000_ARRAY_1D_TILED_THIN1; 656 } 657 } 658 659 r = r600_init_surface(rscreen, &surface, templ, array_mode, 660 templ->flags & R600_RESOURCE_FLAG_TRANSFER, 661 templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); 662 if (r) { 663 return NULL; 664 } 665 r = rscreen->ws->surface_best(rscreen->ws, &surface); 666 if (r) { 667 return NULL; 668 } 669 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 670 0, 0, NULL, TRUE, &surface); 671} 672 673static struct pipe_surface *r600_create_surface(struct pipe_context *pipe, 674 struct pipe_resource *texture, 675 const struct pipe_surface *surf_tmpl) 676{ 677 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 678 struct r600_surface *surface = CALLOC_STRUCT(r600_surface); 679 unsigned level = surf_tmpl->u.tex.level; 680 681 assert(surf_tmpl->u.tex.first_layer == surf_tmpl->u.tex.last_layer); 682 if (surface == NULL) 683 return NULL; 684 pipe_reference_init(&surface->base.reference, 1); 685 pipe_resource_reference(&surface->base.texture, texture); 686 surface->base.context = pipe; 687 surface->base.format = surf_tmpl->format; 688 surface->base.width = mip_minify(texture->width0, level); 689 surface->base.height = mip_minify(texture->height0, level); 690 surface->base.usage = surf_tmpl->usage; 691 surface->base.texture = texture; 692 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer; 693 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer; 694 surface->base.u.tex.level = level; 695 696 surface->aligned_height = r600_texture_get_nblocksy(pipe->screen, 697 rtex, level); 698 return &surface->base; 699} 700 701static void r600_surface_destroy(struct pipe_context *pipe, 702 struct pipe_surface *surface) 703{ 704 pipe_resource_reference(&surface->texture, NULL); 705 FREE(surface); 706} 707 708struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, 709 const struct pipe_resource *templ, 710 struct winsys_handle *whandle) 711{ 712 struct r600_screen *rscreen = (struct r600_screen*)screen; 713 struct pb_buffer *buf = NULL; 714 unsigned stride = 0; 715 unsigned array_mode = 0; 716 enum radeon_bo_layout micro, macro; 717 struct radeon_surface surface; 718 int r; 719 720 /* Support only 2D textures without mipmaps */ 721 if ((templ->target != PIPE_TEXTURE_2D && templ->target != PIPE_TEXTURE_RECT) || 722 templ->depth0 != 1 || templ->last_level != 0) 723 return NULL; 724 725 buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle, &stride); 726 if (!buf) 727 return NULL; 728 729 rscreen->ws->buffer_get_tiling(buf, µ, ¯o, 730 &surface.bankw, &surface.bankh, 731 &surface.tile_split, 732 &surface.stencil_tile_split, 733 &surface.mtilea); 734 735 if (macro == RADEON_LAYOUT_TILED) 736 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1; 737 else if (micro == RADEON_LAYOUT_TILED) 738 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1; 739 else 740 array_mode = 0; 741 742 r = r600_init_surface(rscreen, &surface, templ, array_mode, false, false); 743 if (r) { 744 return NULL; 745 } 746 return (struct pipe_resource *)r600_texture_create_object(screen, templ, array_mode, 747 stride, 0, buf, FALSE, &surface); 748} 749 750bool r600_init_flushed_depth_texture(struct pipe_context *ctx, 751 struct pipe_resource *texture, 752 struct r600_resource_texture **staging) 753{ 754 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 755 struct pipe_resource resource; 756 struct r600_resource_texture **flushed_depth_texture = staging ? 757 staging : &rtex->flushed_depth_texture; 758 759 if (!staging && rtex->flushed_depth_texture) 760 return true; /* it's ready */ 761 762 resource.target = texture->target; 763 resource.format = texture->format; 764 resource.width0 = texture->width0; 765 resource.height0 = texture->height0; 766 resource.depth0 = texture->depth0; 767 resource.array_size = texture->array_size; 768 resource.last_level = texture->last_level; 769 resource.nr_samples = texture->nr_samples; 770 resource.usage = staging ? PIPE_USAGE_DYNAMIC : PIPE_USAGE_DEFAULT; 771 resource.bind = texture->bind & ~PIPE_BIND_DEPTH_STENCIL; 772 resource.flags = texture->flags | R600_RESOURCE_FLAG_FLUSHED_DEPTH; 773 774 if (staging) 775 resource.flags |= R600_RESOURCE_FLAG_TRANSFER; 776 777 *flushed_depth_texture = (struct r600_resource_texture *)ctx->screen->resource_create(ctx->screen, &resource); 778 if (*flushed_depth_texture == NULL) { 779 R600_ERR("failed to create temporary texture to hold flushed depth\n"); 780 return false; 781 } 782 783 (*flushed_depth_texture)->is_flushing_texture = TRUE; 784 return true; 785} 786 787/* Needs adjustment for pixelformat: 788 */ 789static INLINE unsigned u_box_volume( const struct pipe_box *box ) 790{ 791 return box->width * box->depth * box->height; 792} 793 794struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, 795 struct pipe_resource *texture, 796 unsigned level, 797 unsigned usage, 798 const struct pipe_box *box) 799{ 800 struct r600_context *rctx = (struct r600_context*)ctx; 801 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 802 struct pipe_resource resource; 803 struct r600_transfer *trans; 804 boolean use_staging_texture = FALSE; 805 806 /* We cannot map a tiled texture directly because the data is 807 * in a different order, therefore we do detiling using a blit. 808 * 809 * Also, use a temporary in GTT memory for read transfers, as 810 * the CPU is much happier reading out of cached system memory 811 * than uncached VRAM. 812 */ 813 if (R600_TEX_IS_TILED(rtex, level)) { 814 use_staging_texture = TRUE; 815 } 816 817 if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024) 818 use_staging_texture = TRUE; 819 820 /* Use a staging texture for uploads if the underlying BO is busy. */ 821 if (!(usage & PIPE_TRANSFER_READ) && 822 (rctx->ws->cs_is_buffer_referenced(rctx->cs, rtex->resource.cs_buf, RADEON_USAGE_READWRITE) || 823 rctx->ws->buffer_is_busy(rtex->resource.buf, RADEON_USAGE_READWRITE))) { 824 use_staging_texture = TRUE; 825 } 826 827 if (!permit_hardware_blit(ctx->screen, texture) || 828 (texture->flags & R600_RESOURCE_FLAG_TRANSFER)) { 829 use_staging_texture = FALSE; 830 } 831 832 if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY)) { 833 return NULL; 834 } 835 836 trans = CALLOC_STRUCT(r600_transfer); 837 if (trans == NULL) 838 return NULL; 839 pipe_resource_reference(&trans->transfer.resource, texture); 840 trans->transfer.level = level; 841 trans->transfer.usage = usage; 842 trans->transfer.box = *box; 843 if (rtex->is_depth) { 844 /* XXX: only readback the rectangle which is being mapped? 845 */ 846 /* XXX: when discard is true, no need to read back from depth texture 847 */ 848 struct r600_resource_texture *staging_depth; 849 850 if (!r600_init_flushed_depth_texture(ctx, texture, &staging_depth)) { 851 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 852 pipe_resource_reference(&trans->transfer.resource, NULL); 853 FREE(trans); 854 return NULL; 855 } 856 857 r600_blit_uncompress_depth(ctx, rtex, staging_depth, 858 level, level, 859 box->z, box->z + box->depth - 1); 860 861 trans->transfer.stride = staging_depth->pitch_in_bytes[level]; 862 trans->offset = r600_texture_get_offset(staging_depth, level, box->z); 863 trans->staging = (struct r600_resource*)staging_depth; 864 return &trans->transfer; 865 } else if (use_staging_texture) { 866 resource.target = PIPE_TEXTURE_2D; 867 resource.format = texture->format; 868 resource.width0 = box->width; 869 resource.height0 = box->height; 870 resource.depth0 = 1; 871 resource.array_size = 1; 872 resource.last_level = 0; 873 resource.nr_samples = 0; 874 resource.usage = PIPE_USAGE_STAGING; 875 resource.bind = 0; 876 resource.flags = R600_RESOURCE_FLAG_TRANSFER; 877 /* For texture reading, the temporary (detiled) texture is used as 878 * a render target when blitting from a tiled texture. */ 879 if (usage & PIPE_TRANSFER_READ) { 880 resource.bind |= PIPE_BIND_RENDER_TARGET; 881 } 882 /* For texture writing, the temporary texture is used as a sampler 883 * when blitting into a tiled texture. */ 884 if (usage & PIPE_TRANSFER_WRITE) { 885 resource.bind |= PIPE_BIND_SAMPLER_VIEW; 886 } 887 /* Create the temporary texture. */ 888 trans->staging = (struct r600_resource*)ctx->screen->resource_create(ctx->screen, &resource); 889 if (trans->staging == NULL) { 890 R600_ERR("failed to create temporary texture to hold untiled copy\n"); 891 pipe_resource_reference(&trans->transfer.resource, NULL); 892 FREE(trans); 893 return NULL; 894 } 895 896 trans->transfer.stride = 897 ((struct r600_resource_texture *)trans->staging)->pitch_in_bytes[0]; 898 if (usage & PIPE_TRANSFER_READ) { 899 r600_copy_to_staging_texture(ctx, trans); 900 /* Always referenced in the blit. */ 901 r600_flush(ctx, NULL, 0); 902 } 903 return &trans->transfer; 904 } 905 trans->transfer.stride = rtex->pitch_in_bytes[level]; 906 trans->transfer.layer_stride = rtex->layer_size[level]; 907 trans->offset = r600_texture_get_offset(rtex, level, box->z); 908 return &trans->transfer; 909} 910 911void r600_texture_transfer_destroy(struct pipe_context *ctx, 912 struct pipe_transfer *transfer) 913{ 914 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 915 struct pipe_resource *texture = transfer->resource; 916 struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture; 917 918 if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtransfer->staging) { 919 if (rtex->is_depth) { 920 ctx->resource_copy_region(ctx, texture, transfer->level, 921 transfer->box.x, transfer->box.y, transfer->box.z, 922 &rtransfer->staging->b.b, transfer->level, 923 &transfer->box); 924 } else { 925 r600_copy_from_staging_texture(ctx, rtransfer); 926 } 927 } 928 929 if (rtransfer->staging) 930 pipe_resource_reference((struct pipe_resource**)&rtransfer->staging, NULL); 931 932 pipe_resource_reference(&transfer->resource, NULL); 933 FREE(transfer); 934} 935 936void* r600_texture_transfer_map(struct pipe_context *ctx, 937 struct pipe_transfer* transfer) 938{ 939 struct r600_context *rctx = (struct r600_context *)ctx; 940 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 941 struct radeon_winsys_cs_handle *buf; 942 struct r600_resource_texture *rtex = 943 (struct r600_resource_texture*)transfer->resource; 944 enum pipe_format format = transfer->resource->format; 945 unsigned offset = 0; 946 char *map; 947 948 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 949 return r600_compute_global_transfer_map(ctx, transfer); 950 } 951 952 if (rtransfer->staging) { 953 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 954 } else { 955 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 956 } 957 958 if (rtex->is_depth || !rtransfer->staging) 959 offset = rtransfer->offset + 960 transfer->box.y / util_format_get_blockheight(format) * transfer->stride + 961 transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format); 962 963 if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) { 964 return NULL; 965 } 966 967 return map + offset; 968} 969 970void r600_texture_transfer_unmap(struct pipe_context *ctx, 971 struct pipe_transfer* transfer) 972{ 973 struct r600_transfer *rtransfer = (struct r600_transfer*)transfer; 974 struct r600_context *rctx = (struct r600_context*)ctx; 975 struct radeon_winsys_cs_handle *buf; 976 977 if ((transfer->resource->bind & PIPE_BIND_GLOBAL) && transfer->resource->target == PIPE_BUFFER) { 978 return r600_compute_global_transfer_unmap(ctx, transfer); 979 } 980 981 if (rtransfer->staging) { 982 buf = ((struct r600_resource *)rtransfer->staging)->cs_buf; 983 } else { 984 buf = ((struct r600_resource *)transfer->resource)->cs_buf; 985 } 986 rctx->ws->buffer_unmap(buf); 987} 988 989void r600_init_surface_functions(struct r600_context *r600) 990{ 991 r600->context.create_surface = r600_create_surface; 992 r600->context.surface_destroy = r600_surface_destroy; 993} 994 995static unsigned r600_get_swizzle_combined(const unsigned char *swizzle_format, 996 const unsigned char *swizzle_view) 997{ 998 unsigned i; 999 unsigned char swizzle[4]; 1000 unsigned result = 0; 1001 const uint32_t swizzle_shift[4] = { 1002 16, 19, 22, 25, 1003 }; 1004 const uint32_t swizzle_bit[4] = { 1005 0, 1, 2, 3, 1006 }; 1007 1008 if (swizzle_view) { 1009 util_format_compose_swizzles(swizzle_format, swizzle_view, swizzle); 1010 } else { 1011 memcpy(swizzle, swizzle_format, 4); 1012 } 1013 1014 /* Get swizzle. */ 1015 for (i = 0; i < 4; i++) { 1016 switch (swizzle[i]) { 1017 case UTIL_FORMAT_SWIZZLE_Y: 1018 result |= swizzle_bit[1] << swizzle_shift[i]; 1019 break; 1020 case UTIL_FORMAT_SWIZZLE_Z: 1021 result |= swizzle_bit[2] << swizzle_shift[i]; 1022 break; 1023 case UTIL_FORMAT_SWIZZLE_W: 1024 result |= swizzle_bit[3] << swizzle_shift[i]; 1025 break; 1026 case UTIL_FORMAT_SWIZZLE_0: 1027 result |= V_038010_SQ_SEL_0 << swizzle_shift[i]; 1028 break; 1029 case UTIL_FORMAT_SWIZZLE_1: 1030 result |= V_038010_SQ_SEL_1 << swizzle_shift[i]; 1031 break; 1032 default: /* UTIL_FORMAT_SWIZZLE_X */ 1033 result |= swizzle_bit[0] << swizzle_shift[i]; 1034 } 1035 } 1036 return result; 1037} 1038 1039/* texture format translate */ 1040uint32_t r600_translate_texformat(struct pipe_screen *screen, 1041 enum pipe_format format, 1042 const unsigned char *swizzle_view, 1043 uint32_t *word4_p, uint32_t *yuv_format_p) 1044{ 1045 uint32_t result = 0, word4 = 0, yuv_format = 0; 1046 const struct util_format_description *desc; 1047 boolean uniform = TRUE; 1048 static int r600_enable_s3tc = -1; 1049 bool is_srgb_valid = FALSE; 1050 1051 int i; 1052 const uint32_t sign_bit[4] = { 1053 S_038010_FORMAT_COMP_X(V_038010_SQ_FORMAT_COMP_SIGNED), 1054 S_038010_FORMAT_COMP_Y(V_038010_SQ_FORMAT_COMP_SIGNED), 1055 S_038010_FORMAT_COMP_Z(V_038010_SQ_FORMAT_COMP_SIGNED), 1056 S_038010_FORMAT_COMP_W(V_038010_SQ_FORMAT_COMP_SIGNED) 1057 }; 1058 desc = util_format_description(format); 1059 1060 word4 |= r600_get_swizzle_combined(desc->swizzle, swizzle_view); 1061 1062 /* Colorspace (return non-RGB formats directly). */ 1063 switch (desc->colorspace) { 1064 /* Depth stencil formats */ 1065 case UTIL_FORMAT_COLORSPACE_ZS: 1066 switch (format) { 1067 case PIPE_FORMAT_Z16_UNORM: 1068 result = FMT_16; 1069 goto out_word4; 1070 case PIPE_FORMAT_X24S8_UINT: 1071 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1072 case PIPE_FORMAT_Z24X8_UNORM: 1073 case PIPE_FORMAT_Z24_UNORM_S8_UINT: 1074 result = FMT_8_24; 1075 goto out_word4; 1076 case PIPE_FORMAT_S8X24_UINT: 1077 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1078 case PIPE_FORMAT_X8Z24_UNORM: 1079 case PIPE_FORMAT_S8_UINT_Z24_UNORM: 1080 result = FMT_24_8; 1081 goto out_word4; 1082 case PIPE_FORMAT_S8_UINT: 1083 result = FMT_8; 1084 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1085 goto out_word4; 1086 case PIPE_FORMAT_Z32_FLOAT: 1087 result = FMT_32_FLOAT; 1088 goto out_word4; 1089 case PIPE_FORMAT_X32_S8X24_UINT: 1090 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1091 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT: 1092 result = FMT_X24_8_32_FLOAT; 1093 goto out_word4; 1094 default: 1095 goto out_unknown; 1096 } 1097 1098 case UTIL_FORMAT_COLORSPACE_YUV: 1099 yuv_format |= (1 << 30); 1100 switch (format) { 1101 case PIPE_FORMAT_UYVY: 1102 case PIPE_FORMAT_YUYV: 1103 default: 1104 break; 1105 } 1106 goto out_unknown; /* XXX */ 1107 1108 case UTIL_FORMAT_COLORSPACE_SRGB: 1109 word4 |= S_038010_FORCE_DEGAMMA(1); 1110 break; 1111 1112 default: 1113 break; 1114 } 1115 1116 if (r600_enable_s3tc == -1) { 1117 struct r600_screen *rscreen = (struct r600_screen *)screen; 1118 if (rscreen->info.drm_minor >= 9) 1119 r600_enable_s3tc = 1; 1120 else 1121 r600_enable_s3tc = debug_get_bool_option("R600_ENABLE_S3TC", FALSE); 1122 } 1123 1124 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) { 1125 if (!r600_enable_s3tc) 1126 goto out_unknown; 1127 1128 switch (format) { 1129 case PIPE_FORMAT_RGTC1_SNORM: 1130 case PIPE_FORMAT_LATC1_SNORM: 1131 word4 |= sign_bit[0]; 1132 case PIPE_FORMAT_RGTC1_UNORM: 1133 case PIPE_FORMAT_LATC1_UNORM: 1134 result = FMT_BC4; 1135 goto out_word4; 1136 case PIPE_FORMAT_RGTC2_SNORM: 1137 case PIPE_FORMAT_LATC2_SNORM: 1138 word4 |= sign_bit[0] | sign_bit[1]; 1139 case PIPE_FORMAT_RGTC2_UNORM: 1140 case PIPE_FORMAT_LATC2_UNORM: 1141 result = FMT_BC5; 1142 goto out_word4; 1143 default: 1144 goto out_unknown; 1145 } 1146 } 1147 1148 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) { 1149 1150 if (!r600_enable_s3tc) 1151 goto out_unknown; 1152 1153 if (!util_format_s3tc_enabled) { 1154 goto out_unknown; 1155 } 1156 1157 switch (format) { 1158 case PIPE_FORMAT_DXT1_RGB: 1159 case PIPE_FORMAT_DXT1_RGBA: 1160 case PIPE_FORMAT_DXT1_SRGB: 1161 case PIPE_FORMAT_DXT1_SRGBA: 1162 result = FMT_BC1; 1163 is_srgb_valid = TRUE; 1164 goto out_word4; 1165 case PIPE_FORMAT_DXT3_RGBA: 1166 case PIPE_FORMAT_DXT3_SRGBA: 1167 result = FMT_BC2; 1168 is_srgb_valid = TRUE; 1169 goto out_word4; 1170 case PIPE_FORMAT_DXT5_RGBA: 1171 case PIPE_FORMAT_DXT5_SRGBA: 1172 result = FMT_BC3; 1173 is_srgb_valid = TRUE; 1174 goto out_word4; 1175 default: 1176 goto out_unknown; 1177 } 1178 } 1179 1180 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) { 1181 switch (format) { 1182 case PIPE_FORMAT_R8G8_B8G8_UNORM: 1183 case PIPE_FORMAT_G8R8_B8R8_UNORM: 1184 result = FMT_GB_GR; 1185 goto out_word4; 1186 case PIPE_FORMAT_G8R8_G8B8_UNORM: 1187 case PIPE_FORMAT_R8G8_R8B8_UNORM: 1188 result = FMT_BG_RG; 1189 goto out_word4; 1190 default: 1191 goto out_unknown; 1192 } 1193 } 1194 1195 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) { 1196 result = FMT_5_9_9_9_SHAREDEXP; 1197 goto out_word4; 1198 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) { 1199 result = FMT_10_11_11_FLOAT; 1200 goto out_word4; 1201 } 1202 1203 1204 for (i = 0; i < desc->nr_channels; i++) { 1205 if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) { 1206 word4 |= sign_bit[i]; 1207 } 1208 } 1209 1210 /* R8G8Bx_SNORM - XXX CxV8U8 */ 1211 1212 /* See whether the components are of the same size. */ 1213 for (i = 1; i < desc->nr_channels; i++) { 1214 uniform = uniform && desc->channel[0].size == desc->channel[i].size; 1215 } 1216 1217 /* Non-uniform formats. */ 1218 if (!uniform) { 1219 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 1220 desc->channel[0].pure_integer) 1221 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1222 switch(desc->nr_channels) { 1223 case 3: 1224 if (desc->channel[0].size == 5 && 1225 desc->channel[1].size == 6 && 1226 desc->channel[2].size == 5) { 1227 result = FMT_5_6_5; 1228 goto out_word4; 1229 } 1230 goto out_unknown; 1231 case 4: 1232 if (desc->channel[0].size == 5 && 1233 desc->channel[1].size == 5 && 1234 desc->channel[2].size == 5 && 1235 desc->channel[3].size == 1) { 1236 result = FMT_1_5_5_5; 1237 goto out_word4; 1238 } 1239 if (desc->channel[0].size == 10 && 1240 desc->channel[1].size == 10 && 1241 desc->channel[2].size == 10 && 1242 desc->channel[3].size == 2) { 1243 result = FMT_2_10_10_10; 1244 goto out_word4; 1245 } 1246 goto out_unknown; 1247 } 1248 goto out_unknown; 1249 } 1250 1251 /* Find the first non-VOID channel. */ 1252 for (i = 0; i < 4; i++) { 1253 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) { 1254 break; 1255 } 1256 } 1257 1258 if (i == 4) 1259 goto out_unknown; 1260 1261 /* uniform formats */ 1262 switch (desc->channel[i].type) { 1263 case UTIL_FORMAT_TYPE_UNSIGNED: 1264 case UTIL_FORMAT_TYPE_SIGNED: 1265#if 0 1266 if (!desc->channel[i].normalized && 1267 desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB) { 1268 goto out_unknown; 1269 } 1270#endif 1271 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_SRGB && 1272 desc->channel[i].pure_integer) 1273 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT); 1274 1275 switch (desc->channel[i].size) { 1276 case 4: 1277 switch (desc->nr_channels) { 1278 case 2: 1279 result = FMT_4_4; 1280 goto out_word4; 1281 case 4: 1282 result = FMT_4_4_4_4; 1283 goto out_word4; 1284 } 1285 goto out_unknown; 1286 case 8: 1287 switch (desc->nr_channels) { 1288 case 1: 1289 result = FMT_8; 1290 goto out_word4; 1291 case 2: 1292 result = FMT_8_8; 1293 goto out_word4; 1294 case 4: 1295 result = FMT_8_8_8_8; 1296 is_srgb_valid = TRUE; 1297 goto out_word4; 1298 } 1299 goto out_unknown; 1300 case 16: 1301 switch (desc->nr_channels) { 1302 case 1: 1303 result = FMT_16; 1304 goto out_word4; 1305 case 2: 1306 result = FMT_16_16; 1307 goto out_word4; 1308 case 4: 1309 result = FMT_16_16_16_16; 1310 goto out_word4; 1311 } 1312 goto out_unknown; 1313 case 32: 1314 switch (desc->nr_channels) { 1315 case 1: 1316 result = FMT_32; 1317 goto out_word4; 1318 case 2: 1319 result = FMT_32_32; 1320 goto out_word4; 1321 case 4: 1322 result = FMT_32_32_32_32; 1323 goto out_word4; 1324 } 1325 } 1326 goto out_unknown; 1327 1328 case UTIL_FORMAT_TYPE_FLOAT: 1329 switch (desc->channel[i].size) { 1330 case 16: 1331 switch (desc->nr_channels) { 1332 case 1: 1333 result = FMT_16_FLOAT; 1334 goto out_word4; 1335 case 2: 1336 result = FMT_16_16_FLOAT; 1337 goto out_word4; 1338 case 4: 1339 result = FMT_16_16_16_16_FLOAT; 1340 goto out_word4; 1341 } 1342 goto out_unknown; 1343 case 32: 1344 switch (desc->nr_channels) { 1345 case 1: 1346 result = FMT_32_FLOAT; 1347 goto out_word4; 1348 case 2: 1349 result = FMT_32_32_FLOAT; 1350 goto out_word4; 1351 case 4: 1352 result = FMT_32_32_32_32_FLOAT; 1353 goto out_word4; 1354 } 1355 } 1356 goto out_unknown; 1357 } 1358 1359out_word4: 1360 1361 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB && !is_srgb_valid) 1362 return ~0; 1363 if (word4_p) 1364 *word4_p = word4; 1365 if (yuv_format_p) 1366 *yuv_format_p = yuv_format; 1367 return result; 1368out_unknown: 1369 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */ 1370 return ~0; 1371} 1372