1a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===-- AMDGPUInstrInfo.cpp - Base class for AMD GPU InstrInfo ------------===// 2a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 3a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// The LLVM Compiler Infrastructure 4a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 5a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// This file is distributed under the University of Illinois Open Source 6a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// License. See LICENSE.TXT for details. 7a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 8a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 9a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 10a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// This file contains the implementation of the TargetInstrInfo class that is 11a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// common to all AMD GPUs. 12a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard// 13a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard//===----------------------------------------------------------------------===// 14a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 15a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "AMDGPUInstrInfo.h" 16a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "AMDGPURegisterInfo.h" 17a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "AMDGPUTargetMachine.h" 18a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "AMDIL.h" 19ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard#include "AMDILUtilityFunctions.h" 20ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard#include "llvm/CodeGen/MachineFrameInfo.h" 2127ae41c83dafcec09e870b3cf08b060064dbb122Tom Stellard#include "llvm/CodeGen/MachineInstrBuilder.h" 22a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard#include "llvm/CodeGen/MachineRegisterInfo.h" 23a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 24ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard#define GET_INSTRINFO_CTOR 25ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard#include "AMDGPUGenInstrInfo.inc" 26ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 27a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellardusing namespace llvm; 28a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 29ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm) 305a1edb8655aeab17bf0d90e202fb31a1adb53498Tom Stellard : AMDGPUGenInstrInfo(0,0), RI(tm, *this), TM(tm) { } 31ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 32ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardconst AMDGPURegisterInfo &AMDGPUInstrInfo::getRegisterInfo() const { 33ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return RI; 34ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 35ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 36ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool AMDGPUInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 37ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard unsigned &SrcReg, unsigned &DstReg, 38ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard unsigned &SubIdx) const { 39ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard// TODO: Implement this function 40ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return false; 41ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 42ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 43ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardunsigned AMDGPUInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 44ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard int &FrameIndex) const { 45ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard// TODO: Implement this function 46ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return 0; 47ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 48ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 49ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardunsigned AMDGPUInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 50ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard int &FrameIndex) const { 51ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard// TODO: Implement this function 52ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return 0; 53ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 54ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 55ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool AMDGPUInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 56ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const MachineMemOperand *&MMO, 57ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard int &FrameIndex) const { 58ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard// TODO: Implement this function 59ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return false; 60ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 61ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardunsigned AMDGPUInstrInfo::isStoreFromStackSlot(const MachineInstr *MI, 62ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard int &FrameIndex) const { 63ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard// TODO: Implement this function 64ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return 0; 65ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 66ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardunsigned AMDGPUInstrInfo::isStoreFromStackSlotPostFE(const MachineInstr *MI, 67ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard int &FrameIndex) const { 68ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard// TODO: Implement this function 69ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return 0; 70ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 71ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool AMDGPUInstrInfo::hasStoreFromStackSlot(const MachineInstr *MI, 72ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const MachineMemOperand *&MMO, 73ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard int &FrameIndex) const { 74ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard// TODO: Implement this function 75ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return false; 76ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 77ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 78ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardMachineInstr * 79ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 80ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard MachineBasicBlock::iterator &MBBI, 81ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard LiveVariables *LV) const { 82ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard// TODO: Implement this function 83ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return NULL; 84ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 85ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool AMDGPUInstrInfo::getNextBranchInstr(MachineBasicBlock::iterator &iter, 86ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard MachineBasicBlock &MBB) const { 87ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard while (iter != MBB.end()) { 88ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard switch (iter->getOpcode()) { 89ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard default: 90ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard break; 91ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard ExpandCaseToAllScalarTypes(AMDGPU::BRANCH_COND); 92ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard case AMDGPU::BRANCH: 93ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return true; 94ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard }; 95ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard ++iter; 96ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard } 97ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return false; 98ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 99ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 100ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardMachineBasicBlock::iterator skipFlowControl(MachineBasicBlock *MBB) { 101ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard MachineBasicBlock::iterator tmp = MBB->end(); 102ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard if (!MBB->size()) { 103ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return MBB->end(); 104ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard } 105ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard while (--tmp) { 106ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard if (tmp->getOpcode() == AMDGPU::ENDLOOP 107ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard || tmp->getOpcode() == AMDGPU::ENDIF 108ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard || tmp->getOpcode() == AMDGPU::ELSE) { 109ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard if (tmp == MBB->begin()) { 110ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return tmp; 111ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard } else { 112ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard continue; 113ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard } 114ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard } else { 115ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return ++tmp; 116ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard } 117ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard } 118ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return MBB->end(); 119ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 120ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 121ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardvoid 122ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 123ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard MachineBasicBlock::iterator MI, 124ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard unsigned SrcReg, bool isKill, 125ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard int FrameIndex, 126ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const TargetRegisterClass *RC, 127ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const TargetRegisterInfo *TRI) const { 1280ce6e506016222b264163ee718202371f19064dbTom Stellard assert(!"Not Implemented"); 129ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 130ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 131ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardvoid 132ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 133ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard MachineBasicBlock::iterator MI, 134ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard unsigned DestReg, int FrameIndex, 135ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const TargetRegisterClass *RC, 136ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const TargetRegisterInfo *TRI) const { 1370ce6e506016222b264163ee718202371f19064dbTom Stellard assert(!"Not Implemented"); 138ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 1390ce6e506016222b264163ee718202371f19064dbTom Stellard 140ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardMachineInstr * 141ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 142ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard MachineInstr *MI, 143ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const SmallVectorImpl<unsigned> &Ops, 144ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard int FrameIndex) const { 145ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard// TODO: Implement this function 146ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return 0; 147ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 148ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardMachineInstr* 149ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 150ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard MachineInstr *MI, 151ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const SmallVectorImpl<unsigned> &Ops, 152ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard MachineInstr *LoadMI) const { 153ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 154ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return 0; 155ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 156ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool 157ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 158ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const SmallVectorImpl<unsigned> &Ops) const 159ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard{ 160ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 161ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return false; 162ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 163ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool 164ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 165ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard unsigned Reg, bool UnfoldLoad, 166ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard bool UnfoldStore, 167ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard SmallVectorImpl<MachineInstr*> &NewMIs) const { 168ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 169ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return false; 170ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 171ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 172ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool 173ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 174ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard SmallVectorImpl<SDNode*> &NewNodes) const { 175ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 176ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return false; 177ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 178ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 179ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardunsigned 180ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 181ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard bool UnfoldLoad, bool UnfoldStore, 182ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard unsigned *LoadRegIndex) const { 183ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 184ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return 0; 185ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 186ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 187ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool AMDGPUInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 188ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard int64_t Offset1, int64_t Offset2, 189ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard unsigned NumLoads) const { 190ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard assert(Offset2 > Offset1 191ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard && "Second offset should be larger than first offset!"); 192ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // If we have less than 16 loads in a row, and the offsets are within 16, 193ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // then schedule together. 194ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Make the loads schedule near if it fits in a cacheline 195ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return (NumLoads < 16 && (Offset2 - Offset1) < 16); 196ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 197ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 198ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool 199ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) 200ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const { 201ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 202ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return true; 203ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 204ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardvoid AMDGPUInstrInfo::insertNoop(MachineBasicBlock &MBB, 205ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard MachineBasicBlock::iterator MI) const { 206ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 207ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 208ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 209ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool AMDGPUInstrInfo::isPredicated(const MachineInstr *MI) const { 210ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 211ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return false; 212ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 213ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool 214ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 215ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const SmallVectorImpl<MachineOperand> &Pred2) 216ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard const { 217ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 218ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return false; 219ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 220ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 221ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool AMDGPUInstrInfo::DefinesPredicate(MachineInstr *MI, 222ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard std::vector<MachineOperand> &Pred) const { 223ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 224ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return false; 225ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 226ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 227ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool AMDGPUInstrInfo::isPredicable(MachineInstr *MI) const { 228ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 229ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return MI->getDesc().isPredicable(); 230ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 231ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard 232ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellardbool 233ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom StellardAMDGPUInstrInfo::isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 234ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard // TODO: Implement this function 235ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard return true; 236ac669c32c6e80841e3ee63d65b58c0031b22e7b8Tom Stellard} 2375a1edb8655aeab17bf0d90e202fb31a1adb53498Tom Stellard 2385a1edb8655aeab17bf0d90e202fb31a1adb53498Tom Stellardvoid AMDGPUInstrInfo::convertToISA(MachineInstr & MI, MachineFunction &MF, 239a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard DebugLoc DL) const 240a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard{ 241a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineRegisterInfo &MRI = MF.getRegInfo(); 242a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard const AMDGPURegisterInfo & RI = getRegisterInfo(); 243a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 244a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard for (unsigned i = 0; i < MI.getNumOperands(); i++) { 245a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MachineOperand &MO = MI.getOperand(i); 246bcfc97dbf40c256ed59c2424e0c55b845f0f2569Tom Stellard // Convert dst regclass to one that is supported by the ISA 247a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard if (MO.isReg() && MO.isDef()) { 248a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard if (TargetRegisterInfo::isVirtualRegister(MO.getReg())) { 249a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard const TargetRegisterClass * oldRegClass = MRI.getRegClass(MO.getReg()); 250a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard const TargetRegisterClass * newRegClass = RI.getISARegClass(oldRegClass); 251a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 252a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard assert(newRegClass); 253a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard 254a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard MRI.setRegClass(MO.getReg(), newRegClass); 255a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard } 256a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard } 257a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard } 258a75c6163e605f35b14f26930dd9227e4f337ec9eTom Stellard} 259