AMDGPUInstrInfo.h revision 67a47a445b544ac638d10303dc697d70f25d12fb 
1//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the definition of a TargetInstrInfo class that is common
11// to all AMD GPUs.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef AMDGPUINSTRUCTIONINFO_H_
16#define AMDGPUINSTRUCTIONINFO_H_
17
18#include "AMDGPURegisterInfo.h"
19#include "AMDGPUInstrInfo.h"
20#include "llvm/Target/TargetInstrInfo.h"
21
22#include <map>
23
24#define GET_INSTRINFO_HEADER
25#define GET_INSTRINFO_ENUM
26#include "AMDGPUGenInstrInfo.inc"
27
28#define MO_FLAG_CLAMP (1 << 0)
29#define MO_FLAG_NEG   (1 << 1)
30#define MO_FLAG_ABS   (1 << 2)
31#define MO_FLAG_MASK  (1 << 3)
32#define MO_FLAG_PUSH  (1 << 4)
33#define MO_FLAG_LAST  (1 << 5)
34#define NUM_MO_FLAGS 6
35
36#define OPCODE_IS_ZERO_INT 0x00000045
37#define OPCODE_IS_NOT_ZERO_INT 0x00000042
38#define OPCODE_IS_ZERO 0x00000020
39#define OPCODE_IS_NOT_ZERO 0x00000023
40
41namespace llvm {
42
43class AMDGPUTargetMachine;
44class MachineFunction;
45class MachineInstr;
46class MachineInstrBuilder;
47
48class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
49private:
50  const AMDGPURegisterInfo RI;
51  TargetMachine &TM;
52  bool getNextBranchInstr(MachineBasicBlock::iterator &iter,
53                          MachineBasicBlock &MBB) const;
54public:
55  explicit AMDGPUInstrInfo(TargetMachine &tm);
56
57  virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0;
58
59  bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
60                             unsigned &DstReg, unsigned &SubIdx) const;
61
62  unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
63  unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
64                                     int &FrameIndex) const;
65  bool hasLoadFromStackSlot(const MachineInstr *MI,
66                            const MachineMemOperand *&MMO,
67                            int &FrameIndex) const;
68  unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
69  unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI,
70                                      int &FrameIndex) const;
71  bool hasStoreFromStackSlot(const MachineInstr *MI,
72                             const MachineMemOperand *&MMO,
73                             int &FrameIndex) const;
74
75  MachineInstr *
76  convertToThreeAddress(MachineFunction::iterator &MFI,
77                        MachineBasicBlock::iterator &MBBI,
78                        LiveVariables *LV) const;
79
80
81  virtual void copyPhysReg(MachineBasicBlock &MBB,
82                           MachineBasicBlock::iterator MI, DebugLoc DL,
83                           unsigned DestReg, unsigned SrcReg,
84                           bool KillSrc) const = 0;
85
86  void storeRegToStackSlot(MachineBasicBlock &MBB,
87                           MachineBasicBlock::iterator MI,
88                           unsigned SrcReg, bool isKill, int FrameIndex,
89                           const TargetRegisterClass *RC,
90                           const TargetRegisterInfo *TRI) const;
91  void loadRegFromStackSlot(MachineBasicBlock &MBB,
92                            MachineBasicBlock::iterator MI,
93                            unsigned DestReg, int FrameIndex,
94                            const TargetRegisterClass *RC,
95                            const TargetRegisterInfo *TRI) const;
96
97protected:
98  MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
99                                      MachineInstr *MI,
100                                      const SmallVectorImpl<unsigned> &Ops,
101                                      int FrameIndex) const;
102  MachineInstr *foldMemoryOperandImpl(MachineFunction &MF,
103                                      MachineInstr *MI,
104                                      const SmallVectorImpl<unsigned> &Ops,
105                                      MachineInstr *LoadMI) const;
106public:
107  bool canFoldMemoryOperand(const MachineInstr *MI,
108                            const SmallVectorImpl<unsigned> &Ops) const;
109  bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
110                           unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
111                           SmallVectorImpl<MachineInstr *> &NewMIs) const;
112  bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
113                           SmallVectorImpl<SDNode *> &NewNodes) const;
114  unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
115                                      bool UnfoldLoad, bool UnfoldStore,
116                                      unsigned *LoadRegIndex = 0) const;
117  bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
118                               int64_t Offset1, int64_t Offset2,
119                               unsigned NumLoads) const;
120
121  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
122  void insertNoop(MachineBasicBlock &MBB,
123                  MachineBasicBlock::iterator MI) const;
124  bool isPredicated(const MachineInstr *MI) const;
125  bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
126                         const SmallVectorImpl<MachineOperand> &Pred2) const;
127  bool DefinesPredicate(MachineInstr *MI,
128                        std::vector<MachineOperand> &Pred) const;
129  bool isPredicable(MachineInstr *MI) const;
130  bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
131
132  // Helper functions that check the opcode for status information
133  bool isLoadInst(llvm::MachineInstr *MI) const;
134  bool isExtLoadInst(llvm::MachineInstr *MI) const;
135  bool isSWSExtLoadInst(llvm::MachineInstr *MI) const;
136  bool isSExtLoadInst(llvm::MachineInstr *MI) const;
137  bool isZExtLoadInst(llvm::MachineInstr *MI) const;
138  bool isAExtLoadInst(llvm::MachineInstr *MI) const;
139  bool isStoreInst(llvm::MachineInstr *MI) const;
140  bool isTruncStoreInst(llvm::MachineInstr *MI) const;
141
142  virtual MachineInstr* getMovImmInstr(MachineFunction *MF, unsigned DstReg,
143                                       int64_t Imm) const = 0;
144  virtual unsigned getIEQOpcode() const = 0;
145  virtual bool isMov(unsigned opcode) const = 0;
146
147  /// convertToISA - Convert the AMDIL MachineInstr to a supported ISA
148  /// MachineInstr
149  virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF,
150    DebugLoc DL) const;
151
152};
153
154} // End llvm namespace
155
156#endif // AMDGPUINSTRINFO_H_
157