AMDGPUInstrInfo.h revision 82a5d0c64142990236b40567561b6e99b7158216
1//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the definition of a TargetInstrInfo class that is common 11// to all AMD GPUs. 12// 13//===----------------------------------------------------------------------===// 14 15#ifndef AMDGPUINSTRUCTIONINFO_H_ 16#define AMDGPUINSTRUCTIONINFO_H_ 17 18#include "AMDGPURegisterInfo.h" 19#include "AMDGPUInstrInfo.h" 20#include "llvm/Target/TargetInstrInfo.h" 21 22#include <map> 23 24#define GET_INSTRINFO_HEADER 25#define GET_INSTRINFO_ENUM 26#include "AMDGPUGenInstrInfo.inc" 27 28#define MO_FLAG_CLAMP (1 << 0) 29#define MO_FLAG_NEG (1 << 1) 30#define MO_FLAG_ABS (1 << 2) 31#define MO_FLAG_MASK (1 << 3) 32#define MO_FLAG_PUSH (1 << 4) 33#define MO_FLAG_LAST (1 << 5) 34 35#define OPCODE_IS_ZERO_INT 0x00000045 36#define OPCODE_IS_NOT_ZERO_INT 0x00000042 37#define OPCODE_IS_ZERO 0x00000020 38#define OPCODE_IS_NOT_ZERO 0x00000023 39 40namespace llvm { 41 42class AMDGPUTargetMachine; 43class MachineFunction; 44class MachineInstr; 45class MachineInstrBuilder; 46 47class AMDGPUInstrInfo : public AMDGPUGenInstrInfo { 48private: 49 const AMDGPURegisterInfo RI; 50 TargetMachine &TM; 51 bool getNextBranchInstr(MachineBasicBlock::iterator &iter, 52 MachineBasicBlock &MBB) const; 53public: 54 explicit AMDGPUInstrInfo(TargetMachine &tm); 55 56 virtual const AMDGPURegisterInfo &getRegisterInfo() const = 0; 57 58 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg, 59 unsigned &DstReg, unsigned &SubIdx) const; 60 61 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 62 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, 63 int &FrameIndex) const; 64 bool hasLoadFromStackSlot(const MachineInstr *MI, 65 const MachineMemOperand *&MMO, 66 int &FrameIndex) const; 67 unsigned isStoreFromStackSlot(const MachineInstr *MI, int &FrameIndex) const; 68 unsigned isStoreFromStackSlotPostFE(const MachineInstr *MI, 69 int &FrameIndex) const; 70 bool hasStoreFromStackSlot(const MachineInstr *MI, 71 const MachineMemOperand *&MMO, 72 int &FrameIndex) const; 73 74 MachineInstr * 75 convertToThreeAddress(MachineFunction::iterator &MFI, 76 MachineBasicBlock::iterator &MBBI, 77 LiveVariables *LV) const; 78 79 80 virtual void copyPhysReg(MachineBasicBlock &MBB, 81 MachineBasicBlock::iterator MI, DebugLoc DL, 82 unsigned DestReg, unsigned SrcReg, 83 bool KillSrc) const = 0; 84 85 void storeRegToStackSlot(MachineBasicBlock &MBB, 86 MachineBasicBlock::iterator MI, 87 unsigned SrcReg, bool isKill, int FrameIndex, 88 const TargetRegisterClass *RC, 89 const TargetRegisterInfo *TRI) const; 90 void loadRegFromStackSlot(MachineBasicBlock &MBB, 91 MachineBasicBlock::iterator MI, 92 unsigned DestReg, int FrameIndex, 93 const TargetRegisterClass *RC, 94 const TargetRegisterInfo *TRI) const; 95 96protected: 97 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, 98 MachineInstr *MI, 99 const SmallVectorImpl<unsigned> &Ops, 100 int FrameIndex) const; 101 MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, 102 MachineInstr *MI, 103 const SmallVectorImpl<unsigned> &Ops, 104 MachineInstr *LoadMI) const; 105public: 106 bool canFoldMemoryOperand(const MachineInstr *MI, 107 const SmallVectorImpl<unsigned> &Ops) const; 108 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 109 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 110 SmallVectorImpl<MachineInstr *> &NewMIs) const; 111 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 112 SmallVectorImpl<SDNode *> &NewNodes) const; 113 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, 114 bool UnfoldLoad, bool UnfoldStore, 115 unsigned *LoadRegIndex = 0) const; 116 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 117 int64_t Offset1, int64_t Offset2, 118 unsigned NumLoads) const; 119 120 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 121 void insertNoop(MachineBasicBlock &MBB, 122 MachineBasicBlock::iterator MI) const; 123 bool isPredicated(const MachineInstr *MI) const; 124 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 125 const SmallVectorImpl<MachineOperand> &Pred2) const; 126 bool DefinesPredicate(MachineInstr *MI, 127 std::vector<MachineOperand> &Pred) const; 128 bool isPredicable(MachineInstr *MI) const; 129 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 130 131 // Helper functions that check the opcode for status information 132 bool isLoadInst(llvm::MachineInstr *MI) const; 133 bool isExtLoadInst(llvm::MachineInstr *MI) const; 134 bool isSWSExtLoadInst(llvm::MachineInstr *MI) const; 135 bool isSExtLoadInst(llvm::MachineInstr *MI) const; 136 bool isZExtLoadInst(llvm::MachineInstr *MI) const; 137 bool isAExtLoadInst(llvm::MachineInstr *MI) const; 138 bool isStoreInst(llvm::MachineInstr *MI) const; 139 bool isTruncStoreInst(llvm::MachineInstr *MI) const; 140 141 virtual MachineInstr* getMovImmInstr(MachineFunction *MF, unsigned DstReg, 142 int64_t Imm) const = 0; 143 virtual unsigned getIEQOpcode() const = 0; 144 virtual bool isMov(unsigned opcode) const = 0; 145 146 /// convertToISA - Convert the AMDIL MachineInstr to a supported ISA 147 /// MachineInstr 148 virtual MachineInstr * convertToISA(MachineInstr & MI, MachineFunction &MF, 149 DebugLoc DL) const; 150 151}; 152 153} // End llvm namespace 154 155#endif // AMDGPUINSTRINFO_H_ 156