1//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains instruction defs that are common to all hw codegen 11// targets. 12// 13//===----------------------------------------------------------------------===// 14 15class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction { 16 field bits<16> AMDILOp = 0; 17 field bits<3> Gen = 0; 18 19 let Namespace = "AMDGPU"; 20 let OutOperandList = outs; 21 let InOperandList = ins; 22 let AsmString = asm; 23 let Pattern = pattern; 24 let Itinerary = NullALU; 25 let TSFlags{42-40} = Gen; 26 let TSFlags{63-48} = AMDILOp; 27} 28 29class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern> 30 : AMDGPUInst<outs, ins, asm, pattern> { 31 32 field bits<32> Inst = 0xffffffff; 33 34} 35 36def COND_EQ : PatLeaf < 37 (cond), 38 [{switch(N->get()){{default: return false; 39 case ISD::SETOEQ: case ISD::SETUEQ: 40 case ISD::SETEQ: return true;}}}] 41>; 42 43def COND_NE : PatLeaf < 44 (cond), 45 [{switch(N->get()){{default: return false; 46 case ISD::SETONE: case ISD::SETUNE: 47 case ISD::SETNE: return true;}}}] 48>; 49def COND_GT : PatLeaf < 50 (cond), 51 [{switch(N->get()){{default: return false; 52 case ISD::SETOGT: case ISD::SETUGT: 53 case ISD::SETGT: return true;}}}] 54>; 55 56def COND_GE : PatLeaf < 57 (cond), 58 [{switch(N->get()){{default: return false; 59 case ISD::SETOGE: case ISD::SETUGE: 60 case ISD::SETGE: return true;}}}] 61>; 62 63def COND_LT : PatLeaf < 64 (cond), 65 [{switch(N->get()){{default: return false; 66 case ISD::SETOLT: case ISD::SETULT: 67 case ISD::SETLT: return true;}}}] 68>; 69 70def COND_LE : PatLeaf < 71 (cond), 72 [{switch(N->get()){{default: return false; 73 case ISD::SETOLE: case ISD::SETULE: 74 case ISD::SETLE: return true;}}}] 75>; 76 77class Constants { 78int TWO_PI = 0x40c90fdb; 79int PI = 0x40490fdb; 80int TWO_PI_INV = 0x3e22f983; 81} 82def CONST : Constants; 83 84def FP_ZERO : PatLeaf < 85 (fpimm), 86 [{return N->getValueAPF().isZero();}] 87>; 88 89def FP_ONE : PatLeaf < 90 (fpimm), 91 [{return N->isExactlyValue(1.0);}] 92>; 93 94let isCodeGenOnly = 1, isPseudo = 1, usesCustomInserter = 1 in { 95 96class CLAMP <RegisterClass rc> : AMDGPUShaderInst < 97 (outs rc:$dst), 98 (ins rc:$src0), 99 "CLAMP $dst, $src0", 100 [(set rc:$dst, (int_AMDIL_clamp rc:$src0, (f32 FP_ZERO), (f32 FP_ONE)))] 101>; 102 103class FABS <RegisterClass rc> : AMDGPUShaderInst < 104 (outs rc:$dst), 105 (ins rc:$src0), 106 "FABS $dst, $src0", 107 [(set rc:$dst, (fabs rc:$src0))] 108>; 109 110class FNEG <RegisterClass rc> : AMDGPUShaderInst < 111 (outs rc:$dst), 112 (ins rc:$src0), 113 "FNEG $dst, $src0", 114 [(set rc:$dst, (fneg rc:$src0))] 115>; 116 117} // End isCodeGenOnly = 1, isPseudo = 1, hasCustomInserter = 1 118 119/* Generic helper patterns for intrinsics */ 120/* -------------------------------------- */ 121 122class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul, 123 RegisterClass rc> : Pat < 124 (int_AMDGPU_pow rc:$src0, rc:$src1), 125 (exp_ieee (mul rc:$src1, (log_ieee rc:$src0))) 126>; 127 128/* Other helper patterns */ 129/* --------------------- */ 130 131/* Extract element pattern */ 132class Extract_Element <ValueType sub_type, ValueType vec_type, 133 RegisterClass vec_class, int sub_idx, 134 SubRegIndex sub_reg>: Pat< 135 (sub_type (vector_extract (vec_type vec_class:$src), sub_idx)), 136 (EXTRACT_SUBREG vec_class:$src, sub_reg) 137>; 138 139/* Insert element pattern */ 140class Insert_Element <ValueType elem_type, ValueType vec_type, 141 RegisterClass elem_class, RegisterClass vec_class, 142 int sub_idx, SubRegIndex sub_reg> : Pat < 143 144 (vec_type (vector_insert (vec_type vec_class:$vec), 145 (elem_type elem_class:$elem), sub_idx)), 146 (INSERT_SUBREG vec_class:$vec, elem_class:$elem, sub_reg) 147>; 148 149// Vector Build pattern 150class Vector_Build <ValueType vecType, RegisterClass elemClass> : Pat < 151 (IL_vbuild elemClass:$src), 152 (INSERT_SUBREG (vecType (IMPLICIT_DEF)), elemClass:$src, sel_x) 153>; 154 155// bitconvert pattern 156class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat < 157 (dt (bitconvert (st rc:$src0))), 158 (dt rc:$src0) 159>; 160 161include "R600Instructions.td" 162 163include "SIInstrInfo.td" 164 165