Makefile.sources revision 542f6feda9bf18267dbd337943a5e871400d425a 
1
2TD_FILES := \
3	AMDGPU.td		\
4	AMDGPUInstrInfo.td	\
5	AMDGPUInstructions.td	\
6	AMDGPUIntrinsics.td	\
7	AMDGPURegisterInfo.td	\
8	AMDILBase.td		\
9	AMDILInstrInfo.td	\
10	AMDILIntrinsics.td	\
11	AMDILRegisterInfo.td	\
12	Processors.td		\
13	R600Instructions.td	\
14	R600Intrinsics.td	\
15	R600IntrinsicsNoOpenCL.td	\
16	R600IntrinsicsOpenCL.td	\
17	R600RegisterInfo.td	\
18	R600Schedule.td		\
19	SIInstrFormats.td	\
20	SIInstrInfo.td		\
21	SIInstructions.td	\
22	SIIntrinsics.td		\
23	SIRegisterInfo.td	\
24	SISchedule.td
25
26
27GENERATED_SOURCES := \
28	R600Intrinsics.td		\
29	R600RegisterInfo.td		\
30	SIRegisterInfo.td		\
31	SIRegisterGetHWRegNum.inc		\
32	AMDGPUGenRegisterInfo.inc	\
33	AMDGPUGenInstrInfo.inc		\
34	AMDGPUGenAsmWriter.inc		\
35	AMDGPUGenDAGISel.inc		\
36	AMDGPUGenCallingConv.inc		\
37	AMDGPUGenSubtargetInfo.inc		\
38	AMDGPUGenEDInfo.inc		\
39	AMDGPUGenIntrinsics.inc		\
40	AMDGPUGenCodeEmitter.inc	\
41	AMDGPUGenMCCodeEmitter.inc	\
42	AMDGPUGenDFAPacketizer.inc
43
44CPP_SOURCES := \
45	AMDIL7XXDevice.cpp		\
46	AMDILCFGStructurizer.cpp	\
47	AMDILDevice.cpp			\
48	AMDILDeviceInfo.cpp		\
49	AMDILEvergreenDevice.cpp	\
50	AMDILFrameLowering.cpp		\
51	AMDILIntrinsicInfo.cpp		\
52	AMDILISelDAGToDAG.cpp		\
53	AMDILISelLowering.cpp		\
54	AMDILNIDevice.cpp		\
55	AMDILPeepholeOptimizer.cpp	\
56	AMDILSIDevice.cpp		\
57	AMDGPUAsmPrinter.cpp \
58	AMDGPUMCInstLower.cpp \
59	AMDGPUSubtarget.cpp		\
60	AMDGPUTargetMachine.cpp		\
61	AMDGPUISelLowering.cpp		\
62	AMDGPUConvertToISA.cpp		\
63	AMDGPUInstrInfo.cpp		\
64	AMDGPURegisterInfo.cpp		\
65	R600ExpandSpecialInstrs.cpp	\
66	R600ISelLowering.cpp		\
67	R600InstrInfo.cpp		\
68	R600KernelParameters.cpp	\
69	R600MachineFunctionInfo.cpp	\
70	R600RegisterInfo.cpp		\
71	SIAssignInterpRegs.cpp		\
72	SIInstrInfo.cpp			\
73	SIISelLowering.cpp		\
74	SIMachineFunctionInfo.cpp	\
75	SIRegisterInfo.cpp		\
76	InstPrinter/AMDGPUInstPrinter.cpp \
77	MCTargetDesc/AMDGPUMCAsmInfo.cpp	\
78	MCTargetDesc/AMDGPUAsmBackend.cpp \
79	MCTargetDesc/AMDGPUMCTargetDesc.cpp	\
80	MCTargetDesc/SIMCCodeEmitter.cpp \
81	MCTargetDesc/R600MCCodeEmitter.cpp \
82	TargetInfo/AMDGPUTargetInfo.cpp	\
83	radeon_llvm_emit.cpp
84
85C_SOURCES := \
86	radeon_setup_tgsi_llvm.c
87