Makefile.sources revision 71b5503164deee189df5ac4e2b8d2fcd09a8ec55 
1
2TD_FILES := \
3	AMDGPU.td		\
4	AMDGPUInstrInfo.td	\
5	AMDGPUInstructions.td	\
6	AMDGPUIntrinsics.td	\
7	AMDGPURegisterInfo.td	\
8	AMDILBase.td		\
9	AMDILInstrInfo.td	\
10	AMDILIntrinsics.td	\
11	AMDILRegisterInfo.td	\
12	Processors.td		\
13	R600InstrInfo.td	\
14	R600Instructions.td	\
15	R600Intrinsics.td	\
16	R600IntrinsicsNoOpenCL.td	\
17	R600IntrinsicsOpenCL.td	\
18	R600RegisterInfo.td	\
19	R600Schedule.td		\
20	SIInstrFormats.td	\
21	SIInstrInfo.td		\
22	SIInstructions.td	\
23	SIIntrinsics.td		\
24	SIRegisterInfo.td	\
25	SISchedule.td
26
27
28GENERATED_SOURCES := \
29	R600Intrinsics.td		\
30	R600RegisterInfo.td		\
31	SIRegisterInfo.td		\
32	SIRegisterGetHWRegNum.inc		\
33	AMDGPUGenRegisterInfo.inc	\
34	AMDGPUGenInstrInfo.inc		\
35	AMDGPUGenAsmWriter.inc		\
36	AMDGPUGenDAGISel.inc		\
37	AMDGPUGenCallingConv.inc		\
38	AMDGPUGenSubtargetInfo.inc		\
39	AMDGPUGenEDInfo.inc		\
40	AMDGPUGenIntrinsics.inc		\
41	AMDGPUGenCodeEmitter.inc	\
42	AMDGPUGenMCCodeEmitter.inc	\
43	AMDGPUGenDFAPacketizer.inc
44
45CPP_SOURCES := \
46	AMDIL7XXDevice.cpp		\
47	AMDILCFGStructurizer.cpp	\
48	AMDILDevice.cpp			\
49	AMDILDeviceInfo.cpp		\
50	AMDILEvergreenDevice.cpp	\
51	AMDILFrameLowering.cpp		\
52	AMDILIntrinsicInfo.cpp		\
53	AMDILISelDAGToDAG.cpp		\
54	AMDILISelLowering.cpp		\
55	AMDILNIDevice.cpp		\
56	AMDILPeepholeOptimizer.cpp	\
57	AMDILSIDevice.cpp		\
58	AMDGPUAsmPrinter.cpp \
59	AMDGPUMCInstLower.cpp \
60	AMDGPUSubtarget.cpp		\
61	AMDGPUTargetMachine.cpp		\
62	AMDGPUISelLowering.cpp		\
63	AMDGPUConvertToISA.cpp		\
64	AMDGPUInstrInfo.cpp		\
65	AMDGPURegisterInfo.cpp		\
66	R600ExpandSpecialInstrs.cpp	\
67	R600ISelLowering.cpp		\
68	R600InstrInfo.cpp		\
69	R600KernelParameters.cpp	\
70	R600MachineFunctionInfo.cpp	\
71	R600RegisterInfo.cpp		\
72	SIAssignInterpRegs.cpp		\
73	SIInstrInfo.cpp			\
74	SIISelLowering.cpp		\
75	SIMachineFunctionInfo.cpp	\
76	SIRegisterInfo.cpp		\
77	InstPrinter/AMDGPUInstPrinter.cpp \
78	MCTargetDesc/AMDGPUMCAsmInfo.cpp	\
79	MCTargetDesc/AMDGPUAsmBackend.cpp \
80	MCTargetDesc/AMDGPUMCTargetDesc.cpp	\
81	MCTargetDesc/SIMCCodeEmitter.cpp \
82	MCTargetDesc/R600MCCodeEmitter.cpp \
83	TargetInfo/AMDGPUTargetInfo.cpp	\
84	radeon_llvm_emit.cpp
85
86C_SOURCES := \
87	radeon_setup_tgsi_llvm.c
88