Makefile.sources revision ba333a6518d3d7ed1c1fcd7bc6da457e54941dcd
1 2GENERATED_SOURCES := \ 3 R600ShaderPatterns.td \ 4 R600RegisterInfo.td \ 5 AMDGPUInstrEnums.td \ 6 SIRegisterInfo.td \ 7 SIRegisterGetHWRegNum.inc \ 8 AMDILGenRegisterInfo.inc \ 9 AMDILGenInstrInfo.inc \ 10 AMDILGenAsmWriter.inc \ 11 AMDILGenDAGISel.inc \ 12 AMDILGenCallingConv.inc \ 13 AMDILGenSubtargetInfo.inc \ 14 AMDILGenEDInfo.inc \ 15 AMDILGenIntrinsics.inc \ 16 AMDILGenCodeEmitter.inc \ 17 AMDGPUInstrEnums.h.include \ 18 AMDGPUInstrEnums.include 19 20CPP_SOURCES := \ 21 AMDIL7XXDevice.cpp \ 22 AMDILCFGStructurizer.cpp \ 23 AMDILDevice.cpp \ 24 AMDILDeviceInfo.cpp \ 25 AMDILEvergreenDevice.cpp \ 26 AMDILELFWriterInfo.cpp \ 27 AMDILFrameLowering.cpp \ 28 AMDILInstrInfo.cpp \ 29 AMDILIntrinsicInfo.cpp \ 30 AMDILISelDAGToDAG.cpp \ 31 AMDILISelLowering.cpp \ 32 AMDILLiteralManager.cpp \ 33 AMDILMachineFunctionInfo.cpp \ 34 AMDILMachinePeephole.cpp \ 35 AMDILMCCodeEmitter.cpp \ 36 AMDILModuleInfo.cpp \ 37 AMDILNIDevice.cpp \ 38 AMDILPeepholeOptimizer.cpp \ 39 AMDILRegisterInfo.cpp \ 40 AMDILSIDevice.cpp \ 41 AMDILSubtarget.cpp \ 42 AMDILTargetMachine.cpp \ 43 AMDILUtilityFunctions.cpp \ 44 AMDGPUTargetMachine.cpp \ 45 AMDGPUISelLowering.cpp \ 46 AMDGPUConvertToISA.cpp \ 47 AMDGPULowerInstructions.cpp \ 48 AMDGPULowerShaderInstructions.cpp \ 49 AMDGPUReorderPreloadInstructions.cpp \ 50 AMDGPUInstrInfo.cpp \ 51 AMDGPURegisterInfo.cpp \ 52 AMDGPUUtil.cpp \ 53 R600CodeEmitter.cpp \ 54 R600ISelLowering.cpp \ 55 R600InstrInfo.cpp \ 56 R600KernelParameters.cpp \ 57 R600LowerInstructions.cpp \ 58 R600LowerShaderInstructions.cpp \ 59 R600RegisterInfo.cpp \ 60 SIAssignInterpRegs.cpp \ 61 SICodeEmitter.cpp \ 62 SIInstrInfo.cpp \ 63 SIISelLowering.cpp \ 64 SILowerShaderInstructions.cpp \ 65 SIMachineFunctionInfo.cpp \ 66 SIPropagateImmReads.cpp \ 67 SIRegisterInfo.cpp \ 68 MCTargetDesc/AMDILMCAsmInfo.cpp \ 69 MCTargetDesc/AMDILMCTargetDesc.cpp \ 70 TargetInfo/AMDILTargetInfo.cpp \ 71 radeon_llvm_emit.cpp 72 73C_SOURCES := \ 74 radeon_setup_tgsi_llvm.c 75