R600InstrInfo.h revision 040c2e04568e2fe9ec07167f5300a3dcdfebb04e 
1//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Interface definition for R600InstrInfo
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef R600INSTRUCTIONINFO_H_
15#define R600INSTRUCTIONINFO_H_
16
17#include "AMDIL.h"
18#include "AMDGPUInstrInfo.h"
19#include "R600RegisterInfo.h"
20
21#include <map>
22
23namespace llvm {
24
25  class AMDGPUTargetMachine;
26  class DFAPacketizer;
27  class ScheduleDAG;
28  class MachineFunction;
29  class MachineInstr;
30  class MachineInstrBuilder;
31
32  class R600InstrInfo : public AMDGPUInstrInfo {
33  private:
34  const R600RegisterInfo RI;
35  AMDGPUTargetMachine &TM;
36
37  public:
38  explicit R600InstrInfo(AMDGPUTargetMachine &tm);
39
40  const R600RegisterInfo &getRegisterInfo() const;
41  virtual void copyPhysReg(MachineBasicBlock &MBB,
42                           MachineBasicBlock::iterator MI, DebugLoc DL,
43                           unsigned DestReg, unsigned SrcReg,
44                           bool KillSrc) const;
45
46  bool isTrig(const MachineInstr &MI) const;
47  bool isPlaceHolderOpcode(unsigned opcode) const;
48  bool isTexOp(unsigned opcode) const;
49  bool isReductionOp(unsigned opcode) const;
50  bool isCubeOp(unsigned opcode) const;
51  bool isFCOp(unsigned opcode) const;
52
53  /// isVector - Vector instructions are instructions that must fill all
54  /// instruction slots within an instruction group.
55  bool isVector(const MachineInstr &MI) const;
56
57  virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
58                                        int64_t Imm) const;
59
60  virtual unsigned getIEQOpcode() const;
61  virtual bool isMov(unsigned Opcode) const;
62
63  DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
64                                           const ScheduleDAG *DAG) const;
65};
66
67} // End llvm namespace
68
69namespace R600_InstFlag {
70	enum TIF {
71		TRANS_ONLY = (1 << 0),
72		TEX = (1 << 1),
73		REDUCTION = (1 << 2),
74		FC = (1 << 3),
75		TRIG = (1 << 4),
76		OP3 = (1 << 5),
77		VECTOR = (1 << 6)
78	};
79}
80
81#endif // R600INSTRINFO_H_
82